drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101 #define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double))
 102
 103 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 104 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 105
 106 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 107 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 108 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 109   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 110
 111 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 112 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 113 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 114
 115 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 116 enum DPM_EVENT_SRC {
 117         DPM_EVENT_SRC_ANALOG = 0,
 118         DPM_EVENT_SRC_EXTERNAL = 1,
 119         DPM_EVENT_SRC_DIGITAL = 2,
 120         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 121         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 122 };
 123
 124 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 125
 126 struct polaris10_power_state *cast_phw_polaris10_power_state(
 127                                   struct pp_hw_power_state *hw_ps)
 128 {
 129         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 130                                 "Invalid Powerstate Type!",
 131                                  return NULL);
 132
 133         return (struct polaris10_power_state *)hw_ps;
 134 }
 135
 136 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 137                                  const struct pp_hw_power_state *hw_ps)
 138 {
 139         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 140                                 "Invalid Powerstate Type!",
 141                                  return NULL);
 142
 143         return (const struct polaris10_power_state *)hw_ps;
 144 }
 145
 146 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 147 {
 148         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 149                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 150                         ? true : false;
 151 }
 152
 153 /**
 154  * Find the MC microcode version and store it in the HwMgr struct
 155  *
 156  * @param    hwmgr  the address of the powerplay hardware manager.
 157  * @return   always 0
 158  */
 159 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 160 {
 161         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 162
 163         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 164
 165         return 0;
 166 }
 167
 168 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 169 {
 170         uint32_t speedCntl = 0;
 171
 172         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 173         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 174                         ixPCIE_LC_SPEED_CNTL);
 175         return((uint16_t)PHM_GET_FIELD(speedCntl,
 176                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 177 }
 178
 179 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 180 {
 181         uint32_t link_width;
 182
 183         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 184         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 185                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 186
 187         PP_ASSERT_WITH_CODE((7 >= link_width),
 188                         "Invalid PCIe lane width!", return 0);
 189
 190         return decode_pcie_lane_width(link_width);
 191 }
 192
 193 /**
 194 * Enable voltage control
 195 *
 196 * @param    pHwMgr  the address of the powerplay hardware manager.
 197 * @return   always PP_Result_OK
 198 */
 199 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 200 {
 201         PP_ASSERT_WITH_CODE(
 202                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 203                 "Failed to enable voltage DPM during DPM Start Function!",
 204                 return 1;
 205         );
 206
 207         return 0;
 208 }
 209
 210 /**
 211 * Checks if we want to support voltage control
 212 *
 213 * @param    hwmgr  the address of the powerplay hardware manager.
 214 */
 215 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 216 {
 217         const struct polaris10_hwmgr *data =
 218                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 219
 220         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 221 }
 222
 223 /**
 224 * Enable voltage control
 225 *
 226 * @param    hwmgr  the address of the powerplay hardware manager.
 227 * @return   always 0
 228 */
 229 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 230 {
 231         /* enable voltage control */
 232         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 233                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 234
 235         return 0;
 236 }
 237
 238 /**
 239 * Create Voltage Tables.
 240 *
 241 * @param    hwmgr  the address of the powerplay hardware manager.
 242 * @return   always 0
 243 */
 244 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 245 {
 246         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 247         struct phm_ppt_v1_information *table_info =
 248                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 249         int result;
 250
 251         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 252                 result = atomctrl_get_voltage_table_v3(hwmgr,
 253                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 254                                 &(data->mvdd_voltage_table));
 255                 PP_ASSERT_WITH_CODE((0 == result),
 256                                 "Failed to retrieve MVDD table.",
 257                                 return result);
 258         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 259                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 260                                 table_info->vdd_dep_on_mclk);
 261                 PP_ASSERT_WITH_CODE((0 == result),
 262                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 263                                 return result;);
 264         }
 265
 266         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 267                 result = atomctrl_get_voltage_table_v3(hwmgr,
 268                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 269                                 &(data->vddci_voltage_table));
 270                 PP_ASSERT_WITH_CODE((0 == result),
 271                                 "Failed to retrieve VDDCI table.",
 272                                 return result);
 273         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 274                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 275                                 table_info->vdd_dep_on_mclk);
 276                 PP_ASSERT_WITH_CODE((0 == result),
 277                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 278                                 return result);
 279         }
 280
 281         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 282                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 283                                 table_info->vddc_lookup_table);
 284                 PP_ASSERT_WITH_CODE((0 == result),
 285                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 286                                 return result);
 287         }
 288
 289         PP_ASSERT_WITH_CODE(
 290                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 291                         "Too many voltage values for VDDC. Trimming to fit state table.",
 292                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 293                                                                 &(data->vddc_voltage_table)));
 294
 295         PP_ASSERT_WITH_CODE(
 296                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 297                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 298                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 299                                         &(data->vddci_voltage_table)));
 300
 301         PP_ASSERT_WITH_CODE(
 302                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 303                         "Too many voltage values for MVDD. Trimming to fit state table.",
 304                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 305                                                            &(data->mvdd_voltage_table)));
 306
 307         return 0;
 308 }
 309
 310 /**
 311 * Programs static screed detection parameters
 312 *
 313 * @param    hwmgr  the address of the powerplay hardware manager.
 314 * @return   always 0
 315 */
 316 static int polaris10_program_static_screen_threshold_parameters(
 317                                                         struct pp_hwmgr *hwmgr)
 318 {
 319         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 320
 321         /* Set static screen threshold unit */
 322         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 323                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 324                         data->static_screen_threshold_unit);
 325         /* Set static screen threshold */
 326         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 327                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 328                         data->static_screen_threshold);
 329
 330         return 0;
 331 }
 332
 333 /**
 334 * Setup display gap for glitch free memory clock switching.
 335 *
 336 * @param    hwmgr  the address of the powerplay hardware manager.
 337 * @return   always  0
 338 */
 339 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 340 {
 341         uint32_t display_gap =
 342                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 343                                         ixCG_DISPLAY_GAP_CNTL);
 344
 345         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 346                         DISP_GAP, DISPLAY_GAP_IGNORE);
 347
 348         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 349                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 350
 351         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 352                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 353
 354         return 0;
 355 }
 356
 357 /**
 358 * Programs activity state transition voting clients
 359 *
 360 * @param    hwmgr  the address of the powerplay hardware manager.
 361 * @return   always  0
 362 */
 363 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 364 {
 365         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 366
 367         /* Clear reset for voting clients before enabling DPM */
 368         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 369                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 370         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 371                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 372
 373         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 374                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 375         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 376                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 377         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 378                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 379         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 380                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 381         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 382                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 383         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 384                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 385         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 386                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 387         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 388                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 389
 390         return 0;
 391 }
 392
 393 /**
 394 * Get the location of various tables inside the FW image.
 395 *
 396 * @param    hwmgr  the address of the powerplay hardware manager.
 397 * @return   always  0
 398 */
 399 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 400 {
 401         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 402         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 403         uint32_t tmp;
 404         int result;
 405         bool error = false;
 406
 407         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 408                         SMU7_FIRMWARE_HEADER_LOCATION +
 409                         offsetof(SMU74_Firmware_Header, DpmTable),
 410                         &tmp, data->sram_end);
 411
 412         if (0 == result)
 413                 data->dpm_table_start = tmp;
 414
 415         error |= (0 != result);
 416
 417         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 418                         SMU7_FIRMWARE_HEADER_LOCATION +
 419                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 420                         &tmp, data->sram_end);
 421
 422         if (!result) {
 423                 data->soft_regs_start = tmp;
 424                 smu_data->soft_regs_start = tmp;
 425         }
 426
 427         error |= (0 != result);
 428
 429         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 430                         SMU7_FIRMWARE_HEADER_LOCATION +
 431                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 432                         &tmp, data->sram_end);
 433
 434         if (!result)
 435                 data->mc_reg_table_start = tmp;
 436
 437         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 438                         SMU7_FIRMWARE_HEADER_LOCATION +
 439                         offsetof(SMU74_Firmware_Header, FanTable),
 440                         &tmp, data->sram_end);
 441
 442         if (!result)
 443                 data->fan_table_start = tmp;
 444
 445         error |= (0 != result);
 446
 447         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 448                         SMU7_FIRMWARE_HEADER_LOCATION +
 449                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 450                         &tmp, data->sram_end);
 451
 452         if (!result)
 453                 data->arb_table_start = tmp;
 454
 455         error |= (0 != result);
 456
 457         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 458                         SMU7_FIRMWARE_HEADER_LOCATION +
 459                         offsetof(SMU74_Firmware_Header, Version),
 460                         &tmp, data->sram_end);
 461
 462         if (!result)
 463                 hwmgr->microcode_version_info.SMC = tmp;
 464
 465         error |= (0 != result);
 466
 467         return error ? -1 : 0;
 468 }
 469
 470 /* Copy one arb setting to another and then switch the active set.
 471  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 472  */
 473 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 474                 uint32_t arb_src, uint32_t arb_dest)
 475 {
 476         uint32_t mc_arb_dram_timing;
 477         uint32_t mc_arb_dram_timing2;
 478         uint32_t burst_time;
 479         uint32_t mc_cg_config;
 480
 481         switch (arb_src) {
 482         case MC_CG_ARB_FREQ_F0:
 483                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 484                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 485                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 486                 break;
 487         case MC_CG_ARB_FREQ_F1:
 488                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 489                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 490                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 491                 break;
 492         default:
 493                 return -EINVAL;
 494         }
 495
 496         switch (arb_dest) {
 497         case MC_CG_ARB_FREQ_F0:
 498                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 499                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 500                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 501                 break;
 502         case MC_CG_ARB_FREQ_F1:
 503                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 504                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 505                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 506                 break;
 507         default:
 508                 return -EINVAL;
 509         }
 510
 511         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 512         mc_cg_config |= 0x0000000F;
 513         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 514         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 515
 516         return 0;
 517 }
 518
 519 /**
 520 * Initial switch from ARB F0->F1
 521 *
 522 * @param    hwmgr  the address of the powerplay hardware manager.
 523 * @return   always 0
 524 * This function is to be called from the SetPowerState table.
 525 */
 526 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 527 {
 528         return polaris10_copy_and_switch_arb_sets(hwmgr,
 529                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 530 }
 531
 532 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 533 {
 534         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 535         struct phm_ppt_v1_information *table_info =
 536                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 537         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 538         uint32_t i, max_entry;
 539
 540         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 541                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 542                         return -EINVAL);
 543
 544         if (data->use_pcie_performance_levels &&
 545                         !data->use_pcie_power_saving_levels) {
 546                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 547                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 548         } else if (!data->use_pcie_performance_levels &&
 549                         data->use_pcie_power_saving_levels) {
 550                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 551                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 552         }
 553
 554         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 555                                         SMU74_MAX_LEVELS_LINK,
 556                                         MAX_REGULAR_DPM_NUMBER);
 557
 558         if (pcie_table != NULL) {
 559                 /* max_entry is used to make sure we reserve one PCIE level
 560                  * for boot level (fix for A+A PSPP issue).
 561                  * If PCIE table from PPTable have ULV entry + 8 entries,
 562                  * then ignore the last entry.*/
 563                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 564                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 565                 for (i = 1; i < max_entry; i++) {
 566                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 567                                         get_pcie_gen_support(data->pcie_gen_cap,
 568                                                         pcie_table->entries[i].gen_speed),
 569                                         get_pcie_lane_support(data->pcie_lane_cap,
 570                                                         pcie_table->entries[i].lane_width));
 571                 }
 572                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 573
 574                 /* Setup BIF_SCLK levels */
 575                 for (i = 0; i < max_entry; i++)
 576                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 577         } else {
 578                 /* Hardcode Pcie Table */
 579                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 580                                 get_pcie_gen_support(data->pcie_gen_cap,
 581                                                 PP_Min_PCIEGen),
 582                                 get_pcie_lane_support(data->pcie_lane_cap,
 583                                                 PP_Max_PCIELane));
 584                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 585                                 get_pcie_gen_support(data->pcie_gen_cap,
 586                                                 PP_Min_PCIEGen),
 587                                 get_pcie_lane_support(data->pcie_lane_cap,
 588                                                 PP_Max_PCIELane));
 589                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 590                                 get_pcie_gen_support(data->pcie_gen_cap,
 591                                                 PP_Max_PCIEGen),
 592                                 get_pcie_lane_support(data->pcie_lane_cap,
 593                                                 PP_Max_PCIELane));
 594                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 595                                 get_pcie_gen_support(data->pcie_gen_cap,
 596                                                 PP_Max_PCIEGen),
 597                                 get_pcie_lane_support(data->pcie_lane_cap,
 598                                                 PP_Max_PCIELane));
 599                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 600                                 get_pcie_gen_support(data->pcie_gen_cap,
 601                                                 PP_Max_PCIEGen),
 602                                 get_pcie_lane_support(data->pcie_lane_cap,
 603                                                 PP_Max_PCIELane));
 604                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 605                                 get_pcie_gen_support(data->pcie_gen_cap,
 606                                                 PP_Max_PCIEGen),
 607                                 get_pcie_lane_support(data->pcie_lane_cap,
 608                                                 PP_Max_PCIELane));
 609
 610                 data->dpm_table.pcie_speed_table.count = 6;
 611         }
 612         /* Populate last level for boot PCIE level, but do not increment count. */
 613         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 614                         data->dpm_table.pcie_speed_table.count,
 615                         get_pcie_gen_support(data->pcie_gen_cap,
 616                                         PP_Min_PCIEGen),
 617                         get_pcie_lane_support(data->pcie_lane_cap,
 618                                         PP_Max_PCIELane));
 619
 620         return 0;
 621 }
 622
 623 /*
 624  * This function is to initalize all DPM state tables
 625  * for SMU7 based on the dependency table.
 626  * Dynamic state patching function will then trim these
 627  * state tables to the allowed range based
 628  * on the power policy or external client requests,
 629  * such as UVD request, etc.
 630  */
 631 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 632 {
 633         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 634         struct phm_ppt_v1_information *table_info =
 635                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 636         uint32_t i;
 637
 638         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 639                         table_info->vdd_dep_on_sclk;
 640         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 641                         table_info->vdd_dep_on_mclk;
 642
 643         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 644                         "SCLK dependency table is missing. This table is mandatory",
 645                         return -EINVAL);
 646         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 647                         "SCLK dependency table has to have is missing."
 648                         "This table is mandatory",
 649                         return -EINVAL);
 650
 651         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 652                         "MCLK dependency table is missing. This table is mandatory",
 653                         return -EINVAL);
 654         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 655                         "MCLK dependency table has to have is missing."
 656                         "This table is mandatory",
 657                         return -EINVAL);
 658
 659         /* clear the state table to reset everything to default */
 660         phm_reset_single_dpm_table(
 661                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 662         phm_reset_single_dpm_table(
 663                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 664
 665
 666         /* Initialize Sclk DPM table based on allow Sclk values */
 667         data->dpm_table.sclk_table.count = 0;
 668         for (i = 0; i < dep_sclk_table->count; i++) {
 669                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 670                                                 dep_sclk_table->entries[i].clk) {
 671
 672                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 673                                         dep_sclk_table->entries[i].clk;
 674
 675                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 676                                         (i == 0) ? true : false;
 677                         data->dpm_table.sclk_table.count++;
 678                 }
 679         }
 680
 681         /* Initialize Mclk DPM table based on allow Mclk values */
 682         data->dpm_table.mclk_table.count = 0;
 683         for (i = 0; i < dep_mclk_table->count; i++) {
 684                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 685                                 [data->dpm_table.mclk_table.count - 1].value !=
 686                                                 dep_mclk_table->entries[i].clk) {
 687                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 688                                                         dep_mclk_table->entries[i].clk;
 689                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 690                                                         (i == 0) ? true : false;
 691                         data->dpm_table.mclk_table.count++;
 692                 }
 693         }
 694
 695         /* setup PCIE gen speed levels */
 696         polaris10_setup_default_pcie_table(hwmgr);
 697
 698         /* save a copy of the default DPM table */
 699         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 700                         sizeof(struct polaris10_dpm_table));
 701
 702         return 0;
 703 }
 704
 705 uint8_t convert_to_vid(uint16_t vddc)
 706 {
 707         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 708 }
 709
 710 /**
 711  * Mvdd table preparation for SMC.
 712  *
 713  * @param    *hwmgr The address of the hardware manager.
 714  * @param    *table The SMC DPM table structure to be populated.
 715  * @return   0
 716  */
 717 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 718                         SMU74_Discrete_DpmTable *table)
 719 {
 720         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 721         uint32_t count, level;
 722
 723         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 724                 count = data->mvdd_voltage_table.count;
 725                 if (count > SMU_MAX_SMIO_LEVELS)
 726                         count = SMU_MAX_SMIO_LEVELS;
 727                 for (level = 0; level < count; level++) {
 728                         table->SmioTable2.Pattern[level].Voltage =
 729                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 730                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 731                         table->SmioTable2.Pattern[level].Smio =
 732                                 (uint8_t) level;
 733                         table->Smio[level] |=
 734                                 data->mvdd_voltage_table.entries[level].smio_low;
 735                 }
 736                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 737
 738                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 739         }
 740
 741         return 0;
 742 }
 743
 744 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 745                                         struct SMU74_Discrete_DpmTable *table)
 746 {
 747         uint32_t count, level;
 748         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 749
 750         count = data->vddci_voltage_table.count;
 751
 752         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 753                 if (count > SMU_MAX_SMIO_LEVELS)
 754                         count = SMU_MAX_SMIO_LEVELS;
 755                 for (level = 0; level < count; ++level) {
 756                         table->SmioTable1.Pattern[level].Voltage =
 757                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 758                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 759
 760                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 761                 }
 762         }
 763
 764         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 765
 766         return 0;
 767 }
 768
 769 /**
 770 * Preparation of vddc and vddgfx CAC tables for SMC.
 771 *
 772 * @param    hwmgr  the address of the hardware manager
 773 * @param    table  the SMC DPM table structure to be populated
 774 * @return   always 0
 775 */
 776 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 777                 struct SMU74_Discrete_DpmTable *table)
 778 {
 779         uint32_t count;
 780         uint8_t index;
 781         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 782         struct phm_ppt_v1_information *table_info =
 783                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 784         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 785                         table_info->vddc_lookup_table;
 786         /* tables is already swapped, so in order to use the value from it,
 787          * we need to swap it back.
 788          * We are populating vddc CAC data to BapmVddc table
 789          * in split and merged mode
 790          */
 791         for (count = 0; count < lookup_table->count; count++) {
 792                 index = phm_get_voltage_index(lookup_table,
 793                                 data->vddc_voltage_table.entries[count].value);
 794                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 795                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 796                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 797         }
 798
 799         return 0;
 800 }
 801
 802 /**
 803 * Preparation of voltage tables for SMC.
 804 *
 805 * @param    hwmgr   the address of the hardware manager
 806 * @param    table   the SMC DPM table structure to be populated
 807 * @return   always  0
 808 */
 809
 810 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 811                 struct SMU74_Discrete_DpmTable *table)
 812 {
 813         polaris10_populate_smc_vddci_table(hwmgr, table);
 814         polaris10_populate_smc_mvdd_table(hwmgr, table);
 815         polaris10_populate_cac_table(hwmgr, table);
 816
 817         return 0;
 818 }
 819
 820 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 821                 struct SMU74_Discrete_Ulv *state)
 822 {
 823         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 824         struct phm_ppt_v1_information *table_info =
 825                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 826
 827         state->CcPwrDynRm = 0;
 828         state->CcPwrDynRm1 = 0;
 829
 830         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 831         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 832                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 833
 834         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 835
 836         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 837         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 838         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 839
 840         return 0;
 841 }
 842
 843 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 844                 struct SMU74_Discrete_DpmTable *table)
 845 {
 846         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 847 }
 848
 849 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 850                 struct SMU74_Discrete_DpmTable *table)
 851 {
 852         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 853         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 854         int i;
 855
 856         /* Index (dpm_table->pcie_speed_table.count)
 857          * is reserved for PCIE boot level. */
 858         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 859                 table->LinkLevel[i].PcieGenSpeed  =
 860                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 861                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 862                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 863                 table->LinkLevel[i].EnabledForActivity = 1;
 864                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 865                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 866                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 867         }
 868
 869         data->smc_state_table.LinkLevelCount =
 870                         (uint8_t)dpm_table->pcie_speed_table.count;
 871         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 872                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 873
 874         return 0;
 875 }
 876
 877 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 878 {
 879         uint32_t reference_clock, tmp;
 880         struct cgs_display_info info = {0};
 881         struct cgs_mode_info mode_info;
 882
 883         info.mode_info = &mode_info;
 884
 885         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 886
 887         if (tmp)
 888                 return TCLK;
 889
 890         cgs_get_active_displays_info(hwmgr->device, &info);
 891         reference_clock = mode_info.ref_clock;
 892
 893         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 894
 895         if (0 != tmp)
 896                 return reference_clock / 4;
 897
 898         return reference_clock;
 899 }
 900
 901 /**
 902 * Calculates the SCLK dividers using the provided engine clock
 903 *
 904 * @param    hwmgr  the address of the hardware manager
 905 * @param    clock  the engine clock to use to populate the structure
 906 * @param    sclk   the SMC SCLK structure to be populated
 907 */
 908 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 909                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 910 {
 911         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 912         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 913         struct pp_atomctrl_clock_dividers_ai dividers;
 914
 915         uint32_t ref_clock;
 916         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 917         uint8_t i;
 918         int result;
 919         uint64_t temp;
 920
 921         sclk_setting->SclkFrequency = clock;
 922         /* get the engine clock dividers for this clock value */
 923         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 924         if (result == 0) {
 925                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 926                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 927                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 928                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 929                 sclk_setting->Sclk_slew_rate = 0x400;
 930                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 931                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 932                 sclk_setting->SSc_En = dividers.ucSscEnable;
 933                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 934                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 935                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 936                 return result;
 937         }
 938
 939         ref_clock = polaris10_get_xclk(hwmgr);
 940
 941         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 942                 if (clock > data->range_table[i].trans_lower_frequency
 943                 && clock <= data->range_table[i].trans_upper_frequency) {
 944                         sclk_setting->PllRange = i;
 945                         break;
 946                 }
 947         }
 948
 949         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 950         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 951         temp <<= 0x10;
 952         do_div(temp, ref_clock);
 953         sclk_setting->Fcw_frac = temp & 0xffff;
 954
 955         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 956         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 957         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 958
 959         ss_target_percent = 2; /*  Hardcode 2% for now. */
 960         sclk_setting->SSc_En = 0;
 961         if (ss_target_percent) {
 962                 sclk_setting->SSc_En = 1;
 963                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 964                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 965                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 966                 temp <<= 0x10;
 967                 do_div(temp, ref_clock);
 968                 sclk_setting->Fcw1_frac = temp & 0xffff;
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 975                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
 976                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
 977 {
 978         uint32_t i;
 979         uint16_t vddci;
 980         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 981
 982         *voltage = *mvdd = 0;
 983
 984         /* clock - voltage dependency table is empty table */
 985         if (dep_table->count == 0)
 986                 return -EINVAL;
 987
 988         for (i = 0; i < dep_table->count; i++) {
 989                 /* find first sclk bigger than request */
 990                 if (dep_table->entries[i].clk >= clock) {
 991                         *voltage |= (dep_table->entries[i].vddc *
 992                                         VOLTAGE_SCALE) << VDDC_SHIFT;
 993                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
 994                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 995                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 996                         else if (dep_table->entries[i].vddci)
 997                                 *voltage |= (dep_table->entries[i].vddci *
 998                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 999                         else {
1000                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1001                                                 (dep_table->entries[i].vddc -
1002                                                                 (uint16_t)data->vddc_vddci_delta));
1003                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1004                         }
1005
1006                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1007                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1008                                         VOLTAGE_SCALE;
1009                         else if (dep_table->entries[i].mvdd)
1010                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1011                                         VOLTAGE_SCALE;
1012
1013                         *voltage |= 1 << PHASES_SHIFT;
1014                         return 0;
1015                 }
1016         }
1017
1018         /* sclk is bigger than max sclk in the dependence table */
1019         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1020
1021         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1022                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1023                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1024         else if (dep_table->entries[i-1].vddci) {
1025                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1026                                 (dep_table->entries[i].vddc -
1027                                                 (uint16_t)data->vddc_vddci_delta));
1028                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1029         }
1030
1031         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1032                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1033         else if (dep_table->entries[i].mvdd)
1034                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1035
1036         return 0;
1037 }
1038
1039 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1040 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1041   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1042   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1043   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1044   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1045   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1046   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1047   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1048
1049 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1050 {
1051         uint32_t i, ref_clk;
1052         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1053         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1054         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1055
1056         ref_clk = polaris10_get_xclk(hwmgr);
1057
1058         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1059                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1060                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1061                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1062                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1063
1064                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1065                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1066
1067                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1068                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1069                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1070                 }
1071                 return;
1072         }
1073
1074         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1075
1076                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1077                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1078
1079                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1080                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1081                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1082
1083                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1084                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1085
1086                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1087                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1088                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1089         }
1090 }
1091
1092 /**
1093 * Populates single SMC SCLK structure using the provided engine clock
1094 *
1095 * @param    hwmgr      the address of the hardware manager
1096 * @param    clock the engine clock to use to populate the structure
1097 * @param    sclk        the SMC SCLK structure to be populated
1098 */
1099
1100 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1101                 uint32_t clock, uint16_t sclk_al_threshold,
1102                 struct SMU74_Discrete_GraphicsLevel *level)
1103 {
1104         int result, i, temp;
1105         /* PP_Clocks minClocks; */
1106         uint32_t mvdd;
1107         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1108         struct phm_ppt_v1_information *table_info =
1109                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1110         SMU_SclkSetting curr_sclk_setting = { 0 };
1111
1112         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1113
1114         /* populate graphics levels */
1115         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1116                         table_info->vdd_dep_on_sclk, clock,
1117                         &level->MinVoltage, &mvdd);
1118
1119         PP_ASSERT_WITH_CODE((0 == result),
1120                         "can not find VDDC voltage value for "
1121                         "VDDC engine clock dependency table",
1122                         return result);
1123         level->ActivityLevel = sclk_al_threshold;
1124
1125         level->CcPwrDynRm = 0;
1126         level->CcPwrDynRm1 = 0;
1127         level->EnabledForActivity = 0;
1128         level->EnabledForThrottle = 1;
1129         level->UpHyst = 10;
1130         level->DownHyst = 0;
1131         level->VoltageDownHyst = 0;
1132         level->PowerThrottle = 0;
1133
1134         /*
1135         * TODO: get minimum clocks from dal configaration
1136         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1137         */
1138         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1139
1140         /* get level->DeepSleepDivId
1141         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1142                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1143         */
1144         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1145         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1146                 temp = clock >> i;
1147
1148                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1149                         break;
1150         }
1151
1152         level->DeepSleepDivId = i;
1153
1154         /* Default to slow, highest DPM level will be
1155          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1156          */
1157         if (data->update_up_hyst)
1158                 level->UpHyst = (uint8_t)data->up_hyst;
1159         if (data->update_down_hyst)
1160                 level->DownHyst = (uint8_t)data->down_hyst;
1161
1162         level->SclkSetting = curr_sclk_setting;
1163
1164         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1165         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1166         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1167         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1168         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1169         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1170         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1171         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1172         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1173         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1174         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1175         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1176         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1177         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1178         return 0;
1179 }
1180
1181 /**
1182 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1183 *
1184 * @param    hwmgr      the address of the hardware manager
1185 */
1186 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1187 {
1188         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1189         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1190         struct phm_ppt_v1_information *table_info =
1191                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1192         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1193         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1194         int result = 0;
1195         uint32_t array = data->dpm_table_start +
1196                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1197         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1198                         SMU74_MAX_LEVELS_GRAPHICS;
1199         struct SMU74_Discrete_GraphicsLevel *levels =
1200                         data->smc_state_table.GraphicsLevel;
1201         uint32_t i, max_entry;
1202         uint8_t hightest_pcie_level_enabled = 0,
1203                 lowest_pcie_level_enabled = 0,
1204                 mid_pcie_level_enabled = 0,
1205                 count = 0;
1206
1207         polaris10_get_sclk_range_table(hwmgr);
1208
1209         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1210
1211                 result = polaris10_populate_single_graphic_level(hwmgr,
1212                                 dpm_table->sclk_table.dpm_levels[i].value,
1213                                 (uint16_t)data->activity_target[i],
1214                                 &(data->smc_state_table.GraphicsLevel[i]));
1215                 if (result)
1216                         return result;
1217
1218                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1219                 if (i > 1)
1220                         levels[i].DeepSleepDivId = 0;
1221         }
1222         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1223                                         PHM_PlatformCaps_SPLLShutdownSupport))
1224                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1225
1226         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1227         data->smc_state_table.GraphicsDpmLevelCount =
1228                         (uint8_t)dpm_table->sclk_table.count;
1229         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1230                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1231
1232
1233         if (pcie_table != NULL) {
1234                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1235                                 "There must be 1 or more PCIE levels defined in PPTable.",
1236                                 return -EINVAL);
1237                 max_entry = pcie_entry_cnt - 1;
1238                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1239                         levels[i].pcieDpmLevel =
1240                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1241         } else {
1242                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1243                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1244                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1245                         hightest_pcie_level_enabled++;
1246
1247                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1248                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1249                                                 (1 << lowest_pcie_level_enabled)) == 0))
1250                         lowest_pcie_level_enabled++;
1251
1252                 while ((count < hightest_pcie_level_enabled) &&
1253                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1254                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1255                         count++;
1256
1257                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1258                                 hightest_pcie_level_enabled ?
1259                                                 (lowest_pcie_level_enabled + 1 + count) :
1260                                                 hightest_pcie_level_enabled;
1261
1262                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1263                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1264                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1265
1266                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1267                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1268
1269                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1270                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1271         }
1272         /* level count will send to smc once at init smc table and never change */
1273         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1274                         (uint32_t)array_size, data->sram_end);
1275
1276         return result;
1277 }
1278
1279 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1280                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1281 {
1282         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1283         struct phm_ppt_v1_information *table_info =
1284                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1285         int result = 0;
1286         struct cgs_display_info info = {0, 0, NULL};
1287
1288         cgs_get_active_displays_info(hwmgr->device, &info);
1289
1290         if (table_info->vdd_dep_on_mclk) {
1291                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1292                                 table_info->vdd_dep_on_mclk, clock,
1293                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1294                 PP_ASSERT_WITH_CODE((0 == result),
1295                                 "can not find MinVddc voltage value from memory "
1296                                 "VDDC voltage dependency table", return result);
1297         }
1298
1299         mem_level->MclkFrequency = clock;
1300         mem_level->EnabledForThrottle = 1;
1301         mem_level->EnabledForActivity = 0;
1302         mem_level->UpHyst = 0;
1303         mem_level->DownHyst = 100;
1304         mem_level->VoltageDownHyst = 0;
1305         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1306         mem_level->StutterEnable = false;
1307         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1308
1309         data->display_timing.num_existing_displays = info.display_count;
1310
1311         if ((data->mclk_stutter_mode_threshold) &&
1312                 (clock <= data->mclk_stutter_mode_threshold) &&
1313                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1314                                 STUTTER_ENABLE) & 0x1))
1315                 mem_level->StutterEnable = true;
1316
1317         if (!result) {
1318                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1319                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1320                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1321                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1322         }
1323         return result;
1324 }
1325
1326 /**
1327 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1328 *
1329 * @param    hwmgr      the address of the hardware manager
1330 */
1331 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1332 {
1333         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1334         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1335         int result;
1336         /* populate MCLK dpm table to SMU7 */
1337         uint32_t array = data->dpm_table_start +
1338                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1339         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1340                         SMU74_MAX_LEVELS_MEMORY;
1341         struct SMU74_Discrete_MemoryLevel *levels =
1342                         data->smc_state_table.MemoryLevel;
1343         uint32_t i;
1344
1345         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1346                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1347                                 "can not populate memory level as memory clock is zero",
1348                                 return -EINVAL);
1349                 result = polaris10_populate_single_memory_level(hwmgr,
1350                                 dpm_table->mclk_table.dpm_levels[i].value,
1351                                 &levels[i]);
1352                 if (i == dpm_table->mclk_table.count - 1) {
1353                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1354                         levels[i].EnabledForActivity = 1;
1355                 }
1356                 if (result)
1357                         return result;
1358         }
1359
1360         /* in order to prevent MC activity from stutter mode to push DPM up.
1361          * the UVD change complements this by putting the MCLK in
1362          * a higher state by default such that we are not effected by
1363          * up threshold or and MCLK DPM latency.
1364          */
1365         levels[0].ActivityLevel = 0x1f;
1366         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1367
1368         data->smc_state_table.MemoryDpmLevelCount =
1369                         (uint8_t)dpm_table->mclk_table.count;
1370         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1371                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1372
1373         /* level count will send to smc once at init smc table and never change */
1374         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1375                         (uint32_t)array_size, data->sram_end);
1376
1377         return result;
1378 }
1379
1380 /**
1381 * Populates the SMC MVDD structure using the provided memory clock.
1382 *
1383 * @param    hwmgr      the address of the hardware manager
1384 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1385 * @param    voltage     the SMC VOLTAGE structure to be populated
1386 */
1387 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1388                 uint32_t mclk, SMIO_Pattern *smio_pat)
1389 {
1390         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1391         struct phm_ppt_v1_information *table_info =
1392                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1393         uint32_t i = 0;
1394
1395         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1396                 /* find mvdd value which clock is more than request */
1397                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1398                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1399                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1400                                 break;
1401                         }
1402                 }
1403                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1404                                 "MVDD Voltage is outside the supported range.",
1405                                 return -EINVAL);
1406         } else
1407                 return -EINVAL;
1408
1409         return 0;
1410 }
1411
1412 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1413                 SMU74_Discrete_DpmTable *table)
1414 {
1415         int result = 0;
1416         uint32_t sclk_frequency;
1417         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1418         struct phm_ppt_v1_information *table_info =
1419                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1420         SMIO_Pattern vol_level;
1421         uint32_t mvdd;
1422         uint16_t us_mvdd;
1423
1424         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1425
1426         if (!data->sclk_dpm_key_disabled) {
1427                 /* Get MinVoltage and Frequency from DPM0,
1428                  * already converted to SMC_UL */
1429                 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1430                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1431                                 table_info->vdd_dep_on_sclk,
1432                                 table->ACPILevel.SclkFrequency,
1433                                 &table->ACPILevel.MinVoltage, &mvdd);
1434                 PP_ASSERT_WITH_CODE((0 == result),
1435                                 "Cannot find ACPI VDDC voltage value "
1436                                 "in Clock Dependency Table", );
1437         } else {
1438                 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1439                 table->ACPILevel.MinVoltage =
1440                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1441         }
1442
1443         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1444         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1445
1446         table->ACPILevel.DeepSleepDivId = 0;
1447         table->ACPILevel.CcPwrDynRm = 0;
1448         table->ACPILevel.CcPwrDynRm1 = 0;
1449
1450         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1451         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1452         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1453         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1454
1455         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1456         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1457         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1458         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1459         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1460         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1461         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1462         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1463         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1464         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1465
1466         if (!data->mclk_dpm_key_disabled) {
1467                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1468                 table->MemoryACPILevel.MclkFrequency =
1469                                 data->dpm_table.mclk_table.dpm_levels[0].value;
1470                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1471                                 table_info->vdd_dep_on_mclk,
1472                                 table->MemoryACPILevel.MclkFrequency,
1473                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
1474                 PP_ASSERT_WITH_CODE((0 == result),
1475                                 "Cannot find ACPI VDDCI voltage value "
1476                                 "in Clock Dependency Table",
1477                                 );
1478         } else {
1479                 table->MemoryACPILevel.MclkFrequency =
1480                                 data->vbios_boot_state.mclk_bootup_value;
1481                 table->MemoryACPILevel.MinVoltage =
1482                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1483         }
1484
1485         us_mvdd = 0;
1486         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1487                         (data->mclk_dpm_key_disabled))
1488                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1489         else {
1490                 if (!polaris10_populate_mvdd_value(hwmgr,
1491                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1492                                 &vol_level))
1493                         us_mvdd = vol_level.Voltage;
1494         }
1495
1496         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1497                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1498         else
1499                 table->MemoryACPILevel.MinMvdd = 0;
1500
1501         table->MemoryACPILevel.StutterEnable = false;
1502
1503         table->MemoryACPILevel.EnabledForThrottle = 0;
1504         table->MemoryACPILevel.EnabledForActivity = 0;
1505         table->MemoryACPILevel.UpHyst = 0;
1506         table->MemoryACPILevel.DownHyst = 100;
1507         table->MemoryACPILevel.VoltageDownHyst = 0;
1508         table->MemoryACPILevel.ActivityLevel =
1509                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1510
1511         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1512         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1513
1514         return result;
1515 }
1516
1517 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1518                 SMU74_Discrete_DpmTable *table)
1519 {
1520         int result = -EINVAL;
1521         uint8_t count;
1522         struct pp_atomctrl_clock_dividers_vi dividers;
1523         struct phm_ppt_v1_information *table_info =
1524                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1525         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1526                         table_info->mm_dep_table;
1527         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1528
1529         table->VceLevelCount = (uint8_t)(mm_table->count);
1530         table->VceBootLevel = 0;
1531
1532         for (count = 0; count < table->VceLevelCount; count++) {
1533                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1534                 table->VceLevel[count].MinVoltage = 0;
1535                 table->VceLevel[count].MinVoltage |=
1536                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1537                 table->VceLevel[count].MinVoltage |=
1538                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1539                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1540                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1541
1542                 /*retrieve divider value for VBIOS */
1543                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1544                                 table->VceLevel[count].Frequency, &dividers);
1545                 PP_ASSERT_WITH_CODE((0 == result),
1546                                 "can not find divide id for VCE engine clock",
1547                                 return result);
1548
1549                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1550
1551                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1552                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1553         }
1554         return result;
1555 }
1556
1557 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1558                 SMU74_Discrete_DpmTable *table)
1559 {
1560         int result = -EINVAL;
1561         uint8_t count;
1562         struct pp_atomctrl_clock_dividers_vi dividers;
1563         struct phm_ppt_v1_information *table_info =
1564                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1565         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1566                         table_info->mm_dep_table;
1567         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1568
1569         table->SamuBootLevel = 0;
1570         table->SamuLevelCount = (uint8_t)(mm_table->count);
1571
1572         for (count = 0; count < table->SamuLevelCount; count++) {
1573                 /* not sure whether we need evclk or not */
1574                 table->SamuLevel[count].MinVoltage = 0;
1575                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1576                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1577                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1578                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1579                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1580                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1581
1582                 /* retrieve divider value for VBIOS */
1583                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1584                                 table->SamuLevel[count].Frequency, &dividers);
1585                 PP_ASSERT_WITH_CODE((0 == result),
1586                                 "can not find divide id for samu clock", return result);
1587
1588                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1589
1590                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1591                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1592         }
1593         return result;
1594 }
1595
1596 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1597                 int32_t eng_clock, int32_t mem_clock,
1598                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1599 {
1600         uint32_t dram_timing;
1601         uint32_t dram_timing2;
1602         uint32_t burst_time;
1603         int result;
1604
1605         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1606                         eng_clock, mem_clock);
1607         PP_ASSERT_WITH_CODE(result == 0,
1608                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1609
1610         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1611         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1612         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1613
1614
1615         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1616         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1617         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1618
1619         return 0;
1620 }
1621
1622 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1623 {
1624         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1625         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1626         uint32_t i, j;
1627         int result = 0;
1628
1629         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1630                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1631                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1632                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1633                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1634                                         &arb_regs.entries[i][j]);
1635                         if (result == 0)
1636                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1637                         if (result != 0)
1638                                 return result;
1639                 }
1640         }
1641
1642         result = polaris10_copy_bytes_to_smc(
1643                         hwmgr->smumgr,
1644                         data->arb_table_start,
1645                         (uint8_t *)&arb_regs,
1646                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1647                         data->sram_end);
1648         return result;
1649 }
1650
1651 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1652                 struct SMU74_Discrete_DpmTable *table)
1653 {
1654         int result = -EINVAL;
1655         uint8_t count;
1656         struct pp_atomctrl_clock_dividers_vi dividers;
1657         struct phm_ppt_v1_information *table_info =
1658                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1659         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1660                         table_info->mm_dep_table;
1661         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1662
1663         table->UvdLevelCount = (uint8_t)(mm_table->count);
1664         table->UvdBootLevel = 0;
1665
1666         for (count = 0; count < table->UvdLevelCount; count++) {
1667                 table->UvdLevel[count].MinVoltage = 0;
1668                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1669                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1670                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1671                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1672                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1673                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1674                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1675
1676                 /* retrieve divider value for VBIOS */
1677                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1678                                 table->UvdLevel[count].VclkFrequency, &dividers);
1679                 PP_ASSERT_WITH_CODE((0 == result),
1680                                 "can not find divide id for Vclk clock", return result);
1681
1682                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1683
1684                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1685                                 table->UvdLevel[count].DclkFrequency, &dividers);
1686                 PP_ASSERT_WITH_CODE((0 == result),
1687                                 "can not find divide id for Dclk clock", return result);
1688
1689                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1690
1691                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1692                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1693                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1694
1695         }
1696         return result;
1697 }
1698
1699 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1700                 struct SMU74_Discrete_DpmTable *table)
1701 {
1702         int result = 0;
1703         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1704
1705         table->GraphicsBootLevel = 0;
1706         table->MemoryBootLevel = 0;
1707
1708         /* find boot level from dpm table */
1709         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1710                         data->vbios_boot_state.sclk_bootup_value,
1711                         (uint32_t *)&(table->GraphicsBootLevel));
1712
1713         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1714                         data->vbios_boot_state.mclk_bootup_value,
1715                         (uint32_t *)&(table->MemoryBootLevel));
1716
1717         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1718                         VOLTAGE_SCALE;
1719         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1720                         VOLTAGE_SCALE;
1721         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1722                         VOLTAGE_SCALE;
1723
1724         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1725         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1726         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1727
1728         return 0;
1729 }
1730
1731
1732 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1733 {
1734         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1735         struct phm_ppt_v1_information *table_info =
1736                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1737         uint8_t count, level;
1738
1739         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1740
1741         for (level = 0; level < count; level++) {
1742                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1743                                 data->vbios_boot_state.sclk_bootup_value) {
1744                         data->smc_state_table.GraphicsBootLevel = level;
1745                         break;
1746                 }
1747         }
1748
1749         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1750         for (level = 0; level < count; level++) {
1751                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1752                                 data->vbios_boot_state.mclk_bootup_value) {
1753                         data->smc_state_table.MemoryBootLevel = level;
1754                         break;
1755                 }
1756         }
1757
1758         return 0;
1759 }
1760
1761 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1762 {
1763         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1764         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1765         uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1766         struct phm_ppt_v1_information *table_info =
1767                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1768         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1769                         table_info->vdd_dep_on_sclk;
1770
1771         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1772
1773         /* Read SMU_Eefuse to read and calculate RO and determine
1774          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1775          */
1776         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1777                         ixSMU_EFUSE_0 + (67 * 4));
1778         efuse &= 0xFF000000;
1779         efuse = efuse >> 24;
1780
1781         if (hwmgr->chip_id == CHIP_POLARIS10) {
1782                 min = 1000;
1783                 max = 2300;
1784         } else {
1785                 min = 1100;
1786                 max = 2100;
1787         }
1788
1789         ro = efuse * (max -min)/255 + min;
1790
1791         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset
1792          * there is a little difference in calculating
1793          * volt_with_cks with windows */
1794         for (i = 0; i < sclk_table->count; i++) {
1795                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1796                                 sclk_table->entries[i].cks_enable << i;
1797                 if (hwmgr->chip_id == CHIP_POLARIS10) {
1798                         volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1799                                                 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1800                         volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \
1801                                         (252248000 - sclk_table->entries[i].clk/100 * 115764));
1802                 } else {
1803                         volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1804                                                 (2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000));
1805                         volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \
1806                                         (3422454 - sclk_table->entries[i].clk/100 * 18886376/10000));
1807                 }
1808
1809                 if (volt_without_cks >= volt_with_cks)
1810                         volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks +
1811                                         sclk_table->entries[i].cks_voffset) * 100 / 625);
1812
1813                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1814         }
1815
1816         data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1817         /* Populate CKS Lookup Table */
1818         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1819                 stretch_amount2 = 0;
1820         else if (stretch_amount == 3 || stretch_amount == 4)
1821                 stretch_amount2 = 1;
1822         else {
1823                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1824                                 PHM_PlatformCaps_ClockStretcher);
1825                 PP_ASSERT_WITH_CODE(false,
1826                                 "Stretch Amount in PPTable not supported\n",
1827                                 return -EINVAL);
1828         }
1829
1830         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1831         value &= 0xFFFFFFFE;
1832         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1833
1834         return 0;
1835 }
1836
1837 /**
1838 * Populates the SMC VRConfig field in DPM table.
1839 *
1840 * @param    hwmgr   the address of the hardware manager
1841 * @param    table   the SMC DPM table structure to be populated
1842 * @return   always 0
1843 */
1844 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1845                 struct SMU74_Discrete_DpmTable *table)
1846 {
1847         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1848         uint16_t config;
1849
1850         config = VR_MERGED_WITH_VDDC;
1851         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1852
1853         /* Set Vddc Voltage Controller */
1854         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1855                 config = VR_SVI2_PLANE_1;
1856                 table->VRConfig |= config;
1857         } else {
1858                 PP_ASSERT_WITH_CODE(false,
1859                                 "VDDC should be on SVI2 control in merged mode!",
1860                                 );
1861         }
1862         /* Set Vddci Voltage Controller */
1863         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1864                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1865                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1866         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1867                 config = VR_SMIO_PATTERN_1;
1868                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1869         } else {
1870                 config = VR_STATIC_VOLTAGE;
1871                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1872         }
1873         /* Set Mvdd Voltage Controller */
1874         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1875                 config = VR_SVI2_PLANE_2;
1876                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1877         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1878                 config = VR_SMIO_PATTERN_2;
1879                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1880         } else {
1881                 config = VR_STATIC_VOLTAGE;
1882                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1883         }
1884
1885         return 0;
1886 }
1887
1888
1889 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1890 {
1891         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1892         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1893         int result = 0;
1894         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1895         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1896         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1897         uint32_t tmp, i;
1898         struct pp_smumgr *smumgr = hwmgr->smumgr;
1899         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1900
1901         struct phm_ppt_v1_information *table_info =
1902                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1903         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1904                         table_info->vdd_dep_on_sclk;
1905
1906
1907         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1908                 return result;
1909
1910         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1911
1912         if (0 == result) {
1913                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1914                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1915                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1916                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1917                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1918                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1919                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1920                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1921                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1922                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1923                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1924                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1925                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1926                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1927                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1928                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1929                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1930                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1931                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1932                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1933                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1934                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1935                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1936                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1937
1938                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1939                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1940                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1941                 }
1942
1943                 result = polaris10_read_smc_sram_dword(smumgr,
1944                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1945                                 &tmp, data->sram_end);
1946
1947                 polaris10_copy_bytes_to_smc(smumgr,
1948                                         tmp,
1949                                         (uint8_t *)&AVFS_meanNsigma,
1950                                         sizeof(AVFS_meanNsigma_t),
1951                                         data->sram_end);
1952
1953                 result = polaris10_read_smc_sram_dword(smumgr,
1954                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1955                                 &tmp, data->sram_end);
1956                 polaris10_copy_bytes_to_smc(smumgr,
1957                                         tmp,
1958                                         (uint8_t *)&AVFS_SclkOffset,
1959                                         sizeof(AVFS_Sclk_Offset_t),
1960                                         data->sram_end);
1961
1962                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1963                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1964                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1965                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1966                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1967         }
1968         return result;
1969 }
1970
1971
1972 /**
1973 * Initializes the SMC table and uploads it
1974 *
1975 * @param    hwmgr  the address of the powerplay hardware manager.
1976 * @return   always 0
1977 */
1978 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1979 {
1980         int result;
1981         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1982         struct phm_ppt_v1_information *table_info =
1983                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1984         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1985         const struct polaris10_ulv_parm *ulv = &(data->ulv);
1986         uint8_t i;
1987         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1988         pp_atomctrl_clock_dividers_vi dividers;
1989
1990         result = polaris10_setup_default_dpm_tables(hwmgr);
1991         PP_ASSERT_WITH_CODE(0 == result,
1992                         "Failed to setup default DPM tables!", return result);
1993
1994         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
1995                 polaris10_populate_smc_voltage_tables(hwmgr, table);
1996
1997         table->SystemFlags = 0;
1998         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1999                         PHM_PlatformCaps_AutomaticDCTransition))
2000                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2001
2002         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2003                         PHM_PlatformCaps_StepVddc))
2004                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2005
2006         if (data->is_memory_gddr5)
2007                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2008
2009         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2010                 result = polaris10_populate_ulv_state(hwmgr, table);
2011                 PP_ASSERT_WITH_CODE(0 == result,
2012                                 "Failed to initialize ULV state!", return result);
2013                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2014                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2015         }
2016
2017         result = polaris10_populate_smc_link_level(hwmgr, table);
2018         PP_ASSERT_WITH_CODE(0 == result,
2019                         "Failed to initialize Link Level!", return result);
2020
2021         result = polaris10_populate_all_graphic_levels(hwmgr);
2022         PP_ASSERT_WITH_CODE(0 == result,
2023                         "Failed to initialize Graphics Level!", return result);
2024
2025         result = polaris10_populate_all_memory_levels(hwmgr);
2026         PP_ASSERT_WITH_CODE(0 == result,
2027                         "Failed to initialize Memory Level!", return result);
2028
2029         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2030         PP_ASSERT_WITH_CODE(0 == result,
2031                         "Failed to initialize ACPI Level!", return result);
2032
2033         result = polaris10_populate_smc_vce_level(hwmgr, table);
2034         PP_ASSERT_WITH_CODE(0 == result,
2035                         "Failed to initialize VCE Level!", return result);
2036
2037         result = polaris10_populate_smc_samu_level(hwmgr, table);
2038         PP_ASSERT_WITH_CODE(0 == result,
2039                         "Failed to initialize SAMU Level!", return result);
2040
2041         /* Since only the initial state is completely set up at this point
2042          * (the other states are just copies of the boot state) we only
2043          * need to populate the  ARB settings for the initial state.
2044          */
2045         result = polaris10_program_memory_timing_parameters(hwmgr);
2046         PP_ASSERT_WITH_CODE(0 == result,
2047                         "Failed to Write ARB settings for the initial state.", return result);
2048
2049         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2050         PP_ASSERT_WITH_CODE(0 == result,
2051                         "Failed to initialize UVD Level!", return result);
2052
2053         result = polaris10_populate_smc_boot_level(hwmgr, table);
2054         PP_ASSERT_WITH_CODE(0 == result,
2055                         "Failed to initialize Boot Level!", return result);
2056
2057         result = polaris10_populate_smc_initailial_state(hwmgr);
2058         PP_ASSERT_WITH_CODE(0 == result,
2059                         "Failed to initialize Boot State!", return result);
2060
2061         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2062         PP_ASSERT_WITH_CODE(0 == result,
2063                         "Failed to populate BAPM Parameters!", return result);
2064
2065         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2066                         PHM_PlatformCaps_ClockStretcher)) {
2067                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2068                 PP_ASSERT_WITH_CODE(0 == result,
2069                                 "Failed to populate Clock Stretcher Data Table!",
2070                                 return result);
2071         }
2072
2073         result = polaris10_populate_avfs_parameters(hwmgr);
2074         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2075
2076         table->CurrSclkPllRange = 0xff;
2077         table->GraphicsVoltageChangeEnable  = 1;
2078         table->GraphicsThermThrottleEnable  = 1;
2079         table->GraphicsInterval = 1;
2080         table->VoltageInterval  = 1;
2081         table->ThermalInterval  = 1;
2082         table->TemperatureLimitHigh =
2083                         table_info->cac_dtp_table->usTargetOperatingTemp *
2084                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2085         table->TemperatureLimitLow  =
2086                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2087                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2088         table->MemoryVoltageChangeEnable = 1;
2089         table->MemoryInterval = 1;
2090         table->VoltageResponseTime = 0;
2091         table->PhaseResponseTime = 0;
2092         table->MemoryThermThrottleEnable = 1;
2093         table->PCIeBootLinkLevel = 0;
2094         table->PCIeGenInterval = 1;
2095         table->VRConfig = 0;
2096
2097         result = polaris10_populate_vr_config(hwmgr, table);
2098         PP_ASSERT_WITH_CODE(0 == result,
2099                         "Failed to populate VRConfig setting!", return result);
2100
2101         table->ThermGpio = 17;
2102         table->SclkStepSize = 0x4000;
2103
2104         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2105                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2106         } else {
2107                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2108                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2109                                 PHM_PlatformCaps_RegulatorHot);
2110         }
2111
2112         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2113                         &gpio_pin)) {
2114                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2115                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2116                                 PHM_PlatformCaps_AutomaticDCTransition);
2117         } else {
2118                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2119                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2120                                 PHM_PlatformCaps_AutomaticDCTransition);
2121         }
2122
2123         /* Thermal Output GPIO */
2124         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2125                         &gpio_pin)) {
2126                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2127                                 PHM_PlatformCaps_ThermalOutGPIO);
2128
2129                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2130
2131                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2132                  * since VBIOS will program this register to set 'inactive state',
2133                  * driver can then determine 'active state' from this and
2134                  * program SMU with correct polarity
2135                  */
2136                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2137                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2138                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2139
2140                 /* if required, combine VRHot/PCC with thermal out GPIO */
2141                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2142                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2143                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2144         } else {
2145                 table->ThermOutGpio = 17;
2146                 table->ThermOutPolarity = 1;
2147                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2148         }
2149
2150         /* Populate BIF_SCLK levels into SMC DPM table */
2151         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2152                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2153                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2154
2155                 if (i == 0)
2156                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2157                 else
2158                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2159         }
2160
2161         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2162                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2163
2164         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2165         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2166         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2167         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2168         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2169         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2170         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2171         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2172         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2173         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2174
2175         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2176         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2177                         data->dpm_table_start +
2178                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2179                         (uint8_t *)&(table->SystemFlags),
2180                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2181                         data->sram_end);
2182         PP_ASSERT_WITH_CODE(0 == result,
2183                         "Failed to upload dpm data to SMC memory!", return result);
2184
2185         return 0;
2186 }
2187
2188 /**
2189 * Initialize the ARB DRAM timing table's index field.
2190 *
2191 * @param    hwmgr  the address of the powerplay hardware manager.
2192 * @return   always 0
2193 */
2194 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2195 {
2196         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2197         uint32_t tmp;
2198         int result;
2199
2200         /* This is a read-modify-write on the first byte of the ARB table.
2201          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2202          * is the field 'current'.
2203          * This solution is ugly, but we never write the whole table only
2204          * individual fields in it.
2205          * In reality this field should not be in that structure
2206          * but in a soft register.
2207          */
2208         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2209                         data->arb_table_start, &tmp, data->sram_end);
2210
2211         if (result)
2212                 return result;
2213
2214         tmp &= 0x00FFFFFF;
2215         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2216
2217         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2218                         data->arb_table_start, tmp, data->sram_end);
2219 }
2220
2221 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2222 {
2223         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2224                         PHM_PlatformCaps_RegulatorHot))
2225                 return smum_send_msg_to_smc(hwmgr->smumgr,
2226                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2227
2228         return 0;
2229 }
2230
2231 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2232 {
2233         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2234                         SCLK_PWRMGT_OFF, 0);
2235         return 0;
2236 }
2237
2238 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2239 {
2240         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2241         struct polaris10_ulv_parm *ulv = &(data->ulv);
2242
2243         if (ulv->ulv_supported)
2244                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2245
2246         return 0;
2247 }
2248
2249 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2250 {
2251         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2252                         PHM_PlatformCaps_SclkDeepSleep)) {
2253                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2254                         PP_ASSERT_WITH_CODE(false,
2255                                         "Attempt to enable Master Deep Sleep switch failed!",
2256                                         return -1);
2257         } else {
2258                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2259                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2260                         PP_ASSERT_WITH_CODE(false,
2261                                         "Attempt to disable Master Deep Sleep switch failed!",
2262                                         return -1);
2263                 }
2264         }
2265
2266         return 0;
2267 }
2268
2269 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2270 {
2271         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2272         uint32_t soft_register_value = 0;
2273         uint32_t handshake_disables_offset = data->soft_regs_start
2274                                 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2275
2276         /* enable SCLK dpm */
2277         if (!data->sclk_dpm_key_disabled)
2278                 PP_ASSERT_WITH_CODE(
2279                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2280                 "Failed to enable SCLK DPM during DPM Start Function!",
2281                 return -1);
2282
2283         /* enable MCLK dpm */
2284         if (0 == data->mclk_dpm_key_disabled) {
2285 /* Disable UVD - SMU handshake for MCLK. */
2286                 soft_register_value = cgs_read_ind_register(hwmgr->device,
2287                                         CGS_IND_REG__SMC, handshake_disables_offset);
2288                 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2289                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2290                                 handshake_disables_offset, soft_register_value);
2291
2292                 PP_ASSERT_WITH_CODE(
2293                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2294                                                 PPSMC_MSG_MCLKDPM_Enable)),
2295                                 "Failed to enable MCLK DPM during DPM Start Function!",
2296                                 return -1);
2297
2298                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2299
2300                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2301                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2302                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2303                 udelay(10);
2304                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2305                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2306                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2307         }
2308
2309         return 0;
2310 }
2311
2312 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2313 {
2314         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2315
2316         /*enable general power management */
2317
2318         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2319                         GLOBAL_PWRMGT_EN, 1);
2320
2321         /* enable sclk deep sleep */
2322
2323         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2324                         DYNAMIC_PM_EN, 1);
2325
2326         /* prepare for PCIE DPM */
2327
2328         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2329                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2330                                         VoltageChangeTimeout), 0x1000);
2331         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2332                         SWRST_COMMAND_1, RESETLC, 0x0);
2333 /*
2334         PP_ASSERT_WITH_CODE(
2335                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2336                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2337                         "Failed to enable voltage DPM during DPM Start Function!",
2338                         return -1);
2339 */
2340
2341         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2342                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2343                 return -1;
2344         }
2345
2346         /* enable PCIE dpm */
2347         if (0 == data->pcie_dpm_key_disabled) {
2348                 PP_ASSERT_WITH_CODE(
2349                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2350                                                 PPSMC_MSG_PCIeDPM_Enable)),
2351                                 "Failed to enable pcie DPM during DPM Start Function!",
2352                                 return -1);
2353         }
2354
2355         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2356                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2357                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2358                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2359                                 "Failed to enable AC DC GPIO Interrupt!",
2360                                 );
2361         }
2362
2363         return 0;
2364 }
2365
2366 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2367 {
2368         bool protection;
2369         enum DPM_EVENT_SRC src;
2370
2371         switch (sources) {
2372         default:
2373                 printk(KERN_ERR "Unknown throttling event sources.");
2374                 /* fall through */
2375         case 0:
2376                 protection = false;
2377                 /* src is unused */
2378                 break;
2379         case (1 << PHM_AutoThrottleSource_Thermal):
2380                 protection = true;
2381                 src = DPM_EVENT_SRC_DIGITAL;
2382                 break;
2383         case (1 << PHM_AutoThrottleSource_External):
2384                 protection = true;
2385                 src = DPM_EVENT_SRC_EXTERNAL;
2386                 break;
2387         case (1 << PHM_AutoThrottleSource_External) |
2388                         (1 << PHM_AutoThrottleSource_Thermal):
2389                 protection = true;
2390                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2391                 break;
2392         }
2393         /* Order matters - don't enable thermal protection for the wrong source. */
2394         if (protection) {
2395                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2396                                 DPM_EVENT_SRC, src);
2397                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2398                                 THERMAL_PROTECTION_DIS,
2399                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2400                                                 PHM_PlatformCaps_ThermalController));
2401         } else
2402                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2403                                 THERMAL_PROTECTION_DIS, 1);
2404 }
2405
2406 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2407                 PHM_AutoThrottleSource source)
2408 {
2409         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2410
2411         if (!(data->active_auto_throttle_sources & (1 << source))) {
2412                 data->active_auto_throttle_sources |= 1 << source;
2413                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2414         }
2415         return 0;
2416 }
2417
2418 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2419 {
2420         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2421 }
2422
2423 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2424 {
2425         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2426         data->pcie_performance_request = true;
2427
2428         return 0;
2429 }
2430
2431 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2432 {
2433         int tmp_result, result = 0;
2434         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2435         PP_ASSERT_WITH_CODE(result == 0,
2436                         "DPM is already running right now, no need to enable DPM!",
2437                         return 0);
2438
2439         if (polaris10_voltage_control(hwmgr)) {
2440                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2441                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2442                                 "Failed to enable voltage control!",
2443                                 result = tmp_result);
2444
2445                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2446                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2447                                 "Failed to contruct voltage tables!",
2448                                 result = tmp_result);
2449         }
2450
2451         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2452                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2453                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2454                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2455
2456         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2457                         PHM_PlatformCaps_ThermalController))
2458                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2459                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2460
2461         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2462         PP_ASSERT_WITH_CODE((0 == tmp_result),
2463                         "Failed to program static screen threshold parameters!",
2464                         result = tmp_result);
2465
2466         tmp_result = polaris10_enable_display_gap(hwmgr);
2467         PP_ASSERT_WITH_CODE((0 == tmp_result),
2468                         "Failed to enable display gap!", result = tmp_result);
2469
2470         tmp_result = polaris10_program_voting_clients(hwmgr);
2471         PP_ASSERT_WITH_CODE((0 == tmp_result),
2472                         "Failed to program voting clients!", result = tmp_result);
2473
2474         tmp_result = polaris10_process_firmware_header(hwmgr);
2475         PP_ASSERT_WITH_CODE((0 == tmp_result),
2476                         "Failed to process firmware header!", result = tmp_result);
2477
2478         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2479         PP_ASSERT_WITH_CODE((0 == tmp_result),
2480                         "Failed to initialize switch from ArbF0 to F1!",
2481                         result = tmp_result);
2482
2483         tmp_result = polaris10_init_smc_table(hwmgr);
2484         PP_ASSERT_WITH_CODE((0 == tmp_result),
2485                         "Failed to initialize SMC table!", result = tmp_result);
2486
2487         tmp_result = polaris10_init_arb_table_index(hwmgr);
2488         PP_ASSERT_WITH_CODE((0 == tmp_result),
2489                         "Failed to initialize ARB table index!", result = tmp_result);
2490
2491         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2492         PP_ASSERT_WITH_CODE((0 == tmp_result),
2493                         "Failed to populate PM fuses!", result = tmp_result);
2494
2495         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2496         PP_ASSERT_WITH_CODE((0 == tmp_result),
2497                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2498
2499         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2500
2501         tmp_result = polaris10_enable_sclk_control(hwmgr);
2502         PP_ASSERT_WITH_CODE((0 == tmp_result),
2503                         "Failed to enable SCLK control!", result = tmp_result);
2504
2505         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2506         PP_ASSERT_WITH_CODE((0 == tmp_result),
2507                         "Failed to enable voltage control!", result = tmp_result);
2508
2509         tmp_result = polaris10_enable_ulv(hwmgr);
2510         PP_ASSERT_WITH_CODE((0 == tmp_result),
2511                         "Failed to enable ULV!", result = tmp_result);
2512
2513         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2514         PP_ASSERT_WITH_CODE((0 == tmp_result),
2515                         "Failed to enable deep sleep master switch!", result = tmp_result);
2516
2517         tmp_result = polaris10_start_dpm(hwmgr);
2518         PP_ASSERT_WITH_CODE((0 == tmp_result),
2519                         "Failed to start DPM!", result = tmp_result);
2520
2521         tmp_result = polaris10_enable_smc_cac(hwmgr);
2522         PP_ASSERT_WITH_CODE((0 == tmp_result),
2523                         "Failed to enable SMC CAC!", result = tmp_result);
2524
2525         tmp_result = polaris10_enable_power_containment(hwmgr);
2526         PP_ASSERT_WITH_CODE((0 == tmp_result),
2527                         "Failed to enable power containment!", result = tmp_result);
2528
2529         tmp_result = polaris10_power_control_set_level(hwmgr);
2530         PP_ASSERT_WITH_CODE((0 == tmp_result),
2531                         "Failed to power control set level!", result = tmp_result);
2532
2533         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2534         PP_ASSERT_WITH_CODE((0 == tmp_result),
2535                         "Failed to enable thermal auto throttle!", result = tmp_result);
2536
2537         tmp_result = polaris10_pcie_performance_request(hwmgr);
2538         PP_ASSERT_WITH_CODE((0 == tmp_result),
2539                         "pcie performance request failed!", result = tmp_result);
2540
2541         return result;
2542 }
2543
2544 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2545 {
2546
2547         return 0;
2548 }
2549
2550 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2551 {
2552
2553         return 0;
2554 }
2555
2556 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2557 {
2558         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2559
2560         if (data->soft_pp_table) {
2561                 kfree(data->soft_pp_table);
2562                 data->soft_pp_table = NULL;
2563         }
2564
2565         return phm_hwmgr_backend_fini(hwmgr);
2566 }
2567
2568 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2569 {
2570         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2571
2572         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2573                         PHM_PlatformCaps_SclkDeepSleep);
2574
2575         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2576                 PHM_PlatformCaps_DynamicPatchPowerState);
2577
2578         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2579                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2580                                 PHM_PlatformCaps_EnableMVDDControl);
2581
2582         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2583                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2584                                 PHM_PlatformCaps_ControlVDDCI);
2585
2586         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2587                          PHM_PlatformCaps_TablelessHardwareInterface);
2588
2589         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2590                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2591
2592         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2593                         PHM_PlatformCaps_DynamicPowerManagement);
2594
2595         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2596                         PHM_PlatformCaps_UnTabledHardwareInterface);
2597
2598         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2599                         PHM_PlatformCaps_TablelessHardwareInterface);
2600
2601         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2602                                         PHM_PlatformCaps_SMC);
2603
2604         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2605                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2606
2607         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2608                                         PHM_PlatformCaps_DynamicUVDState);
2609
2610         /* power tune caps Assume disabled */
2611         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2612                                                 PHM_PlatformCaps_SQRamping);
2613         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2614                                                 PHM_PlatformCaps_DBRamping);
2615         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2616                                                 PHM_PlatformCaps_TDRamping);
2617         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2618                                                 PHM_PlatformCaps_TCPRamping);
2619
2620         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2621                                         PHM_PlatformCaps_PowerContainment);
2622         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2623                                                         PHM_PlatformCaps_CAC);
2624
2625         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2626                                                 PHM_PlatformCaps_RegulatorHot);
2627
2628         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2629                                                 PHM_PlatformCaps_AutomaticDCTransition);
2630
2631         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2632                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2633
2634         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2635                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2636
2637         if (hwmgr->chip_id == CHIP_POLARIS11)
2638                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2639                                         PHM_PlatformCaps_SPLLShutdownSupport);
2640         return 0;
2641 }
2642
2643 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2644 {
2645         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2646
2647         polaris10_initialize_power_tune_defaults(hwmgr);
2648
2649         data->pcie_gen_performance.max = PP_PCIEGen1;
2650         data->pcie_gen_performance.min = PP_PCIEGen3;
2651         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2652         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2653         data->pcie_lane_performance.max = 0;
2654         data->pcie_lane_performance.min = 16;
2655         data->pcie_lane_power_saving.max = 0;
2656         data->pcie_lane_power_saving.min = 16;
2657 }
2658
2659 /**
2660 * Get Leakage VDDC based on leakage ID.
2661 *
2662 * @param    hwmgr  the address of the powerplay hardware manager.
2663 * @return   always 0
2664 */
2665 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2666 {
2667         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2668         uint16_t vv_id;
2669         uint16_t vddc = 0;
2670         uint16_t i, j;
2671         uint32_t sclk = 0;
2672         struct phm_ppt_v1_information *table_info =
2673                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2674         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2675                         table_info->vdd_dep_on_sclk;
2676         int result;
2677
2678         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2679                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2680                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2681                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2682                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2683                                         PHM_PlatformCaps_ClockStretcher)) {
2684                                 for (j = 1; j < sclk_table->count; j++) {
2685                                         if (sclk_table->entries[j].clk == sclk &&
2686                                                         sclk_table->entries[j].cks_enable == 0) {
2687                                                 sclk += 5000;
2688                                                 break;
2689                                         }
2690                                 }
2691                         }
2692
2693
2694                         PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2695                                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2696                                                 "Error retrieving EVV voltage value!",
2697                                                 continue);
2698
2699
2700                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2701                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2702                                         "Invalid VDDC value", result = -EINVAL;);
2703
2704                         /* the voltage should not be zero nor equal to leakage ID */
2705                         if (vddc != 0 && vddc != vv_id) {
2706                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2707                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2708                                 data->vddc_leakage.count++;
2709                         }
2710                 }
2711         }
2712
2713         return 0;
2714 }
2715
2716 /**
2717  * Change virtual leakage voltage to actual value.
2718  *
2719  * @param     hwmgr  the address of the powerplay hardware manager.
2720  * @param     pointer to changing voltage
2721  * @param     pointer to leakage table
2722  */
2723 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2724                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2725 {
2726         uint32_t index;
2727
2728         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2729         for (index = 0; index < leakage_table->count; index++) {
2730                 /* if this voltage matches a leakage voltage ID */
2731                 /* patch with actual leakage voltage */
2732                 if (leakage_table->leakage_id[index] == *voltage) {
2733                         *voltage = leakage_table->actual_voltage[index];
2734                         break;
2735                 }
2736         }
2737
2738         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2739                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2740 }
2741
2742 /**
2743 * Patch voltage lookup table by EVV leakages.
2744 *
2745 * @param     hwmgr  the address of the powerplay hardware manager.
2746 * @param     pointer to voltage lookup table
2747 * @param     pointer to leakage table
2748 * @return     always 0
2749 */
2750 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2751                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2752                 struct polaris10_leakage_voltage *leakage_table)
2753 {
2754         uint32_t i;
2755
2756         for (i = 0; i < lookup_table->count; i++)
2757                 polaris10_patch_with_vdd_leakage(hwmgr,
2758                                 &lookup_table->entries[i].us_vdd, leakage_table);
2759
2760         return 0;
2761 }
2762
2763 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2764                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2765                 uint16_t *vddc)
2766 {
2767         struct phm_ppt_v1_information *table_info =
2768                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2769         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2770         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2771                         table_info->max_clock_voltage_on_dc.vddc;
2772         return 0;
2773 }
2774
2775 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2776                 struct pp_hwmgr *hwmgr)
2777 {
2778         uint8_t entryId;
2779         uint8_t voltageId;
2780         struct phm_ppt_v1_information *table_info =
2781                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2782
2783         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2784                         table_info->vdd_dep_on_sclk;
2785         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2786                         table_info->vdd_dep_on_mclk;
2787         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2788                         table_info->mm_dep_table;
2789
2790         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2791                 voltageId = sclk_table->entries[entryId].vddInd;
2792                 sclk_table->entries[entryId].vddc =
2793                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2794         }
2795
2796         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2797                 voltageId = mclk_table->entries[entryId].vddInd;
2798                 mclk_table->entries[entryId].vddc =
2799                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2800         }
2801
2802         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2803                 voltageId = mm_table->entries[entryId].vddcInd;
2804                 mm_table->entries[entryId].vddc =
2805                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2806         }
2807
2808         return 0;
2809
2810 }
2811
2812 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2813 {
2814         /* Need to determine if we need calculated voltage. */
2815         return 0;
2816 }
2817
2818 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2819 {
2820         /* Need to determine if we need calculated voltage from mm table. */
2821         return 0;
2822 }
2823
2824 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2825                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2826 {
2827         uint32_t table_size, i, j;
2828         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2829         table_size = lookup_table->count;
2830
2831         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2832                 "Lookup table is empty", return -EINVAL);
2833
2834         /* Sorting voltages */
2835         for (i = 0; i < table_size - 1; i++) {
2836                 for (j = i + 1; j > 0; j--) {
2837                         if (lookup_table->entries[j].us_vdd <
2838                                         lookup_table->entries[j - 1].us_vdd) {
2839                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2840                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2841                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2842                         }
2843                 }
2844         }
2845
2846         return 0;
2847 }
2848
2849 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2850 {
2851         int result = 0;
2852         int tmp_result;
2853         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2854         struct phm_ppt_v1_information *table_info =
2855                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2856
2857         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2858                         table_info->vddc_lookup_table, &(data->vddc_leakage));
2859         if (tmp_result)
2860                 result = tmp_result;
2861
2862         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2863                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2864         if (tmp_result)
2865                 result = tmp_result;
2866
2867         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2868         if (tmp_result)
2869                 result = tmp_result;
2870
2871         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2872         if (tmp_result)
2873                 result = tmp_result;
2874
2875         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2876         if (tmp_result)
2877                 result = tmp_result;
2878
2879         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2880         if (tmp_result)
2881                 result = tmp_result;
2882
2883         return result;
2884 }
2885
2886 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2887 {
2888         struct phm_ppt_v1_information *table_info =
2889                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2890
2891         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2892                                                 table_info->vdd_dep_on_sclk;
2893         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2894                                                 table_info->vdd_dep_on_mclk;
2895
2896         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2897                 "VDD dependency on SCLK table is missing.       \
2898                 This table is mandatory", return -EINVAL);
2899         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2900                 "VDD dependency on SCLK table has to have is missing.   \
2901                 This table is mandatory", return -EINVAL);
2902
2903         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2904                 "VDD dependency on MCLK table is missing.       \
2905                 This table is mandatory", return -EINVAL);
2906         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2907                 "VDD dependency on MCLK table has to have is missing.    \
2908                 This table is mandatory", return -EINVAL);
2909
2910         table_info->max_clock_voltage_on_ac.sclk =
2911                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2912         table_info->max_clock_voltage_on_ac.mclk =
2913                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2914         table_info->max_clock_voltage_on_ac.vddc =
2915                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2916         table_info->max_clock_voltage_on_ac.vddci =
2917                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2918
2919         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2920         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2921         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2922         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2923
2924         return 0;
2925 }
2926
2927 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2928 {
2929         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2930         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2931         uint32_t temp_reg;
2932         int result;
2933         struct phm_ppt_v1_information *table_info =
2934                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2935
2936         data->dll_default_on = false;
2937         data->sram_end = SMC_RAM_END;
2938         data->mclk_dpm0_activity_target = 0xa;
2939         data->disable_dpm_mask = 0xFF;
2940         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2941         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2942         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2943         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2944         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2945         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2946         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2947         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2948         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2949         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2950
2951         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2952         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2953         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2954         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2955         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2956         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2957         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2958         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
2959
2960         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2961
2962         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
2963
2964         /* need to set voltage control types before EVV patching */
2965         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2966         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2967         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2968
2969         data->enable_tdc_limit_feature = true;
2970         data->enable_pkg_pwr_tracking_feature = true;
2971         data->force_pcie_gen = PP_PCIEGenInvalid;
2972         data->mclk_stutter_mode_threshold = 40000;
2973
2974         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2975                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2976                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2977
2978         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2979                         PHM_PlatformCaps_EnableMVDDControl)) {
2980                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2981                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2982                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2983                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2984                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2985                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2986         }
2987
2988         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2989                         PHM_PlatformCaps_ControlVDDCI)) {
2990                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2991                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2992                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2993                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2994                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2995                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2996         }
2997
2998         if (table_info->cac_dtp_table->usClockStretchAmount != 0)
2999                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3000                                         PHM_PlatformCaps_ClockStretcher);
3001
3002         polaris10_set_features_platform_caps(hwmgr);
3003
3004         polaris10_init_dpm_defaults(hwmgr);
3005
3006         /* Get leakage voltage based on leakage ID. */
3007         result = polaris10_get_evv_voltages(hwmgr);
3008
3009         if (result) {
3010                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
3011                 return -1;
3012         }
3013
3014         polaris10_complete_dependency_tables(hwmgr);
3015         polaris10_set_private_data_based_on_pptable(hwmgr);
3016
3017         /* Initalize Dynamic State Adjustment Rule Settings */
3018         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3019
3020         if (0 == result) {
3021                 struct cgs_system_info sys_info = {0};
3022
3023                 data->is_tlu_enabled = 0;
3024
3025                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3026                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3027                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3028                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3029
3030
3031                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3032                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3033                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3034                         case 0:
3035                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3036                                 break;
3037                         case 1:
3038                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3039                                 break;
3040                         case 2:
3041                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3042                                 break;
3043                         case 3:
3044                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3045                                 break;
3046                         case 4:
3047                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3048                                 break;
3049                         default:
3050                                 PP_ASSERT_WITH_CODE(0,
3051                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3052                                 );
3053                                 break;
3054                         }
3055                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3056                 }
3057
3058                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3059                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3060                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3061                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3062
3063                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3064                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3065
3066                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3067
3068                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3069
3070                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3071                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3072
3073                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3074
3075                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3076                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3077
3078                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3079                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3080                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3081
3082                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3083                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3084
3085                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3086                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3087
3088                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3089                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3090
3091                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3092                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3093
3094                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3095                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3096
3097                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3098                                        table_info->cac_dtp_table->usOperatingTempStep;
3099
3100                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3101                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3102                 }
3103
3104                 sys_info.size = sizeof(struct cgs_system_info);
3105                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3106                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3107                 if (result)
3108                         data->pcie_gen_cap = 0x30007;
3109                 else
3110                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3111                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3112                         data->pcie_spc_cap = 20;
3113                 sys_info.size = sizeof(struct cgs_system_info);
3114                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3115                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3116                 if (result)
3117                         data->pcie_lane_cap = 0x2f0000;
3118                 else
3119                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3120
3121                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3122 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3123                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3124                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3125         } else {
3126                 /* Ignore return value in here, we are cleaning up a mess. */
3127                 polaris10_hwmgr_backend_fini(hwmgr);
3128         }
3129
3130         return 0;
3131 }
3132
3133 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3134 {
3135         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3136         uint32_t level, tmp;
3137
3138         if (!data->pcie_dpm_key_disabled) {
3139                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3140                         level = 0;
3141                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3142                         while (tmp >>= 1)
3143                                 level++;
3144
3145                         if (level)
3146                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3147                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3148                 }
3149         }
3150
3151         if (!data->sclk_dpm_key_disabled) {
3152                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3153                         level = 0;
3154                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3155                         while (tmp >>= 1)
3156                                 level++;
3157
3158                         if (level)
3159                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3160                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3161                                                 (1 << level));
3162                 }
3163         }
3164
3165         if (!data->mclk_dpm_key_disabled) {
3166                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3167                         level = 0;
3168                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3169                         while (tmp >>= 1)
3170                                 level++;
3171
3172                         if (level)
3173                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3174                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3175                                                 (1 << level));
3176                 }
3177         }
3178
3179         return 0;
3180 }
3181
3182 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3183 {
3184         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3185
3186         phm_apply_dal_min_voltage_request(hwmgr);
3187
3188         if (!data->sclk_dpm_key_disabled) {
3189                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3190                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3191                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3192                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3193         }
3194
3195         if (!data->mclk_dpm_key_disabled) {
3196                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3197                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3198                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3199                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3200         }
3201
3202         return 0;
3203 }
3204
3205 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3206 {
3207         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3208
3209         if (!polaris10_is_dpm_running(hwmgr))
3210                 return -EINVAL;
3211
3212         if (!data->pcie_dpm_key_disabled) {
3213                 smum_send_msg_to_smc(hwmgr->smumgr,
3214                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3215         }
3216
3217         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3218 }
3219
3220 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3221 {
3222         struct polaris10_hwmgr *data =
3223                         (struct polaris10_hwmgr *)(hwmgr->backend);
3224         uint32_t level;
3225
3226         if (!data->sclk_dpm_key_disabled)
3227                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3228                         level = phm_get_lowest_enabled_level(hwmgr,
3229                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3230                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3231                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3232                                                             (1 << level));
3233
3234         }
3235
3236         if (!data->mclk_dpm_key_disabled) {
3237                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3238                         level = phm_get_lowest_enabled_level(hwmgr,
3239                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3240                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3241                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3242                                                             (1 << level));
3243                 }
3244         }
3245
3246         if (!data->pcie_dpm_key_disabled) {
3247                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3248                         level = phm_get_lowest_enabled_level(hwmgr,
3249                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3250                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3251                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3252                                                             (level));
3253                 }
3254         }
3255
3256         return 0;
3257
3258 }
3259 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3260                                 enum amd_dpm_forced_level level)
3261 {
3262         int ret = 0;
3263
3264         switch (level) {
3265         case AMD_DPM_FORCED_LEVEL_HIGH:
3266                 ret = polaris10_force_dpm_highest(hwmgr);
3267                 if (ret)
3268                         return ret;
3269                 break;
3270         case AMD_DPM_FORCED_LEVEL_LOW:
3271                 ret = polaris10_force_dpm_lowest(hwmgr);
3272                 if (ret)
3273                         return ret;
3274                 break;
3275         case AMD_DPM_FORCED_LEVEL_AUTO:
3276                 ret = polaris10_unforce_dpm_levels(hwmgr);
3277                 if (ret)
3278                         return ret;
3279                 break;
3280         default:
3281                 break;
3282         }
3283
3284         hwmgr->dpm_level = level;
3285
3286         return ret;
3287 }
3288
3289 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3290 {
3291         return sizeof(struct polaris10_power_state);
3292 }
3293
3294
3295 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3296                                 struct pp_power_state *request_ps,
3297                         const struct pp_power_state *current_ps)
3298 {
3299
3300         struct polaris10_power_state *polaris10_ps =
3301                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3302         uint32_t sclk;
3303         uint32_t mclk;
3304         struct PP_Clocks minimum_clocks = {0};
3305         bool disable_mclk_switching;
3306         bool disable_mclk_switching_for_frame_lock;
3307         struct cgs_display_info info = {0};
3308         const struct phm_clock_and_voltage_limits *max_limits;
3309         uint32_t i;
3310         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3311         struct phm_ppt_v1_information *table_info =
3312                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3313         int32_t count;
3314         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3315
3316         data->battery_state = (PP_StateUILabel_Battery ==
3317                         request_ps->classification.ui_label);
3318
3319         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3320                                  "VI should always have 2 performance levels",
3321                                 );
3322
3323         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3324                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3325                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3326
3327         /* Cap clock DPM tables at DC MAX if it is in DC. */
3328         if (PP_PowerSource_DC == hwmgr->power_source) {
3329                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3330                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3331                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3332                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3333                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3334                 }
3335         }
3336
3337         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3338         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3339
3340         cgs_get_active_displays_info(hwmgr->device, &info);
3341
3342         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3343
3344         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3345
3346         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3347                         PHM_PlatformCaps_StablePState)) {
3348                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3349                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3350
3351                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3352                                 count >= 0; count--) {
3353                         if (stable_pstate_sclk >=
3354                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3355                                 stable_pstate_sclk =
3356                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3357                                 break;
3358                         }
3359                 }
3360
3361                 if (count < 0)
3362                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3363
3364                 stable_pstate_mclk = max_limits->mclk;
3365
3366                 minimum_clocks.engineClock = stable_pstate_sclk;
3367                 minimum_clocks.memoryClock = stable_pstate_mclk;
3368         }
3369
3370         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3371                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3372
3373         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3374                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3375
3376         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3377
3378         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3379                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3380                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3381                                 "Overdrive sclk exceeds limit",
3382                                 hwmgr->gfx_arbiter.sclk_over_drive =
3383                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3384
3385                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3386                         polaris10_ps->performance_levels[1].engine_clock =
3387                                         hwmgr->gfx_arbiter.sclk_over_drive;
3388         }
3389
3390         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3391                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3392                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3393                                 "Overdrive mclk exceeds limit",
3394                                 hwmgr->gfx_arbiter.mclk_over_drive =
3395                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3396
3397                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3398                         polaris10_ps->performance_levels[1].memory_clock =
3399                                         hwmgr->gfx_arbiter.mclk_over_drive;
3400         }
3401
3402         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3403                                     hwmgr->platform_descriptor.platformCaps,
3404                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3405
3406         disable_mclk_switching = (1 < info.display_count) ||
3407                                     disable_mclk_switching_for_frame_lock;
3408
3409         sclk = polaris10_ps->performance_levels[0].engine_clock;
3410         mclk = polaris10_ps->performance_levels[0].memory_clock;
3411
3412         if (disable_mclk_switching)
3413                 mclk = polaris10_ps->performance_levels
3414                 [polaris10_ps->performance_level_count - 1].memory_clock;
3415
3416         if (sclk < minimum_clocks.engineClock)
3417                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3418                                 max_limits->sclk : minimum_clocks.engineClock;
3419
3420         if (mclk < minimum_clocks.memoryClock)
3421                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3422                                 max_limits->mclk : minimum_clocks.memoryClock;
3423
3424         polaris10_ps->performance_levels[0].engine_clock = sclk;
3425         polaris10_ps->performance_levels[0].memory_clock = mclk;
3426
3427         polaris10_ps->performance_levels[1].engine_clock =
3428                 (polaris10_ps->performance_levels[1].engine_clock >=
3429                                 polaris10_ps->performance_levels[0].engine_clock) ?
3430                                                 polaris10_ps->performance_levels[1].engine_clock :
3431                                                 polaris10_ps->performance_levels[0].engine_clock;
3432
3433         if (disable_mclk_switching) {
3434                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3435                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3436
3437                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3438                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3439         } else {
3440                 if (polaris10_ps->performance_levels[1].memory_clock <
3441                                 polaris10_ps->performance_levels[0].memory_clock)
3442                         polaris10_ps->performance_levels[1].memory_clock =
3443                                         polaris10_ps->performance_levels[0].memory_clock;
3444         }
3445
3446         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3447                         PHM_PlatformCaps_StablePState)) {
3448                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3449                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3450                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3451                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3452                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3453                 }
3454         }
3455         return 0;
3456 }
3457
3458
3459 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3460 {
3461         struct pp_power_state  *ps;
3462         struct polaris10_power_state  *polaris10_ps;
3463
3464         if (hwmgr == NULL)
3465                 return -EINVAL;
3466
3467         ps = hwmgr->request_ps;
3468
3469         if (ps == NULL)
3470                 return -EINVAL;
3471
3472         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3473
3474         if (low)
3475                 return polaris10_ps->performance_levels[0].memory_clock;
3476         else
3477                 return polaris10_ps->performance_levels
3478                                 [polaris10_ps->performance_level_count-1].memory_clock;
3479 }
3480
3481 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3482 {
3483         struct pp_power_state  *ps;
3484         struct polaris10_power_state  *polaris10_ps;
3485
3486         if (hwmgr == NULL)
3487                 return -EINVAL;
3488
3489         ps = hwmgr->request_ps;
3490
3491         if (ps == NULL)
3492                 return -EINVAL;
3493
3494         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3495
3496         if (low)
3497                 return polaris10_ps->performance_levels[0].engine_clock;
3498         else
3499                 return polaris10_ps->performance_levels
3500                                 [polaris10_ps->performance_level_count-1].engine_clock;
3501 }
3502
3503 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3504                                         struct pp_hw_power_state *hw_ps)
3505 {
3506         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3507         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3508         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3509         uint16_t size;
3510         uint8_t frev, crev;
3511         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3512
3513         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3514          * We assume here that fw_info is unchanged if this call fails.
3515          */
3516         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3517                         hwmgr->device, index,
3518                         &size, &frev, &crev);
3519         if (!fw_info)
3520                 /* During a test, there is no firmware info table. */
3521                 return 0;
3522
3523         /* Patch the state. */
3524         data->vbios_boot_state.sclk_bootup_value =
3525                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3526         data->vbios_boot_state.mclk_bootup_value =
3527                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3528         data->vbios_boot_state.mvdd_bootup_value =
3529                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3530         data->vbios_boot_state.vddc_bootup_value =
3531                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3532         data->vbios_boot_state.vddci_bootup_value =
3533                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3534         data->vbios_boot_state.pcie_gen_bootup_value =
3535                         phm_get_current_pcie_speed(hwmgr);
3536
3537         data->vbios_boot_state.pcie_lane_bootup_value =
3538                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3539
3540         /* set boot power state */
3541         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3542         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3543         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3544         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3545
3546         return 0;
3547 }
3548
3549 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3550                 void *state, struct pp_power_state *power_state,
3551                 void *pp_table, uint32_t classification_flag)
3552 {
3553         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3554         struct polaris10_power_state  *polaris10_power_state =
3555                         (struct polaris10_power_state *)(&(power_state->hardware));
3556         struct polaris10_performance_level *performance_level;
3557         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3558         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3559                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3560         PPTable_Generic_SubTable_Header *sclk_dep_table =
3561                         (PPTable_Generic_SubTable_Header *)
3562                         (((unsigned long)powerplay_table) +
3563                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3564
3565         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3566                         (ATOM_Tonga_MCLK_Dependency_Table *)
3567                         (((unsigned long)powerplay_table) +
3568                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3569
3570         /* The following fields are not initialized here: id orderedList allStatesList */
3571         power_state->classification.ui_label =
3572                         (le16_to_cpu(state_entry->usClassification) &
3573                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3574                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3575         power_state->classification.flags = classification_flag;
3576         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3577
3578         power_state->classification.temporary_state = false;
3579         power_state->classification.to_be_deleted = false;
3580
3581         power_state->validation.disallowOnDC =
3582                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3583                                         ATOM_Tonga_DISALLOW_ON_DC));
3584
3585         power_state->pcie.lanes = 0;
3586
3587         power_state->display.disableFrameModulation = false;
3588         power_state->display.limitRefreshrate = false;
3589         power_state->display.enableVariBright =
3590                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3591                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3592
3593         power_state->validation.supportedPowerLevels = 0;
3594         power_state->uvd_clocks.VCLK = 0;
3595         power_state->uvd_clocks.DCLK = 0;
3596         power_state->temperatures.min = 0;
3597         power_state->temperatures.max = 0;
3598
3599         performance_level = &(polaris10_power_state->performance_levels
3600                         [polaris10_power_state->performance_level_count++]);
3601
3602         PP_ASSERT_WITH_CODE(
3603                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3604                         "Performance levels exceeds SMC limit!",
3605                         return -1);
3606
3607         PP_ASSERT_WITH_CODE(
3608                         (polaris10_power_state->performance_level_count <=
3609                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3610                         "Performance levels exceeds Driver limit!",
3611                         return -1);
3612
3613         /* Performance levels are arranged from low to high. */
3614         performance_level->memory_clock = mclk_dep_table->entries
3615                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3616         if (sclk_dep_table->ucRevId == 0)
3617                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3618                         [state_entry->ucEngineClockIndexLow].ulSclk;
3619         else if (sclk_dep_table->ucRevId == 1)
3620                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3621                         [state_entry->ucEngineClockIndexLow].ulSclk;
3622         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3623                         state_entry->ucPCIEGenLow);
3624         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3625                         state_entry->ucPCIELaneHigh);
3626
3627         performance_level = &(polaris10_power_state->performance_levels
3628                         [polaris10_power_state->performance_level_count++]);
3629         performance_level->memory_clock = mclk_dep_table->entries
3630                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3631
3632         if (sclk_dep_table->ucRevId == 0)
3633                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3634                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3635         else if (sclk_dep_table->ucRevId == 1)
3636                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3637                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3638
3639         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3640                         state_entry->ucPCIEGenHigh);
3641         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3642                         state_entry->ucPCIELaneHigh);
3643
3644         return 0;
3645 }
3646
3647 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3648                 unsigned long entry_index, struct pp_power_state *state)
3649 {
3650         int result;
3651         struct polaris10_power_state *ps;
3652         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3653         struct phm_ppt_v1_information *table_info =
3654                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3655         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3656                         table_info->vdd_dep_on_mclk;
3657
3658         state->hardware.magic = PHM_VIslands_Magic;
3659
3660         ps = (struct polaris10_power_state *)(&state->hardware);
3661
3662         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3663                         polaris10_get_pp_table_entry_callback_func);
3664
3665         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3666          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3667          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3668          */
3669         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3670                 if (dep_mclk_table->entries[0].clk !=
3671                                 data->vbios_boot_state.mclk_bootup_value)
3672                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3673                                         "does not match VBIOS boot MCLK level");
3674                 if (dep_mclk_table->entries[0].vddci !=
3675                                 data->vbios_boot_state.vddci_bootup_value)
3676                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3677                                         "does not match VBIOS boot VDDCI level");
3678         }
3679
3680         /* set DC compatible flag if this state supports DC */
3681         if (!state->validation.disallowOnDC)
3682                 ps->dc_compatible = true;
3683
3684         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3685                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3686
3687         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3688         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3689
3690         if (!result) {
3691                 uint32_t i;
3692
3693                 switch (state->classification.ui_label) {
3694                 case PP_StateUILabel_Performance:
3695                         data->use_pcie_performance_levels = true;
3696                         for (i = 0; i < ps->performance_level_count; i++) {
3697                                 if (data->pcie_gen_performance.max <
3698                                                 ps->performance_levels[i].pcie_gen)
3699                                         data->pcie_gen_performance.max =
3700                                                         ps->performance_levels[i].pcie_gen;
3701
3702                                 if (data->pcie_gen_performance.min >
3703                                                 ps->performance_levels[i].pcie_gen)
3704                                         data->pcie_gen_performance.min =
3705                                                         ps->performance_levels[i].pcie_gen;
3706
3707                                 if (data->pcie_lane_performance.max <
3708                                                 ps->performance_levels[i].pcie_lane)
3709                                         data->pcie_lane_performance.max =
3710                                                         ps->performance_levels[i].pcie_lane;
3711                                 if (data->pcie_lane_performance.min >
3712                                                 ps->performance_levels[i].pcie_lane)
3713                                         data->pcie_lane_performance.min =
3714                                                         ps->performance_levels[i].pcie_lane;
3715                         }
3716                         break;
3717                 case PP_StateUILabel_Battery:
3718                         data->use_pcie_power_saving_levels = true;
3719
3720                         for (i = 0; i < ps->performance_level_count; i++) {
3721                                 if (data->pcie_gen_power_saving.max <
3722                                                 ps->performance_levels[i].pcie_gen)
3723                                         data->pcie_gen_power_saving.max =
3724                                                         ps->performance_levels[i].pcie_gen;
3725
3726                                 if (data->pcie_gen_power_saving.min >
3727                                                 ps->performance_levels[i].pcie_gen)
3728                                         data->pcie_gen_power_saving.min =
3729                                                         ps->performance_levels[i].pcie_gen;
3730
3731                                 if (data->pcie_lane_power_saving.max <
3732                                                 ps->performance_levels[i].pcie_lane)
3733                                         data->pcie_lane_power_saving.max =
3734                                                         ps->performance_levels[i].pcie_lane;
3735
3736                                 if (data->pcie_lane_power_saving.min >
3737                                                 ps->performance_levels[i].pcie_lane)
3738                                         data->pcie_lane_power_saving.min =
3739                                                         ps->performance_levels[i].pcie_lane;
3740                         }
3741                         break;
3742                 default:
3743                         break;
3744                 }
3745         }
3746         return 0;
3747 }
3748
3749 static void
3750 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3751 {
3752         uint32_t sclk, mclk, activity_percent;
3753         uint32_t offset;
3754         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3755
3756         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3757
3758         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3759
3760         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3761
3762         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3763         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3764                         mclk / 100, sclk / 100);
3765
3766         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3767         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3768         activity_percent += 0x80;
3769         activity_percent >>= 8;
3770
3771         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3772
3773         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3774
3775         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3776 }
3777
3778 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3779 {
3780         const struct phm_set_power_state_input *states =
3781                         (const struct phm_set_power_state_input *)input;
3782         const struct polaris10_power_state *polaris10_ps =
3783                         cast_const_phw_polaris10_power_state(states->pnew_state);
3784         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3785         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3786         uint32_t sclk = polaris10_ps->performance_levels
3787                         [polaris10_ps->performance_level_count - 1].engine_clock;
3788         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3789         uint32_t mclk = polaris10_ps->performance_levels
3790                         [polaris10_ps->performance_level_count - 1].memory_clock;
3791         struct PP_Clocks min_clocks = {0};
3792         uint32_t i;
3793         struct cgs_display_info info = {0};
3794
3795         data->need_update_smu7_dpm_table = 0;
3796
3797         for (i = 0; i < sclk_table->count; i++) {
3798                 if (sclk == sclk_table->dpm_levels[i].value)
3799                         break;
3800         }
3801
3802         if (i >= sclk_table->count)
3803                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3804         else {
3805         /* TODO: Check SCLK in DAL's minimum clocks
3806          * in case DeepSleep divider update is required.
3807          */
3808                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3809                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3810                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3811                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3812         }
3813
3814         for (i = 0; i < mclk_table->count; i++) {
3815                 if (mclk == mclk_table->dpm_levels[i].value)
3816                         break;
3817         }
3818
3819         if (i >= mclk_table->count)
3820                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3821
3822         cgs_get_active_displays_info(hwmgr->device, &info);
3823
3824         if (data->display_timing.num_existing_displays != info.display_count)
3825                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3826
3827         return 0;
3828 }
3829
3830 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3831                 const struct polaris10_power_state *polaris10_ps)
3832 {
3833         uint32_t i;
3834         uint32_t sclk, max_sclk = 0;
3835         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3836         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3837
3838         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3839                 sclk = polaris10_ps->performance_levels[i].engine_clock;
3840                 if (max_sclk < sclk)
3841                         max_sclk = sclk;
3842         }
3843
3844         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3845                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3846                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3847                                         dpm_table->pcie_speed_table.dpm_levels
3848                                         [dpm_table->pcie_speed_table.count - 1].value :
3849                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3850         }
3851
3852         return 0;
3853 }
3854
3855 static int polaris10_request_link_speed_change_before_state_change(
3856                 struct pp_hwmgr *hwmgr, const void *input)
3857 {
3858         const struct phm_set_power_state_input *states =
3859                         (const struct phm_set_power_state_input *)input;
3860         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3861         const struct polaris10_power_state *polaris10_nps =
3862                         cast_const_phw_polaris10_power_state(states->pnew_state);
3863         const struct polaris10_power_state *polaris10_cps =
3864                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
3865
3866         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3867         uint16_t current_link_speed;
3868
3869         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3870                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3871         else
3872                 current_link_speed = data->force_pcie_gen;
3873
3874         data->force_pcie_gen = PP_PCIEGenInvalid;
3875         data->pspp_notify_required = false;
3876
3877         if (target_link_speed > current_link_speed) {
3878                 switch (target_link_speed) {
3879                 case PP_PCIEGen3:
3880                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3881                                 break;
3882                         data->force_pcie_gen = PP_PCIEGen2;
3883                         if (current_link_speed == PP_PCIEGen2)
3884                                 break;
3885                 case PP_PCIEGen2:
3886                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3887                                 break;
3888                 default:
3889                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3890                         break;
3891                 }
3892         } else {
3893                 if (target_link_speed < current_link_speed)
3894                         data->pspp_notify_required = true;
3895         }
3896
3897         return 0;
3898 }
3899
3900 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3901 {
3902         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3903
3904         if (0 == data->need_update_smu7_dpm_table)
3905                 return 0;
3906
3907         if ((0 == data->sclk_dpm_key_disabled) &&
3908                 (data->need_update_smu7_dpm_table &
3909                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3910                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3911                                 "Trying to freeze SCLK DPM when DPM is disabled",
3912                                 );
3913                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3914                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
3915                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3916                                 return -1);
3917         }
3918
3919         if ((0 == data->mclk_dpm_key_disabled) &&
3920                 (data->need_update_smu7_dpm_table &
3921                  DPMTABLE_OD_UPDATE_MCLK)) {
3922                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3923                                 "Trying to freeze MCLK DPM when DPM is disabled",
3924                                 );
3925                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3926                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
3927                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3928                                 return -1);
3929         }
3930
3931         return 0;
3932 }
3933
3934 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3935                 struct pp_hwmgr *hwmgr, const void *input)
3936 {
3937         int result = 0;
3938         const struct phm_set_power_state_input *states =
3939                         (const struct phm_set_power_state_input *)input;
3940         const struct polaris10_power_state *polaris10_ps =
3941                         cast_const_phw_polaris10_power_state(states->pnew_state);
3942         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3943         uint32_t sclk = polaris10_ps->performance_levels
3944                         [polaris10_ps->performance_level_count - 1].engine_clock;
3945         uint32_t mclk = polaris10_ps->performance_levels
3946                         [polaris10_ps->performance_level_count - 1].memory_clock;
3947         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3948
3949         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3950         uint32_t dpm_count, clock_percent;
3951         uint32_t i;
3952
3953         if (0 == data->need_update_smu7_dpm_table)
3954                 return 0;
3955
3956         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3957                 dpm_table->sclk_table.dpm_levels
3958                 [dpm_table->sclk_table.count - 1].value = sclk;
3959
3960                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3961                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3962                 /* Need to do calculation based on the golden DPM table
3963                  * as the Heatmap GPU Clock axis is also based on the default values
3964                  */
3965                         PP_ASSERT_WITH_CODE(
3966                                 (golden_dpm_table->sclk_table.dpm_levels
3967                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
3968                                 "Divide by 0!",
3969                                 return -1);
3970                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3971
3972                         for (i = dpm_count; i > 1; i--) {
3973                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3974                                         clock_percent =
3975                                               ((sclk
3976                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3977                                                 ) * 100)
3978                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3979
3980                                         dpm_table->sclk_table.dpm_levels[i].value =
3981                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
3982                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3983                                                                 clock_percent)/100;
3984
3985                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3986                                         clock_percent =
3987                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3988                                                 - sclk) * 100)
3989                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3990
3991                                         dpm_table->sclk_table.dpm_levels[i].value =
3992                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
3993                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3994                                                                         clock_percent) / 100;
3995                                 } else
3996                                         dpm_table->sclk_table.dpm_levels[i].value =
3997                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
3998                         }
3999                 }
4000         }
4001
4002         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4003                 dpm_table->mclk_table.dpm_levels
4004                         [dpm_table->mclk_table.count - 1].value = mclk;
4005
4006                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4007                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4008
4009                         PP_ASSERT_WITH_CODE(
4010                                         (golden_dpm_table->mclk_table.dpm_levels
4011                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4012                                         "Divide by 0!",
4013                                         return -1);
4014                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4015                         for (i = dpm_count; i > 1; i--) {
4016                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4017                                         clock_percent = ((mclk -
4018                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4019                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4020
4021                                         dpm_table->mclk_table.dpm_levels[i].value =
4022                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4023                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4024                                                         clock_percent) / 100;
4025
4026                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4027                                         clock_percent = (
4028                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4029                                         * 100)
4030                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4031
4032                                         dpm_table->mclk_table.dpm_levels[i].value =
4033                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4034                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4035                                                                         clock_percent) / 100;
4036                                 } else
4037                                         dpm_table->mclk_table.dpm_levels[i].value =
4038                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4039                         }
4040                 }
4041         }
4042
4043         if (data->need_update_smu7_dpm_table &
4044                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4045                 result = polaris10_populate_all_graphic_levels(hwmgr);
4046                 PP_ASSERT_WITH_CODE((0 == result),
4047                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4048                                 return result);
4049         }
4050
4051         if (data->need_update_smu7_dpm_table &
4052                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4053                 /*populate MCLK dpm table to SMU7 */
4054                 result = polaris10_populate_all_memory_levels(hwmgr);
4055                 PP_ASSERT_WITH_CODE((0 == result),
4056                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4057                                 return result);
4058         }
4059
4060         return result;
4061 }
4062
4063 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4064                           struct polaris10_single_dpm_table *dpm_table,
4065                         uint32_t low_limit, uint32_t high_limit)
4066 {
4067         uint32_t i;
4068
4069         for (i = 0; i < dpm_table->count; i++) {
4070                 if ((dpm_table->dpm_levels[i].value < low_limit)
4071                 || (dpm_table->dpm_levels[i].value > high_limit))
4072                         dpm_table->dpm_levels[i].enabled = false;
4073                 else
4074                         dpm_table->dpm_levels[i].enabled = true;
4075         }
4076
4077         return 0;
4078 }
4079
4080 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4081                 const struct polaris10_power_state *polaris10_ps)
4082 {
4083         int result = 0;
4084         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4085         uint32_t high_limit_count;
4086
4087         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4088                         "power state did not have any performance level",
4089                         return -1);
4090
4091         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4092
4093         polaris10_trim_single_dpm_states(hwmgr,
4094                         &(data->dpm_table.sclk_table),
4095                         polaris10_ps->performance_levels[0].engine_clock,
4096                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4097
4098         polaris10_trim_single_dpm_states(hwmgr,
4099                         &(data->dpm_table.mclk_table),
4100                         polaris10_ps->performance_levels[0].memory_clock,
4101                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4102
4103         return result;
4104 }
4105
4106 static int polaris10_generate_dpm_level_enable_mask(
4107                 struct pp_hwmgr *hwmgr, const void *input)
4108 {
4109         int result;
4110         const struct phm_set_power_state_input *states =
4111                         (const struct phm_set_power_state_input *)input;
4112         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4113         const struct polaris10_power_state *polaris10_ps =
4114                         cast_const_phw_polaris10_power_state(states->pnew_state);
4115
4116         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4117         if (result)
4118                 return result;
4119
4120         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4121                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4122         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4123                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4124         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4125                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4126
4127         return 0;
4128 }
4129
4130 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4131 {
4132         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4133                         PPSMC_MSG_UVDDPM_Enable :
4134                         PPSMC_MSG_UVDDPM_Disable);
4135 }
4136
4137 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4138 {
4139         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4140                         PPSMC_MSG_VCEDPM_Enable :
4141                         PPSMC_MSG_VCEDPM_Disable);
4142 }
4143
4144 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4145 {
4146         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4147                         PPSMC_MSG_SAMUDPM_Enable :
4148                         PPSMC_MSG_SAMUDPM_Disable);
4149 }
4150
4151 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4152 {
4153         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4154         uint32_t mm_boot_level_offset, mm_boot_level_value;
4155         struct phm_ppt_v1_information *table_info =
4156                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4157
4158         if (!bgate) {
4159                 data->smc_state_table.UvdBootLevel = 0;
4160                 if (table_info->mm_dep_table->count > 0)
4161                         data->smc_state_table.UvdBootLevel =
4162                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4163                 mm_boot_level_offset = data->dpm_table_start +
4164                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4165                 mm_boot_level_offset /= 4;
4166                 mm_boot_level_offset *= 4;
4167                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4168                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4169                 mm_boot_level_value &= 0x00FFFFFF;
4170                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4171                 cgs_write_ind_register(hwmgr->device,
4172                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4173
4174                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4175                                 PHM_PlatformCaps_UVDDPM) ||
4176                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4177                                 PHM_PlatformCaps_StablePState))
4178                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4179                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4180                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4181         }
4182
4183         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4184 }
4185
4186 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4187 {
4188         const struct phm_set_power_state_input *states =
4189                         (const struct phm_set_power_state_input *)input;
4190         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4191         const struct polaris10_power_state *polaris10_nps =
4192                         cast_const_phw_polaris10_power_state(states->pnew_state);
4193         const struct polaris10_power_state *polaris10_cps =
4194                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4195
4196         uint32_t mm_boot_level_offset, mm_boot_level_value;
4197         struct phm_ppt_v1_information *table_info =
4198                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4199
4200         if (polaris10_nps->vce_clks.evclk > 0 &&
4201         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4202
4203                 data->smc_state_table.VceBootLevel =
4204                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4205
4206                 mm_boot_level_offset = data->dpm_table_start +
4207                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4208                 mm_boot_level_offset /= 4;
4209                 mm_boot_level_offset *= 4;
4210                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4211                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4212                 mm_boot_level_value &= 0xFF00FFFF;
4213                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4214                 cgs_write_ind_register(hwmgr->device,
4215                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4216
4217                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4218                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4219                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4220                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4221
4222                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4223                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4224                                 polaris10_cps != NULL &&
4225                                 polaris10_cps->vce_clks.evclk > 0)
4226                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4227         }
4228
4229         return 0;
4230 }
4231
4232 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4233 {
4234         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4235         uint32_t mm_boot_level_offset, mm_boot_level_value;
4236
4237         if (!bgate) {
4238                 data->smc_state_table.SamuBootLevel = 0;
4239                 mm_boot_level_offset = data->dpm_table_start +
4240                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4241                 mm_boot_level_offset /= 4;
4242                 mm_boot_level_offset *= 4;
4243                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4244                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4245                 mm_boot_level_value &= 0xFFFFFF00;
4246                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4247                 cgs_write_ind_register(hwmgr->device,
4248                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4249
4250                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4251                                 PHM_PlatformCaps_StablePState))
4252                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4253                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4254                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4255         }
4256
4257         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4258 }
4259
4260 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4261 {
4262         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4263
4264         int result = 0;
4265         uint32_t low_sclk_interrupt_threshold = 0;
4266
4267         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4268                         PHM_PlatformCaps_SclkThrottleLowNotification)
4269                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4270                                 data->low_sclk_interrupt_threshold)) {
4271                 data->low_sclk_interrupt_threshold =
4272                                 hwmgr->gfx_arbiter.sclk_threshold;
4273                 low_sclk_interrupt_threshold =
4274                                 data->low_sclk_interrupt_threshold;
4275
4276                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4277
4278                 result = polaris10_copy_bytes_to_smc(
4279                                 hwmgr->smumgr,
4280                                 data->dpm_table_start +
4281                                 offsetof(SMU74_Discrete_DpmTable,
4282                                         LowSclkInterruptThreshold),
4283                                 (uint8_t *)&low_sclk_interrupt_threshold,
4284                                 sizeof(uint32_t),
4285                                 data->sram_end);
4286         }
4287
4288         return result;
4289 }
4290
4291 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4292 {
4293         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4294
4295         if (data->need_update_smu7_dpm_table &
4296                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4297                 return polaris10_program_memory_timing_parameters(hwmgr);
4298
4299         return 0;
4300 }
4301
4302 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4303 {
4304         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4305
4306         if (0 == data->need_update_smu7_dpm_table)
4307                 return 0;
4308
4309         if ((0 == data->sclk_dpm_key_disabled) &&
4310                 (data->need_update_smu7_dpm_table &
4311                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4312
4313                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4314                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4315                                 );
4316                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4317                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4318                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4319                         return -1);
4320         }
4321
4322         if ((0 == data->mclk_dpm_key_disabled) &&
4323                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4324
4325                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4326                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4327                                 );
4328                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4329                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4330                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4331                     return -1);
4332         }
4333
4334         data->need_update_smu7_dpm_table = 0;
4335
4336         return 0;
4337 }
4338
4339 static int polaris10_notify_link_speed_change_after_state_change(
4340                 struct pp_hwmgr *hwmgr, const void *input)
4341 {
4342         const struct phm_set_power_state_input *states =
4343                         (const struct phm_set_power_state_input *)input;
4344         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4345         const struct polaris10_power_state *polaris10_ps =
4346                         cast_const_phw_polaris10_power_state(states->pnew_state);
4347         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4348         uint8_t  request;
4349
4350         if (data->pspp_notify_required) {
4351                 if (target_link_speed == PP_PCIEGen3)
4352                         request = PCIE_PERF_REQ_GEN3;
4353                 else if (target_link_speed == PP_PCIEGen2)
4354                         request = PCIE_PERF_REQ_GEN2;
4355                 else
4356                         request = PCIE_PERF_REQ_GEN1;
4357
4358                 if (request == PCIE_PERF_REQ_GEN1 &&
4359                                 phm_get_current_pcie_speed(hwmgr) > 0)
4360                         return 0;
4361
4362                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4363                         if (PP_PCIEGen2 == target_link_speed)
4364                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4365                         else
4366                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4367                 }
4368         }
4369
4370         return 0;
4371 }
4372
4373 static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4374 {
4375         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4376
4377         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4378                 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4379         return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
4380 }
4381
4382 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4383 {
4384         int tmp_result, result = 0;
4385         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4386
4387         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4388         PP_ASSERT_WITH_CODE((0 == tmp_result),
4389                         "Failed to find DPM states clocks in DPM table!",
4390                         result = tmp_result);
4391
4392         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4393                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4394                 tmp_result =
4395                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4396                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4397                                 "Failed to request link speed change before state change!",
4398                                 result = tmp_result);
4399         }
4400
4401         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4402         PP_ASSERT_WITH_CODE((0 == tmp_result),
4403                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4404
4405         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4406         PP_ASSERT_WITH_CODE((0 == tmp_result),
4407                         "Failed to populate and upload SCLK MCLK DPM levels!",
4408                         result = tmp_result);
4409
4410         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4411         PP_ASSERT_WITH_CODE((0 == tmp_result),
4412                         "Failed to generate DPM level enabled mask!",
4413                         result = tmp_result);
4414
4415         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4416         PP_ASSERT_WITH_CODE((0 == tmp_result),
4417                         "Failed to update VCE DPM!",
4418                         result = tmp_result);
4419
4420         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4421         PP_ASSERT_WITH_CODE((0 == tmp_result),
4422                         "Failed to update SCLK threshold!",
4423                         result = tmp_result);
4424
4425         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4426         PP_ASSERT_WITH_CODE((0 == tmp_result),
4427                         "Failed to program memory timing parameters!",
4428                         result = tmp_result);
4429
4430         tmp_result = polaris10_notify_smc_display(hwmgr);
4431         PP_ASSERT_WITH_CODE((0 == tmp_result),
4432                         "Failed to notify smc display settings!",
4433                         result = tmp_result);
4434
4435         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4436         PP_ASSERT_WITH_CODE((0 == tmp_result),
4437                         "Failed to unfreeze SCLK MCLK DPM!",
4438                         result = tmp_result);
4439
4440         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4441         PP_ASSERT_WITH_CODE((0 == tmp_result),
4442                         "Failed to upload DPM level enabled mask!",
4443                         result = tmp_result);
4444
4445         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4446                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4447                 tmp_result =
4448                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4449                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4450                                 "Failed to notify link speed change after state change!",
4451                                 result = tmp_result);
4452         }
4453         data->apply_optimized_settings = false;
4454         return result;
4455 }
4456
4457 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4458 {
4459         hwmgr->thermal_controller.
4460         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4461
4462         if (phm_is_hw_access_blocked(hwmgr))
4463                 return 0;
4464
4465         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4466                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4467 }
4468
4469
4470 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4471 {
4472         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4473
4474         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4475 }
4476
4477 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4478 {
4479         uint32_t num_active_displays = 0;
4480         struct cgs_display_info info = {0};
4481         info.mode_info = NULL;
4482
4483         cgs_get_active_displays_info(hwmgr->device, &info);
4484
4485         num_active_displays = info.display_count;
4486
4487         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4488                 polaris10_notify_smc_display_change(hwmgr, false);
4489
4490         return 0;
4491 }
4492
4493 /**
4494 * Programs the display gap
4495 *
4496 * @param    hwmgr  the address of the powerplay hardware manager.
4497 * @return   always OK
4498 */
4499 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4500 {
4501         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4502         uint32_t num_active_displays = 0;
4503         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4504         uint32_t display_gap2;
4505         uint32_t pre_vbi_time_in_us;
4506         uint32_t frame_time_in_us;
4507         uint32_t ref_clock;
4508         uint32_t refresh_rate = 0;
4509         struct cgs_display_info info = {0};
4510         struct cgs_mode_info mode_info;
4511
4512         info.mode_info = &mode_info;
4513
4514         cgs_get_active_displays_info(hwmgr->device, &info);
4515         num_active_displays = info.display_count;
4516
4517         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4518         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4519
4520         ref_clock = mode_info.ref_clock;
4521         refresh_rate = mode_info.refresh_rate;
4522
4523         if (0 == refresh_rate)
4524                 refresh_rate = 60;
4525
4526         frame_time_in_us = 1000000 / refresh_rate;
4527
4528         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4529         data->frame_time_x2 = frame_time_in_us * 2 / 100;
4530
4531         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4532
4533         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4534
4535         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4536
4537         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4538
4539         return 0;
4540 }
4541
4542
4543 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4544 {
4545         return polaris10_program_display_gap(hwmgr);
4546 }
4547
4548 /**
4549 *  Set maximum target operating fan output RPM
4550 *
4551 * @param    hwmgr:  the address of the powerplay hardware manager.
4552 * @param    usMaxFanRpm:  max operating fan RPM value.
4553 * @return   The response that came from the SMC.
4554 */
4555 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4556 {
4557         hwmgr->thermal_controller.
4558         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4559
4560         if (phm_is_hw_access_blocked(hwmgr))
4561                 return 0;
4562
4563         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4564                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4565 }
4566
4567 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4568                                         const void *thermal_interrupt_info)
4569 {
4570         return 0;
4571 }
4572
4573 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4574 {
4575         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4576         bool is_update_required = false;
4577         struct cgs_display_info info = {0, 0, NULL};
4578
4579         cgs_get_active_displays_info(hwmgr->device, &info);
4580
4581         if (data->display_timing.num_existing_displays != info.display_count)
4582                 is_update_required = true;
4583 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4584         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4585                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4586                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4587                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4588                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4589                         is_update_required = true;
4590 */
4591         return is_update_required;
4592 }
4593
4594 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4595                                                            const struct polaris10_performance_level *pl2)
4596 {
4597         return ((pl1->memory_clock == pl2->memory_clock) &&
4598                   (pl1->engine_clock == pl2->engine_clock) &&
4599                   (pl1->pcie_gen == pl2->pcie_gen) &&
4600                   (pl1->pcie_lane == pl2->pcie_lane));
4601 }
4602
4603 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4604 {
4605         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4606         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4607         int i;
4608
4609         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4610                 return -EINVAL;
4611
4612         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4613         if (psa->performance_level_count != psb->performance_level_count) {
4614                 *equal = false;
4615                 return 0;
4616         }
4617
4618         for (i = 0; i < psa->performance_level_count; i++) {
4619                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4620                         /* If we have found even one performance level pair that is different the states are different. */
4621                         *equal = false;
4622                         return 0;
4623                 }
4624         }
4625
4626         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4627         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4628         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4629         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4630
4631         return 0;
4632 }
4633
4634 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4635 {
4636         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4637
4638         uint32_t vbios_version;
4639
4640         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4641
4642         phm_get_mc_microcode_version(hwmgr);
4643         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4644         /*  Full version of MC ucode has already been loaded. */
4645         if (vbios_version == 0) {
4646                 data->need_long_memory_training = false;
4647                 return 0;
4648         }
4649
4650         data->need_long_memory_training = false;
4651
4652 /*
4653  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4654         pfd = &tonga_mcmeFirmware;
4655         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4656                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4657                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4658                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4659 */
4660         return 0;
4661 }
4662
4663 /**
4664  * Read clock related registers.
4665  *
4666  * @param    hwmgr  the address of the powerplay hardware manager.
4667  * @return   always 0
4668  */
4669 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4670 {
4671         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4672
4673         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4674                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4675                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4676
4677         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4678                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4679                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4680
4681         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4682                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4683                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4684
4685         return 0;
4686 }
4687
4688 /**
4689  * Find out if memory is GDDR5.
4690  *
4691  * @param    hwmgr  the address of the powerplay hardware manager.
4692  * @return   always 0
4693  */
4694 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4695 {
4696         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4697         uint32_t temp;
4698
4699         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4700
4701         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4702                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4703                          MC_SEQ_MISC0_GDDR5_SHIFT));
4704
4705         return 0;
4706 }
4707
4708 /**
4709  * Enables Dynamic Power Management by SMC
4710  *
4711  * @param    hwmgr  the address of the powerplay hardware manager.
4712  * @return   always 0
4713  */
4714 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4715 {
4716         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4717                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4718
4719         return 0;
4720 }
4721
4722 /**
4723  * Initialize PowerGating States for different engines
4724  *
4725  * @param    hwmgr  the address of the powerplay hardware manager.
4726  * @return   always 0
4727  */
4728 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4729 {
4730         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4731
4732         data->uvd_power_gated = false;
4733         data->vce_power_gated = false;
4734         data->samu_power_gated = false;
4735
4736         return 0;
4737 }
4738
4739 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4740 {
4741         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4742         data->low_sclk_interrupt_threshold = 0;
4743
4744         return 0;
4745 }
4746
4747 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4748 {
4749         int tmp_result, result = 0;
4750
4751         polaris10_upload_mc_firmware(hwmgr);
4752
4753         tmp_result = polaris10_read_clock_registers(hwmgr);
4754         PP_ASSERT_WITH_CODE((0 == tmp_result),
4755                         "Failed to read clock registers!", result = tmp_result);
4756
4757         tmp_result = polaris10_get_memory_type(hwmgr);
4758         PP_ASSERT_WITH_CODE((0 == tmp_result),
4759                         "Failed to get memory type!", result = tmp_result);
4760
4761         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4762         PP_ASSERT_WITH_CODE((0 == tmp_result),
4763                         "Failed to enable ACPI power management!", result = tmp_result);
4764
4765         tmp_result = polaris10_init_power_gate_state(hwmgr);
4766         PP_ASSERT_WITH_CODE((0 == tmp_result),
4767                         "Failed to init power gate state!", result = tmp_result);
4768
4769         tmp_result = phm_get_mc_microcode_version(hwmgr);
4770         PP_ASSERT_WITH_CODE((0 == tmp_result),
4771                         "Failed to get MC microcode version!", result = tmp_result);
4772
4773         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4774         PP_ASSERT_WITH_CODE((0 == tmp_result),
4775                         "Failed to init sclk threshold!", result = tmp_result);
4776
4777         return result;
4778 }
4779
4780 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4781 {
4782         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4783
4784         if (!data->soft_pp_table) {
4785                 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4786                                               hwmgr->soft_pp_table_size,
4787                                               GFP_KERNEL);
4788                 if (!data->soft_pp_table)
4789                         return -ENOMEM;
4790         }
4791
4792         *table = (char *)&data->soft_pp_table;
4793
4794         return hwmgr->soft_pp_table_size;
4795 }
4796
4797 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4798 {
4799         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4800
4801         if (!data->soft_pp_table) {
4802                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4803                 if (!data->soft_pp_table)
4804                         return -ENOMEM;
4805         }
4806
4807         memcpy(data->soft_pp_table, buf, size);
4808
4809         hwmgr->soft_pp_table = data->soft_pp_table;
4810
4811         /* TODO: re-init powerplay to implement modified pptable */
4812
4813         return 0;
4814 }
4815
4816 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4817                 enum pp_clock_type type, uint32_t mask)
4818 {
4819         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4820
4821         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4822                 return -EINVAL;
4823
4824         switch (type) {
4825         case PP_SCLK:
4826                 if (!data->sclk_dpm_key_disabled)
4827                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4828                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4829                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4830                 break;
4831         case PP_MCLK:
4832                 if (!data->mclk_dpm_key_disabled)
4833                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4834                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4835                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4836                 break;
4837         case PP_PCIE:
4838         {
4839                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4840                 uint32_t level = 0;
4841
4842                 while (tmp >>= 1)
4843                         level++;
4844
4845                 if (!data->pcie_dpm_key_disabled)
4846                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4847                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4848                                         level);
4849                 break;
4850         }
4851         default:
4852                 break;
4853         }
4854
4855         return 0;
4856 }
4857
4858 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4859 {
4860         uint32_t speedCntl = 0;
4861
4862         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4863         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4864                         ixPCIE_LC_SPEED_CNTL);
4865         return((uint16_t)PHM_GET_FIELD(speedCntl,
4866                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4867 }
4868
4869 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4870                 enum pp_clock_type type, char *buf)
4871 {
4872         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4873         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4874         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4875         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4876         int i, now, size = 0;
4877         uint32_t clock, pcie_speed;
4878
4879         switch (type) {
4880         case PP_SCLK:
4881                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4882                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4883
4884                 for (i = 0; i < sclk_table->count; i++) {
4885                         if (clock > sclk_table->dpm_levels[i].value)
4886                                 continue;
4887                         break;
4888                 }
4889                 now = i;
4890
4891                 for (i = 0; i < sclk_table->count; i++)
4892                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4893                                         i, sclk_table->dpm_levels[i].value / 100,
4894                                         (i == now) ? "*" : "");
4895                 break;
4896         case PP_MCLK:
4897                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4898                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4899
4900                 for (i = 0; i < mclk_table->count; i++) {
4901                         if (clock > mclk_table->dpm_levels[i].value)
4902                                 continue;
4903                         break;
4904                 }
4905                 now = i;
4906
4907                 for (i = 0; i < mclk_table->count; i++)
4908                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4909                                         i, mclk_table->dpm_levels[i].value / 100,
4910                                         (i == now) ? "*" : "");
4911                 break;
4912         case PP_PCIE:
4913                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4914                 for (i = 0; i < pcie_table->count; i++) {
4915                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4916                                 continue;
4917                         break;
4918                 }
4919                 now = i;
4920
4921                 for (i = 0; i < pcie_table->count; i++)
4922                         size += sprintf(buf + size, "%d: %s %s\n", i,
4923                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4924                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4925                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4926                                         (i == now) ? "*" : "");
4927                 break;
4928         default:
4929                 break;
4930         }
4931         return size;
4932 }
4933
4934 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4935 {
4936         if (mode) {
4937                 /* stop auto-manage */
4938                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4939                                 PHM_PlatformCaps_MicrocodeFanControl))
4940                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4941                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4942         } else
4943                 /* restart auto-manage */
4944                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4945
4946         return 0;
4947 }
4948
4949 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4950 {
4951         if (hwmgr->fan_ctrl_is_in_default_mode)
4952                 return hwmgr->fan_ctrl_default_mode;
4953         else
4954                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4955                                 CG_FDO_CTRL2, FDO_PWM_MODE);
4956 }
4957
4958 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4959         .backend_init = &polaris10_hwmgr_backend_init,
4960         .backend_fini = &polaris10_hwmgr_backend_fini,
4961         .asic_setup = &polaris10_setup_asic_task,
4962         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4963         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4964         .force_dpm_level = &polaris10_force_dpm_level,
4965         .power_state_set = polaris10_set_power_state_tasks,
4966         .get_power_state_size = polaris10_get_power_state_size,
4967         .get_mclk = polaris10_dpm_get_mclk,
4968         .get_sclk = polaris10_dpm_get_sclk,
4969         .patch_boot_state = polaris10_dpm_patch_boot_state,
4970         .get_pp_table_entry = polaris10_get_pp_table_entry,
4971         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
4972         .print_current_perforce_level = polaris10_print_current_perforce_level,
4973         .powerdown_uvd = polaris10_phm_powerdown_uvd,
4974         .powergate_uvd = polaris10_phm_powergate_uvd,
4975         .powergate_vce = polaris10_phm_powergate_vce,
4976         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4977         .update_clock_gatings = polaris10_phm_update_clock_gatings,
4978         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4979         .display_config_changed = polaris10_display_configuration_changed_task,
4980         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4981         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4982         .get_temperature = polaris10_thermal_get_temperature,
4983         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4984         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4985         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4986         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4987         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4988         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4989         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4990         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4991         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4992         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4993         .check_states_equal = polaris10_check_states_equal,
4994         .set_fan_control_mode = polaris10_set_fan_control_mode,
4995         .get_fan_control_mode = polaris10_get_fan_control_mode,
4996         .get_pp_table = polaris10_get_pp_table,
4997         .set_pp_table = polaris10_set_pp_table,
4998         .force_clock_level = polaris10_force_clock_level,
4999         .print_clock_levels = polaris10_print_clock_levels,
5000         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5001 };
5002
5003 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5004 {
5005         struct polaris10_hwmgr  *data;
5006
5007         data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
5008         if (data == NULL)
5009                 return -ENOMEM;
5010
5011         hwmgr->backend = data;
5012         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5013         hwmgr->pptable_func = &tonga_pptable_funcs;
5014         pp_polaris10_thermal_initialize(hwmgr);
5015
5016         return 0;
5017 }