drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v13_0.h"
  35 #include "smu13_driver_if_v13_0_7.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "smu_v13_0_7_ppt.h"
  39 #include "smu_v13_0_7_pptable.h"
  40 #include "smu_v13_0_7_ppsmc.h"
  41 #include "nbio/nbio_4_3_0_offset.h"
  42 #include "nbio/nbio_4_3_0_sh_mask.h"
  43 #include "mp/mp_13_0_0_offset.h"
  44 #include "mp/mp_13_0_0_sh_mask.h"
  45
  46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
  47 #include "smu_cmn.h"
  48 #include "amdgpu_ras.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define FEATURE_MASK(feature) (1ULL << feature)
  63 #define SMC_DPM_FEATURE ( \
  64         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  65         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  66         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  67         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  68         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  70
  71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7   0x3b10028
  72
  73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE   0x4000
  74
  75 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
  76         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  77         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  78         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  79         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  80         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  81         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  82         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  83         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  84         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  85         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  86         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  87         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  88         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  89         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  90         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  91         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
  92         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
  93         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  94         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  95         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
  96         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  97         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  98         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
  99         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 100         MSG_MAP(ExitBaco,           PPSMC_MSG_ExitBaco,                            0),
 101         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 102         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 103         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 104         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 105         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 106         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 107         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 108         MSG_MAP(PowerUpVcn,                             PPSMC_MSG_PowerUpVcn,                  0),
 109         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 110         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 111         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 112         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 113         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 114         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 115         MSG_MAP(AllowIHHostInterrupt,           PPSMC_MSG_AllowIHHostInterrupt,       0),
 116         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,      0),
 117         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,       0),
 118         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,          0),
 119         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 120         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 121         MSG_MAP(Mode1Reset,             PPSMC_MSG_Mode1Reset,                  0),
 122         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         0),
 123         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 124         MSG_MAP(DFCstateControl,                PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
 125         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 126         MSG_MAP(AllowGpo,                       PPSMC_MSG_SetGpoAllow,           0),
 127         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 128 };
 129
 130 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
 131         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 132         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 133         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 134         CLK_MAP(FCLK,           PPCLK_FCLK),
 135         CLK_MAP(UCLK,           PPCLK_UCLK),
 136         CLK_MAP(MCLK,           PPCLK_UCLK),
 137         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 138         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 139         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 140         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 141 };
 142
 143 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
 144         FEA_MAP(FW_DATA_READ),
 145         FEA_MAP(DPM_GFXCLK),
 146         FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
 147         FEA_MAP(DPM_UCLK),
 148         FEA_MAP(DPM_FCLK),
 149         FEA_MAP(DPM_SOCCLK),
 150         FEA_MAP(DPM_MP0CLK),
 151         FEA_MAP(DPM_LINK),
 152         FEA_MAP(DPM_DCN),
 153         FEA_MAP(VMEMP_SCALING),
 154         FEA_MAP(VDDIO_MEM_SCALING),
 155         FEA_MAP(DS_GFXCLK),
 156         FEA_MAP(DS_SOCCLK),
 157         FEA_MAP(DS_FCLK),
 158         FEA_MAP(DS_LCLK),
 159         FEA_MAP(DS_DCFCLK),
 160         FEA_MAP(DS_UCLK),
 161         FEA_MAP(GFX_ULV),
 162         FEA_MAP(FW_DSTATE),
 163         FEA_MAP(GFXOFF),
 164         FEA_MAP(BACO),
 165         FEA_MAP(MM_DPM),
 166         FEA_MAP(SOC_MPCLK_DS),
 167         FEA_MAP(BACO_MPCLK_DS),
 168         FEA_MAP(THROTTLERS),
 169         FEA_MAP(SMARTSHIFT),
 170         FEA_MAP(GTHR),
 171         FEA_MAP(ACDC),
 172         FEA_MAP(VR0HOT),
 173         FEA_MAP(FW_CTF),
 174         FEA_MAP(FAN_CONTROL),
 175         FEA_MAP(GFX_DCS),
 176         FEA_MAP(GFX_READ_MARGIN),
 177         FEA_MAP(LED_DISPLAY),
 178         FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
 179         FEA_MAP(OUT_OF_BAND_MONITOR),
 180         FEA_MAP(OPTIMIZED_VMIN),
 181         FEA_MAP(GFX_IMU),
 182         FEA_MAP(BOOT_TIME_CAL),
 183         FEA_MAP(GFX_PCC_DFLL),
 184         FEA_MAP(SOC_CG),
 185         FEA_MAP(DF_CSTATE),
 186         FEA_MAP(GFX_EDC),
 187         FEA_MAP(BOOT_POWER_OPT),
 188         FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
 189         FEA_MAP(DS_VCN),
 190         FEA_MAP(BACO_CG),
 191         FEA_MAP(MEM_TEMP_READ),
 192         FEA_MAP(ATHUB_MMHUB_PG),
 193         FEA_MAP(SOC_PCC),
 194         [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 195         [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 196         [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
 197 };
 198
 199 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
 200         TAB_MAP(PPTABLE),
 201         TAB_MAP(WATERMARKS),
 202         TAB_MAP(AVFS_PSM_DEBUG),
 203         TAB_MAP(PMSTATUSLOG),
 204         TAB_MAP(SMU_METRICS),
 205         TAB_MAP(DRIVER_SMU_CONFIG),
 206         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 207         [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
 208 };
 209
 210 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 211         PWR_MAP(AC),
 212         PWR_MAP(DC),
 213 };
 214
 215 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 216         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 217         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 223         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D,             WORKLOAD_PPLIB_WINDOW_3D_BIT),
 224 };
 225
 226 static const uint8_t smu_v13_0_7_throttler_map[] = {
 227         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 228         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 229         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 230         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 231         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 232         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 233         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 234         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 235         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 236         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 237         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 238         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 239         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 240         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 241         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 242         [THROTTLER_GFX_APCC_PLUS_BIT]   = (SMU_THROTTLER_APCC_BIT),
 243         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 244 };
 245
 246 static int
 247 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
 248                                   uint32_t *feature_mask, uint32_t num)
 249 {
 250         struct amdgpu_device *adev = smu->adev;
 251
 252         if (num > 2)
 253                 return -EINVAL;
 254
 255         memset(feature_mask, 0, sizeof(uint32_t) * num);
 256
 257         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
 258
 259         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 260                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 261                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
 262                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
 263         }
 264
 265         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 266                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 267
 268         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
 269                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
 270                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
 271                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
 272                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
 273         }
 274
 275         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 276
 277         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 278                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 279
 280         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 281                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 282
 283         if (adev->pm.pp_feature & PP_ULV_MASK)
 284                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 285
 286         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 287         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
 288         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
 289         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
 290         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
 291         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
 292         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
 293         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
 294         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
 295         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
 296         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 297         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
 298         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
 299         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
 300         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
 301         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
 302         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
 303         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
 304         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
 305
 306         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 307                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
 308
 309         if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
 310             (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
 311                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
 312
 313         return 0;
 314 }
 315
 316 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
 317 {
 318         struct smu_table_context *table_context = &smu->smu_table;
 319         struct smu_13_0_7_powerplay_table *powerplay_table =
 320                 table_context->power_play_table;
 321         struct smu_baco_context *smu_baco = &smu->smu_baco;
 322         PPTable_t *smc_pptable = table_context->driver_pptable;
 323         BoardTable_t *BoardTable = &smc_pptable->BoardTable;
 324
 325         if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 326                 smu->dc_controlled_by_gpio = true;
 327
 328         if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO ||
 329             powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
 330                 smu_baco->platform_support = true;
 331
 332         if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
 333                 smu_baco->maco_support = true;
 334
 335         table_context->thermal_controller_type =
 336                 powerplay_table->thermal_controller_type;
 337
 338         /*
 339          * Instead of having its own buffer space and get overdrive_table copied,
 340          * smu->od_settings just points to the actual overdrive_table
 341          */
 342         smu->od_settings = &powerplay_table->overdrive_table;
 343
 344         return 0;
 345 }
 346
 347 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
 348 {
 349         struct smu_table_context *table_context = &smu->smu_table;
 350         struct smu_13_0_7_powerplay_table *powerplay_table =
 351                 table_context->power_play_table;
 352         struct amdgpu_device *adev = smu->adev;
 353
 354         if (adev->pdev->device == 0x51)
 355                 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080;
 356
 357         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 358                sizeof(PPTable_t));
 359
 360         return 0;
 361 }
 362
 363 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
 364 {
 365         struct amdgpu_device *adev = smu->adev;
 366         uint32_t mp1_fw_flags;
 367
 368         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 369                                    (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff));
 370
 371         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 372                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 373                 return 0;
 374
 375         return -EIO;
 376 }
 377
 378 #ifndef atom_smc_dpm_info_table_13_0_7
 379 struct atom_smc_dpm_info_table_13_0_7
 380 {
 381         struct atom_common_table_header table_header;
 382         BoardTable_t BoardTable;
 383 };
 384 #endif
 385
 386 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
 387 {
 388         struct smu_table_context *table_context = &smu->smu_table;
 389
 390         PPTable_t *smc_pptable = table_context->driver_pptable;
 391
 392         struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table;
 393
 394         BoardTable_t *BoardTable = &smc_pptable->BoardTable;
 395
 396         int index, ret;
 397
 398         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 399         smc_dpm_info);
 400
 401         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 402                         (uint8_t **)&smc_dpm_table);
 403         if (ret)
 404                 return ret;
 405
 406         memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
 407
 408         return 0;
 409 }
 410
 411 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
 412                                              void **table,
 413                                              uint32_t *size)
 414 {
 415         struct smu_table_context *smu_table = &smu->smu_table;
 416         void *combo_pptable = smu_table->combo_pptable;
 417         int ret = 0;
 418
 419         ret = smu_cmn_get_combo_pptable(smu);
 420         if (ret)
 421                 return ret;
 422
 423         *table = combo_pptable;
 424         *size = sizeof(struct smu_13_0_7_powerplay_table);
 425
 426         return 0;
 427 }
 428
 429 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
 430 {
 431         struct smu_table_context *smu_table = &smu->smu_table;
 432         struct amdgpu_device *adev = smu->adev;
 433         int ret = 0;
 434
 435         /*
 436          * With SCPM enabled, the pptable used will be signed. It cannot
 437          * be used directly by driver. To get the raw pptable, we need to
 438          * rely on the combo pptable(and its revelant SMU message).
 439          */
 440         ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
 441                                                 &smu_table->power_play_table,
 442                                                 &smu_table->power_play_table_size);
 443         if (ret)
 444                 return ret;
 445
 446         ret = smu_v13_0_7_store_powerplay_table(smu);
 447         if (ret)
 448                 return ret;
 449
 450         /*
 451          * With SCPM enabled, the operation below will be handled
 452          * by PSP. Driver involvment is unnecessary and useless.
 453          */
 454         if (!adev->scpm_enabled) {
 455                 ret = smu_v13_0_7_append_powerplay_table(smu);
 456                 if (ret)
 457                         return ret;
 458         }
 459
 460         ret = smu_v13_0_7_check_powerplay_table(smu);
 461         if (ret)
 462                 return ret;
 463
 464         return ret;
 465 }
 466
 467 static int smu_v13_0_7_tables_init(struct smu_context *smu)
 468 {
 469         struct smu_table_context *smu_table = &smu->smu_table;
 470         struct smu_table *tables = smu_table->tables;
 471
 472         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 473                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 474
 475         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 476                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 477         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 478                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 479         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 480                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 481         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 482                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 483         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 484                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 485         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 486                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 487                        AMDGPU_GEM_DOMAIN_VRAM);
 488         SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
 489                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 490
 491         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 492         if (!smu_table->metrics_table)
 493                 goto err0_out;
 494         smu_table->metrics_time = 0;
 495
 496         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 497         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 498         if (!smu_table->gpu_metrics_table)
 499                 goto err1_out;
 500
 501         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 502         if (!smu_table->watermarks_table)
 503                 goto err2_out;
 504
 505         return 0;
 506
 507 err2_out:
 508         kfree(smu_table->gpu_metrics_table);
 509 err1_out:
 510         kfree(smu_table->metrics_table);
 511 err0_out:
 512         return -ENOMEM;
 513 }
 514
 515 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
 516 {
 517         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 518
 519         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 520                                        GFP_KERNEL);
 521         if (!smu_dpm->dpm_context)
 522                 return -ENOMEM;
 523
 524         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 525
 526         return 0;
 527 }
 528
 529 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
 530 {
 531         int ret = 0;
 532
 533         ret = smu_v13_0_7_tables_init(smu);
 534         if (ret)
 535                 return ret;
 536
 537         ret = smu_v13_0_7_allocate_dpm_context(smu);
 538         if (ret)
 539                 return ret;
 540
 541         return smu_v13_0_init_smc_tables(smu);
 542 }
 543
 544 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
 545 {
 546         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 547         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 548         SkuTable_t *skutable = &driver_ppt->SkuTable;
 549         struct smu_13_0_dpm_table *dpm_table;
 550         struct smu_13_0_pcie_table *pcie_table;
 551         uint32_t link_level;
 552         int ret = 0;
 553
 554         /* socclk dpm table setup */
 555         dpm_table = &dpm_context->dpm_tables.soc_table;
 556         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 557                 ret = smu_v13_0_set_single_dpm_table(smu,
 558                                                      SMU_SOCCLK,
 559                                                      dpm_table);
 560                 if (ret)
 561                         return ret;
 562         } else {
 563                 dpm_table->count = 1;
 564                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 565                 dpm_table->dpm_levels[0].enabled = true;
 566                 dpm_table->min = dpm_table->dpm_levels[0].value;
 567                 dpm_table->max = dpm_table->dpm_levels[0].value;
 568         }
 569
 570         /* gfxclk dpm table setup */
 571         dpm_table = &dpm_context->dpm_tables.gfx_table;
 572         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 573                 ret = smu_v13_0_set_single_dpm_table(smu,
 574                                                      SMU_GFXCLK,
 575                                                      dpm_table);
 576                 if (ret)
 577                         return ret;
 578         } else {
 579                 dpm_table->count = 1;
 580                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 581                 dpm_table->dpm_levels[0].enabled = true;
 582                 dpm_table->min = dpm_table->dpm_levels[0].value;
 583                 dpm_table->max = dpm_table->dpm_levels[0].value;
 584         }
 585
 586         /* uclk dpm table setup */
 587         dpm_table = &dpm_context->dpm_tables.uclk_table;
 588         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 589                 ret = smu_v13_0_set_single_dpm_table(smu,
 590                                                      SMU_UCLK,
 591                                                      dpm_table);
 592                 if (ret)
 593                         return ret;
 594         } else {
 595                 dpm_table->count = 1;
 596                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 597                 dpm_table->dpm_levels[0].enabled = true;
 598                 dpm_table->min = dpm_table->dpm_levels[0].value;
 599                 dpm_table->max = dpm_table->dpm_levels[0].value;
 600         }
 601
 602         /* fclk dpm table setup */
 603         dpm_table = &dpm_context->dpm_tables.fclk_table;
 604         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 605                 ret = smu_v13_0_set_single_dpm_table(smu,
 606                                                      SMU_FCLK,
 607                                                      dpm_table);
 608                 if (ret)
 609                         return ret;
 610         } else {
 611                 dpm_table->count = 1;
 612                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 613                 dpm_table->dpm_levels[0].enabled = true;
 614                 dpm_table->min = dpm_table->dpm_levels[0].value;
 615                 dpm_table->max = dpm_table->dpm_levels[0].value;
 616         }
 617
 618         /* vclk dpm table setup */
 619         dpm_table = &dpm_context->dpm_tables.vclk_table;
 620         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
 621                 ret = smu_v13_0_set_single_dpm_table(smu,
 622                                                      SMU_VCLK,
 623                                                      dpm_table);
 624                 if (ret)
 625                         return ret;
 626         } else {
 627                 dpm_table->count = 1;
 628                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 629                 dpm_table->dpm_levels[0].enabled = true;
 630                 dpm_table->min = dpm_table->dpm_levels[0].value;
 631                 dpm_table->max = dpm_table->dpm_levels[0].value;
 632         }
 633
 634         /* dclk dpm table setup */
 635         dpm_table = &dpm_context->dpm_tables.dclk_table;
 636         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
 637                 ret = smu_v13_0_set_single_dpm_table(smu,
 638                                                      SMU_DCLK,
 639                                                      dpm_table);
 640                 if (ret)
 641                         return ret;
 642         } else {
 643                 dpm_table->count = 1;
 644                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 645                 dpm_table->dpm_levels[0].enabled = true;
 646                 dpm_table->min = dpm_table->dpm_levels[0].value;
 647                 dpm_table->max = dpm_table->dpm_levels[0].value;
 648         }
 649
 650         /* lclk dpm table setup */
 651         pcie_table = &dpm_context->dpm_tables.pcie_table;
 652         pcie_table->num_of_link_levels = 0;
 653         for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
 654                 if (!skutable->PcieGenSpeed[link_level] &&
 655                     !skutable->PcieLaneCount[link_level] &&
 656                     !skutable->LclkFreq[link_level])
 657                         continue;
 658
 659                 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
 660                                         skutable->PcieGenSpeed[link_level];
 661                 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
 662                                         skutable->PcieLaneCount[link_level];
 663                 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
 664                                         skutable->LclkFreq[link_level];
 665                 pcie_table->num_of_link_levels++;
 666         }
 667
 668         return 0;
 669 }
 670
 671 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
 672 {
 673         int ret = 0;
 674         uint64_t feature_enabled;
 675
 676         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 677         if (ret)
 678                 return false;
 679
 680         return !!(feature_enabled & SMC_DPM_FEATURE);
 681 }
 682
 683 static void smu_v13_0_7_dump_pptable(struct smu_context *smu)
 684 {
 685        struct smu_table_context *table_context = &smu->smu_table;
 686        PPTable_t *pptable = table_context->driver_pptable;
 687        SkuTable_t *skutable = &pptable->SkuTable;
 688
 689        dev_info(smu->adev->dev, "Dumped PPTable:\n");
 690
 691        dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
 692        dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
 693        dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
 694 }
 695
 696 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
 697 {
 698         uint32_t throttler_status = 0;
 699         int i;
 700
 701         for (i = 0; i < THROTTLER_COUNT; i++)
 702                 throttler_status |=
 703                         (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
 704
 705         return throttler_status;
 706 }
 707
 708 #define SMU_13_0_7_BUSY_THRESHOLD       15
 709 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
 710                                             MetricsMember_t member,
 711                                             uint32_t *value)
 712 {
 713         struct smu_table_context *smu_table= &smu->smu_table;
 714         SmuMetrics_t *metrics =
 715                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 716         int ret = 0;
 717
 718         ret = smu_cmn_get_metrics_table(smu,
 719                                         NULL,
 720                                         false);
 721         if (ret)
 722                 return ret;
 723
 724         switch (member) {
 725         case METRICS_CURR_GFXCLK:
 726                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 727                 break;
 728         case METRICS_CURR_SOCCLK:
 729                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 730                 break;
 731         case METRICS_CURR_UCLK:
 732                 *value = metrics->CurrClock[PPCLK_UCLK];
 733                 break;
 734         case METRICS_CURR_VCLK:
 735                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 736                 break;
 737         case METRICS_CURR_VCLK1:
 738                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 739                 break;
 740         case METRICS_CURR_DCLK:
 741                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 742                 break;
 743         case METRICS_CURR_DCLK1:
 744                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 745                 break;
 746         case METRICS_CURR_FCLK:
 747                 *value = metrics->CurrClock[PPCLK_FCLK];
 748                 break;
 749         case METRICS_AVERAGE_GFXCLK:
 750                 *value = metrics->AverageGfxclkFrequencyPreDs;
 751                 break;
 752         case METRICS_AVERAGE_FCLK:
 753                 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
 754                         *value = metrics->AverageFclkFrequencyPostDs;
 755                 else
 756                         *value = metrics->AverageFclkFrequencyPreDs;
 757                 break;
 758         case METRICS_AVERAGE_UCLK:
 759                 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
 760                         *value = metrics->AverageMemclkFrequencyPostDs;
 761                 else
 762                         *value = metrics->AverageMemclkFrequencyPreDs;
 763                 break;
 764         case METRICS_AVERAGE_VCLK:
 765                 *value = metrics->AverageVclk0Frequency;
 766                 break;
 767         case METRICS_AVERAGE_DCLK:
 768                 *value = metrics->AverageDclk0Frequency;
 769                 break;
 770         case METRICS_AVERAGE_VCLK1:
 771                 *value = metrics->AverageVclk1Frequency;
 772                 break;
 773         case METRICS_AVERAGE_DCLK1:
 774                 *value = metrics->AverageDclk1Frequency;
 775                 break;
 776         case METRICS_AVERAGE_GFXACTIVITY:
 777                 *value = metrics->AverageGfxActivity;
 778                 break;
 779         case METRICS_AVERAGE_MEMACTIVITY:
 780                 *value = metrics->AverageUclkActivity;
 781                 break;
 782         case METRICS_AVERAGE_SOCKETPOWER:
 783                 *value = metrics->AverageSocketPower << 8;
 784                 break;
 785         case METRICS_TEMPERATURE_EDGE:
 786                 *value = metrics->AvgTemperature[TEMP_EDGE] *
 787                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 788                 break;
 789         case METRICS_TEMPERATURE_HOTSPOT:
 790                 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
 791                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 792                 break;
 793         case METRICS_TEMPERATURE_MEM:
 794                 *value = metrics->AvgTemperature[TEMP_MEM] *
 795                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 796                 break;
 797         case METRICS_TEMPERATURE_VRGFX:
 798                 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
 799                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 800                 break;
 801         case METRICS_TEMPERATURE_VRSOC:
 802                 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
 803                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 804                 break;
 805         case METRICS_THROTTLER_STATUS:
 806                 *value = smu_v13_0_7_get_throttler_status(metrics);
 807                 break;
 808         case METRICS_CURR_FANSPEED:
 809                 *value = metrics->AvgFanRpm;
 810                 break;
 811         case METRICS_CURR_FANPWM:
 812                 *value = metrics->AvgFanPwm;
 813                 break;
 814         case METRICS_VOLTAGE_VDDGFX:
 815                 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
 816                 break;
 817         case METRICS_PCIE_RATE:
 818                 *value = metrics->PcieRate;
 819                 break;
 820         case METRICS_PCIE_WIDTH:
 821                 *value = metrics->PcieWidth;
 822                 break;
 823         default:
 824                 *value = UINT_MAX;
 825                 break;
 826         }
 827
 828         return ret;
 829 }
 830
 831 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
 832                                    enum amd_pp_sensors sensor,
 833                                    void *data,
 834                                    uint32_t *size)
 835 {
 836         struct smu_table_context *table_context = &smu->smu_table;
 837         PPTable_t *smc_pptable = table_context->driver_pptable;
 838         int ret = 0;
 839
 840         switch (sensor) {
 841         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 842                 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
 843                 *size = 4;
 844                 break;
 845         case AMDGPU_PP_SENSOR_MEM_LOAD:
 846                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 847                                                        METRICS_AVERAGE_MEMACTIVITY,
 848                                                        (uint32_t *)data);
 849                 *size = 4;
 850                 break;
 851         case AMDGPU_PP_SENSOR_GPU_LOAD:
 852                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 853                                                        METRICS_AVERAGE_GFXACTIVITY,
 854                                                        (uint32_t *)data);
 855                 *size = 4;
 856                 break;
 857         case AMDGPU_PP_SENSOR_GPU_POWER:
 858                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 859                                                        METRICS_AVERAGE_SOCKETPOWER,
 860                                                        (uint32_t *)data);
 861                 *size = 4;
 862                 break;
 863         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 864                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 865                                                        METRICS_TEMPERATURE_HOTSPOT,
 866                                                        (uint32_t *)data);
 867                 *size = 4;
 868                 break;
 869         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 870                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 871                                                        METRICS_TEMPERATURE_EDGE,
 872                                                        (uint32_t *)data);
 873                 *size = 4;
 874                 break;
 875         case AMDGPU_PP_SENSOR_MEM_TEMP:
 876                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 877                                                        METRICS_TEMPERATURE_MEM,
 878                                                        (uint32_t *)data);
 879                 *size = 4;
 880                 break;
 881         case AMDGPU_PP_SENSOR_GFX_MCLK:
 882                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 883                                                        METRICS_AVERAGE_UCLK,
 884                                                        (uint32_t *)data);
 885                 *(uint32_t *)data *= 100;
 886                 *size = 4;
 887                 break;
 888         case AMDGPU_PP_SENSOR_GFX_SCLK:
 889                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 890                                                        METRICS_AVERAGE_GFXCLK,
 891                                                        (uint32_t *)data);
 892                 *(uint32_t *)data *= 100;
 893                 *size = 4;
 894                 break;
 895         case AMDGPU_PP_SENSOR_VDDGFX:
 896                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 897                                                        METRICS_VOLTAGE_VDDGFX,
 898                                                        (uint32_t *)data);
 899                 *size = 4;
 900                 break;
 901         default:
 902                 ret = -EOPNOTSUPP;
 903                 break;
 904         }
 905
 906         return ret;
 907 }
 908
 909 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
 910                                                      enum smu_clk_type clk_type,
 911                                                      uint32_t *value)
 912 {
 913         MetricsMember_t member_type;
 914         int clk_id = 0;
 915
 916         clk_id = smu_cmn_to_asic_specific_index(smu,
 917                                                 CMN2ASIC_MAPPING_CLK,
 918                                                 clk_type);
 919         if (clk_id < 0)
 920                 return -EINVAL;
 921
 922         switch (clk_id) {
 923         case PPCLK_GFXCLK:
 924                 member_type = METRICS_AVERAGE_GFXCLK;
 925                 break;
 926         case PPCLK_UCLK:
 927                 member_type = METRICS_CURR_UCLK;
 928                 break;
 929         case PPCLK_FCLK:
 930                 member_type = METRICS_CURR_FCLK;
 931                 break;
 932         case PPCLK_SOCCLK:
 933                 member_type = METRICS_CURR_SOCCLK;
 934                 break;
 935         case PPCLK_VCLK_0:
 936                 member_type = METRICS_CURR_VCLK;
 937                 break;
 938         case PPCLK_DCLK_0:
 939                 member_type = METRICS_CURR_DCLK;
 940                 break;
 941         case PPCLK_VCLK_1:
 942                 member_type = METRICS_CURR_VCLK1;
 943                 break;
 944         case PPCLK_DCLK_1:
 945                 member_type = METRICS_CURR_DCLK1;
 946                 break;
 947         default:
 948                 return -EINVAL;
 949         }
 950
 951         return smu_v13_0_7_get_smu_metrics_data(smu,
 952                                                 member_type,
 953                                                 value);
 954 }
 955
 956 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
 957                                         enum smu_clk_type clk_type,
 958                                         char *buf)
 959 {
 960         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 961         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 962         struct smu_13_0_dpm_table *single_dpm_table;
 963         struct smu_13_0_pcie_table *pcie_table;
 964         uint32_t gen_speed, lane_width;
 965         int i, curr_freq, size = 0;
 966         int ret = 0;
 967
 968         smu_cmn_get_sysfs_buf(&buf, &size);
 969
 970         if (amdgpu_ras_intr_triggered()) {
 971                 size += sysfs_emit_at(buf, size, "unavailable\n");
 972                 return size;
 973         }
 974
 975         switch (clk_type) {
 976         case SMU_SCLK:
 977                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 978                 break;
 979         case SMU_MCLK:
 980                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 981                 break;
 982         case SMU_SOCCLK:
 983                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 984                 break;
 985         case SMU_FCLK:
 986                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 987                 break;
 988         case SMU_VCLK:
 989         case SMU_VCLK1:
 990                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 991                 break;
 992         case SMU_DCLK:
 993         case SMU_DCLK1:
 994                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 995                 break;
 996         default:
 997                 break;
 998         }
 999
1000         switch (clk_type) {
1001         case SMU_SCLK:
1002         case SMU_MCLK:
1003         case SMU_SOCCLK:
1004         case SMU_FCLK:
1005         case SMU_VCLK:
1006         case SMU_VCLK1:
1007         case SMU_DCLK:
1008         case SMU_DCLK1:
1009                 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1010                 if (ret) {
1011                         dev_err(smu->adev->dev, "Failed to get current clock freq!");
1012                         return ret;
1013                 }
1014
1015                 if (single_dpm_table->is_fine_grained) {
1016                         /*
1017                          * For fine grained dpms, there are only two dpm levels:
1018                          *   - level 0 -> min clock freq
1019                          *   - level 1 -> max clock freq
1020                          * And the current clock frequency can be any value between them.
1021                          * So, if the current clock frequency is not at level 0 or level 1,
1022                          * we will fake it as three dpm levels:
1023                          *   - level 0 -> min clock freq
1024                          *   - level 1 -> current actual clock freq
1025                          *   - level 2 -> max clock freq
1026                          */
1027                         if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1028                              (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1029                                 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1030                                                 single_dpm_table->dpm_levels[0].value);
1031                                 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1032                                                 curr_freq);
1033                                 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1034                                                 single_dpm_table->dpm_levels[1].value);
1035                         } else {
1036                                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1037                                                 single_dpm_table->dpm_levels[0].value,
1038                                                 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1039                                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1040                                                 single_dpm_table->dpm_levels[1].value,
1041                                                 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1042                         }
1043                 } else {
1044                         for (i = 0; i < single_dpm_table->count; i++)
1045                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1046                                                 i, single_dpm_table->dpm_levels[i].value,
1047                                                 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1048                 }
1049                 break;
1050         case SMU_PCIE:
1051                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1052                                                        METRICS_PCIE_RATE,
1053                                                        &gen_speed);
1054                 if (ret)
1055                         return ret;
1056
1057                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1058                                                        METRICS_PCIE_WIDTH,
1059                                                        &lane_width);
1060                 if (ret)
1061                         return ret;
1062
1063                 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1064                 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1065                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1066                                         (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1067                                         (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1068                                         (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1069                                         (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1070                                         (pcie_table->pcie_lane[i] == 1) ? "x1" :
1071                                         (pcie_table->pcie_lane[i] == 2) ? "x2" :
1072                                         (pcie_table->pcie_lane[i] == 3) ? "x4" :
1073                                         (pcie_table->pcie_lane[i] == 4) ? "x8" :
1074                                         (pcie_table->pcie_lane[i] == 5) ? "x12" :
1075                                         (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1076                                         pcie_table->clk_freq[i],
1077                                         (gen_speed == pcie_table->pcie_gen[i]) &&
1078                                         (lane_width == pcie_table->pcie_lane[i]) ?
1079                                         "*" : "");
1080                 break;
1081
1082         default:
1083                 break;
1084         }
1085
1086         return size;
1087 }
1088
1089 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1090                                         enum smu_clk_type clk_type,
1091                                         uint32_t mask)
1092 {
1093         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1094         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1095         struct smu_13_0_dpm_table *single_dpm_table;
1096         uint32_t soft_min_level, soft_max_level;
1097         uint32_t min_freq, max_freq;
1098         int ret = 0;
1099
1100         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1101         soft_max_level = mask ? (fls(mask) - 1) : 0;
1102
1103         switch (clk_type) {
1104         case SMU_GFXCLK:
1105         case SMU_SCLK:
1106                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1107                 break;
1108         case SMU_MCLK:
1109         case SMU_UCLK:
1110                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1111                 break;
1112         case SMU_SOCCLK:
1113                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1114                 break;
1115         case SMU_FCLK:
1116                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1117                 break;
1118         case SMU_VCLK:
1119         case SMU_VCLK1:
1120                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1121                 break;
1122         case SMU_DCLK:
1123         case SMU_DCLK1:
1124                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1125                 break;
1126         default:
1127                 break;
1128         }
1129
1130         switch (clk_type) {
1131         case SMU_GFXCLK:
1132         case SMU_SCLK:
1133         case SMU_MCLK:
1134         case SMU_UCLK:
1135         case SMU_SOCCLK:
1136         case SMU_FCLK:
1137         case SMU_VCLK:
1138         case SMU_VCLK1:
1139         case SMU_DCLK:
1140         case SMU_DCLK1:
1141                 if (single_dpm_table->is_fine_grained) {
1142                         /* There is only 2 levels for fine grained DPM */
1143                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1144                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1145                 } else {
1146                         if ((soft_max_level >= single_dpm_table->count) ||
1147                             (soft_min_level >= single_dpm_table->count))
1148                                 return -EINVAL;
1149                 }
1150
1151                 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1152                 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1153
1154                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1155                                                             clk_type,
1156                                                             min_freq,
1157                                                             max_freq);
1158                 break;
1159         case SMU_DCEFCLK:
1160         case SMU_PCIE:
1161         default:
1162                 break;
1163         }
1164
1165         return ret;
1166 }
1167
1168 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
1169                                               uint32_t pcie_gen_cap,
1170                                               uint32_t pcie_width_cap)
1171 {
1172         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1173         struct smu_13_0_pcie_table *pcie_table =
1174                                 &dpm_context->dpm_tables.pcie_table;
1175         uint32_t smu_pcie_arg;
1176         int ret, i;
1177
1178         for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1179                 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1180                         pcie_table->pcie_gen[i] = pcie_gen_cap;
1181                 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1182                         pcie_table->pcie_lane[i] = pcie_width_cap;
1183
1184                 smu_pcie_arg = i << 16;
1185                 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1186                 smu_pcie_arg |= pcie_table->pcie_lane[i];
1187
1188                 ret = smu_cmn_send_smc_msg_with_param(smu,
1189                                                       SMU_MSG_OverridePcieParameters,
1190                                                       smu_pcie_arg,
1191                                                       NULL);
1192                 if (ret)
1193                         return ret;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static const struct smu_temperature_range smu13_thermal_policy[] =
1200 {
1201         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1202         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1203 };
1204
1205 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
1206                                                      struct smu_temperature_range *range)
1207 {
1208         struct smu_table_context *table_context = &smu->smu_table;
1209         struct smu_13_0_7_powerplay_table *powerplay_table =
1210                 table_context->power_play_table;
1211         PPTable_t *pptable = smu->smu_table.driver_pptable;
1212
1213         if (!range)
1214                 return -EINVAL;
1215
1216         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1217
1218         range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
1219                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1220         range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1221                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1222         range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1223                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1224         range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1225                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1226         range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
1227                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1228         range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1229                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1230         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1231
1232         return 0;
1233 }
1234
1235 #define MAX(a, b)       ((a) > (b) ? (a) : (b))
1236 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
1237                                            void **table)
1238 {
1239         struct smu_table_context *smu_table = &smu->smu_table;
1240         struct gpu_metrics_v1_3 *gpu_metrics =
1241                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1242         SmuMetricsExternal_t metrics_ext;
1243         SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
1244         int ret = 0;
1245
1246         ret = smu_cmn_get_metrics_table(smu,
1247                                         &metrics_ext,
1248                                         true);
1249         if (ret)
1250                 return ret;
1251
1252         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1253
1254         gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
1255         gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
1256         gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
1257         gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
1258         gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
1259         gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0],
1260                                              metrics->AvgTemperature[TEMP_VR_MEM1]);
1261
1262         gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
1263         gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
1264         gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage,
1265                                                metrics->Vcn1ActivityPercentage);
1266
1267         gpu_metrics->average_socket_power = metrics->AverageSocketPower;
1268         gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
1269
1270         if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
1271                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
1272         else
1273                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
1274
1275         if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
1276                 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
1277         else
1278                 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
1279
1280         gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
1281         gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
1282         gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
1283         gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
1284
1285         gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
1286         gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
1287         gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
1288         gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
1289         gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
1290
1291         gpu_metrics->throttle_status =
1292                         smu_v13_0_7_get_throttler_status(metrics);
1293         gpu_metrics->indep_throttle_status =
1294                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
1295                                                            smu_v13_0_7_throttler_map);
1296
1297         gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
1298
1299         gpu_metrics->pcie_link_width = metrics->PcieWidth;
1300         gpu_metrics->pcie_link_speed = metrics->PcieRate;
1301
1302         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1303
1304         gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
1305         gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
1306         gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
1307
1308         *table = (void *)gpu_metrics;
1309
1310         return sizeof(struct gpu_metrics_v1_3);
1311 }
1312
1313 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
1314 {
1315         struct smu_13_0_dpm_context *dpm_context =
1316                                 smu->smu_dpm.dpm_context;
1317         struct smu_13_0_dpm_table *gfx_table =
1318                                 &dpm_context->dpm_tables.gfx_table;
1319         struct smu_13_0_dpm_table *mem_table =
1320                                 &dpm_context->dpm_tables.uclk_table;
1321         struct smu_13_0_dpm_table *soc_table =
1322                                 &dpm_context->dpm_tables.soc_table;
1323         struct smu_13_0_dpm_table *vclk_table =
1324                                 &dpm_context->dpm_tables.vclk_table;
1325         struct smu_13_0_dpm_table *dclk_table =
1326                                 &dpm_context->dpm_tables.dclk_table;
1327         struct smu_13_0_dpm_table *fclk_table =
1328                                 &dpm_context->dpm_tables.fclk_table;
1329         struct smu_umd_pstate_table *pstate_table =
1330                                 &smu->pstate_table;
1331
1332         pstate_table->gfxclk_pstate.min = gfx_table->min;
1333         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1334
1335         pstate_table->uclk_pstate.min = mem_table->min;
1336         pstate_table->uclk_pstate.peak = mem_table->max;
1337
1338         pstate_table->socclk_pstate.min = soc_table->min;
1339         pstate_table->socclk_pstate.peak = soc_table->max;
1340
1341         pstate_table->vclk_pstate.min = vclk_table->min;
1342         pstate_table->vclk_pstate.peak = vclk_table->max;
1343
1344         pstate_table->dclk_pstate.min = dclk_table->min;
1345         pstate_table->dclk_pstate.peak = dclk_table->max;
1346
1347         pstate_table->fclk_pstate.min = fclk_table->min;
1348         pstate_table->fclk_pstate.peak = fclk_table->max;
1349
1350         /*
1351          * For now, just use the mininum clock frequency.
1352          * TODO: update them when the real pstate settings available
1353          */
1354         pstate_table->gfxclk_pstate.standard = gfx_table->min;
1355         pstate_table->uclk_pstate.standard = mem_table->min;
1356         pstate_table->socclk_pstate.standard = soc_table->min;
1357         pstate_table->vclk_pstate.standard = vclk_table->min;
1358         pstate_table->dclk_pstate.standard = dclk_table->min;
1359         pstate_table->fclk_pstate.standard = fclk_table->min;
1360
1361         return 0;
1362 }
1363
1364 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
1365                                          uint32_t *speed)
1366 {
1367         int ret;
1368
1369         if (!speed)
1370                 return -EINVAL;
1371
1372         ret = smu_v13_0_7_get_smu_metrics_data(smu,
1373                                                METRICS_CURR_FANPWM,
1374                                                speed);
1375         if (ret) {
1376                 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
1377                 return ret;
1378         }
1379
1380         /* Convert the PMFW output which is in percent to pwm(255) based */
1381         *speed = MIN(*speed * 255 / 100, 255);
1382
1383         return 0;
1384 }
1385
1386 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
1387                                          uint32_t *speed)
1388 {
1389         if (!speed)
1390                 return -EINVAL;
1391
1392         return smu_v13_0_7_get_smu_metrics_data(smu,
1393                                                 METRICS_CURR_FANSPEED,
1394                                                 speed);
1395 }
1396
1397 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
1398 {
1399         struct smu_table_context *table_context = &smu->smu_table;
1400         PPTable_t *pptable = table_context->driver_pptable;
1401         SkuTable_t *skutable = &pptable->SkuTable;
1402
1403         /*
1404          * Skip the MGpuFanBoost setting for those ASICs
1405          * which do not support it
1406          */
1407         if (skutable->MGpuAcousticLimitRpmThreshold == 0)
1408                 return 0;
1409
1410         return smu_cmn_send_smc_msg_with_param(smu,
1411                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
1412                                                0,
1413                                                NULL);
1414 }
1415
1416 static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
1417                                        uint32_t *current_power_limit,
1418                                        uint32_t *default_power_limit,
1419                                        uint32_t *max_power_limit)
1420 {
1421         struct smu_table_context *table_context = &smu->smu_table;
1422         struct smu_13_0_7_powerplay_table *powerplay_table =
1423                 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
1424         PPTable_t *pptable = table_context->driver_pptable;
1425         SkuTable_t *skutable = &pptable->SkuTable;
1426         uint32_t power_limit, od_percent;
1427
1428         if (smu_v13_0_get_current_power_limit(smu, &power_limit))
1429                 power_limit = smu->adev->pm.ac_power ?
1430                               skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1431                               skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1432
1433         if (current_power_limit)
1434                 *current_power_limit = power_limit;
1435         if (default_power_limit)
1436                 *default_power_limit = power_limit;
1437
1438         if (max_power_limit) {
1439                 if (smu->od_enabled) {
1440                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
1441
1442                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1443
1444                         power_limit *= (100 + od_percent);
1445                         power_limit /= 100;
1446                 }
1447                 *max_power_limit = power_limit;
1448         }
1449
1450         return 0;
1451 }
1452
1453 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
1454 {
1455         DpmActivityMonitorCoeffIntExternal_t *activity_monitor_external;
1456         uint32_t i, j, size = 0;
1457         int16_t workload_type = 0;
1458         int result = 0;
1459
1460         if (!buf)
1461                 return -EINVAL;
1462
1463         activity_monitor_external = kcalloc(PP_SMC_POWER_PROFILE_COUNT,
1464                                             sizeof(*activity_monitor_external),
1465                                             GFP_KERNEL);
1466         if (!activity_monitor_external)
1467                 return -ENOMEM;
1468
1469         size += sysfs_emit_at(buf, size, "                              ");
1470         for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
1471                 size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i],
1472                         (i == smu->power_profile_mode) ? "* " : "  ");
1473
1474         size += sysfs_emit_at(buf, size, "\n");
1475
1476         for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) {
1477                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1478                 workload_type = smu_cmn_to_asic_specific_index(smu,
1479                                                                CMN2ASIC_MAPPING_WORKLOAD,
1480                                                                i);
1481                 if (workload_type < 0) {
1482                         result = -EINVAL;
1483                         goto out;
1484                 }
1485
1486                 result = smu_cmn_update_table(smu,
1487                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1488                                           (void *)(&activity_monitor_external[i]), false);
1489                 if (result) {
1490                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1491                         goto out;
1492                 }
1493         }
1494
1495 #define PRINT_DPM_MONITOR(field)                                                                        \
1496 do {                                                                                                    \
1497         size += sysfs_emit_at(buf, size, "%-30s", #field);                                              \
1498         for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++)                                            \
1499                 size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field);               \
1500         size += sysfs_emit_at(buf, size, "\n");                                                         \
1501 } while (0)
1502
1503         PRINT_DPM_MONITOR(Gfx_ActiveHystLimit);
1504         PRINT_DPM_MONITOR(Gfx_IdleHystLimit);
1505         PRINT_DPM_MONITOR(Gfx_FPS);
1506         PRINT_DPM_MONITOR(Gfx_MinActiveFreqType);
1507         PRINT_DPM_MONITOR(Gfx_BoosterFreqType);
1508         PRINT_DPM_MONITOR(Gfx_MinActiveFreq);
1509         PRINT_DPM_MONITOR(Gfx_BoosterFreq);
1510         PRINT_DPM_MONITOR(Fclk_ActiveHystLimit);
1511         PRINT_DPM_MONITOR(Fclk_IdleHystLimit);
1512         PRINT_DPM_MONITOR(Fclk_FPS);
1513         PRINT_DPM_MONITOR(Fclk_MinActiveFreqType);
1514         PRINT_DPM_MONITOR(Fclk_BoosterFreqType);
1515         PRINT_DPM_MONITOR(Fclk_MinActiveFreq);
1516         PRINT_DPM_MONITOR(Fclk_BoosterFreq);
1517 #undef PRINT_DPM_MONITOR
1518
1519         result = size;
1520 out:
1521         kfree(activity_monitor_external);
1522         return result;
1523 }
1524
1525 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1526 {
1527
1528         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1529         DpmActivityMonitorCoeffInt_t *activity_monitor =
1530                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1531         int workload_type, ret = 0;
1532
1533         smu->power_profile_mode = input[size];
1534
1535         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) {
1536                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1537                 return -EINVAL;
1538         }
1539
1540         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1541
1542                 ret = smu_cmn_update_table(smu,
1543                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1544                                        (void *)(&activity_monitor_external), false);
1545                 if (ret) {
1546                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1547                         return ret;
1548                 }
1549
1550                 switch (input[0]) {
1551                 case 0: /* Gfxclk */
1552                         activity_monitor->Gfx_ActiveHystLimit = input[1];
1553                         activity_monitor->Gfx_IdleHystLimit = input[2];
1554                         activity_monitor->Gfx_FPS = input[3];
1555                         activity_monitor->Gfx_MinActiveFreqType = input[4];
1556                         activity_monitor->Gfx_BoosterFreqType = input[5];
1557                         activity_monitor->Gfx_MinActiveFreq = input[6];
1558                         activity_monitor->Gfx_BoosterFreq = input[7];
1559                         break;
1560                 case 1: /* Fclk */
1561                         activity_monitor->Fclk_ActiveHystLimit = input[1];
1562                         activity_monitor->Fclk_IdleHystLimit = input[2];
1563                         activity_monitor->Fclk_FPS = input[3];
1564                         activity_monitor->Fclk_MinActiveFreqType = input[4];
1565                         activity_monitor->Fclk_BoosterFreqType = input[5];
1566                         activity_monitor->Fclk_MinActiveFreq = input[6];
1567                         activity_monitor->Fclk_BoosterFreq = input[7];
1568                         break;
1569                 }
1570
1571                 ret = smu_cmn_update_table(smu,
1572                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1573                                        (void *)(&activity_monitor_external), true);
1574                 if (ret) {
1575                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1576                         return ret;
1577                 }
1578         }
1579
1580         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1581         workload_type = smu_cmn_to_asic_specific_index(smu,
1582                                                        CMN2ASIC_MAPPING_WORKLOAD,
1583                                                        smu->power_profile_mode);
1584         if (workload_type < 0)
1585                 return -EINVAL;
1586         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1587                                     1 << workload_type, NULL);
1588
1589         return ret;
1590 }
1591
1592 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
1593                                      enum pp_mp1_state mp1_state)
1594 {
1595         int ret;
1596
1597         switch (mp1_state) {
1598         case PP_MP1_STATE_UNLOAD:
1599                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
1600                 break;
1601         default:
1602                 /* Ignore others */
1603                 ret = 0;
1604         }
1605
1606         return ret;
1607 }
1608
1609 static int smu_v13_0_7_baco_enter(struct smu_context *smu)
1610 {
1611         struct smu_baco_context *smu_baco = &smu->smu_baco;
1612         struct amdgpu_device *adev = smu->adev;
1613
1614         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
1615                 return smu_v13_0_baco_set_armd3_sequence(smu,
1616                                 smu_baco->maco_support ? BACO_SEQ_BAMACO : BACO_SEQ_BACO);
1617         else
1618                 return smu_v13_0_baco_enter(smu);
1619 }
1620
1621 static int smu_v13_0_7_baco_exit(struct smu_context *smu)
1622 {
1623         struct amdgpu_device *adev = smu->adev;
1624
1625         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
1626                 /* Wait for PMFW handling for the Dstate change */
1627                 usleep_range(10000, 11000);
1628                 return smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
1629         } else {
1630                 return smu_v13_0_baco_exit(smu);
1631         }
1632 }
1633
1634 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
1635 {
1636         struct amdgpu_device *adev = smu->adev;
1637
1638         /* SRIOV does not support SMU mode1 reset */
1639         if (amdgpu_sriov_vf(adev))
1640                 return false;
1641
1642         return true;
1643 }
1644
1645 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
1646                                      enum pp_df_cstate state)
1647 {
1648         return smu_cmn_send_smc_msg_with_param(smu,
1649                                                SMU_MSG_DFCstateControl,
1650                                                state,
1651                                                NULL);
1652 }
1653
1654 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
1655         .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
1656         .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
1657         .is_dpm_running = smu_v13_0_7_is_dpm_running,
1658         .dump_pptable = smu_v13_0_7_dump_pptable,
1659         .init_microcode = smu_v13_0_init_microcode,
1660         .load_microcode = smu_v13_0_load_microcode,
1661         .fini_microcode = smu_v13_0_fini_microcode,
1662         .init_smc_tables = smu_v13_0_7_init_smc_tables,
1663         .fini_smc_tables = smu_v13_0_fini_smc_tables,
1664         .init_power = smu_v13_0_init_power,
1665         .fini_power = smu_v13_0_fini_power,
1666         .check_fw_status = smu_v13_0_7_check_fw_status,
1667         .setup_pptable = smu_v13_0_7_setup_pptable,
1668         .check_fw_version = smu_v13_0_check_fw_version,
1669         .write_pptable = smu_cmn_write_pptable,
1670         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1671         .system_features_control = smu_v13_0_system_features_control,
1672         .set_allowed_mask = smu_v13_0_set_allowed_mask,
1673         .get_enabled_mask = smu_cmn_get_enabled_mask,
1674         .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
1675         .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
1676         .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
1677         .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
1678         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1679         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1680         .read_sensor = smu_v13_0_7_read_sensor,
1681         .feature_is_enabled = smu_cmn_feature_is_enabled,
1682         .print_clk_levels = smu_v13_0_7_print_clk_levels,
1683         .force_clk_levels = smu_v13_0_7_force_clk_levels,
1684         .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,
1685         .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
1686         .register_irq_handler = smu_v13_0_register_irq_handler,
1687         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1688         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1689         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1690         .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
1691         .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
1692         .set_performance_level = smu_v13_0_set_performance_level,
1693         .gfx_off_control = smu_v13_0_gfx_off_control,
1694         .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
1695         .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
1696         .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
1697         .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
1698         .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
1699         .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
1700         .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
1701         .get_power_limit = smu_v13_0_7_get_power_limit,
1702         .set_power_limit = smu_v13_0_set_power_limit,
1703         .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
1704         .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
1705         .set_tool_table_location = smu_v13_0_set_tool_table_location,
1706         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1707         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1708         .baco_is_support = smu_v13_0_baco_is_support,
1709         .baco_get_state = smu_v13_0_baco_get_state,
1710         .baco_set_state = smu_v13_0_baco_set_state,
1711         .baco_enter = smu_v13_0_7_baco_enter,
1712         .baco_exit = smu_v13_0_7_baco_exit,
1713         .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
1714         .mode1_reset = smu_v13_0_mode1_reset,
1715         .set_mp1_state = smu_v13_0_7_set_mp1_state,
1716         .set_df_cstate = smu_v13_0_7_set_df_cstate,
1717         .gpo_control = smu_v13_0_gpo_control,
1718 };
1719
1720 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
1721 {
1722         smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
1723         smu->message_map = smu_v13_0_7_message_map;
1724         smu->clock_map = smu_v13_0_7_clk_map;
1725         smu->feature_map = smu_v13_0_7_feature_mask_map;
1726         smu->table_map = smu_v13_0_7_table_map;
1727         smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
1728         smu->workload_map = smu_v13_0_7_workload_map;
1729         smu_v13_0_set_smu_mailbox_registers(smu);
1730 }