drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_v13_0.h"
  29 #include "smu13_driver_if_v13_0_5.h"
  30 #include "smu_v13_0_5_ppt.h"
  31 #include "smu_v13_0_5_ppsmc.h"
  32 #include "smu_v13_0_5_pmfw.h"
  33 #include "smu_cmn.h"
  34
  35 /*
  36  * DO NOT use these for err/warn/info/debug messages.
  37  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  38  * They are more MGPU friendly.
  39  */
  40 #undef pr_err
  41 #undef pr_warn
  42 #undef pr_info
  43 #undef pr_debug
  44
  45 #define mmMP1_C2PMSG_2                                                                            (0xbee142 + 0xb00000 / 4)
  46 #define mmMP1_C2PMSG_2_BASE_IDX                                                                   0
  47
  48 #define mmMP1_C2PMSG_34                                                                           (0xbee262 + 0xb00000 / 4)
  49 #define mmMP1_C2PMSG_34_BASE_IDX                                                                   0
  50
  51 #define mmMP1_C2PMSG_33                                                                                (0xbee261 + 0xb00000 / 4)
  52 #define mmMP1_C2PMSG_33_BASE_IDX                                                                   0
  53
  54 #define FEATURE_MASK(feature) (1ULL << feature)
  55 #define SMC_DPM_FEATURE ( \
  56         FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
  57         FEATURE_MASK(FEATURE_FCLK_DPM_BIT)       | \
  58         FEATURE_MASK(FEATURE_LCLK_DPM_BIT)       | \
  59         FEATURE_MASK(FEATURE_GFX_DPM_BIT)        | \
  60         FEATURE_MASK(FEATURE_VCN_DPM_BIT)        | \
  61         FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)     | \
  62         FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \
  63         FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \
  64         FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT))
  65
  66 static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
  67         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  68         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  69         MSG_MAP(PowerDownVcn,                    PPSMC_MSG_PowerDownVcn,                        1),
  70         MSG_MAP(PowerUpVcn,                 PPSMC_MSG_PowerUpVcn,               1),
  71         MSG_MAP(SetHardMinVcn,                   PPSMC_MSG_SetHardMinVcn,                       1),
  72         MSG_MAP(SetSoftMinGfxclk,                     PPSMC_MSG_SetSoftMinGfxclk,                       1),
  73         MSG_MAP(Spare0,                  PPSMC_MSG_Spare0,              1),
  74         MSG_MAP(GfxDeviceDriverReset,            PPSMC_MSG_GfxDeviceDriverReset,                1),
  75         MSG_MAP(SetDriverDramAddrHigh,            PPSMC_MSG_SetDriverDramAddrHigh,      1),
  76         MSG_MAP(SetDriverDramAddrLow,          PPSMC_MSG_SetDriverDramAddrLow,  1),
  77         MSG_MAP(TransferTableSmu2Dram,           PPSMC_MSG_TransferTableSmu2Dram,               1),
  78         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        1),
  79         MSG_MAP(GetGfxclkFrequency,          PPSMC_MSG_GetGfxclkFrequency,      1),
  80         MSG_MAP(GetEnabledSmuFeatures,           PPSMC_MSG_GetEnabledSmuFeatures,               1),
  81         MSG_MAP(SetSoftMaxVcn,          PPSMC_MSG_SetSoftMaxVcn,        1),
  82         MSG_MAP(PowerDownJpeg,         PPSMC_MSG_PowerDownJpeg, 1),
  83         MSG_MAP(PowerUpJpeg,                  PPSMC_MSG_PowerUpJpeg,            1),
  84         MSG_MAP(SetSoftMaxGfxClk,             PPSMC_MSG_SetSoftMaxGfxClk,               1),
  85         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,             1),
  86         MSG_MAP(AllowGfxOff,               PPSMC_MSG_AllowGfxOff,               1),
  87         MSG_MAP(DisallowGfxOff,               PPSMC_MSG_DisallowGfxOff,         1),
  88         MSG_MAP(SetSoftMinVcn,         PPSMC_MSG_SetSoftMinVcn, 1),
  89         MSG_MAP(GetDriverIfVersion,           PPSMC_MSG_GetDriverIfVersion,             1),
  90         MSG_MAP(PrepareMp1ForUnload,                  PPSMC_MSG_PrepareMp1ForUnload,            1),
  91 };
  92
  93 static struct cmn2asic_mapping smu_v13_0_5_feature_mask_map[SMU_FEATURE_COUNT] = {
  94         FEA_MAP(DATA_CALCULATION),
  95         FEA_MAP(PPT),
  96         FEA_MAP(TDC),
  97         FEA_MAP(THERMAL),
  98         FEA_MAP(PROCHOT),
  99         FEA_MAP(CCLK_DPM),
 100         FEA_MAP_REVERSE(FCLK),
 101         FEA_MAP(LCLK_DPM),
 102         FEA_MAP(DF_CSTATES),
 103         FEA_MAP(FAN_CONTROLLER),
 104         FEA_MAP(CPPC),
 105         FEA_MAP_HALF_REVERSE(GFX),
 106         FEA_MAP(DS_GFXCLK),
 107         FEA_MAP(S0I3),
 108         FEA_MAP(VCN_DPM),
 109         FEA_MAP(DS_VCN),
 110         FEA_MAP(DCFCLK_DPM),
 111         FEA_MAP(ATHUB_PG),
 112         FEA_MAP_REVERSE(SOCCLK),
 113         FEA_MAP(SHUBCLK_DPM),
 114         FEA_MAP(GFXOFF),
 115 };
 116
 117 static struct cmn2asic_mapping smu_v13_0_5_table_map[SMU_TABLE_COUNT] = {
 118         TAB_MAP_VALID(WATERMARKS),
 119         TAB_MAP_VALID(SMU_METRICS),
 120         TAB_MAP_VALID(CUSTOM_DPM),
 121         TAB_MAP_VALID(DPMCLOCKS),
 122 };
 123
 124 static int smu_v13_0_5_init_smc_tables(struct smu_context *smu)
 125 {
 126         struct smu_table_context *smu_table = &smu->smu_table;
 127         struct smu_table *tables = smu_table->tables;
 128
 129         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 130                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 131         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
 132                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 133         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 134                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 135
 136         smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
 137         if (!smu_table->clocks_table)
 138                 goto err0_out;
 139
 140         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 141         if (!smu_table->metrics_table)
 142                 goto err1_out;
 143         smu_table->metrics_time = 0;
 144
 145         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 146         if (!smu_table->watermarks_table)
 147                 goto err2_out;
 148
 149         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
 150         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 151         if (!smu_table->gpu_metrics_table)
 152                 goto err3_out;
 153
 154         return 0;
 155
 156 err3_out:
 157         kfree(smu_table->watermarks_table);
 158 err2_out:
 159         kfree(smu_table->metrics_table);
 160 err1_out:
 161         kfree(smu_table->clocks_table);
 162 err0_out:
 163         return -ENOMEM;
 164 }
 165
 166 static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu)
 167 {
 168         struct smu_table_context *smu_table = &smu->smu_table;
 169
 170         kfree(smu_table->clocks_table);
 171         smu_table->clocks_table = NULL;
 172
 173         kfree(smu_table->metrics_table);
 174         smu_table->metrics_table = NULL;
 175
 176         kfree(smu_table->watermarks_table);
 177         smu_table->watermarks_table = NULL;
 178
 179         kfree(smu_table->gpu_metrics_table);
 180         smu_table->gpu_metrics_table = NULL;
 181
 182         return 0;
 183 }
 184
 185 static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
 186 {
 187         struct amdgpu_device *adev = smu->adev;
 188         int ret = 0;
 189
 190         if (!en && !adev->in_s0ix)
 191                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
 192
 193         return ret;
 194 }
 195
 196 static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 197 {
 198         int ret = 0;
 199
 200         /* vcn dpm on is a prerequisite for vcn power gate messages */
 201         if (enable)
 202                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 203                                                       0, NULL);
 204         else
 205                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 206                                                       0, NULL);
 207
 208         return ret;
 209 }
 210
 211 static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 212 {
 213         int ret = 0;
 214
 215         if (enable)
 216                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
 217                                                       0, NULL);
 218         else
 219                 ret = smu_cmn_send_smc_msg_with_param(smu,
 220                                                       SMU_MSG_PowerDownJpeg, 0,
 221                                                       NULL);
 222
 223         return ret;
 224 }
 225
 226
 227 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
 228 {
 229         int ret = 0;
 230         uint64_t feature_enabled;
 231
 232         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 233
 234         if (ret)
 235                 return false;
 236
 237         return !!(feature_enabled & SMC_DPM_FEATURE);
 238 }
 239
 240 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
 241 {
 242         int ret = 0;
 243
 244         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
 245         if (ret)
 246                 dev_err(smu->adev->dev, "Failed to mode reset!\n");
 247
 248         return ret;
 249 }
 250
 251 static int smu_v13_0_5_mode2_reset(struct smu_context *smu)
 252 {
 253         return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2);
 254 }
 255
 256 static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
 257                                                         MetricsMember_t member,
 258                                                         uint32_t *value)
 259 {
 260         struct smu_table_context *smu_table = &smu->smu_table;
 261
 262         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 263         int ret = 0;
 264
 265         ret = smu_cmn_get_metrics_table(smu, NULL, false);
 266         if (ret)
 267                 return ret;
 268
 269         switch (member) {
 270         case METRICS_AVERAGE_GFXCLK:
 271                 *value = metrics->GfxclkFrequency;
 272                 break;
 273         case METRICS_AVERAGE_SOCCLK:
 274                 *value = metrics->SocclkFrequency;
 275                 break;
 276         case METRICS_AVERAGE_VCLK:
 277                 *value = metrics->VclkFrequency;
 278                 break;
 279         case METRICS_AVERAGE_DCLK:
 280                 *value = metrics->DclkFrequency;
 281                 break;
 282         case METRICS_AVERAGE_UCLK:
 283                 *value = metrics->MemclkFrequency;
 284                 break;
 285         case METRICS_AVERAGE_GFXACTIVITY:
 286                 *value = metrics->GfxActivity / 100;
 287                 break;
 288         case METRICS_AVERAGE_VCNACTIVITY:
 289                 *value = metrics->UvdActivity;
 290                 break;
 291         case METRICS_CURR_SOCKETPOWER:
 292                 *value = (metrics->CurrentSocketPower << 8) / 1000;
 293                 break;
 294         case METRICS_TEMPERATURE_EDGE:
 295                 *value = metrics->GfxTemperature / 100 *
 296                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 297                 break;
 298         case METRICS_TEMPERATURE_HOTSPOT:
 299                 *value = metrics->SocTemperature / 100 *
 300                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 301                 break;
 302         case METRICS_THROTTLER_STATUS:
 303                 *value = metrics->ThrottlerStatus;
 304                 break;
 305         case METRICS_VOLTAGE_VDDGFX:
 306                 *value = metrics->Voltage[0];
 307                 break;
 308         case METRICS_VOLTAGE_VDDSOC:
 309                 *value = metrics->Voltage[1];
 310                 break;
 311         default:
 312                 *value = UINT_MAX;
 313                 break;
 314         }
 315
 316         return ret;
 317 }
 318
 319 static int smu_v13_0_5_read_sensor(struct smu_context *smu,
 320                                         enum amd_pp_sensors sensor,
 321                                         void *data, uint32_t *size)
 322 {
 323         int ret = 0;
 324
 325         if (!data || !size)
 326                 return -EINVAL;
 327
 328         switch (sensor) {
 329         case AMDGPU_PP_SENSOR_GPU_LOAD:
 330                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 331                                                                 METRICS_AVERAGE_GFXACTIVITY,
 332                                                                 (uint32_t *)data);
 333                 *size = 4;
 334                 break;
 335         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
 336                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 337                                                                 METRICS_CURR_SOCKETPOWER,
 338                                                                 (uint32_t *)data);
 339                 *size = 4;
 340                 break;
 341         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 342                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 343                                                                 METRICS_TEMPERATURE_EDGE,
 344                                                                 (uint32_t *)data);
 345                 *size = 4;
 346                 break;
 347         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 348                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 349                                                                 METRICS_TEMPERATURE_HOTSPOT,
 350                                                                 (uint32_t *)data);
 351                 *size = 4;
 352                 break;
 353         case AMDGPU_PP_SENSOR_GFX_MCLK:
 354                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 355                                                                 METRICS_AVERAGE_UCLK,
 356                                                                 (uint32_t *)data);
 357                 *(uint32_t *)data *= 100;
 358                 *size = 4;
 359                 break;
 360         case AMDGPU_PP_SENSOR_GFX_SCLK:
 361                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 362                                                                 METRICS_AVERAGE_GFXCLK,
 363                                                                 (uint32_t *)data);
 364                 *(uint32_t *)data *= 100;
 365                 *size = 4;
 366                 break;
 367         case AMDGPU_PP_SENSOR_VDDGFX:
 368                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 369                                                                 METRICS_VOLTAGE_VDDGFX,
 370                                                                 (uint32_t *)data);
 371                 *size = 4;
 372                 break;
 373         case AMDGPU_PP_SENSOR_VDDNB:
 374                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 375                                                                 METRICS_VOLTAGE_VDDSOC,
 376                                                                 (uint32_t *)data);
 377                 *size = 4;
 378                 break;
 379         case AMDGPU_PP_SENSOR_SS_APU_SHARE:
 380                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 381                                                        METRICS_SS_APU_SHARE,
 382                                                        (uint32_t *)data);
 383                 *size = 4;
 384                 break;
 385         case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
 386                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 387                                                        METRICS_SS_DGPU_SHARE,
 388                                                        (uint32_t *)data);
 389                 *size = 4;
 390                 break;
 391         case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
 392         default:
 393                 ret = -EOPNOTSUPP;
 394                 break;
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu,
 401                                 struct pp_smu_wm_range_sets *clock_ranges)
 402 {
 403         int i;
 404         int ret = 0;
 405         Watermarks_t *table = smu->smu_table.watermarks_table;
 406
 407         if (!table || !clock_ranges)
 408                 return -EINVAL;
 409
 410         if (clock_ranges) {
 411                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
 412                         clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
 413                         return -EINVAL;
 414
 415                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
 416                         table->WatermarkRow[WM_DCFCLK][i].MinClock =
 417                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
 418                         table->WatermarkRow[WM_DCFCLK][i].MaxClock =
 419                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
 420                         table->WatermarkRow[WM_DCFCLK][i].MinMclk =
 421                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
 422                         table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
 423                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
 424
 425                         table->WatermarkRow[WM_DCFCLK][i].WmSetting =
 426                                 clock_ranges->reader_wm_sets[i].wm_inst;
 427                 }
 428
 429                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
 430                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
 431                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
 432                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
 433                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
 434                         table->WatermarkRow[WM_SOCCLK][i].MinMclk =
 435                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
 436                         table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
 437                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
 438
 439                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
 440                                 clock_ranges->writer_wm_sets[i].wm_inst;
 441                 }
 442
 443                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
 444         }
 445
 446         /* pass data to smu controller */
 447         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 448              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 449                 ret = smu_cmn_write_watermarks_table(smu);
 450                 if (ret) {
 451                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
 452                         return ret;
 453                 }
 454                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
 461                                                 void **table)
 462 {
 463         struct smu_table_context *smu_table = &smu->smu_table;
 464         struct gpu_metrics_v2_1 *gpu_metrics =
 465                 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
 466         SmuMetrics_t metrics;
 467         int ret = 0;
 468
 469         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
 470         if (ret)
 471                 return ret;
 472
 473         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
 474
 475         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
 476         gpu_metrics->temperature_soc = metrics.SocTemperature;
 477
 478         gpu_metrics->average_gfx_activity = metrics.GfxActivity;
 479         gpu_metrics->average_mm_activity = metrics.UvdActivity;
 480
 481         gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
 482         gpu_metrics->average_gfx_power = metrics.Power[0];
 483         gpu_metrics->average_soc_power = metrics.Power[1];
 484         gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
 485         gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
 486         gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
 487         gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
 488         gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
 489         gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
 490         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
 491         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 492
 493         *table = (void *)gpu_metrics;
 494
 495         return sizeof(struct gpu_metrics_v2_1);
 496 }
 497
 498 static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu)
 499 {
 500         struct smu_table_context *smu_table = &smu->smu_table;
 501
 502         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
 503 }
 504
 505 static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
 506                                         long input[], uint32_t size)
 507 {
 508         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
 509         int ret = 0;
 510
 511         /* Only allowed in manual mode */
 512         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
 513                 return -EINVAL;
 514
 515         switch (type) {
 516         case PP_OD_EDIT_SCLK_VDDC_TABLE:
 517                 if (size != 2) {
 518                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 519                         return -EINVAL;
 520                 }
 521
 522                 if (input[0] == 0) {
 523                         if (input[1] < smu->gfx_default_hard_min_freq) {
 524                                 dev_warn(smu->adev->dev,
 525                                         "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
 526                                         input[1], smu->gfx_default_hard_min_freq);
 527                                 return -EINVAL;
 528                         }
 529                         smu->gfx_actual_hard_min_freq = input[1];
 530                 } else if (input[0] == 1) {
 531                         if (input[1] > smu->gfx_default_soft_max_freq) {
 532                                 dev_warn(smu->adev->dev,
 533                                         "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
 534                                         input[1], smu->gfx_default_soft_max_freq);
 535                                 return -EINVAL;
 536                         }
 537                         smu->gfx_actual_soft_max_freq = input[1];
 538                 } else {
 539                         return -EINVAL;
 540                 }
 541                 break;
 542         case PP_OD_RESTORE_DEFAULT_TABLE:
 543                 if (size != 0) {
 544                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 545                         return -EINVAL;
 546                 } else {
 547                         smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 548                         smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 549                 }
 550                 break;
 551         case PP_OD_COMMIT_DPM_TABLE:
 552                 if (size != 0) {
 553                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 554                         return -EINVAL;
 555                 } else {
 556                         if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
 557                                 dev_err(smu->adev->dev,
 558                                         "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
 559                                         smu->gfx_actual_hard_min_freq,
 560                                         smu->gfx_actual_soft_max_freq);
 561                                 return -EINVAL;
 562                         }
 563
 564                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
 565                                                                         smu->gfx_actual_hard_min_freq, NULL);
 566                         if (ret) {
 567                                 dev_err(smu->adev->dev, "Set hard min sclk failed!");
 568                                 return ret;
 569                         }
 570
 571                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
 572                                                                         smu->gfx_actual_soft_max_freq, NULL);
 573                         if (ret) {
 574                                 dev_err(smu->adev->dev, "Set soft max sclk failed!");
 575                                 return ret;
 576                         }
 577                 }
 578                 break;
 579         default:
 580                 return -ENOSYS;
 581         }
 582
 583         return ret;
 584 }
 585
 586 static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
 587                                                 enum smu_clk_type clk_type,
 588                                                 uint32_t *value)
 589 {
 590         MetricsMember_t member_type;
 591
 592         switch (clk_type) {
 593         case SMU_SOCCLK:
 594                 member_type = METRICS_AVERAGE_SOCCLK;
 595                 break;
 596         case SMU_VCLK:
 597             member_type = METRICS_AVERAGE_VCLK;
 598                 break;
 599         case SMU_DCLK:
 600                 member_type = METRICS_AVERAGE_DCLK;
 601                 break;
 602         case SMU_MCLK:
 603                 member_type = METRICS_AVERAGE_UCLK;
 604                 break;
 605         case SMU_GFXCLK:
 606         case SMU_SCLK:
 607                 return smu_cmn_send_smc_msg_with_param(smu,
 608                                 SMU_MSG_GetGfxclkFrequency, 0, value);
 609                 break;
 610         default:
 611                 return -EINVAL;
 612         }
 613
 614         return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value);
 615 }
 616
 617 static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu,
 618                                                 enum smu_clk_type clk_type,
 619                                                 uint32_t *count)
 620 {
 621         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 622
 623         switch (clk_type) {
 624         case SMU_SOCCLK:
 625                 *count = clk_table->NumSocClkLevelsEnabled;
 626                 break;
 627         case SMU_VCLK:
 628                 *count = clk_table->VcnClkLevelsEnabled;
 629                 break;
 630         case SMU_DCLK:
 631                 *count = clk_table->VcnClkLevelsEnabled;
 632                 break;
 633         case SMU_MCLK:
 634                 *count = clk_table->NumDfPstatesEnabled;
 635                 break;
 636         case SMU_FCLK:
 637                 *count = clk_table->NumDfPstatesEnabled;
 638                 break;
 639         default:
 640                 break;
 641         }
 642
 643         return 0;
 644 }
 645
 646 static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu,
 647                                                 enum smu_clk_type clk_type,
 648                                                 uint32_t dpm_level,
 649                                                 uint32_t *freq)
 650 {
 651         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 652
 653         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 654                 return -EINVAL;
 655
 656         switch (clk_type) {
 657         case SMU_SOCCLK:
 658                 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
 659                         return -EINVAL;
 660                 *freq = clk_table->SocClocks[dpm_level];
 661                 break;
 662         case SMU_VCLK:
 663                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 664                         return -EINVAL;
 665                 *freq = clk_table->VClocks[dpm_level];
 666                 break;
 667         case SMU_DCLK:
 668                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 669                         return -EINVAL;
 670                 *freq = clk_table->DClocks[dpm_level];
 671                 break;
 672         case SMU_UCLK:
 673         case SMU_MCLK:
 674                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 675                         return -EINVAL;
 676                 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
 677                 break;
 678         case SMU_FCLK:
 679                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 680                         return -EINVAL;
 681                 *freq = clk_table->DfPstateTable[dpm_level].FClk;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686
 687         return 0;
 688 }
 689
 690 static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu,
 691                                                 enum smu_clk_type clk_type)
 692 {
 693         enum smu_feature_mask feature_id = 0;
 694
 695         switch (clk_type) {
 696         case SMU_MCLK:
 697         case SMU_UCLK:
 698         case SMU_FCLK:
 699                 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
 700                 break;
 701         case SMU_GFXCLK:
 702         case SMU_SCLK:
 703                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 704                 break;
 705         case SMU_SOCCLK:
 706                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 707                 break;
 708         case SMU_VCLK:
 709         case SMU_DCLK:
 710                 feature_id = SMU_FEATURE_VCN_DPM_BIT;
 711                 break;
 712         default:
 713                 return true;
 714         }
 715
 716         return smu_cmn_feature_is_enabled(smu, feature_id);
 717 }
 718
 719 static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu,
 720                                                         enum smu_clk_type clk_type,
 721                                                         uint32_t *min,
 722                                                         uint32_t *max)
 723 {
 724         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 725         uint32_t clock_limit;
 726         uint32_t max_dpm_level, min_dpm_level;
 727         int ret = 0;
 728
 729         if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
 730                 switch (clk_type) {
 731                 case SMU_MCLK:
 732                 case SMU_UCLK:
 733                         clock_limit = smu->smu_table.boot_values.uclk;
 734                         break;
 735                 case SMU_FCLK:
 736                         clock_limit = smu->smu_table.boot_values.fclk;
 737                         break;
 738                 case SMU_GFXCLK:
 739                 case SMU_SCLK:
 740                         clock_limit = smu->smu_table.boot_values.gfxclk;
 741                         break;
 742                 case SMU_SOCCLK:
 743                         clock_limit = smu->smu_table.boot_values.socclk;
 744                         break;
 745                 case SMU_VCLK:
 746                         clock_limit = smu->smu_table.boot_values.vclk;
 747                         break;
 748                 case SMU_DCLK:
 749                         clock_limit = smu->smu_table.boot_values.dclk;
 750                         break;
 751                 default:
 752                         clock_limit = 0;
 753                         break;
 754                 }
 755
 756                 /* clock in Mhz unit */
 757                 if (min)
 758                         *min = clock_limit / 100;
 759                 if (max)
 760                         *max = clock_limit / 100;
 761
 762                 return 0;
 763         }
 764
 765         if (max) {
 766                 switch (clk_type) {
 767                 case SMU_GFXCLK:
 768                 case SMU_SCLK:
 769                         *max = clk_table->MaxGfxClk;
 770                         break;
 771                 case SMU_MCLK:
 772                 case SMU_UCLK:
 773                 case SMU_FCLK:
 774                         max_dpm_level = 0;
 775                         break;
 776                 case SMU_SOCCLK:
 777                         max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
 778                         break;
 779                 case SMU_VCLK:
 780                 case SMU_DCLK:
 781                         max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
 782                         break;
 783                 default:
 784                         ret = -EINVAL;
 785                         goto failed;
 786                 }
 787
 788                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 789                         ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
 790                         if (ret)
 791                                 goto failed;
 792                 }
 793         }
 794
 795         if (min) {
 796                 switch (clk_type) {
 797                 case SMU_GFXCLK:
 798                 case SMU_SCLK:
 799                         *min = clk_table->MinGfxClk;
 800                         break;
 801                 case SMU_MCLK:
 802                 case SMU_UCLK:
 803                 case SMU_FCLK:
 804                         min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
 805                         break;
 806                 case SMU_SOCCLK:
 807                         min_dpm_level = 0;
 808                         break;
 809                 case SMU_VCLK:
 810                 case SMU_DCLK:
 811                         min_dpm_level = 0;
 812                         break;
 813                 default:
 814                         ret = -EINVAL;
 815                         goto failed;
 816                 }
 817
 818                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 819                         ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
 820                         if (ret)
 821                                 goto failed;
 822                 }
 823         }
 824
 825 failed:
 826         return ret;
 827 }
 828
 829 static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
 830                                                         enum smu_clk_type clk_type,
 831                                                         uint32_t min,
 832                                                         uint32_t max)
 833 {
 834         enum smu_message_type msg_set_min, msg_set_max;
 835         uint32_t min_clk = min;
 836         uint32_t max_clk = max;
 837         int ret = 0;
 838
 839         if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
 840                 return -EINVAL;
 841
 842         switch (clk_type) {
 843         case SMU_GFXCLK:
 844         case SMU_SCLK:
 845                 msg_set_min = SMU_MSG_SetHardMinGfxClk;
 846                 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
 847                 break;
 848         case SMU_VCLK:
 849         case SMU_DCLK:
 850                 msg_set_min = SMU_MSG_SetHardMinVcn;
 851                 msg_set_max = SMU_MSG_SetSoftMaxVcn;
 852                 break;
 853         default:
 854                 return -EINVAL;
 855         }
 856
 857         if (clk_type == SMU_VCLK) {
 858                 min_clk = min << SMU_13_VCLK_SHIFT;
 859                 max_clk = max << SMU_13_VCLK_SHIFT;
 860         }
 861
 862         ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
 863         if (ret)
 864                 goto out;
 865
 866         ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
 867         if (ret)
 868                 goto out;
 869
 870 out:
 871         return ret;
 872 }
 873
 874 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
 875                                 enum smu_clk_type clk_type, char *buf)
 876 {
 877         int i, idx, size = 0, ret = 0;
 878         uint32_t cur_value = 0, value = 0, count = 0;
 879         uint32_t min = 0, max = 0;
 880
 881         smu_cmn_get_sysfs_buf(&buf, &size);
 882
 883         switch (clk_type) {
 884         case SMU_OD_SCLK:
 885                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
 886                 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 887                 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
 888                 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 889                 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
 890                 break;
 891         case SMU_OD_RANGE:
 892                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
 893                 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
 894                                                 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
 895                 break;
 896         case SMU_SOCCLK:
 897         case SMU_VCLK:
 898         case SMU_DCLK:
 899         case SMU_MCLK:
 900                 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
 901                 if (ret)
 902                         goto print_clk_out;
 903
 904                 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);
 905                 if (ret)
 906                         goto print_clk_out;
 907
 908                 for (i = 0; i < count; i++) {
 909                         idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
 910                         ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value);
 911                         if (ret)
 912                                 goto print_clk_out;
 913
 914                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
 915                                         cur_value == value ? "*" : "");
 916                 }
 917                 break;
 918         case SMU_GFXCLK:
 919         case SMU_SCLK:
 920                 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
 921                 if (ret)
 922                         goto print_clk_out;
 923                 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
 924                 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
 925                 if (cur_value  == max)
 926                         i = 2;
 927                 else if (cur_value == min)
 928                         i = 0;
 929                 else
 930                         i = 1;
 931                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
 932                                 i == 0 ? "*" : "");
 933                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
 934                                 i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK,
 935                                 i == 1 ? "*" : "");
 936                 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
 937                                 i == 2 ? "*" : "");
 938                 break;
 939         default:
 940                 break;
 941         }
 942
 943 print_clk_out:
 944         return size;
 945 }
 946
 947
 948 static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
 949                                 enum smu_clk_type clk_type, uint32_t mask)
 950 {
 951         uint32_t soft_min_level = 0, soft_max_level = 0;
 952         uint32_t min_freq = 0, max_freq = 0;
 953         int ret = 0;
 954
 955         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 956         soft_max_level = mask ? (fls(mask) - 1) : 0;
 957
 958         switch (clk_type) {
 959         case SMU_VCLK:
 960         case SMU_DCLK:
 961                 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 962                 if (ret)
 963                         goto force_level_out;
 964
 965                 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 966                 if (ret)
 967                         goto force_level_out;
 968
 969                 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
 970                 if (ret)
 971                         goto force_level_out;
 972                 break;
 973         default:
 974                 ret = -EINVAL;
 975                 break;
 976         }
 977
 978 force_level_out:
 979         return ret;
 980 }
 981
 982 static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,
 983                                         enum amd_dpm_forced_level level,
 984                                         enum smu_clk_type clk_type,
 985                                         uint32_t *min_clk,
 986                                         uint32_t *max_clk)
 987 {
 988         int ret = 0;
 989         uint32_t clk_limit = 0;
 990
 991         switch (clk_type) {
 992         case SMU_GFXCLK:
 993         case SMU_SCLK:
 994                 clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK;
 995                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
 996                         smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
 997                 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
 998                         smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
 999                 break;
1000         case SMU_VCLK:
1001                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
1002                 break;
1003         case SMU_DCLK:
1004                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
1005                 break;
1006         default:
1007                 ret = -EINVAL;
1008                 break;
1009         }
1010         *min_clk = *max_clk = clk_limit;
1011         return ret;
1012 }
1013
1014 static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
1015                                                 enum amd_dpm_forced_level level)
1016 {
1017         struct amdgpu_device *adev = smu->adev;
1018         uint32_t sclk_min = 0, sclk_max = 0;
1019         uint32_t vclk_min = 0, vclk_max = 0;
1020         uint32_t dclk_min = 0, dclk_max = 0;
1021         int ret = 0;
1022
1023         switch (level) {
1024         case AMD_DPM_FORCED_LEVEL_HIGH:
1025                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1026                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1027                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
1028                 sclk_min = sclk_max;
1029                 vclk_min = vclk_max;
1030                 dclk_min = dclk_max;
1031                 break;
1032         case AMD_DPM_FORCED_LEVEL_LOW:
1033                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1034                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1035                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
1036                 sclk_max = sclk_min;
1037                 vclk_max = vclk_min;
1038                 dclk_max = dclk_min;
1039                 break;
1040         case AMD_DPM_FORCED_LEVEL_AUTO:
1041                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1042                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1043                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
1044                 break;
1045         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1046         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1047         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1048                 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1049                 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1050                 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
1051                 break;
1052         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1053                 dev_err(adev->dev, "The performance level profile_min_mclk is not supported.");
1054                 return -EOPNOTSUPP;
1055         case AMD_DPM_FORCED_LEVEL_MANUAL:
1056         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1057                 return 0;
1058         default:
1059                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1060                 return -EINVAL;
1061         }
1062
1063         if (sclk_min && sclk_max && smu_v13_0_5_clk_dpm_is_enabled(smu, SMU_SCLK)) {
1064                 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1065                                                             SMU_SCLK,
1066                                                             sclk_min,
1067                                                             sclk_max);
1068                 if (ret)
1069                         return ret;
1070
1071                 smu->gfx_actual_hard_min_freq = sclk_min;
1072                 smu->gfx_actual_soft_max_freq = sclk_max;
1073         }
1074
1075         if (vclk_min && vclk_max) {
1076                 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1077                                                               SMU_VCLK,
1078                                                               vclk_min,
1079                                                               vclk_max);
1080                 if (ret)
1081                         return ret;
1082         }
1083
1084         if (dclk_min && dclk_max) {
1085                 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1086                                                               SMU_DCLK,
1087                                                               dclk_min,
1088                                                               dclk_max);
1089                 if (ret)
1090                         return ret;
1091         }
1092         return ret;
1093 }
1094
1095 static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1096 {
1097         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1098
1099         smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1100         smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1101         smu->gfx_actual_hard_min_freq = 0;
1102         smu->gfx_actual_soft_max_freq = 0;
1103
1104         return 0;
1105 }
1106
1107 static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
1108         .check_fw_status = smu_v13_0_check_fw_status,
1109         .check_fw_version = smu_v13_0_check_fw_version,
1110         .init_smc_tables = smu_v13_0_5_init_smc_tables,
1111         .fini_smc_tables = smu_v13_0_5_fini_smc_tables,
1112         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1113         .system_features_control = smu_v13_0_5_system_features_control,
1114         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1115         .send_smc_msg = smu_cmn_send_smc_msg,
1116         .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable,
1117         .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable,
1118         .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables,
1119         .read_sensor = smu_v13_0_5_read_sensor,
1120         .is_dpm_running = smu_v13_0_5_is_dpm_running,
1121         .set_watermarks_table = smu_v13_0_5_set_watermarks_table,
1122         .get_gpu_metrics = smu_v13_0_5_get_gpu_metrics,
1123         .get_enabled_mask = smu_cmn_get_enabled_mask,
1124         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1125         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1126         .gfx_off_control = smu_v13_0_gfx_off_control,
1127         .mode2_reset = smu_v13_0_5_mode2_reset,
1128         .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq,
1129         .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table,
1130         .print_clk_levels = smu_v13_0_5_print_clk_levels,
1131         .force_clk_levels = smu_v13_0_5_force_clk_levels,
1132         .set_performance_level = smu_v13_0_5_set_performance_level,
1133         .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters,
1134 };
1135
1136 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
1137 {
1138         struct amdgpu_device *adev = smu->adev;
1139
1140         smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
1141         smu->message_map = smu_v13_0_5_message_map;
1142         smu->feature_map = smu_v13_0_5_feature_mask_map;
1143         smu->table_map = smu_v13_0_5_table_map;
1144         smu->is_apu = true;
1145         smu->smc_driver_if_version = SMU13_0_5_DRIVER_IF_VERSION;
1146         smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
1147         smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
1148         smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
1149 }