drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_v13_0.h"
  29 #include "smu13_driver_if_v13_0_5.h"
  30 #include "smu_v13_0_5_ppt.h"
  31 #include "smu_v13_0_5_ppsmc.h"
  32 #include "smu_v13_0_5_pmfw.h"
  33 #include "smu_cmn.h"
  34
  35 /*
  36  * DO NOT use these for err/warn/info/debug messages.
  37  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  38  * They are more MGPU friendly.
  39  */
  40 #undef pr_err
  41 #undef pr_warn
  42 #undef pr_info
  43 #undef pr_debug
  44
  45 #define mmMP1_C2PMSG_2                                                                            (0xbee142 + 0xb00000 / 4)
  46 #define mmMP1_C2PMSG_2_BASE_IDX                                                                   0
  47
  48 #define mmMP1_C2PMSG_34                                                                           (0xbee262 + 0xb00000 / 4)
  49 #define mmMP1_C2PMSG_34_BASE_IDX                                                                   0
  50
  51 #define mmMP1_C2PMSG_33                                                                                (0xbee261 + 0xb00000 / 4)
  52 #define mmMP1_C2PMSG_33_BASE_IDX                                                                   0
  53
  54 #define FEATURE_MASK(feature) (1ULL << feature)
  55 #define SMC_DPM_FEATURE ( \
  56         FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
  57         FEATURE_MASK(FEATURE_FCLK_DPM_BIT)       | \
  58         FEATURE_MASK(FEATURE_LCLK_DPM_BIT)       | \
  59         FEATURE_MASK(FEATURE_GFX_DPM_BIT)        | \
  60         FEATURE_MASK(FEATURE_VCN_DPM_BIT)        | \
  61         FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)     | \
  62         FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \
  63         FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \
  64         FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT))
  65
  66 static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
  67         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  68         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  69         MSG_MAP(PowerDownVcn,                    PPSMC_MSG_PowerDownVcn,                        1),
  70         MSG_MAP(PowerUpVcn,                 PPSMC_MSG_PowerUpVcn,               1),
  71         MSG_MAP(SetHardMinVcn,                   PPSMC_MSG_SetHardMinVcn,                       1),
  72         MSG_MAP(SetSoftMinGfxclk,                     PPSMC_MSG_SetSoftMinGfxclk,                       1),
  73         MSG_MAP(Spare0,                  PPSMC_MSG_Spare0,              1),
  74         MSG_MAP(GfxDeviceDriverReset,            PPSMC_MSG_GfxDeviceDriverReset,                1),
  75         MSG_MAP(SetDriverDramAddrHigh,            PPSMC_MSG_SetDriverDramAddrHigh,      1),
  76         MSG_MAP(SetDriverDramAddrLow,          PPSMC_MSG_SetDriverDramAddrLow,  1),
  77         MSG_MAP(TransferTableSmu2Dram,           PPSMC_MSG_TransferTableSmu2Dram,               1),
  78         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu ,       1),
  79         MSG_MAP(GetGfxclkFrequency,          PPSMC_MSG_GetGfxclkFrequency,      1),
  80         MSG_MAP(GetEnabledSmuFeatures,           PPSMC_MSG_GetEnabledSmuFeatures,               1),
  81         MSG_MAP(SetSoftMaxVcn,          PPSMC_MSG_SetSoftMaxVcn,        1),
  82         MSG_MAP(PowerDownJpeg,         PPSMC_MSG_PowerDownJpeg, 1),
  83         MSG_MAP(PowerUpJpeg,                  PPSMC_MSG_PowerUpJpeg,            1),
  84         MSG_MAP(SetSoftMaxGfxClk,             PPSMC_MSG_SetSoftMaxGfxClk,               1),
  85         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,             1),
  86         MSG_MAP(AllowGfxOff,               PPSMC_MSG_AllowGfxOff,               1),
  87         MSG_MAP(DisallowGfxOff,               PPSMC_MSG_DisallowGfxOff,         1),
  88         MSG_MAP(SetSoftMinVcn,         PPSMC_MSG_SetSoftMinVcn, 1),
  89         MSG_MAP(GetDriverIfVersion,           PPSMC_MSG_GetDriverIfVersion,             1),
  90         MSG_MAP(PrepareMp1ForUnload,                  PPSMC_MSG_PrepareMp1ForUnload,            1),
  91 };
  92
  93 static struct cmn2asic_mapping smu_v13_0_5_feature_mask_map[SMU_FEATURE_COUNT] = {
  94         FEA_MAP(DATA_CALCULATION),
  95         FEA_MAP(PPT),
  96         FEA_MAP(TDC),
  97         FEA_MAP(THERMAL),
  98         FEA_MAP(PROCHOT),
  99         FEA_MAP(CCLK_DPM),
 100         FEA_MAP_REVERSE(FCLK),
 101         FEA_MAP(LCLK_DPM),
 102         FEA_MAP(DF_CSTATES),
 103         FEA_MAP(FAN_CONTROLLER),
 104         FEA_MAP(CPPC),
 105         FEA_MAP_HALF_REVERSE(GFX),
 106         FEA_MAP(DS_GFXCLK),
 107         FEA_MAP(S0I3),
 108         FEA_MAP(VCN_DPM),
 109         FEA_MAP(DS_VCN),
 110         FEA_MAP(DCFCLK_DPM),
 111         FEA_MAP(ATHUB_PG),
 112         FEA_MAP_REVERSE(SOCCLK),
 113         FEA_MAP(SHUBCLK_DPM),
 114         FEA_MAP(GFXOFF),
 115 };
 116
 117 static struct cmn2asic_mapping smu_v13_0_5_table_map[SMU_TABLE_COUNT] = {
 118         TAB_MAP_VALID(WATERMARKS),
 119         TAB_MAP_VALID(SMU_METRICS),
 120         TAB_MAP_VALID(CUSTOM_DPM),
 121         TAB_MAP_VALID(DPMCLOCKS),
 122 };
 123
 124 static int smu_v13_0_5_init_smc_tables(struct smu_context *smu)
 125 {
 126         struct smu_table_context *smu_table = &smu->smu_table;
 127         struct smu_table *tables = smu_table->tables;
 128
 129         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 130                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 131         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
 132                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 133         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 134                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 135
 136         smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
 137         if (!smu_table->clocks_table)
 138                 goto err0_out;
 139
 140         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 141         if (!smu_table->metrics_table)
 142                 goto err1_out;
 143         smu_table->metrics_time = 0;
 144
 145         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 146         if (!smu_table->watermarks_table)
 147                 goto err2_out;
 148
 149         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
 150         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 151         if (!smu_table->gpu_metrics_table)
 152                 goto err3_out;
 153
 154         return 0;
 155
 156 err3_out:
 157         kfree(smu_table->watermarks_table);
 158 err2_out:
 159         kfree(smu_table->metrics_table);
 160 err1_out:
 161         kfree(smu_table->clocks_table);
 162 err0_out:
 163         return -ENOMEM;
 164 }
 165
 166 static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu)
 167 {
 168         struct smu_table_context *smu_table = &smu->smu_table;
 169
 170         kfree(smu_table->clocks_table);
 171         smu_table->clocks_table = NULL;
 172
 173         kfree(smu_table->metrics_table);
 174         smu_table->metrics_table = NULL;
 175
 176         kfree(smu_table->watermarks_table);
 177         smu_table->watermarks_table = NULL;
 178
 179         return 0;
 180 }
 181
 182 static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
 183 {
 184         struct amdgpu_device *adev = smu->adev;
 185         int ret = 0;
 186
 187         if (!en && !adev->in_s0ix)
 188                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
 189
 190         return ret;
 191 }
 192
 193 static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 194 {
 195         int ret = 0;
 196
 197         /* vcn dpm on is a prerequisite for vcn power gate messages */
 198         if (enable)
 199                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 200                                                       0, NULL);
 201         else
 202                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 203                                                       0, NULL);
 204
 205         return ret;
 206 }
 207
 208 static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 209 {
 210         int ret = 0;
 211
 212         if (enable)
 213                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
 214                                                       0, NULL);
 215         else
 216                 ret = smu_cmn_send_smc_msg_with_param(smu,
 217                                                       SMU_MSG_PowerDownJpeg, 0,
 218                                                       NULL);
 219
 220         return ret;
 221 }
 222
 223
 224 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
 225 {
 226         int ret = 0;
 227         uint64_t feature_enabled;
 228
 229         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 230
 231         if (ret)
 232                 return false;
 233
 234         return !!(feature_enabled & SMC_DPM_FEATURE);
 235 }
 236
 237 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
 238 {
 239         int ret = 0;
 240
 241         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
 242         if (ret)
 243                 dev_err(smu->adev->dev, "Failed to mode reset!\n");
 244
 245         return ret;
 246 }
 247
 248 static int smu_v13_0_5_mode2_reset(struct smu_context *smu)
 249 {
 250         return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2);
 251 }
 252
 253 static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
 254                                                         MetricsMember_t member,
 255                                                         uint32_t *value)
 256 {
 257         struct smu_table_context *smu_table = &smu->smu_table;
 258
 259         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 260         int ret = 0;
 261
 262         ret = smu_cmn_get_metrics_table(smu, NULL, false);
 263         if (ret)
 264                 return ret;
 265
 266         switch (member) {
 267         case METRICS_AVERAGE_GFXCLK:
 268                 *value = metrics->GfxclkFrequency;
 269                 break;
 270         case METRICS_AVERAGE_SOCCLK:
 271                 *value = metrics->SocclkFrequency;
 272                 break;
 273         case METRICS_AVERAGE_VCLK:
 274                 *value = metrics->VclkFrequency;
 275                 break;
 276         case METRICS_AVERAGE_DCLK:
 277                 *value = metrics->DclkFrequency;
 278                 break;
 279         case METRICS_AVERAGE_UCLK:
 280                 *value = metrics->MemclkFrequency;
 281                 break;
 282         case METRICS_AVERAGE_GFXACTIVITY:
 283                 *value = metrics->GfxActivity / 100;
 284                 break;
 285         case METRICS_AVERAGE_VCNACTIVITY:
 286                 *value = metrics->UvdActivity;
 287                 break;
 288         case METRICS_AVERAGE_SOCKETPOWER:
 289                 *value = (metrics->CurrentSocketPower << 8) / 1000;
 290                 break;
 291         case METRICS_TEMPERATURE_EDGE:
 292                 *value = metrics->GfxTemperature / 100 *
 293                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 294                 break;
 295         case METRICS_TEMPERATURE_HOTSPOT:
 296                 *value = metrics->SocTemperature / 100 *
 297                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 298                 break;
 299         case METRICS_THROTTLER_STATUS:
 300                 *value = metrics->ThrottlerStatus;
 301                 break;
 302         case METRICS_VOLTAGE_VDDGFX:
 303                 *value = metrics->Voltage[0];
 304                 break;
 305         case METRICS_VOLTAGE_VDDSOC:
 306                 *value = metrics->Voltage[1];
 307                 break;
 308         default:
 309                 *value = UINT_MAX;
 310                 break;
 311         }
 312
 313         return ret;
 314 }
 315
 316 static int smu_v13_0_5_read_sensor(struct smu_context *smu,
 317                                         enum amd_pp_sensors sensor,
 318                                         void *data, uint32_t *size)
 319 {
 320         int ret = 0;
 321
 322         if (!data || !size)
 323                 return -EINVAL;
 324
 325         switch (sensor) {
 326         case AMDGPU_PP_SENSOR_GPU_LOAD:
 327                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 328                                                                 METRICS_AVERAGE_GFXACTIVITY,
 329                                                                 (uint32_t *)data);
 330                 *size = 4;
 331                 break;
 332         case AMDGPU_PP_SENSOR_GPU_POWER:
 333                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 334                                                                 METRICS_AVERAGE_SOCKETPOWER,
 335                                                                 (uint32_t *)data);
 336                 *size = 4;
 337                 break;
 338         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 339                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 340                                                                 METRICS_TEMPERATURE_EDGE,
 341                                                                 (uint32_t *)data);
 342                 *size = 4;
 343                 break;
 344         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 345                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 346                                                                 METRICS_TEMPERATURE_HOTSPOT,
 347                                                                 (uint32_t *)data);
 348                 *size = 4;
 349                 break;
 350         case AMDGPU_PP_SENSOR_GFX_MCLK:
 351                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 352                                                                 METRICS_AVERAGE_UCLK,
 353                                                                 (uint32_t *)data);
 354                 *(uint32_t *)data *= 100;
 355                 *size = 4;
 356                 break;
 357         case AMDGPU_PP_SENSOR_GFX_SCLK:
 358                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 359                                                                 METRICS_AVERAGE_GFXCLK,
 360                                                                 (uint32_t *)data);
 361                 *(uint32_t *)data *= 100;
 362                 *size = 4;
 363                 break;
 364         case AMDGPU_PP_SENSOR_VDDGFX:
 365                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 366                                                                 METRICS_VOLTAGE_VDDGFX,
 367                                                                 (uint32_t *)data);
 368                 *size = 4;
 369                 break;
 370         case AMDGPU_PP_SENSOR_VDDNB:
 371                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 372                                                                 METRICS_VOLTAGE_VDDSOC,
 373                                                                 (uint32_t *)data);
 374                 *size = 4;
 375                 break;
 376         case AMDGPU_PP_SENSOR_SS_APU_SHARE:
 377                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 378                                                        METRICS_SS_APU_SHARE,
 379                                                        (uint32_t *)data);
 380                 *size = 4;
 381                 break;
 382         case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
 383                 ret = smu_v13_0_5_get_smu_metrics_data(smu,
 384                                                        METRICS_SS_DGPU_SHARE,
 385                                                        (uint32_t *)data);
 386                 *size = 4;
 387                 break;
 388         default:
 389                 ret = -EOPNOTSUPP;
 390                 break;
 391         }
 392
 393         return ret;
 394 }
 395
 396 static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu,
 397                                 struct pp_smu_wm_range_sets *clock_ranges)
 398 {
 399         int i;
 400         int ret = 0;
 401         Watermarks_t *table = smu->smu_table.watermarks_table;
 402
 403         if (!table || !clock_ranges)
 404                 return -EINVAL;
 405
 406         if (clock_ranges) {
 407                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
 408                         clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
 409                         return -EINVAL;
 410
 411                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
 412                         table->WatermarkRow[WM_DCFCLK][i].MinClock =
 413                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
 414                         table->WatermarkRow[WM_DCFCLK][i].MaxClock =
 415                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
 416                         table->WatermarkRow[WM_DCFCLK][i].MinMclk =
 417                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
 418                         table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
 419                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
 420
 421                         table->WatermarkRow[WM_DCFCLK][i].WmSetting =
 422                                 clock_ranges->reader_wm_sets[i].wm_inst;
 423                 }
 424
 425                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
 426                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
 427                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
 428                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
 429                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
 430                         table->WatermarkRow[WM_SOCCLK][i].MinMclk =
 431                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
 432                         table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
 433                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
 434
 435                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
 436                                 clock_ranges->writer_wm_sets[i].wm_inst;
 437                 }
 438
 439                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
 440         }
 441
 442         /* pass data to smu controller */
 443         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 444              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 445                 ret = smu_cmn_write_watermarks_table(smu);
 446                 if (ret) {
 447                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
 448                         return ret;
 449                 }
 450                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 451         }
 452
 453         return 0;
 454 }
 455
 456 static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
 457                                                 void **table)
 458 {
 459         struct smu_table_context *smu_table = &smu->smu_table;
 460         struct gpu_metrics_v2_1 *gpu_metrics =
 461                 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
 462         SmuMetrics_t metrics;
 463         int ret = 0;
 464
 465         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
 466         if (ret)
 467                 return ret;
 468
 469         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
 470
 471         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
 472         gpu_metrics->temperature_soc = metrics.SocTemperature;
 473
 474         gpu_metrics->average_gfx_activity = metrics.GfxActivity;
 475         gpu_metrics->average_mm_activity = metrics.UvdActivity;
 476
 477         gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
 478         gpu_metrics->average_gfx_power = metrics.Power[0];
 479         gpu_metrics->average_soc_power = metrics.Power[1];
 480         gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
 481         gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
 482         gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
 483         gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
 484         gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
 485         gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
 486         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
 487         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 488
 489         *table = (void *)gpu_metrics;
 490
 491         return sizeof(struct gpu_metrics_v2_1);
 492 }
 493
 494 static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu)
 495 {
 496         struct smu_table_context *smu_table = &smu->smu_table;
 497
 498         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
 499 }
 500
 501 static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
 502                                         long input[], uint32_t size)
 503 {
 504         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
 505         int ret = 0;
 506
 507         /* Only allowed in manual mode */
 508         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
 509                 return -EINVAL;
 510
 511         switch (type) {
 512         case PP_OD_EDIT_SCLK_VDDC_TABLE:
 513                 if (size != 2) {
 514                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 515                         return -EINVAL;
 516                 }
 517
 518                 if (input[0] == 0) {
 519                         if (input[1] < smu->gfx_default_hard_min_freq) {
 520                                 dev_warn(smu->adev->dev,
 521                                         "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
 522                                         input[1], smu->gfx_default_hard_min_freq);
 523                                 return -EINVAL;
 524                         }
 525                         smu->gfx_actual_hard_min_freq = input[1];
 526                 } else if (input[0] == 1) {
 527                         if (input[1] > smu->gfx_default_soft_max_freq) {
 528                                 dev_warn(smu->adev->dev,
 529                                         "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
 530                                         input[1], smu->gfx_default_soft_max_freq);
 531                                 return -EINVAL;
 532                         }
 533                         smu->gfx_actual_soft_max_freq = input[1];
 534                 } else {
 535                         return -EINVAL;
 536                 }
 537                 break;
 538         case PP_OD_RESTORE_DEFAULT_TABLE:
 539                 if (size != 0) {
 540                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 541                         return -EINVAL;
 542                 } else {
 543                         smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 544                         smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 545                 }
 546                 break;
 547         case PP_OD_COMMIT_DPM_TABLE:
 548                 if (size != 0) {
 549                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 550                         return -EINVAL;
 551                 } else {
 552                         if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
 553                                 dev_err(smu->adev->dev,
 554                                         "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
 555                                         smu->gfx_actual_hard_min_freq,
 556                                         smu->gfx_actual_soft_max_freq);
 557                                 return -EINVAL;
 558                         }
 559
 560                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
 561                                                                         smu->gfx_actual_hard_min_freq, NULL);
 562                         if (ret) {
 563                                 dev_err(smu->adev->dev, "Set hard min sclk failed!");
 564                                 return ret;
 565                         }
 566
 567                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
 568                                                                         smu->gfx_actual_soft_max_freq, NULL);
 569                         if (ret) {
 570                                 dev_err(smu->adev->dev, "Set soft max sclk failed!");
 571                                 return ret;
 572                         }
 573                 }
 574                 break;
 575         default:
 576                 return -ENOSYS;
 577         }
 578
 579         return ret;
 580 }
 581
 582 static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
 583                                                 enum smu_clk_type clk_type,
 584                                                 uint32_t *value)
 585 {
 586         MetricsMember_t member_type;
 587
 588         switch (clk_type) {
 589         case SMU_SOCCLK:
 590                 member_type = METRICS_AVERAGE_SOCCLK;
 591                 break;
 592         case SMU_VCLK:
 593             member_type = METRICS_AVERAGE_VCLK;
 594                 break;
 595         case SMU_DCLK:
 596                 member_type = METRICS_AVERAGE_DCLK;
 597                 break;
 598         case SMU_MCLK:
 599                 member_type = METRICS_AVERAGE_UCLK;
 600                 break;
 601         case SMU_GFXCLK:
 602         case SMU_SCLK:
 603                 return smu_cmn_send_smc_msg_with_param(smu,
 604                                 SMU_MSG_GetGfxclkFrequency, 0, value);
 605                 break;
 606         default:
 607                 return -EINVAL;
 608         }
 609
 610         return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value);
 611 }
 612
 613 static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu,
 614                                                 enum smu_clk_type clk_type,
 615                                                 uint32_t *count)
 616 {
 617         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 618
 619         switch (clk_type) {
 620         case SMU_SOCCLK:
 621                 *count = clk_table->NumSocClkLevelsEnabled;
 622                 break;
 623         case SMU_VCLK:
 624                 *count = clk_table->VcnClkLevelsEnabled;
 625                 break;
 626         case SMU_DCLK:
 627                 *count = clk_table->VcnClkLevelsEnabled;
 628                 break;
 629         case SMU_MCLK:
 630                 *count = clk_table->NumDfPstatesEnabled;
 631                 break;
 632         case SMU_FCLK:
 633                 *count = clk_table->NumDfPstatesEnabled;
 634                 break;
 635         default:
 636                 break;
 637         }
 638
 639         return 0;
 640 }
 641
 642 static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu,
 643                                                 enum smu_clk_type clk_type,
 644                                                 uint32_t dpm_level,
 645                                                 uint32_t *freq)
 646 {
 647         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 648
 649         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 650                 return -EINVAL;
 651
 652         switch (clk_type) {
 653         case SMU_SOCCLK:
 654                 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
 655                         return -EINVAL;
 656                 *freq = clk_table->SocClocks[dpm_level];
 657                 break;
 658         case SMU_VCLK:
 659                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 660                         return -EINVAL;
 661                 *freq = clk_table->VClocks[dpm_level];
 662                 break;
 663         case SMU_DCLK:
 664                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 665                         return -EINVAL;
 666                 *freq = clk_table->DClocks[dpm_level];
 667                 break;
 668         case SMU_UCLK:
 669         case SMU_MCLK:
 670                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 671                         return -EINVAL;
 672                 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
 673                 break;
 674         case SMU_FCLK:
 675                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 676                         return -EINVAL;
 677                 *freq = clk_table->DfPstateTable[dpm_level].FClk;
 678                 break;
 679         default:
 680                 return -EINVAL;
 681         }
 682
 683         return 0;
 684 }
 685
 686 static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu,
 687                                                 enum smu_clk_type clk_type)
 688 {
 689         enum smu_feature_mask feature_id = 0;
 690
 691         switch (clk_type) {
 692         case SMU_MCLK:
 693         case SMU_UCLK:
 694         case SMU_FCLK:
 695                 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
 696                 break;
 697         case SMU_GFXCLK:
 698         case SMU_SCLK:
 699                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 700                 break;
 701         case SMU_SOCCLK:
 702                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 703                 break;
 704         case SMU_VCLK:
 705         case SMU_DCLK:
 706                 feature_id = SMU_FEATURE_VCN_DPM_BIT;
 707                 break;
 708         default:
 709                 return true;
 710         }
 711
 712         return smu_cmn_feature_is_enabled(smu, feature_id);
 713 }
 714
 715 static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu,
 716                                                         enum smu_clk_type clk_type,
 717                                                         uint32_t *min,
 718                                                         uint32_t *max)
 719 {
 720         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 721         uint32_t clock_limit;
 722         uint32_t max_dpm_level, min_dpm_level;
 723         int ret = 0;
 724
 725         if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
 726                 switch (clk_type) {
 727                 case SMU_MCLK:
 728                 case SMU_UCLK:
 729                         clock_limit = smu->smu_table.boot_values.uclk;
 730                         break;
 731                 case SMU_FCLK:
 732                         clock_limit = smu->smu_table.boot_values.fclk;
 733                         break;
 734                 case SMU_GFXCLK:
 735                 case SMU_SCLK:
 736                         clock_limit = smu->smu_table.boot_values.gfxclk;
 737                         break;
 738                 case SMU_SOCCLK:
 739                         clock_limit = smu->smu_table.boot_values.socclk;
 740                         break;
 741                 case SMU_VCLK:
 742                         clock_limit = smu->smu_table.boot_values.vclk;
 743                         break;
 744                 case SMU_DCLK:
 745                         clock_limit = smu->smu_table.boot_values.dclk;
 746                         break;
 747                 default:
 748                         clock_limit = 0;
 749                         break;
 750                 }
 751
 752                 /* clock in Mhz unit */
 753                 if (min)
 754                         *min = clock_limit / 100;
 755                 if (max)
 756                         *max = clock_limit / 100;
 757
 758                 return 0;
 759         }
 760
 761         if (max) {
 762                 switch (clk_type) {
 763                 case SMU_GFXCLK:
 764                 case SMU_SCLK:
 765                         *max = clk_table->MaxGfxClk;
 766                         break;
 767                 case SMU_MCLK:
 768                 case SMU_UCLK:
 769                 case SMU_FCLK:
 770                         max_dpm_level = 0;
 771                         break;
 772                 case SMU_SOCCLK:
 773                         max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
 774                         break;
 775                 case SMU_VCLK:
 776                 case SMU_DCLK:
 777                         max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
 778                         break;
 779                 default:
 780                         ret = -EINVAL;
 781                         goto failed;
 782                 }
 783
 784                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 785                         ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
 786                         if (ret)
 787                                 goto failed;
 788                 }
 789         }
 790
 791         if (min) {
 792                 switch (clk_type) {
 793                 case SMU_GFXCLK:
 794                 case SMU_SCLK:
 795                         *min = clk_table->MinGfxClk;
 796                         break;
 797                 case SMU_MCLK:
 798                 case SMU_UCLK:
 799                 case SMU_FCLK:
 800                         min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
 801                         break;
 802                 case SMU_SOCCLK:
 803                         min_dpm_level = 0;
 804                         break;
 805                 case SMU_VCLK:
 806                 case SMU_DCLK:
 807                         min_dpm_level = 0;
 808                         break;
 809                 default:
 810                         ret = -EINVAL;
 811                         goto failed;
 812                 }
 813
 814                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 815                         ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
 816                         if (ret)
 817                                 goto failed;
 818                 }
 819         }
 820
 821 failed:
 822         return ret;
 823 }
 824
 825 static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
 826                                                         enum smu_clk_type clk_type,
 827                                                         uint32_t min,
 828                                                         uint32_t max)
 829 {
 830         enum smu_message_type msg_set_min, msg_set_max;
 831         int ret = 0;
 832
 833         if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
 834                 return -EINVAL;
 835
 836         switch (clk_type) {
 837         case SMU_GFXCLK:
 838         case SMU_SCLK:
 839                 msg_set_min = SMU_MSG_SetHardMinGfxClk;
 840                 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
 841                 break;
 842         case SMU_VCLK:
 843         case SMU_DCLK:
 844                 msg_set_min = SMU_MSG_SetHardMinVcn;
 845                 msg_set_max = SMU_MSG_SetSoftMaxVcn;
 846                 break;
 847         default:
 848                 return -EINVAL;
 849         }
 850
 851         ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
 852         if (ret)
 853                 goto out;
 854
 855         ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
 856         if (ret)
 857                 goto out;
 858
 859 out:
 860         return ret;
 861 }
 862
 863 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
 864                                 enum smu_clk_type clk_type, char *buf)
 865 {
 866         int i, size = 0, ret = 0;
 867         uint32_t cur_value = 0, value = 0, count = 0;
 868         uint32_t min = 0, max = 0;
 869
 870         smu_cmn_get_sysfs_buf(&buf, &size);
 871
 872         switch (clk_type) {
 873         case SMU_OD_SCLK:
 874                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
 875                 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 876                 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
 877                 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 878                 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
 879                 break;
 880         case SMU_OD_RANGE:
 881                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
 882                 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
 883                                                 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
 884                 break;
 885         case SMU_SOCCLK:
 886         case SMU_VCLK:
 887         case SMU_DCLK:
 888         case SMU_MCLK:
 889                 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
 890                 if (ret)
 891                         goto print_clk_out;
 892
 893                 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);
 894                 if (ret)
 895                         goto print_clk_out;
 896
 897                 for (i = 0; i < count; i++) {
 898                         ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, i, &value);
 899                         if (ret)
 900                                 goto print_clk_out;
 901
 902                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
 903                                         cur_value == value ? "*" : "");
 904                 }
 905                 break;
 906         case SMU_GFXCLK:
 907         case SMU_SCLK:
 908                 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
 909                 if (ret)
 910                         goto print_clk_out;
 911                 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
 912                 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
 913                 if (cur_value  == max)
 914                         i = 2;
 915                 else if (cur_value == min)
 916                         i = 0;
 917                 else
 918                         i = 1;
 919                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
 920                                 i == 0 ? "*" : "");
 921                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
 922                                 i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK,
 923                                 i == 1 ? "*" : "");
 924                 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
 925                                 i == 2 ? "*" : "");
 926                 break;
 927         default:
 928                 break;
 929         }
 930
 931 print_clk_out:
 932         return size;
 933 }
 934
 935
 936 static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
 937                                 enum smu_clk_type clk_type, uint32_t mask)
 938 {
 939         uint32_t soft_min_level = 0, soft_max_level = 0;
 940         uint32_t min_freq = 0, max_freq = 0;
 941         int ret = 0;
 942
 943         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 944         soft_max_level = mask ? (fls(mask) - 1) : 0;
 945
 946         switch (clk_type) {
 947         case SMU_VCLK:
 948         case SMU_DCLK:
 949                 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 950                 if (ret)
 951                         goto force_level_out;
 952
 953                 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 954                 if (ret)
 955                         goto force_level_out;
 956
 957                 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
 958                 if (ret)
 959                         goto force_level_out;
 960                 break;
 961         default:
 962                 ret = -EINVAL;
 963                 break;
 964         }
 965
 966 force_level_out:
 967         return ret;
 968 }
 969
 970 static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
 971                                                 enum amd_dpm_forced_level level)
 972 {
 973         struct amdgpu_device *adev = smu->adev;
 974         uint32_t sclk_min = 0, sclk_max = 0;
 975         int ret = 0;
 976
 977         switch (level) {
 978         case AMD_DPM_FORCED_LEVEL_HIGH:
 979                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
 980                 sclk_min = sclk_max;
 981                 break;
 982         case AMD_DPM_FORCED_LEVEL_LOW:
 983                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
 984                 sclk_max = sclk_min;
 985                 break;
 986         case AMD_DPM_FORCED_LEVEL_AUTO:
 987                 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
 988                 break;
 989         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
 990         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
 991         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
 992         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
 993                 /* Temporarily do nothing since the optimal clocks haven't been provided yet */
 994                 break;
 995         case AMD_DPM_FORCED_LEVEL_MANUAL:
 996         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 997                 return 0;
 998         default:
 999                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1000                 return -EINVAL;
1001         }
1002
1003         if (sclk_min && sclk_max && smu_v13_0_5_clk_dpm_is_enabled(smu, SMU_SCLK)) {
1004                 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1005                                                             SMU_SCLK,
1006                                                             sclk_min,
1007                                                             sclk_max);
1008                 if (ret)
1009                         return ret;
1010
1011                 smu->gfx_actual_hard_min_freq = sclk_min;
1012                 smu->gfx_actual_soft_max_freq = sclk_max;
1013         }
1014
1015         return ret;
1016 }
1017
1018 static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1019 {
1020         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1021
1022         smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1023         smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1024         smu->gfx_actual_hard_min_freq = 0;
1025         smu->gfx_actual_soft_max_freq = 0;
1026
1027         return 0;
1028 }
1029
1030 static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
1031         .check_fw_status = smu_v13_0_check_fw_status,
1032         .check_fw_version = smu_v13_0_check_fw_version,
1033         .init_smc_tables = smu_v13_0_5_init_smc_tables,
1034         .fini_smc_tables = smu_v13_0_5_fini_smc_tables,
1035         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1036         .system_features_control = smu_v13_0_5_system_features_control,
1037         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1038         .send_smc_msg = smu_cmn_send_smc_msg,
1039         .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable,
1040         .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable,
1041         .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables,
1042         .read_sensor = smu_v13_0_5_read_sensor,
1043         .is_dpm_running = smu_v13_0_5_is_dpm_running,
1044         .set_watermarks_table = smu_v13_0_5_set_watermarks_table,
1045         .get_gpu_metrics = smu_v13_0_5_get_gpu_metrics,
1046         .get_enabled_mask = smu_cmn_get_enabled_mask,
1047         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1048         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1049         .gfx_off_control = smu_v13_0_gfx_off_control,
1050         .mode2_reset = smu_v13_0_5_mode2_reset,
1051         .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq,
1052         .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table,
1053         .print_clk_levels = smu_v13_0_5_print_clk_levels,
1054         .force_clk_levels = smu_v13_0_5_force_clk_levels,
1055         .set_performance_level = smu_v13_0_5_set_performance_level,
1056         .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters,
1057 };
1058
1059 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
1060 {
1061         struct amdgpu_device *adev = smu->adev;
1062
1063         smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
1064         smu->message_map = smu_v13_0_5_message_map;
1065         smu->feature_map = smu_v13_0_5_feature_mask_map;
1066         smu->table_map = smu_v13_0_5_table_map;
1067         smu->is_apu = true;
1068         smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
1069         smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
1070         smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
1071 }