drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v13_0.h"
  35 #include "smu13_driver_if_v13_0_0.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "smu_v13_0_0_ppt.h"
  39 #include "smu_v13_0_0_pptable.h"
  40 #include "smu_v13_0_0_ppsmc.h"
  41 #include "nbio/nbio_4_3_0_offset.h"
  42 #include "nbio/nbio_4_3_0_sh_mask.h"
  43 #include "mp/mp_13_0_0_offset.h"
  44 #include "mp/mp_13_0_0_sh_mask.h"
  45
  46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
  47 #include "smu_cmn.h"
  48 #include "amdgpu_ras.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define FEATURE_MASK(feature) (1ULL << feature)
  63 #define SMC_DPM_FEATURE ( \
  64         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  65         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  66         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  67         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  68         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  70
  71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE   0x4000
  72
  73 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
  74         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  75         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  76         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  77         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  78         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  79         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  80         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  81         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  82         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  83         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  84         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  85         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  86         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  87         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  88         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  89         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
  90         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
  91         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  92         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  93         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
  94         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  95         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  96         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
  97         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
  98         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
  99         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 100         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 101         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 102         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 103         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 104         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 105         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 106         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 107         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 108         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 109         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 110         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 111         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 112         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,      0),
 113         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,       0),
 114         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,          0),
 115         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 116         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 117         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 118         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 119         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 120         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 121         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         0),
 122 };
 123
 124 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
 125         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 126         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 127         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 128         CLK_MAP(FCLK,           PPCLK_FCLK),
 129         CLK_MAP(UCLK,           PPCLK_UCLK),
 130         CLK_MAP(MCLK,           PPCLK_UCLK),
 131         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 132         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 133         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 134         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 135 };
 136
 137 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
 138         FEA_MAP(FW_DATA_READ),
 139         FEA_MAP(DPM_GFXCLK),
 140         FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
 141         FEA_MAP(DPM_UCLK),
 142         FEA_MAP(DPM_FCLK),
 143         FEA_MAP(DPM_SOCCLK),
 144         FEA_MAP(DPM_MP0CLK),
 145         FEA_MAP(DPM_LINK),
 146         FEA_MAP(DPM_DCN),
 147         FEA_MAP(VMEMP_SCALING),
 148         FEA_MAP(VDDIO_MEM_SCALING),
 149         FEA_MAP(DS_GFXCLK),
 150         FEA_MAP(DS_SOCCLK),
 151         FEA_MAP(DS_FCLK),
 152         FEA_MAP(DS_LCLK),
 153         FEA_MAP(DS_DCFCLK),
 154         FEA_MAP(DS_UCLK),
 155         FEA_MAP(GFX_ULV),
 156         FEA_MAP(FW_DSTATE),
 157         FEA_MAP(GFXOFF),
 158         FEA_MAP(BACO),
 159         FEA_MAP(MM_DPM),
 160         FEA_MAP(SOC_MPCLK_DS),
 161         FEA_MAP(BACO_MPCLK_DS),
 162         FEA_MAP(THROTTLERS),
 163         FEA_MAP(SMARTSHIFT),
 164         FEA_MAP(GTHR),
 165         FEA_MAP(ACDC),
 166         FEA_MAP(VR0HOT),
 167         FEA_MAP(FW_CTF),
 168         FEA_MAP(FAN_CONTROL),
 169         FEA_MAP(GFX_DCS),
 170         FEA_MAP(GFX_READ_MARGIN),
 171         FEA_MAP(LED_DISPLAY),
 172         FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
 173         FEA_MAP(OUT_OF_BAND_MONITOR),
 174         FEA_MAP(OPTIMIZED_VMIN),
 175         FEA_MAP(GFX_IMU),
 176         FEA_MAP(BOOT_TIME_CAL),
 177         FEA_MAP(GFX_PCC_DFLL),
 178         FEA_MAP(SOC_CG),
 179         FEA_MAP(DF_CSTATE),
 180         FEA_MAP(GFX_EDC),
 181         FEA_MAP(BOOT_POWER_OPT),
 182         FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
 183         FEA_MAP(DS_VCN),
 184         FEA_MAP(BACO_CG),
 185         FEA_MAP(MEM_TEMP_READ),
 186         FEA_MAP(ATHUB_MMHUB_PG),
 187         FEA_MAP(SOC_PCC),
 188 };
 189
 190 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
 191         TAB_MAP(PPTABLE),
 192         TAB_MAP(WATERMARKS),
 193         TAB_MAP(AVFS_PSM_DEBUG),
 194         TAB_MAP(PMSTATUSLOG),
 195         TAB_MAP(SMU_METRICS),
 196         TAB_MAP(DRIVER_SMU_CONFIG),
 197         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 198         [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
 199         TAB_MAP(I2C_COMMANDS),
 200 };
 201
 202 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 203         PWR_MAP(AC),
 204         PWR_MAP(DC),
 205 };
 206
 207 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 213         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 214         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 215 };
 216
 217 static const uint8_t smu_v13_0_0_throttler_map[] = {
 218         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 219         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 220         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 221         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 222         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 223         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 224         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 225         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 226         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 227         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 228         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 229         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 230         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 231         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 232         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 233         [THROTTLER_GFX_APCC_PLUS_BIT]   = (SMU_THROTTLER_APCC_BIT),
 234         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 235 };
 236
 237 static int
 238 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
 239                                   uint32_t *feature_mask, uint32_t num)
 240 {
 241         struct amdgpu_device *adev = smu->adev;
 242
 243         if (num > 2)
 244                 return -EINVAL;
 245
 246         memset(feature_mask, 0, sizeof(uint32_t) * num);
 247
 248         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
 249
 250         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 251                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 252                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
 253         }
 254
 255         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
 256         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
 257
 258         if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
 259             (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
 260                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
 261
 262         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 263                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 264
 265 #if 0
 266         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 267                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 268 #endif
 269
 270         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
 271         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
 272
 273         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
 274
 275         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
 276                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
 277                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
 278                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
 279         }
 280
 281         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
 282
 283         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 284                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 285         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 286         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
 287         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
 288
 289         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
 290         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
 291         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_DCFCLK_BIT);
 292
 293         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) {
 294                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 295                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 296         }
 297
 298         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
 299
 300         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
 301         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
 302
 303         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 304         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
 305
 306         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
 307
 308         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
 309
 310         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_UCLK_BIT);
 311
 312         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
 313
 314         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
 315
 316         if (adev->pm.pp_feature & PP_ULV_MASK)
 317                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 318
 319         return 0;
 320 }
 321
 322 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
 323 {
 324         struct smu_table_context *table_context = &smu->smu_table;
 325         struct smu_13_0_0_powerplay_table *powerplay_table =
 326                 table_context->power_play_table;
 327         struct smu_baco_context *smu_baco = &smu->smu_baco;
 328
 329         if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
 330                 smu->dc_controlled_by_gpio = true;
 331
 332         if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO ||
 333             powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
 334                 smu_baco->platform_support = true;
 335
 336         if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
 337                 smu_baco->maco_support = true;
 338
 339         table_context->thermal_controller_type =
 340                 powerplay_table->thermal_controller_type;
 341
 342         /*
 343          * Instead of having its own buffer space and get overdrive_table copied,
 344          * smu->od_settings just points to the actual overdrive_table
 345          */
 346         smu->od_settings = &powerplay_table->overdrive_table;
 347
 348         return 0;
 349 }
 350
 351 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
 352 {
 353         struct smu_table_context *table_context = &smu->smu_table;
 354         struct smu_13_0_0_powerplay_table *powerplay_table =
 355                 table_context->power_play_table;
 356
 357         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 358                sizeof(PPTable_t));
 359
 360         return 0;
 361 }
 362
 363 #ifndef atom_smc_dpm_info_table_13_0_0
 364 struct atom_smc_dpm_info_table_13_0_0 {
 365         struct atom_common_table_header table_header;
 366         BoardTable_t BoardTable;
 367 };
 368 #endif
 369
 370 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
 371 {
 372         struct smu_table_context *table_context = &smu->smu_table;
 373         PPTable_t *smc_pptable = table_context->driver_pptable;
 374         struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table;
 375         BoardTable_t *BoardTable = &smc_pptable->BoardTable;
 376         int index, ret;
 377
 378         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 379                                             smc_dpm_info);
 380
 381         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 382                                              (uint8_t **)&smc_dpm_table);
 383         if (ret)
 384                 return ret;
 385
 386         memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
 387
 388         return 0;
 389 }
 390
 391 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
 392 {
 393         struct smu_table_context *smu_table = &smu->smu_table;
 394         void *combo_pptable = smu_table->combo_pptable;
 395         struct amdgpu_device *adev = smu->adev;
 396         int ret = 0;
 397
 398         /*
 399          * With SCPM enabled, the pptable used will be signed. It cannot
 400          * be used directly by driver. To get the raw pptable, we need to
 401          * rely on the combo pptable(and its revelant SMU message).
 402          */
 403         if (adev->scpm_enabled) {
 404                 ret = smu_cmn_get_combo_pptable(smu);
 405                 if (ret)
 406                         return ret;
 407
 408                 smu->smu_table.power_play_table = combo_pptable;
 409                 smu->smu_table.power_play_table_size = sizeof(struct smu_13_0_0_powerplay_table);
 410         } else {
 411                 ret = smu_v13_0_setup_pptable(smu);
 412                 if (ret)
 413                         return ret;
 414         }
 415
 416         ret = smu_v13_0_0_store_powerplay_table(smu);
 417         if (ret)
 418                 return ret;
 419
 420         /*
 421          * With SCPM enabled, the operation below will be handled
 422          * by PSP. Driver involvment is unnecessary and useless.
 423          */
 424         if (!adev->scpm_enabled) {
 425                 ret = smu_v13_0_0_append_powerplay_table(smu);
 426                 if (ret)
 427                         return ret;
 428         }
 429
 430         ret = smu_v13_0_0_check_powerplay_table(smu);
 431         if (ret)
 432                 return ret;
 433
 434         return ret;
 435 }
 436
 437 static int smu_v13_0_0_tables_init(struct smu_context *smu)
 438 {
 439         struct smu_table_context *smu_table = &smu->smu_table;
 440         struct smu_table *tables = smu_table->tables;
 441
 442         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 443                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 444         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 445                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 446         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 447                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 448         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 449                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 450         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 451                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 452         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 453                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 454         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 455                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 456                        AMDGPU_GEM_DOMAIN_VRAM);
 457         SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
 458                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 459
 460         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 461         if (!smu_table->metrics_table)
 462                 goto err0_out;
 463         smu_table->metrics_time = 0;
 464
 465         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 466         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 467         if (!smu_table->gpu_metrics_table)
 468                 goto err1_out;
 469
 470         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 471         if (!smu_table->watermarks_table)
 472                 goto err2_out;
 473
 474         return 0;
 475
 476 err2_out:
 477         kfree(smu_table->gpu_metrics_table);
 478 err1_out:
 479         kfree(smu_table->metrics_table);
 480 err0_out:
 481         return -ENOMEM;
 482 }
 483
 484 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
 485 {
 486         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 487
 488         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 489                                        GFP_KERNEL);
 490         if (!smu_dpm->dpm_context)
 491                 return -ENOMEM;
 492
 493         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 494
 495         return 0;
 496 }
 497
 498 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
 499 {
 500         int ret = 0;
 501
 502         ret = smu_v13_0_0_tables_init(smu);
 503         if (ret)
 504                 return ret;
 505
 506         ret = smu_v13_0_0_allocate_dpm_context(smu);
 507         if (ret)
 508                 return ret;
 509
 510         return smu_v13_0_init_smc_tables(smu);
 511 }
 512
 513 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
 514 {
 515         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 516         struct smu_table_context *table_context = &smu->smu_table;
 517         PPTable_t *pptable = table_context->driver_pptable;
 518         SkuTable_t *skutable = &pptable->SkuTable;
 519         struct smu_13_0_dpm_table *dpm_table;
 520         struct smu_13_0_pcie_table *pcie_table;
 521         uint32_t link_level;
 522         int ret = 0;
 523
 524         /* socclk dpm table setup */
 525         dpm_table = &dpm_context->dpm_tables.soc_table;
 526         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 527                 ret = smu_v13_0_set_single_dpm_table(smu,
 528                                                      SMU_SOCCLK,
 529                                                      dpm_table);
 530                 if (ret)
 531                         return ret;
 532         } else {
 533                 dpm_table->count = 1;
 534                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 535                 dpm_table->dpm_levels[0].enabled = true;
 536                 dpm_table->min = dpm_table->dpm_levels[0].value;
 537                 dpm_table->max = dpm_table->dpm_levels[0].value;
 538         }
 539
 540         /* gfxclk dpm table setup */
 541         dpm_table = &dpm_context->dpm_tables.gfx_table;
 542         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 543                 ret = smu_v13_0_set_single_dpm_table(smu,
 544                                                      SMU_GFXCLK,
 545                                                      dpm_table);
 546                 if (ret)
 547                         return ret;
 548         } else {
 549                 dpm_table->count = 1;
 550                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 551                 dpm_table->dpm_levels[0].enabled = true;
 552                 dpm_table->min = dpm_table->dpm_levels[0].value;
 553                 dpm_table->max = dpm_table->dpm_levels[0].value;
 554         }
 555
 556         /* uclk dpm table setup */
 557         dpm_table = &dpm_context->dpm_tables.uclk_table;
 558         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 559                 ret = smu_v13_0_set_single_dpm_table(smu,
 560                                                      SMU_UCLK,
 561                                                      dpm_table);
 562                 if (ret)
 563                         return ret;
 564         } else {
 565                 dpm_table->count = 1;
 566                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 567                 dpm_table->dpm_levels[0].enabled = true;
 568                 dpm_table->min = dpm_table->dpm_levels[0].value;
 569                 dpm_table->max = dpm_table->dpm_levels[0].value;
 570         }
 571
 572         /* fclk dpm table setup */
 573         dpm_table = &dpm_context->dpm_tables.fclk_table;
 574         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 575                 ret = smu_v13_0_set_single_dpm_table(smu,
 576                                                      SMU_FCLK,
 577                                                      dpm_table);
 578                 if (ret)
 579                         return ret;
 580         } else {
 581                 dpm_table->count = 1;
 582                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 583                 dpm_table->dpm_levels[0].enabled = true;
 584                 dpm_table->min = dpm_table->dpm_levels[0].value;
 585                 dpm_table->max = dpm_table->dpm_levels[0].value;
 586         }
 587
 588         /* vclk dpm table setup */
 589         dpm_table = &dpm_context->dpm_tables.vclk_table;
 590         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
 591                 ret = smu_v13_0_set_single_dpm_table(smu,
 592                                                      SMU_VCLK,
 593                                                      dpm_table);
 594                 if (ret)
 595                         return ret;
 596         } else {
 597                 dpm_table->count = 1;
 598                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 599                 dpm_table->dpm_levels[0].enabled = true;
 600                 dpm_table->min = dpm_table->dpm_levels[0].value;
 601                 dpm_table->max = dpm_table->dpm_levels[0].value;
 602         }
 603
 604         /* dclk dpm table setup */
 605         dpm_table = &dpm_context->dpm_tables.dclk_table;
 606         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
 607                 ret = smu_v13_0_set_single_dpm_table(smu,
 608                                                      SMU_DCLK,
 609                                                      dpm_table);
 610                 if (ret)
 611                         return ret;
 612         } else {
 613                 dpm_table->count = 1;
 614                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 615                 dpm_table->dpm_levels[0].enabled = true;
 616                 dpm_table->min = dpm_table->dpm_levels[0].value;
 617                 dpm_table->max = dpm_table->dpm_levels[0].value;
 618         }
 619
 620         /* lclk dpm table setup */
 621         pcie_table = &dpm_context->dpm_tables.pcie_table;
 622         pcie_table->num_of_link_levels = 0;
 623         for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
 624                 if (!skutable->PcieGenSpeed[link_level] &&
 625                     !skutable->PcieLaneCount[link_level] &&
 626                     !skutable->LclkFreq[link_level])
 627                         continue;
 628
 629                 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
 630                                         skutable->PcieGenSpeed[link_level];
 631                 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
 632                                         skutable->PcieLaneCount[link_level];
 633                 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
 634                                         skutable->LclkFreq[link_level];
 635                 pcie_table->num_of_link_levels++;
 636         }
 637
 638         return 0;
 639 }
 640
 641 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
 642 {
 643         int ret = 0;
 644         uint64_t feature_enabled;
 645
 646         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 647         if (ret)
 648                 return false;
 649
 650         return !!(feature_enabled & SMC_DPM_FEATURE);
 651 }
 652
 653 static void smu_v13_0_0_dump_pptable(struct smu_context *smu)
 654 {
 655        struct smu_table_context *table_context = &smu->smu_table;
 656        PPTable_t *pptable = table_context->driver_pptable;
 657        SkuTable_t *skutable = &pptable->SkuTable;
 658
 659        dev_info(smu->adev->dev, "Dumped PPTable:\n");
 660
 661        dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
 662        dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
 663        dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
 664 }
 665
 666 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
 667                                                   bool en)
 668 {
 669         return smu_v13_0_system_features_control(smu, en);
 670 }
 671
 672 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)
 673 {
 674         uint32_t throttler_status = 0;
 675         int i;
 676
 677         for (i = 0; i < THROTTLER_COUNT; i++)
 678                 throttler_status |=
 679                         (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
 680
 681         return throttler_status;
 682 }
 683
 684 #define SMU_13_0_0_BUSY_THRESHOLD       15
 685 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
 686                                             MetricsMember_t member,
 687                                             uint32_t *value)
 688 {
 689         struct smu_table_context *smu_table = &smu->smu_table;
 690         SmuMetrics_t *metrics =
 691                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 692         int ret = 0;
 693
 694         ret = smu_cmn_get_metrics_table(smu,
 695                                         NULL,
 696                                         false);
 697         if (ret)
 698                 return ret;
 699
 700         switch (member) {
 701         case METRICS_CURR_GFXCLK:
 702                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 703                 break;
 704         case METRICS_CURR_SOCCLK:
 705                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 706                 break;
 707         case METRICS_CURR_UCLK:
 708                 *value = metrics->CurrClock[PPCLK_UCLK];
 709                 break;
 710         case METRICS_CURR_VCLK:
 711                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 712                 break;
 713         case METRICS_CURR_VCLK1:
 714                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 715                 break;
 716         case METRICS_CURR_DCLK:
 717                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 718                 break;
 719         case METRICS_CURR_DCLK1:
 720                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 721                 break;
 722         case METRICS_CURR_FCLK:
 723                 *value = metrics->CurrClock[PPCLK_FCLK];
 724                 break;
 725         case METRICS_AVERAGE_GFXCLK:
 726                 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
 727                         *value = metrics->AverageGfxclkFrequencyPostDs;
 728                 else
 729                         *value = metrics->AverageGfxclkFrequencyPreDs;
 730                 break;
 731         case METRICS_AVERAGE_FCLK:
 732                 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
 733                         *value = metrics->AverageFclkFrequencyPostDs;
 734                 else
 735                         *value = metrics->AverageFclkFrequencyPreDs;
 736                 break;
 737         case METRICS_AVERAGE_UCLK:
 738                 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
 739                         *value = metrics->AverageMemclkFrequencyPostDs;
 740                 else
 741                         *value = metrics->AverageMemclkFrequencyPreDs;
 742                 break;
 743         case METRICS_AVERAGE_VCLK:
 744                 *value = metrics->AverageVclk0Frequency;
 745                 break;
 746         case METRICS_AVERAGE_DCLK:
 747                 *value = metrics->AverageDclk0Frequency;
 748                 break;
 749         case METRICS_AVERAGE_VCLK1:
 750                 *value = metrics->AverageVclk1Frequency;
 751                 break;
 752         case METRICS_AVERAGE_DCLK1:
 753                 *value = metrics->AverageDclk1Frequency;
 754                 break;
 755         case METRICS_AVERAGE_GFXACTIVITY:
 756                 *value = metrics->AverageGfxActivity;
 757                 break;
 758         case METRICS_AVERAGE_MEMACTIVITY:
 759                 *value = metrics->AverageUclkActivity;
 760                 break;
 761         case METRICS_AVERAGE_SOCKETPOWER:
 762                 *value = metrics->AverageSocketPower << 8;
 763                 break;
 764         case METRICS_TEMPERATURE_EDGE:
 765                 *value = metrics->AvgTemperature[TEMP_EDGE] *
 766                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 767                 break;
 768         case METRICS_TEMPERATURE_HOTSPOT:
 769                 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
 770                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 771                 break;
 772         case METRICS_TEMPERATURE_MEM:
 773                 *value = metrics->AvgTemperature[TEMP_MEM] *
 774                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 775                 break;
 776         case METRICS_TEMPERATURE_VRGFX:
 777                 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
 778                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 779                 break;
 780         case METRICS_TEMPERATURE_VRSOC:
 781                 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
 782                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 783                 break;
 784         case METRICS_THROTTLER_STATUS:
 785                 *value = smu_v13_0_get_throttler_status(metrics);
 786                 break;
 787         case METRICS_CURR_FANSPEED:
 788                 *value = metrics->AvgFanRpm;
 789                 break;
 790         case METRICS_CURR_FANPWM:
 791                 *value = metrics->AvgFanPwm;
 792                 break;
 793         case METRICS_VOLTAGE_VDDGFX:
 794                 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
 795                 break;
 796         case METRICS_PCIE_RATE:
 797                 *value = metrics->PcieRate;
 798                 break;
 799         case METRICS_PCIE_WIDTH:
 800                 *value = metrics->PcieWidth;
 801                 break;
 802         default:
 803                 *value = UINT_MAX;
 804                 break;
 805         }
 806
 807         return ret;
 808 }
 809
 810 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
 811                                    enum amd_pp_sensors sensor,
 812                                    void *data,
 813                                    uint32_t *size)
 814 {
 815         struct smu_table_context *table_context = &smu->smu_table;
 816         PPTable_t *smc_pptable = table_context->driver_pptable;
 817         int ret = 0;
 818
 819         switch (sensor) {
 820         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 821                 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
 822                 *size = 4;
 823                 break;
 824         case AMDGPU_PP_SENSOR_MEM_LOAD:
 825                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 826                                                        METRICS_AVERAGE_MEMACTIVITY,
 827                                                        (uint32_t *)data);
 828                 *size = 4;
 829                 break;
 830         case AMDGPU_PP_SENSOR_GPU_LOAD:
 831                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 832                                                        METRICS_AVERAGE_GFXACTIVITY,
 833                                                        (uint32_t *)data);
 834                 *size = 4;
 835                 break;
 836         case AMDGPU_PP_SENSOR_GPU_POWER:
 837                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 838                                                        METRICS_AVERAGE_SOCKETPOWER,
 839                                                        (uint32_t *)data);
 840                 *size = 4;
 841                 break;
 842         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 843                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 844                                                        METRICS_TEMPERATURE_HOTSPOT,
 845                                                        (uint32_t *)data);
 846                 *size = 4;
 847                 break;
 848         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 849                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 850                                                        METRICS_TEMPERATURE_EDGE,
 851                                                        (uint32_t *)data);
 852                 *size = 4;
 853                 break;
 854         case AMDGPU_PP_SENSOR_MEM_TEMP:
 855                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 856                                                        METRICS_TEMPERATURE_MEM,
 857                                                        (uint32_t *)data);
 858                 *size = 4;
 859                 break;
 860         case AMDGPU_PP_SENSOR_GFX_MCLK:
 861                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 862                                                        METRICS_CURR_UCLK,
 863                                                        (uint32_t *)data);
 864                 *(uint32_t *)data *= 100;
 865                 *size = 4;
 866                 break;
 867         case AMDGPU_PP_SENSOR_GFX_SCLK:
 868                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 869                                                        METRICS_AVERAGE_GFXCLK,
 870                                                        (uint32_t *)data);
 871                 *(uint32_t *)data *= 100;
 872                 *size = 4;
 873                 break;
 874         case AMDGPU_PP_SENSOR_VDDGFX:
 875                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 876                                                        METRICS_VOLTAGE_VDDGFX,
 877                                                        (uint32_t *)data);
 878                 *size = 4;
 879                 break;
 880         default:
 881                 ret = -EOPNOTSUPP;
 882                 break;
 883         }
 884
 885         return ret;
 886 }
 887
 888 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
 889                                                      enum smu_clk_type clk_type,
 890                                                      uint32_t *value)
 891 {
 892         MetricsMember_t member_type;
 893         int clk_id = 0;
 894
 895         clk_id = smu_cmn_to_asic_specific_index(smu,
 896                                                 CMN2ASIC_MAPPING_CLK,
 897                                                 clk_type);
 898         if (clk_id < 0)
 899                 return -EINVAL;
 900
 901         switch (clk_id) {
 902         case PPCLK_GFXCLK:
 903                 member_type = METRICS_AVERAGE_GFXCLK;
 904                 break;
 905         case PPCLK_UCLK:
 906                 member_type = METRICS_CURR_UCLK;
 907                 break;
 908         case PPCLK_FCLK:
 909                 member_type = METRICS_CURR_FCLK;
 910                 break;
 911         case PPCLK_SOCCLK:
 912                 member_type = METRICS_CURR_SOCCLK;
 913                 break;
 914         case PPCLK_VCLK_0:
 915                 member_type = METRICS_AVERAGE_VCLK;
 916                 break;
 917         case PPCLK_DCLK_0:
 918                 member_type = METRICS_AVERAGE_DCLK;
 919                 break;
 920         case PPCLK_VCLK_1:
 921                 member_type = METRICS_AVERAGE_VCLK1;
 922                 break;
 923         case PPCLK_DCLK_1:
 924                 member_type = METRICS_AVERAGE_DCLK1;
 925                 break;
 926         default:
 927                 return -EINVAL;
 928         }
 929
 930         return smu_v13_0_0_get_smu_metrics_data(smu,
 931                                                 member_type,
 932                                                 value);
 933 }
 934
 935 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
 936                                         enum smu_clk_type clk_type,
 937                                         char *buf)
 938 {
 939         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 940         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 941         struct smu_13_0_dpm_table *single_dpm_table;
 942         struct smu_13_0_pcie_table *pcie_table;
 943         const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
 944         uint32_t gen_speed, lane_width;
 945         int i, curr_freq, size = 0;
 946         int ret = 0;
 947
 948         smu_cmn_get_sysfs_buf(&buf, &size);
 949
 950         if (amdgpu_ras_intr_triggered()) {
 951                 size += sysfs_emit_at(buf, size, "unavailable\n");
 952                 return size;
 953         }
 954
 955         switch (clk_type) {
 956         case SMU_SCLK:
 957                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 958                 break;
 959         case SMU_MCLK:
 960                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 961                 break;
 962         case SMU_SOCCLK:
 963                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 964                 break;
 965         case SMU_FCLK:
 966                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 967                 break;
 968         case SMU_VCLK:
 969         case SMU_VCLK1:
 970                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 971                 break;
 972         case SMU_DCLK:
 973         case SMU_DCLK1:
 974                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 975                 break;
 976         default:
 977                 break;
 978         }
 979
 980         switch (clk_type) {
 981         case SMU_SCLK:
 982         case SMU_MCLK:
 983         case SMU_SOCCLK:
 984         case SMU_FCLK:
 985         case SMU_VCLK:
 986         case SMU_VCLK1:
 987         case SMU_DCLK:
 988         case SMU_DCLK1:
 989                 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
 990                 if (ret) {
 991                         dev_err(smu->adev->dev, "Failed to get current clock freq!");
 992                         return ret;
 993                 }
 994
 995                 if (single_dpm_table->is_fine_grained) {
 996                         /*
 997                          * For fine grained dpms, there are only two dpm levels:
 998                          *   - level 0 -> min clock freq
 999                          *   - level 1 -> max clock freq
1000                          * And the current clock frequency can be any value between them.
1001                          * So, if the current clock frequency is not at level 0 or level 1,
1002                          * we will fake it as three dpm levels:
1003                          *   - level 0 -> min clock freq
1004                          *   - level 1 -> current actual clock freq
1005                          *   - level 2 -> max clock freq
1006                          */
1007                         if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1008                              (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1009                                 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1010                                                 single_dpm_table->dpm_levels[0].value);
1011                                 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1012                                                 curr_freq);
1013                                 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1014                                                 single_dpm_table->dpm_levels[1].value);
1015                         } else {
1016                                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1017                                                 single_dpm_table->dpm_levels[0].value,
1018                                                 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1019                                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1020                                                 single_dpm_table->dpm_levels[1].value,
1021                                                 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1022                         }
1023                 } else {
1024                         for (i = 0; i < single_dpm_table->count; i++)
1025                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1026                                                 i, single_dpm_table->dpm_levels[i].value,
1027                                                 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1028                 }
1029                 break;
1030         case SMU_PCIE:
1031                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1032                                                        METRICS_PCIE_RATE,
1033                                                        &gen_speed);
1034                 if (ret)
1035                         return ret;
1036
1037                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1038                                                        METRICS_PCIE_WIDTH,
1039                                                        &lane_width);
1040                 if (ret)
1041                         return ret;
1042
1043                 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1044                 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1045                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1046                                         (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1047                                         (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1048                                         (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1049                                         (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1050                                         (pcie_table->pcie_lane[i] == 1) ? "x1" :
1051                                         (pcie_table->pcie_lane[i] == 2) ? "x2" :
1052                                         (pcie_table->pcie_lane[i] == 3) ? "x4" :
1053                                         (pcie_table->pcie_lane[i] == 4) ? "x8" :
1054                                         (pcie_table->pcie_lane[i] == 5) ? "x12" :
1055                                         (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1056                                         pcie_table->clk_freq[i],
1057                                         ((gen_speed - 1) == pcie_table->pcie_gen[i]) &&
1058                                         (lane_width == link_width[pcie_table->pcie_lane[i]]) ?
1059                                         "*" : "");
1060                 break;
1061
1062         default:
1063                 break;
1064         }
1065
1066         return size;
1067 }
1068
1069 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
1070                                         enum smu_clk_type clk_type,
1071                                         uint32_t mask)
1072 {
1073         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1074         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1075         struct smu_13_0_dpm_table *single_dpm_table;
1076         uint32_t soft_min_level, soft_max_level;
1077         uint32_t min_freq, max_freq;
1078         int ret = 0;
1079
1080         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1081         soft_max_level = mask ? (fls(mask) - 1) : 0;
1082
1083         switch (clk_type) {
1084         case SMU_GFXCLK:
1085         case SMU_SCLK:
1086                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1087                 break;
1088         case SMU_MCLK:
1089         case SMU_UCLK:
1090                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1091                 break;
1092         case SMU_SOCCLK:
1093                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1094                 break;
1095         case SMU_FCLK:
1096                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1097                 break;
1098         case SMU_VCLK:
1099         case SMU_VCLK1:
1100                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1101                 break;
1102         case SMU_DCLK:
1103         case SMU_DCLK1:
1104                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1105                 break;
1106         default:
1107                 break;
1108         }
1109
1110         switch (clk_type) {
1111         case SMU_GFXCLK:
1112         case SMU_SCLK:
1113         case SMU_MCLK:
1114         case SMU_UCLK:
1115         case SMU_SOCCLK:
1116         case SMU_FCLK:
1117         case SMU_VCLK:
1118         case SMU_VCLK1:
1119         case SMU_DCLK:
1120         case SMU_DCLK1:
1121                 if (single_dpm_table->is_fine_grained) {
1122                         /* There is only 2 levels for fine grained DPM */
1123                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1124                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1125                 } else {
1126                         if ((soft_max_level >= single_dpm_table->count) ||
1127                             (soft_min_level >= single_dpm_table->count))
1128                                 return -EINVAL;
1129                 }
1130
1131                 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1132                 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1133
1134                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1135                                                             clk_type,
1136                                                             min_freq,
1137                                                             max_freq);
1138                 break;
1139         case SMU_DCEFCLK:
1140         case SMU_PCIE:
1141         default:
1142                 break;
1143         }
1144
1145         return ret;
1146 }
1147
1148 static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,
1149                                               uint32_t pcie_gen_cap,
1150                                               uint32_t pcie_width_cap)
1151 {
1152         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1153         struct smu_13_0_pcie_table *pcie_table =
1154                                 &dpm_context->dpm_tables.pcie_table;
1155         uint32_t smu_pcie_arg;
1156         int ret, i;
1157
1158         for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1159                 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1160                         pcie_table->pcie_gen[i] = pcie_gen_cap;
1161                 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1162                         pcie_table->pcie_lane[i] = pcie_width_cap;
1163
1164                 smu_pcie_arg = i << 16;
1165                 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1166                 smu_pcie_arg |= pcie_table->pcie_lane[i];
1167
1168                 ret = smu_cmn_send_smc_msg_with_param(smu,
1169                                                       SMU_MSG_OverridePcieParameters,
1170                                                       smu_pcie_arg,
1171                                                       NULL);
1172                 if (ret)
1173                         return ret;
1174         }
1175
1176         return 0;
1177 }
1178
1179 static const struct smu_temperature_range smu13_thermal_policy[] = {
1180         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1181         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1182 };
1183
1184 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
1185                                                      struct smu_temperature_range *range)
1186 {
1187         struct smu_table_context *table_context = &smu->smu_table;
1188         struct smu_13_0_0_powerplay_table *powerplay_table =
1189                 table_context->power_play_table;
1190         PPTable_t *pptable = smu->smu_table.driver_pptable;
1191
1192         if (!range)
1193                 return -EINVAL;
1194
1195         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1196
1197         range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
1198                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1199         range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1200                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1201         range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1202                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1203         range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1204                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1205         range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
1206                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1207         range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1208                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1209         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1210
1211         return 0;
1212 }
1213
1214 #define MAX(a, b)       ((a) > (b) ? (a) : (b))
1215 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
1216                                            void **table)
1217 {
1218         struct smu_table_context *smu_table = &smu->smu_table;
1219         struct gpu_metrics_v1_3 *gpu_metrics =
1220                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1221         SmuMetricsExternal_t metrics_ext;
1222         SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
1223         int ret = 0;
1224
1225         ret = smu_cmn_get_metrics_table(smu,
1226                                         &metrics_ext,
1227                                         true);
1228         if (ret)
1229                 return ret;
1230
1231         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1232
1233         gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
1234         gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
1235         gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
1236         gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
1237         gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
1238         gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0],
1239                                              metrics->AvgTemperature[TEMP_VR_MEM1]);
1240
1241         gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
1242         gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
1243         gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage,
1244                                                metrics->Vcn1ActivityPercentage);
1245
1246         gpu_metrics->average_socket_power = metrics->AverageSocketPower;
1247         gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
1248
1249         if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
1250                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
1251         else
1252                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
1253
1254         if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
1255                 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
1256         else
1257                 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
1258
1259         gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
1260         gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
1261         gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
1262         gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
1263
1264         gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
1265         gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
1266         gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
1267         gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
1268         gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
1269         gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
1270         gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
1271
1272         gpu_metrics->throttle_status =
1273                         smu_v13_0_get_throttler_status(metrics);
1274         gpu_metrics->indep_throttle_status =
1275                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
1276                                                            smu_v13_0_0_throttler_map);
1277
1278         gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
1279
1280         gpu_metrics->pcie_link_width = metrics->PcieWidth;
1281         gpu_metrics->pcie_link_speed = metrics->PcieRate;
1282
1283         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1284
1285         gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
1286         gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
1287         gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
1288
1289         *table = (void *)gpu_metrics;
1290
1291         return sizeof(struct gpu_metrics_v1_3);
1292 }
1293
1294 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
1295 {
1296         struct smu_13_0_dpm_context *dpm_context =
1297                                 smu->smu_dpm.dpm_context;
1298         struct smu_13_0_dpm_table *gfx_table =
1299                                 &dpm_context->dpm_tables.gfx_table;
1300         struct smu_13_0_dpm_table *mem_table =
1301                                 &dpm_context->dpm_tables.uclk_table;
1302         struct smu_13_0_dpm_table *soc_table =
1303                                 &dpm_context->dpm_tables.soc_table;
1304         struct smu_13_0_dpm_table *vclk_table =
1305                                 &dpm_context->dpm_tables.vclk_table;
1306         struct smu_13_0_dpm_table *dclk_table =
1307                                 &dpm_context->dpm_tables.dclk_table;
1308         struct smu_13_0_dpm_table *fclk_table =
1309                                 &dpm_context->dpm_tables.fclk_table;
1310         struct smu_umd_pstate_table *pstate_table =
1311                                 &smu->pstate_table;
1312
1313         pstate_table->gfxclk_pstate.min = gfx_table->min;
1314         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1315
1316         pstate_table->uclk_pstate.min = mem_table->min;
1317         pstate_table->uclk_pstate.peak = mem_table->max;
1318
1319         pstate_table->socclk_pstate.min = soc_table->min;
1320         pstate_table->socclk_pstate.peak = soc_table->max;
1321
1322         pstate_table->vclk_pstate.min = vclk_table->min;
1323         pstate_table->vclk_pstate.peak = vclk_table->max;
1324
1325         pstate_table->dclk_pstate.min = dclk_table->min;
1326         pstate_table->dclk_pstate.peak = dclk_table->max;
1327
1328         pstate_table->fclk_pstate.min = fclk_table->min;
1329         pstate_table->fclk_pstate.peak = fclk_table->max;
1330
1331         /*
1332          * For now, just use the mininum clock frequency.
1333          * TODO: update them when the real pstate settings available
1334          */
1335         pstate_table->gfxclk_pstate.standard = gfx_table->min;
1336         pstate_table->uclk_pstate.standard = mem_table->min;
1337         pstate_table->socclk_pstate.standard = soc_table->min;
1338         pstate_table->vclk_pstate.standard = vclk_table->min;
1339         pstate_table->dclk_pstate.standard = dclk_table->min;
1340         pstate_table->fclk_pstate.standard = fclk_table->min;
1341
1342         return 0;
1343 }
1344
1345 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
1346 {
1347         struct smu_table_context *smu_table = &smu->smu_table;
1348         SmuMetrics_t *metrics =
1349                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
1350         struct amdgpu_device *adev = smu->adev;
1351         uint32_t upper32 = 0, lower32 = 0;
1352         int ret;
1353
1354         ret = smu_cmn_get_metrics_table(smu, NULL, false);
1355         if (ret)
1356                 goto out;
1357
1358         upper32 = metrics->PublicSerialNumberUpper;
1359         lower32 = metrics->PublicSerialNumberLower;
1360
1361 out:
1362         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1363         if (adev->serial[0] == '\0')
1364                 sprintf(adev->serial, "%016llx", adev->unique_id);
1365 }
1366
1367 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
1368                                          uint32_t *speed)
1369 {
1370         if (!speed)
1371                 return -EINVAL;
1372
1373         return smu_v13_0_0_get_smu_metrics_data(smu,
1374                                                 METRICS_CURR_FANPWM,
1375                                                 speed);
1376 }
1377
1378 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
1379                                          uint32_t *speed)
1380 {
1381         if (!speed)
1382                 return -EINVAL;
1383
1384         return smu_v13_0_0_get_smu_metrics_data(smu,
1385                                                 METRICS_CURR_FANSPEED,
1386                                                 speed);
1387 }
1388
1389 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
1390 {
1391         struct smu_table_context *table_context = &smu->smu_table;
1392         PPTable_t *pptable = table_context->driver_pptable;
1393         SkuTable_t *skutable = &pptable->SkuTable;
1394
1395         /*
1396          * Skip the MGpuFanBoost setting for those ASICs
1397          * which do not support it
1398          */
1399         if (skutable->MGpuAcousticLimitRpmThreshold == 0)
1400                 return 0;
1401
1402         return smu_cmn_send_smc_msg_with_param(smu,
1403                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
1404                                                0,
1405                                                NULL);
1406 }
1407
1408 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
1409                                        uint32_t *current_power_limit,
1410                                        uint32_t *default_power_limit,
1411                                        uint32_t *max_power_limit)
1412 {
1413         struct smu_table_context *table_context = &smu->smu_table;
1414         struct smu_13_0_0_powerplay_table *powerplay_table =
1415                 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
1416         PPTable_t *pptable = table_context->driver_pptable;
1417         SkuTable_t *skutable = &pptable->SkuTable;
1418         uint32_t power_limit, od_percent;
1419
1420         if (smu_v13_0_get_current_power_limit(smu, &power_limit))
1421                 power_limit = smu->adev->pm.ac_power ?
1422                               skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1423                               skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1424
1425         if (current_power_limit)
1426                 *current_power_limit = power_limit;
1427         if (default_power_limit)
1428                 *default_power_limit = power_limit;
1429
1430         if (max_power_limit) {
1431                 if (smu->od_enabled) {
1432                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
1433
1434                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1435
1436                         power_limit *= (100 + od_percent);
1437                         power_limit /= 100;
1438                 }
1439                 *max_power_limit = power_limit;
1440         }
1441
1442         return 0;
1443 }
1444
1445 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
1446                                               char *buf)
1447 {
1448         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1449         DpmActivityMonitorCoeffInt_t *activity_monitor =
1450                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1451         static const char *title[] = {
1452                         "PROFILE_INDEX(NAME)",
1453                         "CLOCK_TYPE(NAME)",
1454                         "FPS",
1455                         "MinActiveFreqType",
1456                         "MinActiveFreq",
1457                         "BoosterFreqType",
1458                         "BoosterFreq",
1459                         "PD_Data_limit_c",
1460                         "PD_Data_error_coeff",
1461                         "PD_Data_error_rate_coeff"};
1462         int16_t workload_type = 0;
1463         uint32_t i, size = 0;
1464         int result = 0;
1465
1466         if (!buf)
1467                 return -EINVAL;
1468
1469         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
1470                         title[0], title[1], title[2], title[3], title[4], title[5],
1471                         title[6], title[7], title[8], title[9]);
1472
1473         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1474                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1475                 workload_type = smu_cmn_to_asic_specific_index(smu,
1476                                                                CMN2ASIC_MAPPING_WORKLOAD,
1477                                                                i);
1478                 if (workload_type < 0)
1479                         return -EINVAL;
1480
1481                 result = smu_cmn_update_table(smu,
1482                                               SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1483                                               workload_type,
1484                                               (void *)(&activity_monitor_external),
1485                                               false);
1486                 if (result) {
1487                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1488                         return result;
1489                 }
1490
1491                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1492                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1493
1494                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1495                         " ",
1496                         0,
1497                         "GFXCLK",
1498                         activity_monitor->Gfx_FPS,
1499                         activity_monitor->Gfx_MinActiveFreqType,
1500                         activity_monitor->Gfx_MinActiveFreq,
1501                         activity_monitor->Gfx_BoosterFreqType,
1502                         activity_monitor->Gfx_BoosterFreq,
1503                         activity_monitor->Gfx_PD_Data_limit_c,
1504                         activity_monitor->Gfx_PD_Data_error_coeff,
1505                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1506
1507                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1508                         " ",
1509                         1,
1510                         "FCLK",
1511                         activity_monitor->Fclk_FPS,
1512                         activity_monitor->Fclk_MinActiveFreqType,
1513                         activity_monitor->Fclk_MinActiveFreq,
1514                         activity_monitor->Fclk_BoosterFreqType,
1515                         activity_monitor->Fclk_BoosterFreq,
1516                         activity_monitor->Fclk_PD_Data_limit_c,
1517                         activity_monitor->Fclk_PD_Data_error_coeff,
1518                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1519         }
1520
1521         return size;
1522 }
1523
1524 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
1525                                               long *input,
1526                                               uint32_t size)
1527 {
1528         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1529         DpmActivityMonitorCoeffInt_t *activity_monitor =
1530                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1531         int workload_type, ret = 0;
1532
1533         smu->power_profile_mode = input[size];
1534
1535         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1536                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1537                 return -EINVAL;
1538         }
1539
1540         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1541                 ret = smu_cmn_update_table(smu,
1542                                            SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1543                                            WORKLOAD_PPLIB_CUSTOM_BIT,
1544                                            (void *)(&activity_monitor_external),
1545                                            false);
1546                 if (ret) {
1547                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1548                         return ret;
1549                 }
1550
1551                 switch (input[0]) {
1552                 case 0: /* Gfxclk */
1553                         activity_monitor->Gfx_FPS = input[1];
1554                         activity_monitor->Gfx_MinActiveFreqType = input[2];
1555                         activity_monitor->Gfx_MinActiveFreq = input[3];
1556                         activity_monitor->Gfx_BoosterFreqType = input[4];
1557                         activity_monitor->Gfx_BoosterFreq = input[5];
1558                         activity_monitor->Gfx_PD_Data_limit_c = input[6];
1559                         activity_monitor->Gfx_PD_Data_error_coeff = input[7];
1560                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8];
1561                         break;
1562                 case 1: /* Fclk */
1563                         activity_monitor->Fclk_FPS = input[1];
1564                         activity_monitor->Fclk_MinActiveFreqType = input[2];
1565                         activity_monitor->Fclk_MinActiveFreq = input[3];
1566                         activity_monitor->Fclk_BoosterFreqType = input[4];
1567                         activity_monitor->Fclk_BoosterFreq = input[5];
1568                         activity_monitor->Fclk_PD_Data_limit_c = input[6];
1569                         activity_monitor->Fclk_PD_Data_error_coeff = input[7];
1570                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8];
1571                         break;
1572                 }
1573
1574                 ret = smu_cmn_update_table(smu,
1575                                            SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1576                                            WORKLOAD_PPLIB_CUSTOM_BIT,
1577                                            (void *)(&activity_monitor_external),
1578                                            true);
1579                 if (ret) {
1580                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1581                         return ret;
1582                 }
1583         }
1584
1585         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1586         workload_type = smu_cmn_to_asic_specific_index(smu,
1587                                                        CMN2ASIC_MAPPING_WORKLOAD,
1588                                                        smu->power_profile_mode);
1589         if (workload_type < 0)
1590                 return -EINVAL;
1591
1592         return smu_cmn_send_smc_msg_with_param(smu,
1593                                                SMU_MSG_SetWorkloadMask,
1594                                                1 << workload_type,
1595                                                NULL);
1596 }
1597
1598 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
1599 {
1600         struct amdgpu_device *adev = smu->adev;
1601         u32 smu_version;
1602
1603         /* SRIOV does not support SMU mode1 reset */
1604         if (amdgpu_sriov_vf(adev))
1605                 return false;
1606
1607         /* PMFW support is available since 78.41 */
1608         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1609         if (smu_version < 0x004e2900)
1610                 return false;
1611
1612         return true;
1613 }
1614
1615 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
1616                                    struct i2c_msg *msg, int num_msgs)
1617 {
1618         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1619         struct amdgpu_device *adev = smu_i2c->adev;
1620         struct smu_context *smu = adev->powerplay.pp_handle;
1621         struct smu_table_context *smu_table = &smu->smu_table;
1622         struct smu_table *table = &smu_table->driver_table;
1623         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1624         int i, j, r, c;
1625         u16 dir;
1626
1627         if (!adev->pm.dpm_enabled)
1628                 return -EBUSY;
1629
1630         req = kzalloc(sizeof(*req), GFP_KERNEL);
1631         if (!req)
1632                 return -ENOMEM;
1633
1634         req->I2CcontrollerPort = smu_i2c->port;
1635         req->I2CSpeed = I2C_SPEED_FAST_400K;
1636         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1637         dir = msg[0].flags & I2C_M_RD;
1638
1639         for (c = i = 0; i < num_msgs; i++) {
1640                 for (j = 0; j < msg[i].len; j++, c++) {
1641                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1642
1643                         if (!(msg[i].flags & I2C_M_RD)) {
1644                                 /* write */
1645                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1646                                 cmd->ReadWriteData = msg[i].buf[j];
1647                         }
1648
1649                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
1650                                 /* The direction changes.
1651                                  */
1652                                 dir = msg[i].flags & I2C_M_RD;
1653                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1654                         }
1655
1656                         req->NumCmds++;
1657
1658                         /*
1659                          * Insert STOP if we are at the last byte of either last
1660                          * message for the transaction or the client explicitly
1661                          * requires a STOP at this particular message.
1662                          */
1663                         if ((j == msg[i].len - 1) &&
1664                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1665                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1666                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1667                         }
1668                 }
1669         }
1670         mutex_lock(&adev->pm.mutex);
1671         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1672         mutex_unlock(&adev->pm.mutex);
1673         if (r)
1674                 goto fail;
1675
1676         for (c = i = 0; i < num_msgs; i++) {
1677                 if (!(msg[i].flags & I2C_M_RD)) {
1678                         c += msg[i].len;
1679                         continue;
1680                 }
1681                 for (j = 0; j < msg[i].len; j++, c++) {
1682                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1683
1684                         msg[i].buf[j] = cmd->ReadWriteData;
1685                 }
1686         }
1687         r = num_msgs;
1688 fail:
1689         kfree(req);
1690         return r;
1691 }
1692
1693 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
1694 {
1695         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1696 }
1697
1698 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
1699         .master_xfer = smu_v13_0_0_i2c_xfer,
1700         .functionality = smu_v13_0_0_i2c_func,
1701 };
1702
1703 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
1704         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1705         .max_read_len  = MAX_SW_I2C_COMMANDS,
1706         .max_write_len = MAX_SW_I2C_COMMANDS,
1707         .max_comb_1st_msg_len = 2,
1708         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1709 };
1710
1711 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
1712 {
1713         struct amdgpu_device *adev = smu->adev;
1714         int res, i;
1715
1716         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1717                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1718                 struct i2c_adapter *control = &smu_i2c->adapter;
1719
1720                 smu_i2c->adev = adev;
1721                 smu_i2c->port = i;
1722                 mutex_init(&smu_i2c->mutex);
1723                 control->owner = THIS_MODULE;
1724                 control->class = I2C_CLASS_SPD;
1725                 control->dev.parent = &adev->pdev->dev;
1726                 control->algo = &smu_v13_0_0_i2c_algo;
1727                 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
1728                 control->quirks = &smu_v13_0_0_i2c_control_quirks;
1729                 i2c_set_adapdata(control, smu_i2c);
1730
1731                 res = i2c_add_adapter(control);
1732                 if (res) {
1733                         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1734                         goto Out_err;
1735                 }
1736         }
1737
1738         /* assign the buses used for the FRU EEPROM and RAS EEPROM */
1739         /* XXX ideally this would be something in a vbios data table */
1740         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
1741         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1742
1743         return 0;
1744 Out_err:
1745         for ( ; i >= 0; i--) {
1746                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1747                 struct i2c_adapter *control = &smu_i2c->adapter;
1748
1749                 i2c_del_adapter(control);
1750         }
1751         return res;
1752 }
1753
1754 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
1755 {
1756         struct amdgpu_device *adev = smu->adev;
1757         int i;
1758
1759         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1760                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1761                 struct i2c_adapter *control = &smu_i2c->adapter;
1762
1763                 i2c_del_adapter(control);
1764         }
1765         adev->pm.ras_eeprom_i2c_bus = NULL;
1766         adev->pm.fru_eeprom_i2c_bus = NULL;
1767 }
1768
1769 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
1770                                      enum pp_mp1_state mp1_state)
1771 {
1772         int ret;
1773
1774         switch (mp1_state) {
1775         case PP_MP1_STATE_UNLOAD:
1776                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
1777                 break;
1778         default:
1779                 /* Ignore others */
1780                 ret = 0;
1781         }
1782
1783         return ret;
1784 }
1785
1786 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
1787         .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
1788         .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
1789         .i2c_init = smu_v13_0_0_i2c_control_init,
1790         .i2c_fini = smu_v13_0_0_i2c_control_fini,
1791         .is_dpm_running = smu_v13_0_0_is_dpm_running,
1792         .dump_pptable = smu_v13_0_0_dump_pptable,
1793         .init_microcode = smu_v13_0_init_microcode,
1794         .load_microcode = smu_v13_0_load_microcode,
1795         .fini_microcode = smu_v13_0_fini_microcode,
1796         .init_smc_tables = smu_v13_0_0_init_smc_tables,
1797         .fini_smc_tables = smu_v13_0_fini_smc_tables,
1798         .init_power = smu_v13_0_init_power,
1799         .fini_power = smu_v13_0_fini_power,
1800         .check_fw_status = smu_v13_0_check_fw_status,
1801         .setup_pptable = smu_v13_0_0_setup_pptable,
1802         .check_fw_version = smu_v13_0_check_fw_version,
1803         .write_pptable = smu_cmn_write_pptable,
1804         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1805         .system_features_control = smu_v13_0_0_system_features_control,
1806         .set_allowed_mask = smu_v13_0_set_allowed_mask,
1807         .get_enabled_mask = smu_cmn_get_enabled_mask,
1808         .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
1809         .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
1810         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1811         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1812         .read_sensor = smu_v13_0_0_read_sensor,
1813         .feature_is_enabled = smu_cmn_feature_is_enabled,
1814         .print_clk_levels = smu_v13_0_0_print_clk_levels,
1815         .force_clk_levels = smu_v13_0_0_force_clk_levels,
1816         .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,
1817         .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
1818         .register_irq_handler = smu_v13_0_register_irq_handler,
1819         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1820         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1821         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1822         .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics,
1823         .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
1824         .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
1825         .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk,
1826         .set_performance_level = smu_v13_0_set_performance_level,
1827         .gfx_off_control = smu_v13_0_gfx_off_control,
1828         .get_unique_id = smu_v13_0_0_get_unique_id,
1829         .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm,
1830         .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm,
1831         .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
1832         .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
1833         .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
1834         .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
1835         .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
1836         .get_power_limit = smu_v13_0_0_get_power_limit,
1837         .set_power_limit = smu_v13_0_set_power_limit,
1838         .set_power_source = smu_v13_0_set_power_source,
1839         .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
1840         .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
1841         .run_btc = smu_v13_0_run_btc,
1842         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1843         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1844         .set_tool_table_location = smu_v13_0_set_tool_table_location,
1845         .deep_sleep_control = smu_v13_0_deep_sleep_control,
1846         .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
1847         .baco_is_support = smu_v13_0_baco_is_support,
1848         .baco_get_state = smu_v13_0_baco_get_state,
1849         .baco_set_state = smu_v13_0_baco_set_state,
1850         .baco_enter = smu_v13_0_baco_enter,
1851         .baco_exit = smu_v13_0_baco_exit,
1852         .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
1853         .mode1_reset = smu_v13_0_mode1_reset,
1854         .set_mp1_state = smu_v13_0_0_set_mp1_state,
1855 };
1856
1857 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
1858 {
1859         smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
1860         smu->message_map = smu_v13_0_0_message_map;
1861         smu->clock_map = smu_v13_0_0_clk_map;
1862         smu->feature_map = smu_v13_0_0_feature_mask_map;
1863         smu->table_map = smu_v13_0_0_table_map;
1864         smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
1865         smu->workload_map = smu_v13_0_0_workload_map;
1866         smu_v13_0_set_smu_mailbox_registers(smu);
1867 }