2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
39 #include "amdgpu_ras.h"
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
63 #define mmMP1_SMN_C2PMSG_66 0x0282
64 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
66 #define mmMP1_SMN_C2PMSG_82 0x0292
67 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
69 #define mmMP1_SMN_C2PMSG_90 0x029a
70 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
72 #define SMU13_VOLTAGE_SCALE 4
74 #define LINK_WIDTH_MAX 6
75 #define LINK_SPEED_MAX 3
77 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
78 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
80 #define smnPCIE_LC_SPEED_CNTL 0x11140290
81 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
84 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
85 static const int link_speed[] = {25, 50, 80, 160};
87 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
90 int smu_v13_0_init_microcode(struct smu_context *smu)
92 struct amdgpu_device *adev = smu->adev;
93 const char *chip_name;
95 char ucode_prefix[30];
97 const struct smc_firmware_header_v1_0 *hdr;
98 const struct common_firmware_header *header;
99 struct amdgpu_firmware_info *ucode = NULL;
101 /* doesn't need to load smu firmware in IOV mode */
102 if (amdgpu_sriov_vf(adev))
105 switch (adev->ip_versions[MP1_HWIP][0]) {
106 case IP_VERSION(13, 0, 2):
107 chip_name = "aldebaran_smc";
110 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
111 chip_name = ucode_prefix;
114 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
116 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
119 err = amdgpu_ucode_validate(adev->pm.fw);
123 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
124 amdgpu_ucode_print_smc_hdr(&hdr->header);
125 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
127 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
128 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
129 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
130 ucode->fw = adev->pm.fw;
131 header = (const struct common_firmware_header *)ucode->fw->data;
132 adev->firmware.fw_size +=
133 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
138 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
140 release_firmware(adev->pm.fw);
146 void smu_v13_0_fini_microcode(struct smu_context *smu)
148 struct amdgpu_device *adev = smu->adev;
150 release_firmware(adev->pm.fw);
152 adev->pm.fw_version = 0;
155 int smu_v13_0_load_microcode(struct smu_context *smu)
158 struct amdgpu_device *adev = smu->adev;
160 const struct smc_firmware_header_v1_0 *hdr;
161 uint32_t addr_start = MP1_SRAM;
163 uint32_t smc_fw_size;
164 uint32_t mp1_fw_flags;
166 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
167 src = (const uint32_t *)(adev->pm.fw->data +
168 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
169 smc_fw_size = hdr->header.ucode_size_bytes;
171 for (i = 1; i < smc_fw_size/4 - 1; i++) {
172 WREG32_PCIE(addr_start, src[i]);
176 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
177 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
178 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
179 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
181 for (i = 0; i < adev->usec_timeout; i++) {
182 mp1_fw_flags = RREG32_PCIE(MP1_Public |
183 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
184 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
185 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
190 if (i == adev->usec_timeout)
197 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
199 struct amdgpu_device *adev = smu->adev;
200 struct amdgpu_firmware_info *ucode = NULL;
201 uint32_t size = 0, pptable_id = 0;
205 /* doesn't need to load smu firmware in IOV mode */
206 if (amdgpu_sriov_vf(adev))
209 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
212 if (!adev->scpm_enabled)
215 /* override pptable_id from driver parameter */
216 if (amdgpu_smu_pptable_id >= 0) {
217 pptable_id = amdgpu_smu_pptable_id;
218 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
220 pptable_id = smu->smu_table.boot_values.pp_table_id;
222 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
226 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
230 * Temporary solution for SMU V13.0.0 with SCPM enabled:
231 * - use 36831 signed pptable when pp_table_id is 3683
232 * - use 36641 signed pptable when pp_table_id is 3664 or 0
233 * TODO: drop these when the pptable carried in vbios is ready.
235 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
236 switch (pptable_id) {
245 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
251 /* "pptable_id == 0" means vbios carries the pptable. */
255 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
259 smu->pptable_firmware.data = table;
260 smu->pptable_firmware.size = size;
262 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
263 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
264 ucode->fw = &smu->pptable_firmware;
265 adev->firmware.fw_size +=
266 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
271 int smu_v13_0_check_fw_status(struct smu_context *smu)
273 struct amdgpu_device *adev = smu->adev;
274 uint32_t mp1_fw_flags;
276 switch (adev->ip_versions[MP1_HWIP][0]) {
277 case IP_VERSION(13, 0, 4):
278 mp1_fw_flags = RREG32_PCIE(MP1_Public |
279 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
282 mp1_fw_flags = RREG32_PCIE(MP1_Public |
283 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
287 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
288 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
294 int smu_v13_0_check_fw_version(struct smu_context *smu)
296 struct amdgpu_device *adev = smu->adev;
297 uint32_t if_version = 0xff, smu_version = 0xff;
298 uint8_t smu_program, smu_major, smu_minor, smu_debug;
301 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
305 smu_program = (smu_version >> 24) & 0xff;
306 smu_major = (smu_version >> 16) & 0xff;
307 smu_minor = (smu_version >> 8) & 0xff;
308 smu_debug = (smu_version >> 0) & 0xff;
310 adev->pm.fw_version = smu_version;
312 switch (adev->ip_versions[MP1_HWIP][0]) {
313 case IP_VERSION(13, 0, 2):
314 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
316 case IP_VERSION(13, 0, 0):
317 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0;
319 case IP_VERSION(13, 0, 7):
320 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
322 case IP_VERSION(13, 0, 1):
323 case IP_VERSION(13, 0, 3):
324 case IP_VERSION(13, 0, 8):
325 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
327 case IP_VERSION(13, 0, 4):
328 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
330 case IP_VERSION(13, 0, 5):
331 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
334 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
335 adev->ip_versions[MP1_HWIP][0]);
336 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
340 /* only for dGPU w/ SMU13*/
342 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
343 smu_program, smu_version, smu_major, smu_minor, smu_debug);
346 * 1. if_version mismatch is not critical as our fw is designed
347 * to be backward compatible.
348 * 2. New fw usually brings some optimizations. But that's visible
349 * only on the paired driver.
350 * Considering above, we just leave user a warning message instead
351 * of halt driver loading.
353 if (if_version != smu->smc_driver_if_version) {
354 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
355 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
356 smu->smc_driver_if_version, if_version,
357 smu_program, smu_version, smu_major, smu_minor, smu_debug);
358 dev_warn(adev->dev, "SMU driver if version not matched\n");
364 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
366 struct amdgpu_device *adev = smu->adev;
367 uint32_t ppt_offset_bytes;
368 const struct smc_firmware_header_v2_0 *v2;
370 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
372 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
373 *size = le32_to_cpu(v2->ppt_size_bytes);
374 *table = (uint8_t *)v2 + ppt_offset_bytes;
379 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
380 uint32_t *size, uint32_t pptable_id)
382 struct amdgpu_device *adev = smu->adev;
383 const struct smc_firmware_header_v2_1 *v2_1;
384 struct smc_soft_pptable_entry *entries;
385 uint32_t pptable_count = 0;
388 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
389 entries = (struct smc_soft_pptable_entry *)
390 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
391 pptable_count = le32_to_cpu(v2_1->pptable_count);
392 for (i = 0; i < pptable_count; i++) {
393 if (le32_to_cpu(entries[i].id) == pptable_id) {
394 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
395 *size = le32_to_cpu(entries[i].ppt_size_bytes);
400 if (i == pptable_count)
406 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
408 struct amdgpu_device *adev = smu->adev;
409 uint16_t atom_table_size;
413 dev_info(adev->dev, "use vbios provided pptable\n");
414 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
417 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
423 *size = atom_table_size;
428 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
431 const struct smc_firmware_header_v1_0 *hdr;
432 struct amdgpu_device *adev = smu->adev;
433 uint16_t version_major, version_minor;
436 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
440 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
442 version_major = le16_to_cpu(hdr->header.header_version_major);
443 version_minor = le16_to_cpu(hdr->header.header_version_minor);
444 if (version_major != 2) {
445 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
446 version_major, version_minor);
450 switch (version_minor) {
452 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
455 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
465 int smu_v13_0_setup_pptable(struct smu_context *smu)
467 struct amdgpu_device *adev = smu->adev;
468 uint32_t size = 0, pptable_id = 0;
472 /* override pptable_id from driver parameter */
473 if (amdgpu_smu_pptable_id >= 0) {
474 pptable_id = amdgpu_smu_pptable_id;
475 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
477 pptable_id = smu->smu_table.boot_values.pp_table_id;
480 * Temporary solution for SMU V13.0.0 with SCPM disabled:
481 * - use 3664 or 3683 on request
482 * - use 3664 when pptable_id is 0
483 * TODO: drop these when the pptable carried in vbios is ready.
485 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
486 switch (pptable_id) {
494 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
500 /* force using vbios pptable in sriov mode */
501 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
502 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
504 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
509 if (!smu->smu_table.power_play_table)
510 smu->smu_table.power_play_table = table;
511 if (!smu->smu_table.power_play_table_size)
512 smu->smu_table.power_play_table_size = size;
517 int smu_v13_0_init_smc_tables(struct smu_context *smu)
519 struct smu_table_context *smu_table = &smu->smu_table;
520 struct smu_table *tables = smu_table->tables;
523 smu_table->driver_pptable =
524 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
525 if (!smu_table->driver_pptable) {
530 smu_table->max_sustainable_clocks =
531 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
532 if (!smu_table->max_sustainable_clocks) {
537 /* Aldebaran does not support OVERDRIVE */
538 if (tables[SMU_TABLE_OVERDRIVE].size) {
539 smu_table->overdrive_table =
540 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
541 if (!smu_table->overdrive_table) {
546 smu_table->boot_overdrive_table =
547 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
548 if (!smu_table->boot_overdrive_table) {
554 smu_table->combo_pptable =
555 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
556 if (!smu_table->combo_pptable) {
564 kfree(smu_table->boot_overdrive_table);
566 kfree(smu_table->overdrive_table);
568 kfree(smu_table->max_sustainable_clocks);
570 kfree(smu_table->driver_pptable);
575 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
577 struct smu_table_context *smu_table = &smu->smu_table;
578 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
580 kfree(smu_table->gpu_metrics_table);
581 kfree(smu_table->combo_pptable);
582 kfree(smu_table->boot_overdrive_table);
583 kfree(smu_table->overdrive_table);
584 kfree(smu_table->max_sustainable_clocks);
585 kfree(smu_table->driver_pptable);
586 smu_table->gpu_metrics_table = NULL;
587 smu_table->combo_pptable = NULL;
588 smu_table->boot_overdrive_table = NULL;
589 smu_table->overdrive_table = NULL;
590 smu_table->max_sustainable_clocks = NULL;
591 smu_table->driver_pptable = NULL;
592 kfree(smu_table->hardcode_pptable);
593 smu_table->hardcode_pptable = NULL;
595 kfree(smu_table->ecc_table);
596 kfree(smu_table->metrics_table);
597 kfree(smu_table->watermarks_table);
598 smu_table->ecc_table = NULL;
599 smu_table->metrics_table = NULL;
600 smu_table->watermarks_table = NULL;
601 smu_table->metrics_time = 0;
603 kfree(smu_dpm->dpm_context);
604 kfree(smu_dpm->golden_dpm_context);
605 kfree(smu_dpm->dpm_current_power_state);
606 kfree(smu_dpm->dpm_request_power_state);
607 smu_dpm->dpm_context = NULL;
608 smu_dpm->golden_dpm_context = NULL;
609 smu_dpm->dpm_context_size = 0;
610 smu_dpm->dpm_current_power_state = NULL;
611 smu_dpm->dpm_request_power_state = NULL;
616 int smu_v13_0_init_power(struct smu_context *smu)
618 struct smu_power_context *smu_power = &smu->smu_power;
620 if (smu_power->power_context || smu_power->power_context_size != 0)
623 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
625 if (!smu_power->power_context)
627 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
632 int smu_v13_0_fini_power(struct smu_context *smu)
634 struct smu_power_context *smu_power = &smu->smu_power;
636 if (!smu_power->power_context || smu_power->power_context_size == 0)
639 kfree(smu_power->power_context);
640 smu_power->power_context = NULL;
641 smu_power->power_context_size = 0;
646 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
651 struct atom_common_table_header *header;
652 struct atom_firmware_info_v3_4 *v_3_4;
653 struct atom_firmware_info_v3_3 *v_3_3;
654 struct atom_firmware_info_v3_1 *v_3_1;
655 struct atom_smu_info_v3_6 *smu_info_v3_6;
656 struct atom_smu_info_v4_0 *smu_info_v4_0;
658 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
661 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
662 (uint8_t **)&header);
666 if (header->format_revision != 3) {
667 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
671 switch (header->content_revision) {
675 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
676 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
677 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
678 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
679 smu->smu_table.boot_values.socclk = 0;
680 smu->smu_table.boot_values.dcefclk = 0;
681 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
682 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
683 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
684 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
685 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
686 smu->smu_table.boot_values.pp_table_id = 0;
689 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
690 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
691 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
692 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
693 smu->smu_table.boot_values.socclk = 0;
694 smu->smu_table.boot_values.dcefclk = 0;
695 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
696 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
697 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
698 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
699 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
700 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
704 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
705 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
706 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
707 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
708 smu->smu_table.boot_values.socclk = 0;
709 smu->smu_table.boot_values.dcefclk = 0;
710 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
711 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
712 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
713 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
714 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
715 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
719 smu->smu_table.boot_values.format_revision = header->format_revision;
720 smu->smu_table.boot_values.content_revision = header->content_revision;
722 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
724 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
725 (uint8_t **)&header)) {
727 if ((frev == 3) && (crev == 6)) {
728 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
730 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
731 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
732 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
733 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
734 } else if ((frev == 3) && (crev == 1)) {
736 } else if ((frev == 4) && (crev == 0)) {
737 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
739 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
740 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
741 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
742 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
743 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
745 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
746 (uint32_t)frev, (uint32_t)crev);
754 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
756 struct smu_table_context *smu_table = &smu->smu_table;
757 struct smu_table *memory_pool = &smu_table->memory_pool;
760 uint32_t address_low, address_high;
762 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
765 address = memory_pool->mc_address;
766 address_high = (uint32_t)upper_32_bits(address);
767 address_low = (uint32_t)lower_32_bits(address);
769 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
773 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
777 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
778 (uint32_t)memory_pool->size, NULL);
785 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
789 ret = smu_cmn_send_smc_msg_with_param(smu,
790 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
792 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
797 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
799 struct smu_table *driver_table = &smu->smu_table.driver_table;
802 if (driver_table->mc_address) {
803 ret = smu_cmn_send_smc_msg_with_param(smu,
804 SMU_MSG_SetDriverDramAddrHigh,
805 upper_32_bits(driver_table->mc_address),
808 ret = smu_cmn_send_smc_msg_with_param(smu,
809 SMU_MSG_SetDriverDramAddrLow,
810 lower_32_bits(driver_table->mc_address),
817 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
820 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
822 if (tool_table->mc_address) {
823 ret = smu_cmn_send_smc_msg_with_param(smu,
824 SMU_MSG_SetToolsDramAddrHigh,
825 upper_32_bits(tool_table->mc_address),
828 ret = smu_cmn_send_smc_msg_with_param(smu,
829 SMU_MSG_SetToolsDramAddrLow,
830 lower_32_bits(tool_table->mc_address),
837 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
841 if (!smu->pm_enabled)
844 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
849 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
851 struct smu_feature *feature = &smu->smu_feature;
853 uint32_t feature_mask[2];
855 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
856 feature->feature_num < 64)
859 bitmap_to_arr32(feature_mask, feature->allowed, 64);
861 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
862 feature_mask[1], NULL);
866 return smu_cmn_send_smc_msg_with_param(smu,
867 SMU_MSG_SetAllowedFeaturesMaskLow,
872 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
875 struct amdgpu_device *adev = smu->adev;
877 switch (adev->ip_versions[MP1_HWIP][0]) {
878 case IP_VERSION(13, 0, 0):
879 case IP_VERSION(13, 0, 1):
880 case IP_VERSION(13, 0, 3):
881 case IP_VERSION(13, 0, 4):
882 case IP_VERSION(13, 0, 5):
883 case IP_VERSION(13, 0, 7):
884 case IP_VERSION(13, 0, 8):
885 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
888 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
890 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
899 int smu_v13_0_system_features_control(struct smu_context *smu,
902 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
903 SMU_MSG_DisableAllSmuFeatures), NULL);
906 int smu_v13_0_notify_display_change(struct smu_context *smu)
910 if (!smu->pm_enabled)
913 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
914 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
915 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
921 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
922 enum smu_clk_type clock_select)
927 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
928 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
931 clk_id = smu_cmn_to_asic_specific_index(smu,
932 CMN2ASIC_MAPPING_CLK,
937 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
938 clk_id << 16, clock);
940 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
947 /* if DC limit is zero, return AC limit */
948 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
949 clk_id << 16, clock);
951 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
958 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
960 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
961 smu->smu_table.max_sustainable_clocks;
964 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
965 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
966 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
967 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
968 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
969 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
972 ret = smu_v13_0_get_max_sustainable_clock(smu,
973 &(max_sustainable_clocks->uclock),
976 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
982 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
983 ret = smu_v13_0_get_max_sustainable_clock(smu,
984 &(max_sustainable_clocks->soc_clock),
987 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
993 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
994 ret = smu_v13_0_get_max_sustainable_clock(smu,
995 &(max_sustainable_clocks->dcef_clock),
998 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
1003 ret = smu_v13_0_get_max_sustainable_clock(smu,
1004 &(max_sustainable_clocks->display_clock),
1007 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
1011 ret = smu_v13_0_get_max_sustainable_clock(smu,
1012 &(max_sustainable_clocks->phy_clock),
1015 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
1019 ret = smu_v13_0_get_max_sustainable_clock(smu,
1020 &(max_sustainable_clocks->pixel_clock),
1023 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
1029 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1030 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1035 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
1036 uint32_t *power_limit)
1041 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1044 power_src = smu_cmn_to_asic_specific_index(smu,
1045 CMN2ASIC_MAPPING_PWR,
1046 smu->adev->pm.ac_power ?
1047 SMU_POWER_SOURCE_AC :
1048 SMU_POWER_SOURCE_DC);
1052 ret = smu_cmn_send_smc_msg_with_param(smu,
1053 SMU_MSG_GetPptLimit,
1057 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1062 int smu_v13_0_set_power_limit(struct smu_context *smu,
1063 enum smu_ppt_limit_type limit_type,
1068 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1071 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1072 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1076 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1078 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1082 smu->current_power_limit = limit;
1087 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1089 return smu_cmn_send_smc_msg(smu,
1090 SMU_MSG_AllowIHHostInterrupt,
1094 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1098 if (smu->dc_controlled_by_gpio &&
1099 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1100 ret = smu_v13_0_allow_ih_interrupt(smu);
1105 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1109 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1113 return smu_v13_0_process_pending_interrupt(smu);
1116 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1118 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1121 static uint16_t convert_to_vddc(uint8_t vid)
1123 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1126 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1128 struct amdgpu_device *adev = smu->adev;
1129 uint32_t vdd = 0, val_vid = 0;
1133 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1134 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1135 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1137 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1146 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1147 struct pp_display_clock_request
1150 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1152 enum smu_clk_type clk_select = 0;
1153 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1155 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1156 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1158 case amd_pp_dcef_clock:
1159 clk_select = SMU_DCEFCLK;
1161 case amd_pp_disp_clock:
1162 clk_select = SMU_DISPCLK;
1164 case amd_pp_pixel_clock:
1165 clk_select = SMU_PIXCLK;
1167 case amd_pp_phy_clock:
1168 clk_select = SMU_PHYCLK;
1170 case amd_pp_mem_clock:
1171 clk_select = SMU_UCLK;
1174 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1182 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1185 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1187 if(clk_select == SMU_UCLK)
1188 smu->hard_min_uclk_req_from_dal = clk_freq;
1195 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1197 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1198 return AMD_FAN_CTRL_MANUAL;
1200 return AMD_FAN_CTRL_AUTO;
1204 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1208 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1211 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1213 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1214 __func__, (auto_fan_control ? "Start" : "Stop"));
1220 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1222 struct amdgpu_device *adev = smu->adev;
1224 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1225 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1226 CG_FDO_CTRL2, TMIN, 0));
1227 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1228 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1229 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1234 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1237 struct amdgpu_device *adev = smu->adev;
1238 uint32_t duty100, duty;
1241 speed = MIN(speed, 255);
1243 if (smu_v13_0_auto_fan_control(smu, 0))
1246 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1247 CG_FDO_CTRL1, FMAX_DUTY100);
1251 tmp64 = (uint64_t)speed * duty100;
1253 duty = (uint32_t)tmp64;
1255 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1256 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1257 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1259 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1263 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1269 case AMD_FAN_CTRL_NONE:
1270 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1272 case AMD_FAN_CTRL_MANUAL:
1273 ret = smu_v13_0_auto_fan_control(smu, 0);
1275 case AMD_FAN_CTRL_AUTO:
1276 ret = smu_v13_0_auto_fan_control(smu, 1);
1283 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1290 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1293 struct amdgpu_device *adev = smu->adev;
1294 uint32_t tach_period, crystal_clock_freq;
1300 ret = smu_v13_0_auto_fan_control(smu, 0);
1304 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1305 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1306 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1307 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1308 CG_TACH_CTRL, TARGET_PERIOD,
1311 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1314 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1318 ret = smu_cmn_send_smc_msg_with_param(smu,
1319 SMU_MSG_SetXgmiMode,
1320 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1325 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1326 struct amdgpu_irq_src *source,
1328 enum amdgpu_interrupt_state state)
1330 struct smu_context *smu = adev->powerplay.pp_handle;
1335 case AMDGPU_IRQ_STATE_DISABLE:
1337 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1338 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1339 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1340 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1342 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1344 /* For MP1 SW irqs */
1345 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1346 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1347 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1350 case AMDGPU_IRQ_STATE_ENABLE:
1352 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1353 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1354 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1355 smu->thermal_range.software_shutdown_temp);
1357 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1358 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1359 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1360 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1361 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1362 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1363 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1364 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1365 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1367 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1368 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1369 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1370 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1372 /* For MP1 SW irqs */
1373 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1374 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1375 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1376 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1378 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1379 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1380 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1390 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1392 return smu_cmn_send_smc_msg(smu,
1393 SMU_MSG_ReenableAcDcInterrupt,
1397 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1398 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1399 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1401 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1402 struct amdgpu_irq_src *source,
1403 struct amdgpu_iv_entry *entry)
1405 struct smu_context *smu = adev->powerplay.pp_handle;
1406 uint32_t client_id = entry->client_id;
1407 uint32_t src_id = entry->src_id;
1409 * ctxid is used to distinguish different
1410 * events for SMCToHost interrupt.
1412 uint32_t ctxid = entry->src_data[0];
1415 if (client_id == SOC15_IH_CLIENTID_THM) {
1417 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1418 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1420 * SW CTF just occurred.
1421 * Try to do a graceful shutdown to prevent further damage.
1423 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1424 orderly_poweroff(true);
1426 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1427 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1430 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1434 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1435 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1437 * HW CTF just occurred. Shutdown to prevent further damage.
1439 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1440 orderly_poweroff(true);
1441 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1442 if (src_id == 0xfe) {
1443 /* ACK SMUToHost interrupt */
1444 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1445 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1446 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1450 dev_dbg(adev->dev, "Switched to AC mode!\n");
1451 smu_v13_0_ack_ac_dc_interrupt(smu);
1454 dev_dbg(adev->dev, "Switched to DC mode!\n");
1455 smu_v13_0_ack_ac_dc_interrupt(smu);
1459 * Increment the throttle interrupt counter
1461 atomic64_inc(&smu->throttle_int_counter);
1463 if (!atomic_read(&adev->throttling_logging_enabled))
1466 if (__ratelimit(&adev->throttling_logging_rs))
1467 schedule_work(&smu->throttling_logging_work);
1477 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1479 .set = smu_v13_0_set_irq_state,
1480 .process = smu_v13_0_irq_process,
1483 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1485 struct amdgpu_device *adev = smu->adev;
1486 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1489 irq_src->num_types = 1;
1490 irq_src->funcs = &smu_v13_0_irq_funcs;
1492 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1493 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1498 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1499 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1504 /* Register CTF(GPIO_19) interrupt */
1505 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1506 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1511 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1520 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1521 struct pp_smu_nv_clock_table *max_clocks)
1523 struct smu_table_context *table_context = &smu->smu_table;
1524 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1526 if (!max_clocks || !table_context->max_sustainable_clocks)
1529 sustainable_clocks = table_context->max_sustainable_clocks;
1531 max_clocks->dcfClockInKhz =
1532 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1533 max_clocks->displayClockInKhz =
1534 (unsigned int) sustainable_clocks->display_clock * 1000;
1535 max_clocks->phyClockInKhz =
1536 (unsigned int) sustainable_clocks->phy_clock * 1000;
1537 max_clocks->pixelClockInKhz =
1538 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1539 max_clocks->uClockInKhz =
1540 (unsigned int) sustainable_clocks->uclock * 1000;
1541 max_clocks->socClockInKhz =
1542 (unsigned int) sustainable_clocks->soc_clock * 1000;
1543 max_clocks->dscClockInKhz = 0;
1544 max_clocks->dppClockInKhz = 0;
1545 max_clocks->fabricClockInKhz = 0;
1550 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1554 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1559 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1564 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1565 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1570 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1576 case SMU_EVENT_RESET_COMPLETE:
1577 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1586 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1587 uint32_t *min, uint32_t *max)
1589 int ret = 0, clk_id = 0;
1591 uint32_t clock_limit;
1593 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1597 clock_limit = smu->smu_table.boot_values.uclk;
1601 clock_limit = smu->smu_table.boot_values.gfxclk;
1604 clock_limit = smu->smu_table.boot_values.socclk;
1611 /* clock in Mhz unit */
1613 *min = clock_limit / 100;
1615 *max = clock_limit / 100;
1620 clk_id = smu_cmn_to_asic_specific_index(smu,
1621 CMN2ASIC_MAPPING_CLK,
1627 param = (clk_id & 0xffff) << 16;
1630 if (smu->adev->pm.ac_power)
1631 ret = smu_cmn_send_smc_msg_with_param(smu,
1632 SMU_MSG_GetMaxDpmFreq,
1636 ret = smu_cmn_send_smc_msg_with_param(smu,
1637 SMU_MSG_GetDcModeMaxDpmFreq,
1645 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1654 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1655 enum smu_clk_type clk_type,
1659 int ret = 0, clk_id = 0;
1662 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1665 clk_id = smu_cmn_to_asic_specific_index(smu,
1666 CMN2ASIC_MAPPING_CLK,
1672 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1673 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1680 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1681 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1691 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1692 enum smu_clk_type clk_type,
1696 int ret = 0, clk_id = 0;
1699 if (min <= 0 && max <= 0)
1702 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1705 clk_id = smu_cmn_to_asic_specific_index(smu,
1706 CMN2ASIC_MAPPING_CLK,
1712 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1713 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1720 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1721 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1730 int smu_v13_0_set_performance_level(struct smu_context *smu,
1731 enum amd_dpm_forced_level level)
1733 struct smu_13_0_dpm_context *dpm_context =
1734 smu->smu_dpm.dpm_context;
1735 struct smu_13_0_dpm_table *gfx_table =
1736 &dpm_context->dpm_tables.gfx_table;
1737 struct smu_13_0_dpm_table *mem_table =
1738 &dpm_context->dpm_tables.uclk_table;
1739 struct smu_13_0_dpm_table *soc_table =
1740 &dpm_context->dpm_tables.soc_table;
1741 struct smu_13_0_dpm_table *vclk_table =
1742 &dpm_context->dpm_tables.vclk_table;
1743 struct smu_13_0_dpm_table *dclk_table =
1744 &dpm_context->dpm_tables.dclk_table;
1745 struct smu_13_0_dpm_table *fclk_table =
1746 &dpm_context->dpm_tables.fclk_table;
1747 struct smu_umd_pstate_table *pstate_table =
1749 struct amdgpu_device *adev = smu->adev;
1750 uint32_t sclk_min = 0, sclk_max = 0;
1751 uint32_t mclk_min = 0, mclk_max = 0;
1752 uint32_t socclk_min = 0, socclk_max = 0;
1753 uint32_t vclk_min = 0, vclk_max = 0;
1754 uint32_t dclk_min = 0, dclk_max = 0;
1755 uint32_t fclk_min = 0, fclk_max = 0;
1759 case AMD_DPM_FORCED_LEVEL_HIGH:
1760 sclk_min = sclk_max = gfx_table->max;
1761 mclk_min = mclk_max = mem_table->max;
1762 socclk_min = socclk_max = soc_table->max;
1763 vclk_min = vclk_max = vclk_table->max;
1764 dclk_min = dclk_max = dclk_table->max;
1765 fclk_min = fclk_max = fclk_table->max;
1767 case AMD_DPM_FORCED_LEVEL_LOW:
1768 sclk_min = sclk_max = gfx_table->min;
1769 mclk_min = mclk_max = mem_table->min;
1770 socclk_min = socclk_max = soc_table->min;
1771 vclk_min = vclk_max = vclk_table->min;
1772 dclk_min = dclk_max = dclk_table->min;
1773 fclk_min = fclk_max = fclk_table->min;
1775 case AMD_DPM_FORCED_LEVEL_AUTO:
1776 sclk_min = gfx_table->min;
1777 sclk_max = gfx_table->max;
1778 mclk_min = mem_table->min;
1779 mclk_max = mem_table->max;
1780 socclk_min = soc_table->min;
1781 socclk_max = soc_table->max;
1782 vclk_min = vclk_table->min;
1783 vclk_max = vclk_table->max;
1784 dclk_min = dclk_table->min;
1785 dclk_max = dclk_table->max;
1786 fclk_min = fclk_table->min;
1787 fclk_max = fclk_table->max;
1789 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1790 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1791 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1792 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1793 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1794 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1795 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1797 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1798 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1800 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1801 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1803 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1804 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1805 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1806 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1807 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1808 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1809 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1811 case AMD_DPM_FORCED_LEVEL_MANUAL:
1812 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1815 dev_err(adev->dev, "Invalid performance level %d\n", level);
1820 * Unset those settings for SMU 13.0.2. As soft limits settings
1821 * for those clock domains are not supported.
1823 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1824 mclk_min = mclk_max = 0;
1825 socclk_min = socclk_max = 0;
1826 vclk_min = vclk_max = 0;
1827 dclk_min = dclk_max = 0;
1828 fclk_min = fclk_max = 0;
1831 if (sclk_min && sclk_max) {
1832 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1839 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1840 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1843 if (mclk_min && mclk_max) {
1844 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1851 pstate_table->uclk_pstate.curr.min = mclk_min;
1852 pstate_table->uclk_pstate.curr.max = mclk_max;
1855 if (socclk_min && socclk_max) {
1856 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1863 pstate_table->socclk_pstate.curr.min = socclk_min;
1864 pstate_table->socclk_pstate.curr.max = socclk_max;
1867 if (vclk_min && vclk_max) {
1868 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1869 if (adev->vcn.harvest_config & (1 << i))
1871 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1872 i ? SMU_VCLK1 : SMU_VCLK,
1878 pstate_table->vclk_pstate.curr.min = vclk_min;
1879 pstate_table->vclk_pstate.curr.max = vclk_max;
1882 if (dclk_min && dclk_max) {
1883 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1884 if (adev->vcn.harvest_config & (1 << i))
1886 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1887 i ? SMU_DCLK1 : SMU_DCLK,
1893 pstate_table->dclk_pstate.curr.min = dclk_min;
1894 pstate_table->dclk_pstate.curr.max = dclk_max;
1897 if (fclk_min && fclk_max) {
1898 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1905 pstate_table->fclk_pstate.curr.min = fclk_min;
1906 pstate_table->fclk_pstate.curr.max = fclk_max;
1912 int smu_v13_0_set_power_source(struct smu_context *smu,
1913 enum smu_power_src_type power_src)
1917 pwr_source = smu_cmn_to_asic_specific_index(smu,
1918 CMN2ASIC_MAPPING_PWR,
1919 (uint32_t)power_src);
1923 return smu_cmn_send_smc_msg_with_param(smu,
1924 SMU_MSG_NotifyPowerSource,
1929 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1930 enum smu_clk_type clk_type,
1934 int ret = 0, clk_id = 0;
1940 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1943 clk_id = smu_cmn_to_asic_specific_index(smu,
1944 CMN2ASIC_MAPPING_CLK,
1949 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1951 ret = smu_cmn_send_smc_msg_with_param(smu,
1952 SMU_MSG_GetDpmFreqByIndex,
1958 *value = *value & 0x7fffffff;
1963 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1964 enum smu_clk_type clk_type,
1969 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1970 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1971 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1977 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1978 enum smu_clk_type clk_type,
1979 bool *is_fine_grained_dpm)
1981 int ret = 0, clk_id = 0;
1985 if (!is_fine_grained_dpm)
1988 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1991 clk_id = smu_cmn_to_asic_specific_index(smu,
1992 CMN2ASIC_MAPPING_CLK,
1997 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1999 ret = smu_cmn_send_smc_msg_with_param(smu,
2000 SMU_MSG_GetDpmFreqByIndex,
2007 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
2008 * now, we un-support it
2010 *is_fine_grained_dpm = value & 0x80000000;
2015 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
2016 enum smu_clk_type clk_type,
2017 struct smu_13_0_dpm_table *single_dpm_table)
2023 ret = smu_v13_0_get_dpm_level_count(smu,
2025 &single_dpm_table->count);
2027 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2031 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
2032 ret = smu_v13_0_get_fine_grained_status(smu,
2034 &single_dpm_table->is_fine_grained);
2036 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2041 for (i = 0; i < single_dpm_table->count; i++) {
2042 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2047 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2051 single_dpm_table->dpm_levels[i].value = clk;
2052 single_dpm_table->dpm_levels[i].enabled = true;
2055 single_dpm_table->min = clk;
2056 else if (i == single_dpm_table->count - 1)
2057 single_dpm_table->max = clk;
2063 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2064 enum smu_clk_type clk_type,
2065 uint32_t *min_value,
2066 uint32_t *max_value)
2068 uint32_t level_count = 0;
2071 if (!min_value && !max_value)
2075 /* by default, level 0 clock value as min value */
2076 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2085 ret = smu_v13_0_get_dpm_level_count(smu,
2091 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2102 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2104 struct amdgpu_device *adev = smu->adev;
2106 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2107 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2108 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2111 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2113 uint32_t width_level;
2115 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2116 if (width_level > LINK_WIDTH_MAX)
2119 return link_width[width_level];
2122 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2124 struct amdgpu_device *adev = smu->adev;
2126 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2127 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2128 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2131 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2133 uint32_t speed_level;
2135 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2136 if (speed_level > LINK_SPEED_MAX)
2139 return link_speed[speed_level];
2142 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2145 struct amdgpu_device *adev = smu->adev;
2148 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2149 if (adev->vcn.harvest_config & (1 << i))
2152 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2153 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2162 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2165 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2166 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2170 int smu_v13_0_run_btc(struct smu_context *smu)
2174 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2176 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2181 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2184 struct amdgpu_device *adev = smu->adev;
2187 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2188 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2190 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2195 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2196 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2198 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2203 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2204 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2206 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2211 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2212 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2214 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2219 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2220 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2222 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2227 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2228 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2230 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2235 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2236 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2238 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2243 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2244 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2246 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2254 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2259 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2260 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2265 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2267 struct smu_baco_context *smu_baco = &smu->smu_baco;
2269 if (amdgpu_sriov_vf(smu->adev) ||
2270 !smu_baco->platform_support)
2273 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2274 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2280 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2282 struct smu_baco_context *smu_baco = &smu->smu_baco;
2284 return smu_baco->state;
2287 int smu_v13_0_baco_set_state(struct smu_context *smu,
2288 enum smu_baco_state state)
2290 struct smu_baco_context *smu_baco = &smu->smu_baco;
2291 struct amdgpu_device *adev = smu->adev;
2294 if (smu_v13_0_baco_get_state(smu) == state)
2297 if (state == SMU_BACO_STATE_ENTER) {
2298 ret = smu_cmn_send_smc_msg_with_param(smu,
2300 smu_baco->maco_support ?
2301 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2304 ret = smu_cmn_send_smc_msg(smu,
2310 /* clear vbios scratch 6 and 7 for coming asic reinit */
2311 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2312 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2316 smu_baco->state = state;
2321 int smu_v13_0_baco_enter(struct smu_context *smu)
2325 ret = smu_v13_0_baco_set_state(smu,
2326 SMU_BACO_STATE_ENTER);
2335 int smu_v13_0_baco_exit(struct smu_context *smu)
2337 return smu_v13_0_baco_set_state(smu,
2338 SMU_BACO_STATE_EXIT);
2341 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2345 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2346 SMU_MSG_EnableGfxImu);
2348 return smu_cmn_send_msg_without_waiting(smu, index, 0);
2351 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2352 enum PP_OD_DPM_TABLE_COMMAND type,
2353 long input[], uint32_t size)
2355 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2358 /* Only allowed in manual mode */
2359 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2363 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2365 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2369 if (input[0] == 0) {
2370 if (input[1] < smu->gfx_default_hard_min_freq) {
2371 dev_warn(smu->adev->dev,
2372 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2373 input[1], smu->gfx_default_hard_min_freq);
2376 smu->gfx_actual_hard_min_freq = input[1];
2377 } else if (input[0] == 1) {
2378 if (input[1] > smu->gfx_default_soft_max_freq) {
2379 dev_warn(smu->adev->dev,
2380 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2381 input[1], smu->gfx_default_soft_max_freq);
2384 smu->gfx_actual_soft_max_freq = input[1];
2389 case PP_OD_RESTORE_DEFAULT_TABLE:
2391 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2394 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2395 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2397 case PP_OD_COMMIT_DPM_TABLE:
2399 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2402 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2403 dev_err(smu->adev->dev,
2404 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2405 smu->gfx_actual_hard_min_freq,
2406 smu->gfx_actual_soft_max_freq);
2410 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2411 smu->gfx_actual_hard_min_freq,
2414 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2418 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2419 smu->gfx_actual_soft_max_freq,
2422 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2433 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2435 struct smu_table_context *smu_table = &smu->smu_table;
2437 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2438 smu_table->clocks_table, false);
2441 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2443 struct amdgpu_device *adev = smu->adev;
2445 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2446 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2447 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2450 int smu_v13_0_mode1_reset(struct smu_context *smu)
2454 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2456 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);