drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_13_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v13_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_13_0_2_offset.h"
  43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_13_0_2_offset.h"
  45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
  47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
  60
  61 #define SMU13_VOLTAGE_SCALE 4
  62
  63 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  64
  65 #define LINK_WIDTH_MAX                          6
  66 #define LINK_SPEED_MAX                          3
  67
  68 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  69 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  70 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  71 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  72 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  73 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  74
  75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  76 static const int link_speed[] = {25, 50, 80, 160};
  77
  78 int smu_v13_0_init_microcode(struct smu_context *smu)
  79 {
  80         struct amdgpu_device *adev = smu->adev;
  81         const char *chip_name;
  82         char fw_name[30];
  83         int err = 0;
  84         const struct smc_firmware_header_v1_0 *hdr;
  85         const struct common_firmware_header *header;
  86         struct amdgpu_firmware_info *ucode = NULL;
  87
  88         switch (adev->asic_type) {
  89         case CHIP_ALDEBARAN:
  90                 chip_name = "aldebaran";
  91                 break;
  92         default:
  93                 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
  94                 return -EINVAL;
  95         }
  96
  97         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
  98
  99         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 100         if (err)
 101                 goto out;
 102         err = amdgpu_ucode_validate(adev->pm.fw);
 103         if (err)
 104                 goto out;
 105
 106         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 107         amdgpu_ucode_print_smc_hdr(&hdr->header);
 108         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 109
 110         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 111                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 112                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 113                 ucode->fw = adev->pm.fw;
 114                 header = (const struct common_firmware_header *)ucode->fw->data;
 115                 adev->firmware.fw_size +=
 116                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 117         }
 118
 119 out:
 120         if (err) {
 121                 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
 122                           fw_name);
 123                 release_firmware(adev->pm.fw);
 124                 adev->pm.fw = NULL;
 125         }
 126         return err;
 127 }
 128
 129 void smu_v13_0_fini_microcode(struct smu_context *smu)
 130 {
 131         struct amdgpu_device *adev = smu->adev;
 132
 133         release_firmware(adev->pm.fw);
 134         adev->pm.fw = NULL;
 135         adev->pm.fw_version = 0;
 136 }
 137
 138 int smu_v13_0_load_microcode(struct smu_context *smu)
 139 {
 140 #if 0
 141         struct amdgpu_device *adev = smu->adev;
 142         const uint32_t *src;
 143         const struct smc_firmware_header_v1_0 *hdr;
 144         uint32_t addr_start = MP1_SRAM;
 145         uint32_t i;
 146         uint32_t smc_fw_size;
 147         uint32_t mp1_fw_flags;
 148
 149         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 150         src = (const uint32_t *)(adev->pm.fw->data +
 151                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 152         smc_fw_size = hdr->header.ucode_size_bytes;
 153
 154         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 155                 WREG32_PCIE(addr_start, src[i]);
 156                 addr_start += 4;
 157         }
 158
 159         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 160                     1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 161         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 162                     1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 163
 164         for (i = 0; i < adev->usec_timeout; i++) {
 165                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 166                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 167                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 168                     MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 169                         break;
 170                 udelay(1);
 171         }
 172
 173         if (i == adev->usec_timeout)
 174                 return -ETIME;
 175 #endif
 176         return 0;
 177 }
 178
 179 int smu_v13_0_check_fw_status(struct smu_context *smu)
 180 {
 181         struct amdgpu_device *adev = smu->adev;
 182         uint32_t mp1_fw_flags;
 183
 184         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 185                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 186
 187         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 188             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 189                 return 0;
 190
 191         return -EIO;
 192 }
 193
 194 int smu_v13_0_check_fw_version(struct smu_context *smu)
 195 {
 196         uint32_t if_version = 0xff, smu_version = 0xff;
 197         uint16_t smu_major;
 198         uint8_t smu_minor, smu_debug;
 199         int ret = 0;
 200
 201         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 202         if (ret)
 203                 return ret;
 204
 205         smu_major = (smu_version >> 16) & 0xffff;
 206         smu_minor = (smu_version >> 8) & 0xff;
 207         smu_debug = (smu_version >> 0) & 0xff;
 208
 209         switch (smu->adev->asic_type) {
 210         case CHIP_ALDEBARAN:
 211                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
 212                 break;
 213         default:
 214                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 215                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
 216                 break;
 217         }
 218
 219         dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
 220                          smu_version, smu_major, smu_minor, smu_debug);
 221
 222         /*
 223          * 1. if_version mismatch is not critical as our fw is designed
 224          * to be backward compatible.
 225          * 2. New fw usually brings some optimizations. But that's visible
 226          * only on the paired driver.
 227          * Considering above, we just leave user a warning message instead
 228          * of halt driver loading.
 229          */
 230         if (if_version != smu->smc_driver_if_version) {
 231                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 232                          "smu fw version = 0x%08x (%d.%d.%d)\n",
 233                          smu->smc_driver_if_version, if_version,
 234                          smu_version, smu_major, smu_minor, smu_debug);
 235                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 236         }
 237
 238         return ret;
 239 }
 240
 241 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 242                                       uint32_t *size, uint32_t pptable_id)
 243 {
 244         struct amdgpu_device *adev = smu->adev;
 245         const struct smc_firmware_header_v2_1 *v2_1;
 246         struct smc_soft_pptable_entry *entries;
 247         uint32_t pptable_count = 0;
 248         int i = 0;
 249
 250         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 251         entries = (struct smc_soft_pptable_entry *)
 252                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 253         pptable_count = le32_to_cpu(v2_1->pptable_count);
 254         for (i = 0; i < pptable_count; i++) {
 255                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 256                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 257                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 258                         break;
 259                 }
 260         }
 261
 262         if (i == pptable_count)
 263                 return -EINVAL;
 264
 265         return 0;
 266 }
 267
 268 int smu_v13_0_setup_pptable(struct smu_context *smu)
 269 {
 270         struct amdgpu_device *adev = smu->adev;
 271         const struct smc_firmware_header_v1_0 *hdr;
 272         int ret, index;
 273         uint32_t size = 0;
 274         uint16_t atom_table_size;
 275         uint8_t frev, crev;
 276         void *table;
 277         uint16_t version_major, version_minor;
 278
 279
 280         if (amdgpu_smu_pptable_id >= 0) {
 281                 smu->smu_table.boot_values.pp_table_id = amdgpu_smu_pptable_id;
 282                 dev_info(adev->dev, "override pptable id %d\n", amdgpu_smu_pptable_id);
 283         }
 284
 285         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 286         version_major = le16_to_cpu(hdr->header.header_version_major);
 287         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 288         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 289                 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 290                 switch (version_minor) {
 291                 case 1:
 292                         ret = smu_v13_0_set_pptable_v2_1(smu, &table, &size,
 293                                                          smu->smu_table.boot_values.pp_table_id);
 294                         break;
 295                 default:
 296                         ret = -EINVAL;
 297                         break;
 298                 }
 299                 if (ret)
 300                         return ret;
 301
 302         } else {
 303                 dev_info(adev->dev, "use vbios provided pptable\n");
 304                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 305                                                     powerplayinfo);
 306
 307                 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 308                                                      (uint8_t **)&table);
 309                 if (ret)
 310                         return ret;
 311                 size = atom_table_size;
 312         }
 313
 314         if (!smu->smu_table.power_play_table)
 315                 smu->smu_table.power_play_table = table;
 316         if (!smu->smu_table.power_play_table_size)
 317                 smu->smu_table.power_play_table_size = size;
 318
 319         return 0;
 320 }
 321
 322 int smu_v13_0_init_smc_tables(struct smu_context *smu)
 323 {
 324         struct smu_table_context *smu_table = &smu->smu_table;
 325         struct smu_table *tables = smu_table->tables;
 326         int ret = 0;
 327
 328         smu_table->driver_pptable =
 329                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 330         if (!smu_table->driver_pptable) {
 331                 ret = -ENOMEM;
 332                 goto err0_out;
 333         }
 334
 335         smu_table->max_sustainable_clocks =
 336                 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
 337         if (!smu_table->max_sustainable_clocks) {
 338                 ret = -ENOMEM;
 339                 goto err1_out;
 340         }
 341
 342         /* Aldebaran does not support OVERDRIVE */
 343         if (tables[SMU_TABLE_OVERDRIVE].size) {
 344                 smu_table->overdrive_table =
 345                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 346                 if (!smu_table->overdrive_table) {
 347                         ret = -ENOMEM;
 348                         goto err2_out;
 349                 }
 350
 351                 smu_table->boot_overdrive_table =
 352                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 353                 if (!smu_table->boot_overdrive_table) {
 354                         ret = -ENOMEM;
 355                         goto err3_out;
 356                 }
 357         }
 358
 359         return 0;
 360
 361 err3_out:
 362         kfree(smu_table->overdrive_table);
 363 err2_out:
 364         kfree(smu_table->max_sustainable_clocks);
 365 err1_out:
 366         kfree(smu_table->driver_pptable);
 367 err0_out:
 368         return ret;
 369 }
 370
 371 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 372 {
 373         struct smu_table_context *smu_table = &smu->smu_table;
 374         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 375
 376         kfree(smu_table->gpu_metrics_table);
 377         kfree(smu_table->boot_overdrive_table);
 378         kfree(smu_table->overdrive_table);
 379         kfree(smu_table->max_sustainable_clocks);
 380         kfree(smu_table->driver_pptable);
 381         smu_table->gpu_metrics_table = NULL;
 382         smu_table->boot_overdrive_table = NULL;
 383         smu_table->overdrive_table = NULL;
 384         smu_table->max_sustainable_clocks = NULL;
 385         smu_table->driver_pptable = NULL;
 386         kfree(smu_table->hardcode_pptable);
 387         smu_table->hardcode_pptable = NULL;
 388
 389         kfree(smu_table->metrics_table);
 390         kfree(smu_table->watermarks_table);
 391         smu_table->metrics_table = NULL;
 392         smu_table->watermarks_table = NULL;
 393         smu_table->metrics_time = 0;
 394
 395         kfree(smu_dpm->dpm_context);
 396         kfree(smu_dpm->golden_dpm_context);
 397         kfree(smu_dpm->dpm_current_power_state);
 398         kfree(smu_dpm->dpm_request_power_state);
 399         smu_dpm->dpm_context = NULL;
 400         smu_dpm->golden_dpm_context = NULL;
 401         smu_dpm->dpm_context_size = 0;
 402         smu_dpm->dpm_current_power_state = NULL;
 403         smu_dpm->dpm_request_power_state = NULL;
 404
 405         return 0;
 406 }
 407
 408 int smu_v13_0_init_power(struct smu_context *smu)
 409 {
 410         struct smu_power_context *smu_power = &smu->smu_power;
 411
 412         if (smu_power->power_context || smu_power->power_context_size != 0)
 413                 return -EINVAL;
 414
 415         smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 416                                            GFP_KERNEL);
 417         if (!smu_power->power_context)
 418                 return -ENOMEM;
 419         smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
 420
 421         return 0;
 422 }
 423
 424 int smu_v13_0_fini_power(struct smu_context *smu)
 425 {
 426         struct smu_power_context *smu_power = &smu->smu_power;
 427
 428         if (!smu_power->power_context || smu_power->power_context_size == 0)
 429                 return -EINVAL;
 430
 431         kfree(smu_power->power_context);
 432         smu_power->power_context = NULL;
 433         smu_power->power_context_size = 0;
 434
 435         return 0;
 436 }
 437
 438 static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 439                                             uint8_t clk_id,
 440                                             uint8_t syspll_id,
 441                                             uint32_t *clk_freq)
 442 {
 443         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 444         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 445         int ret, index;
 446
 447         input.clk_id = clk_id;
 448         input.syspll_id = syspll_id;
 449         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 450         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 451                                             getsmuclockinfo);
 452
 453         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 454                                         (uint32_t *)&input);
 455         if (ret)
 456                 return -EINVAL;
 457
 458         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 459         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 460
 461         return 0;
 462 }
 463
 464 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 465 {
 466         int ret, index;
 467         uint16_t size;
 468         uint8_t frev, crev;
 469         struct atom_common_table_header *header;
 470         struct atom_firmware_info_v3_4 *v_3_4;
 471         struct atom_firmware_info_v3_3 *v_3_3;
 472         struct atom_firmware_info_v3_1 *v_3_1;
 473
 474         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 475                                             firmwareinfo);
 476
 477         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 478                                              (uint8_t **)&header);
 479         if (ret)
 480                 return ret;
 481
 482         if (header->format_revision != 3) {
 483                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 484                 return -EINVAL;
 485         }
 486
 487         switch (header->content_revision) {
 488         case 0:
 489         case 1:
 490         case 2:
 491                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 492                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 493                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 494                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 495                 smu->smu_table.boot_values.socclk = 0;
 496                 smu->smu_table.boot_values.dcefclk = 0;
 497                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 498                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 499                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 500                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 501                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 502                 smu->smu_table.boot_values.pp_table_id = 0;
 503                 break;
 504         case 3:
 505                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 506                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 507                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 508                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 509                 smu->smu_table.boot_values.socclk = 0;
 510                 smu->smu_table.boot_values.dcefclk = 0;
 511                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 512                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 513                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 514                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 515                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 516                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 517                 break;
 518         case 4:
 519         default:
 520                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 521                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 522                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 523                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 524                 smu->smu_table.boot_values.socclk = 0;
 525                 smu->smu_table.boot_values.dcefclk = 0;
 526                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 527                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 528                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 529                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 530                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 531                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 532                 break;
 533         }
 534
 535         smu->smu_table.boot_values.format_revision = header->format_revision;
 536         smu->smu_table.boot_values.content_revision = header->content_revision;
 537
 538         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 539                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 540                                          (uint8_t)0,
 541                                          &smu->smu_table.boot_values.socclk);
 542
 543         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 544                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 545                                          (uint8_t)0,
 546                                          &smu->smu_table.boot_values.dcefclk);
 547
 548         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 549                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 550                                          (uint8_t)0,
 551                                          &smu->smu_table.boot_values.eclk);
 552
 553         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 554                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 555                                          (uint8_t)0,
 556                                          &smu->smu_table.boot_values.vclk);
 557
 558         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 559                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 560                                          (uint8_t)0,
 561                                          &smu->smu_table.boot_values.dclk);
 562
 563         if ((smu->smu_table.boot_values.format_revision == 3) &&
 564             (smu->smu_table.boot_values.content_revision >= 2))
 565                 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 566                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 567                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 568                                                  &smu->smu_table.boot_values.fclk);
 569
 570         return 0;
 571 }
 572
 573
 574 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
 575 {
 576         struct smu_table_context *smu_table = &smu->smu_table;
 577         struct smu_table *memory_pool = &smu_table->memory_pool;
 578         int ret = 0;
 579         uint64_t address;
 580         uint32_t address_low, address_high;
 581
 582         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 583                 return ret;
 584
 585         address = memory_pool->mc_address;
 586         address_high = (uint32_t)upper_32_bits(address);
 587         address_low  = (uint32_t)lower_32_bits(address);
 588
 589         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 590                                               address_high, NULL);
 591         if (ret)
 592                 return ret;
 593         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 594                                               address_low, NULL);
 595         if (ret)
 596                 return ret;
 597         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 598                                               (uint32_t)memory_pool->size, NULL);
 599         if (ret)
 600                 return ret;
 601
 602         return ret;
 603 }
 604
 605 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 606 {
 607         int ret;
 608
 609         ret = smu_cmn_send_smc_msg_with_param(smu,
 610                                               SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 611         if (ret)
 612                 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
 613
 614         return ret;
 615 }
 616
 617 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
 618 {
 619         struct smu_table *driver_table = &smu->smu_table.driver_table;
 620         int ret = 0;
 621
 622         if (driver_table->mc_address) {
 623                 ret = smu_cmn_send_smc_msg_with_param(smu,
 624                                                       SMU_MSG_SetDriverDramAddrHigh,
 625                                                       upper_32_bits(driver_table->mc_address),
 626                                                       NULL);
 627                 if (!ret)
 628                         ret = smu_cmn_send_smc_msg_with_param(smu,
 629                                                               SMU_MSG_SetDriverDramAddrLow,
 630                                                               lower_32_bits(driver_table->mc_address),
 631                                                               NULL);
 632         }
 633
 634         return ret;
 635 }
 636
 637 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
 638 {
 639         int ret = 0;
 640         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 641
 642         if (tool_table->mc_address) {
 643                 ret = smu_cmn_send_smc_msg_with_param(smu,
 644                                                       SMU_MSG_SetToolsDramAddrHigh,
 645                                                       upper_32_bits(tool_table->mc_address),
 646                                                       NULL);
 647                 if (!ret)
 648                         ret = smu_cmn_send_smc_msg_with_param(smu,
 649                                                               SMU_MSG_SetToolsDramAddrLow,
 650                                                               lower_32_bits(tool_table->mc_address),
 651                                                               NULL);
 652         }
 653
 654         return ret;
 655 }
 656
 657 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
 658 {
 659         int ret = 0;
 660
 661         if (!smu->pm_enabled)
 662                 return ret;
 663
 664         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 665
 666         return ret;
 667 }
 668
 669
 670 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
 671 {
 672         struct smu_feature *feature = &smu->smu_feature;
 673         int ret = 0;
 674         uint32_t feature_mask[2];
 675
 676         mutex_lock(&feature->mutex);
 677         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 678                 goto failed;
 679
 680         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 681
 682         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 683                                               feature_mask[1], NULL);
 684         if (ret)
 685                 goto failed;
 686
 687         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 688                                               feature_mask[0], NULL);
 689         if (ret)
 690                 goto failed;
 691
 692 failed:
 693         mutex_unlock(&feature->mutex);
 694         return ret;
 695 }
 696
 697 int smu_v13_0_system_features_control(struct smu_context *smu,
 698                                       bool en)
 699 {
 700         struct smu_feature *feature = &smu->smu_feature;
 701         uint32_t feature_mask[2];
 702         int ret = 0;
 703
 704         ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 705                                          SMU_MSG_DisableAllSmuFeatures), NULL);
 706         if (ret)
 707                 return ret;
 708
 709         bitmap_zero(feature->enabled, feature->feature_num);
 710         bitmap_zero(feature->supported, feature->feature_num);
 711
 712         if (en) {
 713                 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 714                 if (ret)
 715                         return ret;
 716
 717                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 718                             feature->feature_num);
 719                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 720                             feature->feature_num);
 721         }
 722
 723         return ret;
 724 }
 725
 726 int smu_v13_0_notify_display_change(struct smu_context *smu)
 727 {
 728         int ret = 0;
 729
 730         if (!smu->pm_enabled)
 731                 return ret;
 732
 733         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 734             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 735                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 736
 737         return ret;
 738 }
 739
 740         static int
 741 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 742                                     enum smu_clk_type clock_select)
 743 {
 744         int ret = 0;
 745         int clk_id;
 746
 747         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 748             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 749                 return 0;
 750
 751         clk_id = smu_cmn_to_asic_specific_index(smu,
 752                                                 CMN2ASIC_MAPPING_CLK,
 753                                                 clock_select);
 754         if (clk_id < 0)
 755                 return -EINVAL;
 756
 757         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 758                                               clk_id << 16, clock);
 759         if (ret) {
 760                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 761                 return ret;
 762         }
 763
 764         if (*clock != 0)
 765                 return 0;
 766
 767         /* if DC limit is zero, return AC limit */
 768         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 769                                               clk_id << 16, clock);
 770         if (ret) {
 771                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 772                 return ret;
 773         }
 774
 775         return 0;
 776 }
 777
 778 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
 779 {
 780         struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
 781                 smu->smu_table.max_sustainable_clocks;
 782         int ret = 0;
 783
 784         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 785         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 786         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 787         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 788         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 789         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 790
 791         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 792                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 793                                                           &(max_sustainable_clocks->uclock),
 794                                                           SMU_UCLK);
 795                 if (ret) {
 796                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 797                                 __func__);
 798                         return ret;
 799                 }
 800         }
 801
 802         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 803                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 804                                                           &(max_sustainable_clocks->soc_clock),
 805                                                           SMU_SOCCLK);
 806                 if (ret) {
 807                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 808                                 __func__);
 809                         return ret;
 810                 }
 811         }
 812
 813         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 814                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 815                                                           &(max_sustainable_clocks->dcef_clock),
 816                                                           SMU_DCEFCLK);
 817                 if (ret) {
 818                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 819                                 __func__);
 820                         return ret;
 821                 }
 822
 823                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 824                                                           &(max_sustainable_clocks->display_clock),
 825                                                           SMU_DISPCLK);
 826                 if (ret) {
 827                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 828                                 __func__);
 829                         return ret;
 830                 }
 831                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 832                                                           &(max_sustainable_clocks->phy_clock),
 833                                                           SMU_PHYCLK);
 834                 if (ret) {
 835                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 836                                 __func__);
 837                         return ret;
 838                 }
 839                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 840                                                           &(max_sustainable_clocks->pixel_clock),
 841                                                           SMU_PIXCLK);
 842                 if (ret) {
 843                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 844                                 __func__);
 845                         return ret;
 846                 }
 847         }
 848
 849         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 850                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 851
 852         return 0;
 853 }
 854
 855 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
 856                                       uint32_t *power_limit)
 857 {
 858         int power_src;
 859         int ret = 0;
 860
 861         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 862                 return -EINVAL;
 863
 864         power_src = smu_cmn_to_asic_specific_index(smu,
 865                                                    CMN2ASIC_MAPPING_PWR,
 866                                                    smu->adev->pm.ac_power ?
 867                                                    SMU_POWER_SOURCE_AC :
 868                                                    SMU_POWER_SOURCE_DC);
 869         if (power_src < 0)
 870                 return -EINVAL;
 871
 872         ret = smu_cmn_send_smc_msg_with_param(smu,
 873                                               SMU_MSG_GetPptLimit,
 874                                               power_src << 16,
 875                                               power_limit);
 876         if (ret)
 877                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 878
 879         return ret;
 880 }
 881
 882 int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n)
 883 {
 884         int ret = 0;
 885
 886         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 887                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 888                 return -EOPNOTSUPP;
 889         }
 890
 891         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
 892         if (ret) {
 893                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 894                 return ret;
 895         }
 896
 897         smu->current_power_limit = n;
 898
 899         return 0;
 900 }
 901
 902 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
 903 {
 904         if (smu->smu_table.thermal_controller_type)
 905                 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 906
 907         return 0;
 908 }
 909
 910 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
 911 {
 912         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
 913 }
 914
 915 static uint16_t convert_to_vddc(uint8_t vid)
 916 {
 917         return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
 918 }
 919
 920 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
 921 {
 922         struct amdgpu_device *adev = smu->adev;
 923         uint32_t vdd = 0, val_vid = 0;
 924
 925         if (!value)
 926                 return -EINVAL;
 927         val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
 928                    SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
 929                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
 930
 931         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
 932
 933         *value = vdd;
 934
 935         return 0;
 936
 937 }
 938
 939 int
 940 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
 941                                         struct pp_display_clock_request
 942                                         *clock_req)
 943 {
 944         enum amd_pp_clock_type clk_type = clock_req->clock_type;
 945         int ret = 0;
 946         enum smu_clk_type clk_select = 0;
 947         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
 948
 949         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
 950             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 951                 switch (clk_type) {
 952                 case amd_pp_dcef_clock:
 953                         clk_select = SMU_DCEFCLK;
 954                         break;
 955                 case amd_pp_disp_clock:
 956                         clk_select = SMU_DISPCLK;
 957                         break;
 958                 case amd_pp_pixel_clock:
 959                         clk_select = SMU_PIXCLK;
 960                         break;
 961                 case amd_pp_phy_clock:
 962                         clk_select = SMU_PHYCLK;
 963                         break;
 964                 case amd_pp_mem_clock:
 965                         clk_select = SMU_UCLK;
 966                         break;
 967                 default:
 968                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
 969                         ret = -EINVAL;
 970                         break;
 971                 }
 972
 973                 if (ret)
 974                         goto failed;
 975
 976                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
 977                         return 0;
 978
 979                 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
 980
 981                 if(clk_select == SMU_UCLK)
 982                         smu->hard_min_uclk_req_from_dal = clk_freq;
 983         }
 984
 985 failed:
 986         return ret;
 987 }
 988
 989 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
 990 {
 991         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
 992                 return AMD_FAN_CTRL_MANUAL;
 993         else
 994                 return AMD_FAN_CTRL_AUTO;
 995 }
 996
 997         static int
 998 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
 999 {
1000         int ret = 0;
1001
1002         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1003                 return 0;
1004
1005         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1006         if (ret)
1007                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1008                         __func__, (auto_fan_control ? "Start" : "Stop"));
1009
1010         return ret;
1011 }
1012
1013         static int
1014 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1015 {
1016         struct amdgpu_device *adev = smu->adev;
1017
1018         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1019                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1020                                    CG_FDO_CTRL2, TMIN, 0));
1021         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1022                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1023                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1024
1025         return 0;
1026 }
1027
1028         int
1029 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1030 {
1031         struct amdgpu_device *adev = smu->adev;
1032         uint32_t duty100, duty;
1033         uint64_t tmp64;
1034
1035         if (speed > 100)
1036                 speed = 100;
1037
1038         if (smu_v13_0_auto_fan_control(smu, 0))
1039                 return -EINVAL;
1040
1041         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1042                                 CG_FDO_CTRL1, FMAX_DUTY100);
1043         if (!duty100)
1044                 return -EINVAL;
1045
1046         tmp64 = (uint64_t)speed * duty100;
1047         do_div(tmp64, 100);
1048         duty = (uint32_t)tmp64;
1049
1050         WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1051                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1052                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1053
1054         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1055 }
1056
1057         int
1058 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1059                                uint32_t mode)
1060 {
1061         int ret = 0;
1062
1063         switch (mode) {
1064         case AMD_FAN_CTRL_NONE:
1065                 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1066                 break;
1067         case AMD_FAN_CTRL_MANUAL:
1068                 ret = smu_v13_0_auto_fan_control(smu, 0);
1069                 break;
1070         case AMD_FAN_CTRL_AUTO:
1071                 ret = smu_v13_0_auto_fan_control(smu, 1);
1072                 break;
1073         default:
1074                 break;
1075         }
1076
1077         if (ret) {
1078                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1079                 return -EINVAL;
1080         }
1081
1082         return ret;
1083 }
1084
1085 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1086                                 uint32_t speed)
1087 {
1088         struct amdgpu_device *adev = smu->adev;
1089         int ret;
1090         uint32_t tach_period, crystal_clock_freq;
1091
1092         if (!speed)
1093                 return -EINVAL;
1094
1095         ret = smu_v13_0_auto_fan_control(smu, 0);
1096         if (ret)
1097                 return ret;
1098
1099         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1100         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1101         WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1102                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1103                                    CG_TACH_CTRL, TARGET_PERIOD,
1104                                    tach_period));
1105
1106         ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1107
1108         return ret;
1109 }
1110
1111 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1112                               uint32_t pstate)
1113 {
1114         int ret = 0;
1115         ret = smu_cmn_send_smc_msg_with_param(smu,
1116                                               SMU_MSG_SetXgmiMode,
1117                                               pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1118                                               NULL);
1119         return ret;
1120 }
1121
1122 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1123                                    struct amdgpu_irq_src *source,
1124                                    unsigned tyep,
1125                                    enum amdgpu_interrupt_state state)
1126 {
1127         struct smu_context *smu = &adev->smu;
1128         uint32_t low, high;
1129         uint32_t val = 0;
1130
1131         switch (state) {
1132         case AMDGPU_IRQ_STATE_DISABLE:
1133                 /* For THM irqs */
1134                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1135                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1136                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1137                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1138
1139                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1140
1141                 /* For MP1 SW irqs */
1142                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1143                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1144                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1145
1146                 break;
1147         case AMDGPU_IRQ_STATE_ENABLE:
1148                 /* For THM irqs */
1149                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1150                           smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1151                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1152                            smu->thermal_range.software_shutdown_temp);
1153
1154                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1155                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1156                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1157                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1158                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1159                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1160                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1161                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1162                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1163
1164                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1165                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1166                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1167                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1168
1169                 /* For MP1 SW irqs */
1170                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1171                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1172                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1173                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1174
1175                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1176                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1177                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1178
1179                 break;
1180         default:
1181                 break;
1182         }
1183
1184         return 0;
1185 }
1186
1187 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1188 {
1189         return smu_cmn_send_smc_msg(smu,
1190                                     SMU_MSG_ReenableAcDcInterrupt,
1191                                     NULL);
1192 }
1193
1194 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1195 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1196 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1197
1198 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1199                                  struct amdgpu_irq_src *source,
1200                                  struct amdgpu_iv_entry *entry)
1201 {
1202         struct smu_context *smu = &adev->smu;
1203         uint32_t client_id = entry->client_id;
1204         uint32_t src_id = entry->src_id;
1205         /*
1206          * ctxid is used to distinguish different
1207          * events for SMCToHost interrupt.
1208          */
1209         uint32_t ctxid = entry->src_data[0];
1210         uint32_t data;
1211
1212         if (client_id == SOC15_IH_CLIENTID_THM) {
1213                 switch (src_id) {
1214                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1215                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1216                         /*
1217                          * SW CTF just occurred.
1218                          * Try to do a graceful shutdown to prevent further damage.
1219                          */
1220                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1221                         orderly_poweroff(true);
1222                         break;
1223                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1224                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1225                         break;
1226                 default:
1227                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1228                                   src_id);
1229                         break;
1230                 }
1231         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1232                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1233                 /*
1234                  * HW CTF just occurred. Shutdown to prevent further damage.
1235                  */
1236                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1237                 orderly_poweroff(true);
1238         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1239                 if (src_id == 0xfe) {
1240                         /* ACK SMUToHost interrupt */
1241                         data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1242                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1243                         WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1244
1245                         switch (ctxid) {
1246                         case 0x3:
1247                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1248                                 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1249                                 break;
1250                         case 0x4:
1251                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1252                                 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1253                                 break;
1254                         case 0x7:
1255                                 /*
1256                                  * Increment the throttle interrupt counter
1257                                  */
1258                                 atomic64_inc(&smu->throttle_int_counter);
1259
1260                                 if (!atomic_read(&adev->throttling_logging_enabled))
1261                                         return 0;
1262
1263                                 if (__ratelimit(&adev->throttling_logging_rs))
1264                                         schedule_work(&smu->throttling_logging_work);
1265
1266                                 break;
1267                         }
1268                 }
1269         }
1270
1271         return 0;
1272 }
1273
1274 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1275 {
1276         .set = smu_v13_0_set_irq_state,
1277         .process = smu_v13_0_irq_process,
1278 };
1279
1280 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1281 {
1282         struct amdgpu_device *adev = smu->adev;
1283         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1284         int ret = 0;
1285
1286         irq_src->num_types = 1;
1287         irq_src->funcs = &smu_v13_0_irq_funcs;
1288
1289         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1290                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1291                                 irq_src);
1292         if (ret)
1293                 return ret;
1294
1295         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1296                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1297                                 irq_src);
1298         if (ret)
1299                 return ret;
1300
1301         /* Register CTF(GPIO_19) interrupt */
1302         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1303                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1304                                 irq_src);
1305         if (ret)
1306                 return ret;
1307
1308         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1309                                 0xfe,
1310                                 irq_src);
1311         if (ret)
1312                 return ret;
1313
1314         return ret;
1315 }
1316
1317 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1318                                                struct pp_smu_nv_clock_table *max_clocks)
1319 {
1320         struct smu_table_context *table_context = &smu->smu_table;
1321         struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1322
1323         if (!max_clocks || !table_context->max_sustainable_clocks)
1324                 return -EINVAL;
1325
1326         sustainable_clocks = table_context->max_sustainable_clocks;
1327
1328         max_clocks->dcfClockInKhz =
1329                 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1330         max_clocks->displayClockInKhz =
1331                 (unsigned int) sustainable_clocks->display_clock * 1000;
1332         max_clocks->phyClockInKhz =
1333                 (unsigned int) sustainable_clocks->phy_clock * 1000;
1334         max_clocks->pixelClockInKhz =
1335                 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1336         max_clocks->uClockInKhz =
1337                 (unsigned int) sustainable_clocks->uclock * 1000;
1338         max_clocks->socClockInKhz =
1339                 (unsigned int) sustainable_clocks->soc_clock * 1000;
1340         max_clocks->dscClockInKhz = 0;
1341         max_clocks->dppClockInKhz = 0;
1342         max_clocks->fabricClockInKhz = 0;
1343
1344         return 0;
1345 }
1346
1347 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1348 {
1349         int ret = 0;
1350
1351         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1352
1353         return ret;
1354 }
1355
1356 int smu_v13_0_mode1_reset(struct smu_context *smu)
1357 {
1358         u32 smu_version;
1359         int ret = 0;
1360         /*
1361         * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1362         */
1363         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1364         if (smu_version < 0x00440700)
1365                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1366         else
1367                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL);
1368
1369         if (!ret)
1370                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1371
1372         return ret;
1373 }
1374
1375 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1376                                              uint64_t event_arg)
1377 {
1378         int ret = 0;
1379
1380         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1381         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1382
1383         return ret;
1384 }
1385
1386 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1387                              uint64_t event_arg)
1388 {
1389         int ret = -EINVAL;
1390
1391         switch (event) {
1392         case SMU_EVENT_RESET_COMPLETE:
1393                 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1394                 break;
1395         default:
1396                 break;
1397         }
1398
1399         return ret;
1400 }
1401
1402 int smu_v13_0_mode2_reset(struct smu_context *smu)
1403 {
1404         int ret;
1405
1406         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1407                         SMU_RESET_MODE_2, NULL);
1408         /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
1409         if (!ret)
1410                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1411
1412         return ret;
1413 }
1414
1415 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1416                                     uint32_t *min, uint32_t *max)
1417 {
1418         int ret = 0, clk_id = 0;
1419         uint32_t param = 0;
1420         uint32_t clock_limit;
1421
1422         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1423                 switch (clk_type) {
1424                 case SMU_MCLK:
1425                 case SMU_UCLK:
1426                         clock_limit = smu->smu_table.boot_values.uclk;
1427                         break;
1428                 case SMU_GFXCLK:
1429                 case SMU_SCLK:
1430                         clock_limit = smu->smu_table.boot_values.gfxclk;
1431                         break;
1432                 case SMU_SOCCLK:
1433                         clock_limit = smu->smu_table.boot_values.socclk;
1434                         break;
1435                 default:
1436                         clock_limit = 0;
1437                         break;
1438                 }
1439
1440                 /* clock in Mhz unit */
1441                 if (min)
1442                         *min = clock_limit / 100;
1443                 if (max)
1444                         *max = clock_limit / 100;
1445
1446                 return 0;
1447         }
1448
1449         clk_id = smu_cmn_to_asic_specific_index(smu,
1450                                                 CMN2ASIC_MAPPING_CLK,
1451                                                 clk_type);
1452         if (clk_id < 0) {
1453                 ret = -EINVAL;
1454                 goto failed;
1455         }
1456         param = (clk_id & 0xffff) << 16;
1457
1458         if (max) {
1459                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1460                 if (ret)
1461                         goto failed;
1462         }
1463
1464         if (min) {
1465                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1466                 if (ret)
1467                         goto failed;
1468         }
1469
1470 failed:
1471         return ret;
1472 }
1473
1474 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1475                                           enum smu_clk_type clk_type,
1476                                           uint32_t min,
1477                                           uint32_t max)
1478 {
1479         struct amdgpu_device *adev = smu->adev;
1480         int ret = 0, clk_id = 0;
1481         uint32_t param;
1482
1483         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1484                 return 0;
1485
1486         clk_id = smu_cmn_to_asic_specific_index(smu,
1487                                                 CMN2ASIC_MAPPING_CLK,
1488                                                 clk_type);
1489         if (clk_id < 0)
1490                 return clk_id;
1491
1492         if (clk_type == SMU_GFXCLK)
1493                 amdgpu_gfx_off_ctrl(adev, false);
1494
1495         if (max > 0) {
1496                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1497                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1498                                                       param, NULL);
1499                 if (ret)
1500                         goto out;
1501         }
1502
1503         if (min > 0) {
1504                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1505                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1506                                                       param, NULL);
1507                 if (ret)
1508                         goto out;
1509         }
1510
1511 out:
1512         if (clk_type == SMU_GFXCLK)
1513                 amdgpu_gfx_off_ctrl(adev, true);
1514
1515         return ret;
1516 }
1517
1518 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1519                                           enum smu_clk_type clk_type,
1520                                           uint32_t min,
1521                                           uint32_t max)
1522 {
1523         int ret = 0, clk_id = 0;
1524         uint32_t param;
1525
1526         if (min <= 0 && max <= 0)
1527                 return -EINVAL;
1528
1529         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1530                 return 0;
1531
1532         clk_id = smu_cmn_to_asic_specific_index(smu,
1533                                                 CMN2ASIC_MAPPING_CLK,
1534                                                 clk_type);
1535         if (clk_id < 0)
1536                 return clk_id;
1537
1538         if (max > 0) {
1539                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1540                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1541                                                       param, NULL);
1542                 if (ret)
1543                         return ret;
1544         }
1545
1546         if (min > 0) {
1547                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1548                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1549                                                       param, NULL);
1550                 if (ret)
1551                         return ret;
1552         }
1553
1554         return ret;
1555 }
1556
1557 int smu_v13_0_set_performance_level(struct smu_context *smu,
1558                                     enum amd_dpm_forced_level level)
1559 {
1560         struct smu_13_0_dpm_context *dpm_context =
1561                 smu->smu_dpm.dpm_context;
1562         struct smu_13_0_dpm_table *gfx_table =
1563                 &dpm_context->dpm_tables.gfx_table;
1564         struct smu_13_0_dpm_table *mem_table =
1565                 &dpm_context->dpm_tables.uclk_table;
1566         struct smu_13_0_dpm_table *soc_table =
1567                 &dpm_context->dpm_tables.soc_table;
1568         struct smu_umd_pstate_table *pstate_table =
1569                 &smu->pstate_table;
1570         struct amdgpu_device *adev = smu->adev;
1571         uint32_t sclk_min = 0, sclk_max = 0;
1572         uint32_t mclk_min = 0, mclk_max = 0;
1573         uint32_t socclk_min = 0, socclk_max = 0;
1574         int ret = 0;
1575
1576         switch (level) {
1577         case AMD_DPM_FORCED_LEVEL_HIGH:
1578                 sclk_min = sclk_max = gfx_table->max;
1579                 mclk_min = mclk_max = mem_table->max;
1580                 socclk_min = socclk_max = soc_table->max;
1581                 break;
1582         case AMD_DPM_FORCED_LEVEL_LOW:
1583                 sclk_min = sclk_max = gfx_table->min;
1584                 mclk_min = mclk_max = mem_table->min;
1585                 socclk_min = socclk_max = soc_table->min;
1586                 break;
1587         case AMD_DPM_FORCED_LEVEL_AUTO:
1588                 sclk_min = gfx_table->min;
1589                 sclk_max = gfx_table->max;
1590                 mclk_min = mem_table->min;
1591                 mclk_max = mem_table->max;
1592                 socclk_min = soc_table->min;
1593                 socclk_max = soc_table->max;
1594                 break;
1595         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1596                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1597                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1598                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1599                 break;
1600         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1601                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1602                 break;
1603         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1604                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1605                 break;
1606         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1607                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1608                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1609                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1610                 break;
1611         case AMD_DPM_FORCED_LEVEL_MANUAL:
1612         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1613                 return 0;
1614         default:
1615                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1616                 return -EINVAL;
1617         }
1618
1619         mclk_min = mclk_max = 0;
1620         socclk_min = socclk_max = 0;
1621
1622         if (sclk_min && sclk_max) {
1623                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1624                                                             SMU_GFXCLK,
1625                                                             sclk_min,
1626                                                             sclk_max);
1627                 if (ret)
1628                         return ret;
1629
1630                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1631                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1632         }
1633
1634         if (mclk_min && mclk_max) {
1635                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1636                                                             SMU_MCLK,
1637                                                             mclk_min,
1638                                                             mclk_max);
1639                 if (ret)
1640                         return ret;
1641
1642                 pstate_table->uclk_pstate.curr.min = mclk_min;
1643                 pstate_table->uclk_pstate.curr.max = mclk_max;
1644         }
1645
1646         if (socclk_min && socclk_max) {
1647                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1648                                                             SMU_SOCCLK,
1649                                                             socclk_min,
1650                                                             socclk_max);
1651                 if (ret)
1652                         return ret;
1653
1654                 pstate_table->socclk_pstate.curr.min = socclk_min;
1655                 pstate_table->socclk_pstate.curr.max = socclk_max;
1656         }
1657
1658         return ret;
1659 }
1660
1661 int smu_v13_0_set_power_source(struct smu_context *smu,
1662                                enum smu_power_src_type power_src)
1663 {
1664         int pwr_source;
1665
1666         pwr_source = smu_cmn_to_asic_specific_index(smu,
1667                                                     CMN2ASIC_MAPPING_PWR,
1668                                                     (uint32_t)power_src);
1669         if (pwr_source < 0)
1670                 return -EINVAL;
1671
1672         return smu_cmn_send_smc_msg_with_param(smu,
1673                                                SMU_MSG_NotifyPowerSource,
1674                                                pwr_source,
1675                                                NULL);
1676 }
1677
1678 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1679                                     enum smu_clk_type clk_type,
1680                                     uint16_t level,
1681                                     uint32_t *value)
1682 {
1683         int ret = 0, clk_id = 0;
1684         uint32_t param;
1685
1686         if (!value)
1687                 return -EINVAL;
1688
1689         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1690                 return 0;
1691
1692         clk_id = smu_cmn_to_asic_specific_index(smu,
1693                                                 CMN2ASIC_MAPPING_CLK,
1694                                                 clk_type);
1695         if (clk_id < 0)
1696                 return clk_id;
1697
1698         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1699
1700         ret = smu_cmn_send_smc_msg_with_param(smu,
1701                                               SMU_MSG_GetDpmFreqByIndex,
1702                                               param,
1703                                               value);
1704         if (ret)
1705                 return ret;
1706
1707         /*
1708          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1709          * now, we un-support it
1710          */
1711         *value = *value & 0x7fffffff;
1712
1713         return ret;
1714 }
1715
1716 int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1717                                   enum smu_clk_type clk_type,
1718                                   uint32_t *value)
1719 {
1720         int ret;
1721
1722         ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1723         /* FW returns 0 based max level, increment by one */
1724         if (!ret && value)
1725                 ++(*value);
1726
1727         return ret;
1728 }
1729
1730 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1731                                    enum smu_clk_type clk_type,
1732                                    struct smu_13_0_dpm_table *single_dpm_table)
1733 {
1734         int ret = 0;
1735         uint32_t clk;
1736         int i;
1737
1738         ret = smu_v13_0_get_dpm_level_count(smu,
1739                                             clk_type,
1740                                             &single_dpm_table->count);
1741         if (ret) {
1742                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1743                 return ret;
1744         }
1745
1746         for (i = 0; i < single_dpm_table->count; i++) {
1747                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1748                                                       clk_type,
1749                                                       i,
1750                                                       &clk);
1751                 if (ret) {
1752                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1753                         return ret;
1754                 }
1755
1756                 single_dpm_table->dpm_levels[i].value = clk;
1757                 single_dpm_table->dpm_levels[i].enabled = true;
1758
1759                 if (i == 0)
1760                         single_dpm_table->min = clk;
1761                 else if (i == single_dpm_table->count - 1)
1762                         single_dpm_table->max = clk;
1763         }
1764
1765         return 0;
1766 }
1767
1768 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1769                                   enum smu_clk_type clk_type,
1770                                   uint32_t *min_value,
1771                                   uint32_t *max_value)
1772 {
1773         uint32_t level_count = 0;
1774         int ret = 0;
1775
1776         if (!min_value && !max_value)
1777                 return -EINVAL;
1778
1779         if (min_value) {
1780                 /* by default, level 0 clock value as min value */
1781                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1782                                                       clk_type,
1783                                                       0,
1784                                                       min_value);
1785                 if (ret)
1786                         return ret;
1787         }
1788
1789         if (max_value) {
1790                 ret = smu_v13_0_get_dpm_level_count(smu,
1791                                                     clk_type,
1792                                                     &level_count);
1793                 if (ret)
1794                         return ret;
1795
1796                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1797                                                       clk_type,
1798                                                       level_count - 1,
1799                                                       max_value);
1800                 if (ret)
1801                         return ret;
1802         }
1803
1804         return ret;
1805 }
1806
1807 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1808 {
1809         struct amdgpu_device *adev = smu->adev;
1810
1811         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1812                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1813                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1814 }
1815
1816 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1817 {
1818         uint32_t width_level;
1819
1820         width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1821         if (width_level > LINK_WIDTH_MAX)
1822                 width_level = 0;
1823
1824         return link_width[width_level];
1825 }
1826
1827 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1828 {
1829         struct amdgpu_device *adev = smu->adev;
1830
1831         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1832                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1833                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1834 }
1835
1836 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1837 {
1838         uint32_t speed_level;
1839
1840         speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1841         if (speed_level > LINK_SPEED_MAX)
1842                 speed_level = 0;
1843
1844         return link_speed[speed_level];
1845 }
1846