drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_13_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v13_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_13_0_2_offset.h"
  43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_13_0_2_offset.h"
  45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
  47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
  61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
  62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
  63
  64 #define mmMP1_SMN_C2PMSG_66                                                                            0x0282
  65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
  66
  67 #define mmMP1_SMN_C2PMSG_82                                                                            0x0292
  68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
  69
  70 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
  71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
  72
  73 #define SMU13_VOLTAGE_SCALE 4
  74
  75 #define LINK_WIDTH_MAX                          6
  76 #define LINK_SPEED_MAX                          3
  77
  78 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  81 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  84
  85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  86 static const int link_speed[] = {25, 50, 80, 160};
  87
  88 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
  89 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
  90
  91 int smu_v13_0_init_microcode(struct smu_context *smu)
  92 {
  93         struct amdgpu_device *adev = smu->adev;
  94         char fw_name[30];
  95         char ucode_prefix[30];
  96         int err = 0;
  97         const struct smc_firmware_header_v1_0 *hdr;
  98         const struct common_firmware_header *header;
  99         struct amdgpu_firmware_info *ucode = NULL;
 100
 101         /* doesn't need to load smu firmware in IOV mode */
 102         if (amdgpu_sriov_vf(adev))
 103                 return 0;
 104
 105         amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
 106
 107         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
 108
 109         err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name);
 110         if (err)
 111                 goto out;
 112
 113         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 114         amdgpu_ucode_print_smc_hdr(&hdr->header);
 115         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 116
 117         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 118                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 119                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 120                 ucode->fw = adev->pm.fw;
 121                 header = (const struct common_firmware_header *)ucode->fw->data;
 122                 adev->firmware.fw_size +=
 123                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 124         }
 125
 126 out:
 127         if (err)
 128                 amdgpu_ucode_release(&adev->pm.fw);
 129         return err;
 130 }
 131
 132 void smu_v13_0_fini_microcode(struct smu_context *smu)
 133 {
 134         struct amdgpu_device *adev = smu->adev;
 135
 136         amdgpu_ucode_release(&adev->pm.fw);
 137         adev->pm.fw_version = 0;
 138 }
 139
 140 int smu_v13_0_load_microcode(struct smu_context *smu)
 141 {
 142 #if 0
 143         struct amdgpu_device *adev = smu->adev;
 144         const uint32_t *src;
 145         const struct smc_firmware_header_v1_0 *hdr;
 146         uint32_t addr_start = MP1_SRAM;
 147         uint32_t i;
 148         uint32_t smc_fw_size;
 149         uint32_t mp1_fw_flags;
 150
 151         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 152         src = (const uint32_t *)(adev->pm.fw->data +
 153                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 154         smc_fw_size = hdr->header.ucode_size_bytes;
 155
 156         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 157                 WREG32_PCIE(addr_start, src[i]);
 158                 addr_start += 4;
 159         }
 160
 161         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 162                     1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 163         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 164                     1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 165
 166         for (i = 0; i < adev->usec_timeout; i++) {
 167                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 168                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 169                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 170                     MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 171                         break;
 172                 udelay(1);
 173         }
 174
 175         if (i == adev->usec_timeout)
 176                 return -ETIME;
 177 #endif
 178
 179         return 0;
 180 }
 181
 182 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
 183 {
 184         struct amdgpu_device *adev = smu->adev;
 185         struct amdgpu_firmware_info *ucode = NULL;
 186         uint32_t size = 0, pptable_id = 0;
 187         int ret = 0;
 188         void *table;
 189
 190         /* doesn't need to load smu firmware in IOV mode */
 191         if (amdgpu_sriov_vf(adev))
 192                 return 0;
 193
 194         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 195                 return 0;
 196
 197         if (!adev->scpm_enabled)
 198                 return 0;
 199
 200         if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) ||
 201             (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) ||
 202             (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)))
 203                 return 0;
 204
 205         /* override pptable_id from driver parameter */
 206         if (amdgpu_smu_pptable_id >= 0) {
 207                 pptable_id = amdgpu_smu_pptable_id;
 208                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 209         } else {
 210                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 211         }
 212
 213         /* "pptable_id == 0" means vbios carries the pptable. */
 214         if (!pptable_id)
 215                 return 0;
 216
 217         ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 218         if (ret)
 219                 return ret;
 220
 221         smu->pptable_firmware.data = table;
 222         smu->pptable_firmware.size = size;
 223
 224         ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
 225         ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
 226         ucode->fw = &smu->pptable_firmware;
 227         adev->firmware.fw_size +=
 228                 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
 229
 230         return 0;
 231 }
 232
 233 int smu_v13_0_check_fw_status(struct smu_context *smu)
 234 {
 235         struct amdgpu_device *adev = smu->adev;
 236         uint32_t mp1_fw_flags;
 237
 238         switch (adev->ip_versions[MP1_HWIP][0]) {
 239         case IP_VERSION(13, 0, 4):
 240         case IP_VERSION(13, 0, 11):
 241                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 242                                            (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
 243                 break;
 244         default:
 245                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 246                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 247                 break;
 248         }
 249
 250         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 251             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 252                 return 0;
 253
 254         return -EIO;
 255 }
 256
 257 int smu_v13_0_check_fw_version(struct smu_context *smu)
 258 {
 259         struct amdgpu_device *adev = smu->adev;
 260         uint32_t if_version = 0xff, smu_version = 0xff;
 261         uint8_t smu_program, smu_major, smu_minor, smu_debug;
 262         int ret = 0;
 263
 264         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 265         if (ret)
 266                 return ret;
 267
 268         smu_program = (smu_version >> 24) & 0xff;
 269         smu_major = (smu_version >> 16) & 0xff;
 270         smu_minor = (smu_version >> 8) & 0xff;
 271         smu_debug = (smu_version >> 0) & 0xff;
 272         if (smu->is_apu ||
 273             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 6))
 274                 adev->pm.fw_version = smu_version;
 275
 276         /* only for dGPU w/ SMU13*/
 277         if (adev->pm.fw)
 278                 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
 279                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 280
 281         /*
 282          * 1. if_version mismatch is not critical as our fw is designed
 283          * to be backward compatible.
 284          * 2. New fw usually brings some optimizations. But that's visible
 285          * only on the paired driver.
 286          * Considering above, we just leave user a verbal message instead
 287          * of halt driver loading.
 288          */
 289         if (if_version != smu->smc_driver_if_version) {
 290                 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 291                          "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
 292                          smu->smc_driver_if_version, if_version,
 293                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 294                 dev_info(adev->dev, "SMU driver if version not matched\n");
 295         }
 296
 297         return ret;
 298 }
 299
 300 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 301 {
 302         struct amdgpu_device *adev = smu->adev;
 303         uint32_t ppt_offset_bytes;
 304         const struct smc_firmware_header_v2_0 *v2;
 305
 306         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 307
 308         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 309         *size = le32_to_cpu(v2->ppt_size_bytes);
 310         *table = (uint8_t *)v2 + ppt_offset_bytes;
 311
 312         return 0;
 313 }
 314
 315 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 316                                       uint32_t *size, uint32_t pptable_id)
 317 {
 318         struct amdgpu_device *adev = smu->adev;
 319         const struct smc_firmware_header_v2_1 *v2_1;
 320         struct smc_soft_pptable_entry *entries;
 321         uint32_t pptable_count = 0;
 322         int i = 0;
 323
 324         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 325         entries = (struct smc_soft_pptable_entry *)
 326                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 327         pptable_count = le32_to_cpu(v2_1->pptable_count);
 328         for (i = 0; i < pptable_count; i++) {
 329                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 330                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 331                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 332                         break;
 333                 }
 334         }
 335
 336         if (i == pptable_count)
 337                 return -EINVAL;
 338
 339         return 0;
 340 }
 341
 342 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
 343 {
 344         struct amdgpu_device *adev = smu->adev;
 345         uint16_t atom_table_size;
 346         uint8_t frev, crev;
 347         int ret, index;
 348
 349         dev_info(adev->dev, "use vbios provided pptable\n");
 350         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 351                                             powerplayinfo);
 352
 353         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 354                                              (uint8_t **)table);
 355         if (ret)
 356                 return ret;
 357
 358         if (size)
 359                 *size = atom_table_size;
 360
 361         return 0;
 362 }
 363
 364 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
 365                                         void **table,
 366                                         uint32_t *size,
 367                                         uint32_t pptable_id)
 368 {
 369         const struct smc_firmware_header_v1_0 *hdr;
 370         struct amdgpu_device *adev = smu->adev;
 371         uint16_t version_major, version_minor;
 372         int ret;
 373
 374         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 375         if (!hdr)
 376                 return -EINVAL;
 377
 378         dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
 379
 380         version_major = le16_to_cpu(hdr->header.header_version_major);
 381         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 382         if (version_major != 2) {
 383                 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
 384                         version_major, version_minor);
 385                 return -EINVAL;
 386         }
 387
 388         switch (version_minor) {
 389         case 0:
 390                 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
 391                 break;
 392         case 1:
 393                 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
 394                 break;
 395         default:
 396                 ret = -EINVAL;
 397                 break;
 398         }
 399
 400         return ret;
 401 }
 402
 403 int smu_v13_0_setup_pptable(struct smu_context *smu)
 404 {
 405         struct amdgpu_device *adev = smu->adev;
 406         uint32_t size = 0, pptable_id = 0;
 407         void *table;
 408         int ret = 0;
 409
 410         /* override pptable_id from driver parameter */
 411         if (amdgpu_smu_pptable_id >= 0) {
 412                 pptable_id = amdgpu_smu_pptable_id;
 413                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 414         } else {
 415                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 416         }
 417
 418         /* force using vbios pptable in sriov mode */
 419         if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
 420                 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
 421         else
 422                 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 423
 424         if (ret)
 425                 return ret;
 426
 427         if (!smu->smu_table.power_play_table)
 428                 smu->smu_table.power_play_table = table;
 429         if (!smu->smu_table.power_play_table_size)
 430                 smu->smu_table.power_play_table_size = size;
 431
 432         return 0;
 433 }
 434
 435 int smu_v13_0_init_smc_tables(struct smu_context *smu)
 436 {
 437         struct smu_table_context *smu_table = &smu->smu_table;
 438         struct smu_table *tables = smu_table->tables;
 439         int ret = 0;
 440
 441         smu_table->driver_pptable =
 442                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 443         if (!smu_table->driver_pptable) {
 444                 ret = -ENOMEM;
 445                 goto err0_out;
 446         }
 447
 448         smu_table->max_sustainable_clocks =
 449                 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
 450         if (!smu_table->max_sustainable_clocks) {
 451                 ret = -ENOMEM;
 452                 goto err1_out;
 453         }
 454
 455         /* Aldebaran does not support OVERDRIVE */
 456         if (tables[SMU_TABLE_OVERDRIVE].size) {
 457                 smu_table->overdrive_table =
 458                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 459                 if (!smu_table->overdrive_table) {
 460                         ret = -ENOMEM;
 461                         goto err2_out;
 462                 }
 463
 464                 smu_table->boot_overdrive_table =
 465                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 466                 if (!smu_table->boot_overdrive_table) {
 467                         ret = -ENOMEM;
 468                         goto err3_out;
 469                 }
 470
 471                 smu_table->user_overdrive_table =
 472                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 473                 if (!smu_table->user_overdrive_table) {
 474                         ret = -ENOMEM;
 475                         goto err4_out;
 476                 }
 477         }
 478
 479         smu_table->combo_pptable =
 480                 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
 481         if (!smu_table->combo_pptable) {
 482                 ret = -ENOMEM;
 483                 goto err5_out;
 484         }
 485
 486         return 0;
 487
 488 err5_out:
 489         kfree(smu_table->user_overdrive_table);
 490 err4_out:
 491         kfree(smu_table->boot_overdrive_table);
 492 err3_out:
 493         kfree(smu_table->overdrive_table);
 494 err2_out:
 495         kfree(smu_table->max_sustainable_clocks);
 496 err1_out:
 497         kfree(smu_table->driver_pptable);
 498 err0_out:
 499         return ret;
 500 }
 501
 502 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 503 {
 504         struct smu_table_context *smu_table = &smu->smu_table;
 505         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 506
 507         kfree(smu_table->gpu_metrics_table);
 508         kfree(smu_table->combo_pptable);
 509         kfree(smu_table->user_overdrive_table);
 510         kfree(smu_table->boot_overdrive_table);
 511         kfree(smu_table->overdrive_table);
 512         kfree(smu_table->max_sustainable_clocks);
 513         kfree(smu_table->driver_pptable);
 514         smu_table->gpu_metrics_table = NULL;
 515         smu_table->combo_pptable = NULL;
 516         smu_table->user_overdrive_table = NULL;
 517         smu_table->boot_overdrive_table = NULL;
 518         smu_table->overdrive_table = NULL;
 519         smu_table->max_sustainable_clocks = NULL;
 520         smu_table->driver_pptable = NULL;
 521         kfree(smu_table->hardcode_pptable);
 522         smu_table->hardcode_pptable = NULL;
 523
 524         kfree(smu_table->ecc_table);
 525         kfree(smu_table->metrics_table);
 526         kfree(smu_table->watermarks_table);
 527         smu_table->ecc_table = NULL;
 528         smu_table->metrics_table = NULL;
 529         smu_table->watermarks_table = NULL;
 530         smu_table->metrics_time = 0;
 531
 532         kfree(smu_dpm->dpm_context);
 533         kfree(smu_dpm->golden_dpm_context);
 534         kfree(smu_dpm->dpm_current_power_state);
 535         kfree(smu_dpm->dpm_request_power_state);
 536         smu_dpm->dpm_context = NULL;
 537         smu_dpm->golden_dpm_context = NULL;
 538         smu_dpm->dpm_context_size = 0;
 539         smu_dpm->dpm_current_power_state = NULL;
 540         smu_dpm->dpm_request_power_state = NULL;
 541
 542         return 0;
 543 }
 544
 545 int smu_v13_0_init_power(struct smu_context *smu)
 546 {
 547         struct smu_power_context *smu_power = &smu->smu_power;
 548
 549         if (smu_power->power_context || smu_power->power_context_size != 0)
 550                 return -EINVAL;
 551
 552         smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
 553                                            GFP_KERNEL);
 554         if (!smu_power->power_context)
 555                 return -ENOMEM;
 556         smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
 557
 558         return 0;
 559 }
 560
 561 int smu_v13_0_fini_power(struct smu_context *smu)
 562 {
 563         struct smu_power_context *smu_power = &smu->smu_power;
 564
 565         if (!smu_power->power_context || smu_power->power_context_size == 0)
 566                 return -EINVAL;
 567
 568         kfree(smu_power->power_context);
 569         smu_power->power_context = NULL;
 570         smu_power->power_context_size = 0;
 571
 572         return 0;
 573 }
 574
 575 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 576 {
 577         int ret, index;
 578         uint16_t size;
 579         uint8_t frev, crev;
 580         struct atom_common_table_header *header;
 581         struct atom_firmware_info_v3_4 *v_3_4;
 582         struct atom_firmware_info_v3_3 *v_3_3;
 583         struct atom_firmware_info_v3_1 *v_3_1;
 584         struct atom_smu_info_v3_6 *smu_info_v3_6;
 585         struct atom_smu_info_v4_0 *smu_info_v4_0;
 586
 587         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 588                                             firmwareinfo);
 589
 590         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 591                                              (uint8_t **)&header);
 592         if (ret)
 593                 return ret;
 594
 595         if (header->format_revision != 3) {
 596                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 597                 return -EINVAL;
 598         }
 599
 600         switch (header->content_revision) {
 601         case 0:
 602         case 1:
 603         case 2:
 604                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 605                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 606                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 607                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 608                 smu->smu_table.boot_values.socclk = 0;
 609                 smu->smu_table.boot_values.dcefclk = 0;
 610                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 611                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 612                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 613                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 614                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 615                 smu->smu_table.boot_values.pp_table_id = 0;
 616                 break;
 617         case 3:
 618                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 619                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 620                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 621                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 622                 smu->smu_table.boot_values.socclk = 0;
 623                 smu->smu_table.boot_values.dcefclk = 0;
 624                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 625                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 626                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 627                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 628                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 629                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 630                 break;
 631         case 4:
 632         default:
 633                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 634                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 635                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 636                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 637                 smu->smu_table.boot_values.socclk = 0;
 638                 smu->smu_table.boot_values.dcefclk = 0;
 639                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 640                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 641                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 642                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 643                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 644                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 645                 break;
 646         }
 647
 648         smu->smu_table.boot_values.format_revision = header->format_revision;
 649         smu->smu_table.boot_values.content_revision = header->content_revision;
 650
 651         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 652                                             smu_info);
 653         if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 654                                             (uint8_t **)&header)) {
 655
 656                 if ((frev == 3) && (crev == 6)) {
 657                         smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
 658
 659                         smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
 660                         smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
 661                         smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
 662                         smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
 663                 } else if ((frev == 3) && (crev == 1)) {
 664                         return 0;
 665                 } else if ((frev == 4) && (crev == 0)) {
 666                         smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
 667
 668                         smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
 669                         smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
 670                         smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
 671                         smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
 672                         smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
 673                 } else {
 674                         dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
 675                                                 (uint32_t)frev, (uint32_t)crev);
 676                 }
 677         }
 678
 679         return 0;
 680 }
 681
 682
 683 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
 684 {
 685         struct smu_table_context *smu_table = &smu->smu_table;
 686         struct smu_table *memory_pool = &smu_table->memory_pool;
 687         int ret = 0;
 688         uint64_t address;
 689         uint32_t address_low, address_high;
 690
 691         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 692                 return ret;
 693
 694         address = memory_pool->mc_address;
 695         address_high = (uint32_t)upper_32_bits(address);
 696         address_low  = (uint32_t)lower_32_bits(address);
 697
 698         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 699                                               address_high, NULL);
 700         if (ret)
 701                 return ret;
 702         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 703                                               address_low, NULL);
 704         if (ret)
 705                 return ret;
 706         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 707                                               (uint32_t)memory_pool->size, NULL);
 708         if (ret)
 709                 return ret;
 710
 711         return ret;
 712 }
 713
 714 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 715 {
 716         int ret;
 717
 718         ret = smu_cmn_send_smc_msg_with_param(smu,
 719                                               SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 720         if (ret)
 721                 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
 722
 723         return ret;
 724 }
 725
 726 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
 727 {
 728         struct smu_table *driver_table = &smu->smu_table.driver_table;
 729         int ret = 0;
 730
 731         if (driver_table->mc_address) {
 732                 ret = smu_cmn_send_smc_msg_with_param(smu,
 733                                                       SMU_MSG_SetDriverDramAddrHigh,
 734                                                       upper_32_bits(driver_table->mc_address),
 735                                                       NULL);
 736                 if (!ret)
 737                         ret = smu_cmn_send_smc_msg_with_param(smu,
 738                                                               SMU_MSG_SetDriverDramAddrLow,
 739                                                               lower_32_bits(driver_table->mc_address),
 740                                                               NULL);
 741         }
 742
 743         return ret;
 744 }
 745
 746 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
 747 {
 748         int ret = 0;
 749         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 750
 751         if (tool_table->mc_address) {
 752                 ret = smu_cmn_send_smc_msg_with_param(smu,
 753                                                       SMU_MSG_SetToolsDramAddrHigh,
 754                                                       upper_32_bits(tool_table->mc_address),
 755                                                       NULL);
 756                 if (!ret)
 757                         ret = smu_cmn_send_smc_msg_with_param(smu,
 758                                                               SMU_MSG_SetToolsDramAddrLow,
 759                                                               lower_32_bits(tool_table->mc_address),
 760                                                               NULL);
 761         }
 762
 763         return ret;
 764 }
 765
 766 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
 767 {
 768         int ret = 0;
 769
 770         if (!smu->pm_enabled)
 771                 return ret;
 772
 773         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 774
 775         return ret;
 776 }
 777
 778 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
 779 {
 780         struct smu_feature *feature = &smu->smu_feature;
 781         int ret = 0;
 782         uint32_t feature_mask[2];
 783
 784         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
 785             feature->feature_num < 64)
 786                 return -EINVAL;
 787
 788         bitmap_to_arr32(feature_mask, feature->allowed, 64);
 789
 790         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 791                                               feature_mask[1], NULL);
 792         if (ret)
 793                 return ret;
 794
 795         return smu_cmn_send_smc_msg_with_param(smu,
 796                                                SMU_MSG_SetAllowedFeaturesMaskLow,
 797                                                feature_mask[0],
 798                                                NULL);
 799 }
 800
 801 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
 802 {
 803         int ret = 0;
 804         struct amdgpu_device *adev = smu->adev;
 805
 806         switch (adev->ip_versions[MP1_HWIP][0]) {
 807         case IP_VERSION(13, 0, 0):
 808         case IP_VERSION(13, 0, 1):
 809         case IP_VERSION(13, 0, 3):
 810         case IP_VERSION(13, 0, 4):
 811         case IP_VERSION(13, 0, 5):
 812         case IP_VERSION(13, 0, 7):
 813         case IP_VERSION(13, 0, 8):
 814         case IP_VERSION(13, 0, 10):
 815         case IP_VERSION(13, 0, 11):
 816                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 817                         return 0;
 818                 if (enable)
 819                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 820                 else
 821                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 822                 break;
 823         default:
 824                 break;
 825         }
 826
 827         return ret;
 828 }
 829
 830 int smu_v13_0_system_features_control(struct smu_context *smu,
 831                                       bool en)
 832 {
 833         return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 834                                           SMU_MSG_DisableAllSmuFeatures), NULL);
 835 }
 836
 837 int smu_v13_0_notify_display_change(struct smu_context *smu)
 838 {
 839         int ret = 0;
 840
 841         if (!smu->pm_enabled)
 842                 return ret;
 843
 844         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 845             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 846                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 847
 848         return ret;
 849 }
 850
 851         static int
 852 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 853                                     enum smu_clk_type clock_select)
 854 {
 855         int ret = 0;
 856         int clk_id;
 857
 858         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 859             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 860                 return 0;
 861
 862         clk_id = smu_cmn_to_asic_specific_index(smu,
 863                                                 CMN2ASIC_MAPPING_CLK,
 864                                                 clock_select);
 865         if (clk_id < 0)
 866                 return -EINVAL;
 867
 868         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 869                                               clk_id << 16, clock);
 870         if (ret) {
 871                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 872                 return ret;
 873         }
 874
 875         if (*clock != 0)
 876                 return 0;
 877
 878         /* if DC limit is zero, return AC limit */
 879         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 880                                               clk_id << 16, clock);
 881         if (ret) {
 882                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 883                 return ret;
 884         }
 885
 886         return 0;
 887 }
 888
 889 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
 890 {
 891         struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
 892                 smu->smu_table.max_sustainable_clocks;
 893         int ret = 0;
 894
 895         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 896         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 897         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 898         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 899         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 900         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 901
 902         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 903                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 904                                                           &(max_sustainable_clocks->uclock),
 905                                                           SMU_UCLK);
 906                 if (ret) {
 907                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 908                                 __func__);
 909                         return ret;
 910                 }
 911         }
 912
 913         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 914                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 915                                                           &(max_sustainable_clocks->soc_clock),
 916                                                           SMU_SOCCLK);
 917                 if (ret) {
 918                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 919                                 __func__);
 920                         return ret;
 921                 }
 922         }
 923
 924         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 925                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 926                                                           &(max_sustainable_clocks->dcef_clock),
 927                                                           SMU_DCEFCLK);
 928                 if (ret) {
 929                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 930                                 __func__);
 931                         return ret;
 932                 }
 933
 934                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 935                                                           &(max_sustainable_clocks->display_clock),
 936                                                           SMU_DISPCLK);
 937                 if (ret) {
 938                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 939                                 __func__);
 940                         return ret;
 941                 }
 942                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 943                                                           &(max_sustainable_clocks->phy_clock),
 944                                                           SMU_PHYCLK);
 945                 if (ret) {
 946                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 947                                 __func__);
 948                         return ret;
 949                 }
 950                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 951                                                           &(max_sustainable_clocks->pixel_clock),
 952                                                           SMU_PIXCLK);
 953                 if (ret) {
 954                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 955                                 __func__);
 956                         return ret;
 957                 }
 958         }
 959
 960         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 961                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 962
 963         return 0;
 964 }
 965
 966 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
 967                                       uint32_t *power_limit)
 968 {
 969         int power_src;
 970         int ret = 0;
 971
 972         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 973                 return -EINVAL;
 974
 975         power_src = smu_cmn_to_asic_specific_index(smu,
 976                                                    CMN2ASIC_MAPPING_PWR,
 977                                                    smu->adev->pm.ac_power ?
 978                                                    SMU_POWER_SOURCE_AC :
 979                                                    SMU_POWER_SOURCE_DC);
 980         if (power_src < 0)
 981                 return -EINVAL;
 982
 983         ret = smu_cmn_send_smc_msg_with_param(smu,
 984                                               SMU_MSG_GetPptLimit,
 985                                               power_src << 16,
 986                                               power_limit);
 987         if (ret)
 988                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 989
 990         return ret;
 991 }
 992
 993 int smu_v13_0_set_power_limit(struct smu_context *smu,
 994                               enum smu_ppt_limit_type limit_type,
 995                               uint32_t limit)
 996 {
 997         int ret = 0;
 998
 999         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1000                 return -EINVAL;
1001
1002         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1003                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1004                 return -EOPNOTSUPP;
1005         }
1006
1007         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1008         if (ret) {
1009                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1010                 return ret;
1011         }
1012
1013         smu->current_power_limit = limit;
1014
1015         return 0;
1016 }
1017
1018 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1019 {
1020         return smu_cmn_send_smc_msg(smu,
1021                                     SMU_MSG_AllowIHHostInterrupt,
1022                                     NULL);
1023 }
1024
1025 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1026 {
1027         int ret = 0;
1028
1029         if (smu->dc_controlled_by_gpio &&
1030             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1031                 ret = smu_v13_0_allow_ih_interrupt(smu);
1032
1033         return ret;
1034 }
1035
1036 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1037 {
1038         int ret = 0;
1039
1040         if (!smu->irq_source.num_types)
1041                 return 0;
1042
1043         ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1044         if (ret)
1045                 return ret;
1046
1047         return smu_v13_0_process_pending_interrupt(smu);
1048 }
1049
1050 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1051 {
1052         if (!smu->irq_source.num_types)
1053                 return 0;
1054
1055         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1056 }
1057
1058 static uint16_t convert_to_vddc(uint8_t vid)
1059 {
1060         return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1061 }
1062
1063 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1064 {
1065         struct amdgpu_device *adev = smu->adev;
1066         uint32_t vdd = 0, val_vid = 0;
1067
1068         if (!value)
1069                 return -EINVAL;
1070         val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1071                    SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1072                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1073
1074         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1075
1076         *value = vdd;
1077
1078         return 0;
1079
1080 }
1081
1082 int
1083 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1084                                         struct pp_display_clock_request
1085                                         *clock_req)
1086 {
1087         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1088         int ret = 0;
1089         enum smu_clk_type clk_select = 0;
1090         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1091
1092         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1093             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1094                 switch (clk_type) {
1095                 case amd_pp_dcef_clock:
1096                         clk_select = SMU_DCEFCLK;
1097                         break;
1098                 case amd_pp_disp_clock:
1099                         clk_select = SMU_DISPCLK;
1100                         break;
1101                 case amd_pp_pixel_clock:
1102                         clk_select = SMU_PIXCLK;
1103                         break;
1104                 case amd_pp_phy_clock:
1105                         clk_select = SMU_PHYCLK;
1106                         break;
1107                 case amd_pp_mem_clock:
1108                         clk_select = SMU_UCLK;
1109                         break;
1110                 default:
1111                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1112                         ret = -EINVAL;
1113                         break;
1114                 }
1115
1116                 if (ret)
1117                         goto failed;
1118
1119                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1120                         return 0;
1121
1122                 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1123
1124                 if (clk_select == SMU_UCLK)
1125                         smu->hard_min_uclk_req_from_dal = clk_freq;
1126         }
1127
1128 failed:
1129         return ret;
1130 }
1131
1132 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1133 {
1134         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1135                 return AMD_FAN_CTRL_MANUAL;
1136         else
1137                 return AMD_FAN_CTRL_AUTO;
1138 }
1139
1140         static int
1141 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1142 {
1143         int ret = 0;
1144
1145         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1146                 return 0;
1147
1148         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1149         if (ret)
1150                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1151                         __func__, (auto_fan_control ? "Start" : "Stop"));
1152
1153         return ret;
1154 }
1155
1156         static int
1157 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1158 {
1159         struct amdgpu_device *adev = smu->adev;
1160
1161         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1162                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1163                                    CG_FDO_CTRL2, TMIN, 0));
1164         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1165                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1166                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1167
1168         return 0;
1169 }
1170
1171 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1172                                 uint32_t speed)
1173 {
1174         struct amdgpu_device *adev = smu->adev;
1175         uint32_t duty100, duty;
1176         uint64_t tmp64;
1177
1178         speed = MIN(speed, 255);
1179
1180         if (smu_v13_0_auto_fan_control(smu, 0))
1181                 return -EINVAL;
1182
1183         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1184                                 CG_FDO_CTRL1, FMAX_DUTY100);
1185         if (!duty100)
1186                 return -EINVAL;
1187
1188         tmp64 = (uint64_t)speed * duty100;
1189         do_div(tmp64, 255);
1190         duty = (uint32_t)tmp64;
1191
1192         WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1193                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1194                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1195
1196         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1197 }
1198
1199         int
1200 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1201                                uint32_t mode)
1202 {
1203         int ret = 0;
1204
1205         switch (mode) {
1206         case AMD_FAN_CTRL_NONE:
1207                 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1208                 break;
1209         case AMD_FAN_CTRL_MANUAL:
1210                 ret = smu_v13_0_auto_fan_control(smu, 0);
1211                 break;
1212         case AMD_FAN_CTRL_AUTO:
1213                 ret = smu_v13_0_auto_fan_control(smu, 1);
1214                 break;
1215         default:
1216                 break;
1217         }
1218
1219         if (ret) {
1220                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1221                 return -EINVAL;
1222         }
1223
1224         return ret;
1225 }
1226
1227 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1228                                 uint32_t speed)
1229 {
1230         struct amdgpu_device *adev = smu->adev;
1231         uint32_t crystal_clock_freq = 2500;
1232         uint32_t tach_period;
1233         int ret;
1234
1235         if (!speed)
1236                 return -EINVAL;
1237
1238         ret = smu_v13_0_auto_fan_control(smu, 0);
1239         if (ret)
1240                 return ret;
1241
1242         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1243         WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1244                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1245                                    CG_TACH_CTRL, TARGET_PERIOD,
1246                                    tach_period));
1247
1248         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1249 }
1250
1251 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1252                               uint32_t pstate)
1253 {
1254         int ret = 0;
1255         ret = smu_cmn_send_smc_msg_with_param(smu,
1256                                               SMU_MSG_SetXgmiMode,
1257                                               pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1258                                               NULL);
1259         return ret;
1260 }
1261
1262 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1263                                    struct amdgpu_irq_src *source,
1264                                    unsigned tyep,
1265                                    enum amdgpu_interrupt_state state)
1266 {
1267         struct smu_context *smu = adev->powerplay.pp_handle;
1268         uint32_t low, high;
1269         uint32_t val = 0;
1270
1271         switch (state) {
1272         case AMDGPU_IRQ_STATE_DISABLE:
1273                 /* For THM irqs */
1274                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1275                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1276                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1277                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1278
1279                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1280
1281                 /* For MP1 SW irqs */
1282                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1283                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1284                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1285
1286                 break;
1287         case AMDGPU_IRQ_STATE_ENABLE:
1288                 /* For THM irqs */
1289                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1290                           smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1291                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1292                            smu->thermal_range.software_shutdown_temp);
1293
1294                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1295                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1296                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1297                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1298                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1299                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1300                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1301                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1302                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1303
1304                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1305                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1306                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1307                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1308
1309                 /* For MP1 SW irqs */
1310                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1311                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1312                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1313                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1314
1315                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1316                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1317                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1318
1319                 break;
1320         default:
1321                 break;
1322         }
1323
1324         return 0;
1325 }
1326
1327 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1328 {
1329         return smu_cmn_send_smc_msg(smu,
1330                                     SMU_MSG_ReenableAcDcInterrupt,
1331                                     NULL);
1332 }
1333
1334 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1335 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1336 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1337
1338 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1339                                  struct amdgpu_irq_src *source,
1340                                  struct amdgpu_iv_entry *entry)
1341 {
1342         struct smu_context *smu = adev->powerplay.pp_handle;
1343         uint32_t client_id = entry->client_id;
1344         uint32_t src_id = entry->src_id;
1345         /*
1346          * ctxid is used to distinguish different
1347          * events for SMCToHost interrupt.
1348          */
1349         uint32_t ctxid = entry->src_data[0];
1350         uint32_t data;
1351         uint32_t high;
1352
1353         if (client_id == SOC15_IH_CLIENTID_THM) {
1354                 switch (src_id) {
1355                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1356                         schedule_delayed_work(&smu->swctf_delayed_work,
1357                                               msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1358                         break;
1359                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1360                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1361                         break;
1362                 default:
1363                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1364                                   src_id);
1365                         break;
1366                 }
1367         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1368                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1369                 /*
1370                  * HW CTF just occurred. Shutdown to prevent further damage.
1371                  */
1372                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1373                 orderly_poweroff(true);
1374         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1375                 if (src_id == 0xfe) {
1376                         /* ACK SMUToHost interrupt */
1377                         data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1378                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1379                         WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1380
1381                         switch (ctxid) {
1382                         case 0x3:
1383                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1384                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1385                                 break;
1386                         case 0x4:
1387                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1388                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1389                                 break;
1390                         case 0x7:
1391                                 /*
1392                                  * Increment the throttle interrupt counter
1393                                  */
1394                                 atomic64_inc(&smu->throttle_int_counter);
1395
1396                                 if (!atomic_read(&adev->throttling_logging_enabled))
1397                                         return 0;
1398
1399                                 if (__ratelimit(&adev->throttling_logging_rs))
1400                                         schedule_work(&smu->throttling_logging_work);
1401
1402                                 break;
1403                         case 0x8:
1404                                 high = smu->thermal_range.software_shutdown_temp +
1405                                         smu->thermal_range.software_shutdown_temp_offset;
1406                                 high = min_t(typeof(high),
1407                                              SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1408                                              high);
1409                                 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1410                                                         high,
1411                                                         smu->thermal_range.software_shutdown_temp_offset);
1412
1413                                 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1414                                 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1415                                                         DIG_THERM_INTH,
1416                                                         (high & 0xff));
1417                                 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1418                                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1419                                 break;
1420                         case 0x9:
1421                                 high = min_t(typeof(high),
1422                                              SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1423                                              smu->thermal_range.software_shutdown_temp);
1424                                 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1425
1426                                 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1427                                 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1428                                                         DIG_THERM_INTH,
1429                                                         (high & 0xff));
1430                                 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1431                                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1432                                 break;
1433                         }
1434                 }
1435         }
1436
1437         return 0;
1438 }
1439
1440 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = {
1441         .set = smu_v13_0_set_irq_state,
1442         .process = smu_v13_0_irq_process,
1443 };
1444
1445 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1446 {
1447         struct amdgpu_device *adev = smu->adev;
1448         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1449         int ret = 0;
1450
1451         if (amdgpu_sriov_vf(adev))
1452                 return 0;
1453
1454         irq_src->num_types = 1;
1455         irq_src->funcs = &smu_v13_0_irq_funcs;
1456
1457         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1458                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1459                                 irq_src);
1460         if (ret)
1461                 return ret;
1462
1463         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1464                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1465                                 irq_src);
1466         if (ret)
1467                 return ret;
1468
1469         /* Register CTF(GPIO_19) interrupt */
1470         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1471                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1472                                 irq_src);
1473         if (ret)
1474                 return ret;
1475
1476         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1477                                 0xfe,
1478                                 irq_src);
1479         if (ret)
1480                 return ret;
1481
1482         return ret;
1483 }
1484
1485 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1486                                                struct pp_smu_nv_clock_table *max_clocks)
1487 {
1488         struct smu_table_context *table_context = &smu->smu_table;
1489         struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1490
1491         if (!max_clocks || !table_context->max_sustainable_clocks)
1492                 return -EINVAL;
1493
1494         sustainable_clocks = table_context->max_sustainable_clocks;
1495
1496         max_clocks->dcfClockInKhz =
1497                 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1498         max_clocks->displayClockInKhz =
1499                 (unsigned int) sustainable_clocks->display_clock * 1000;
1500         max_clocks->phyClockInKhz =
1501                 (unsigned int) sustainable_clocks->phy_clock * 1000;
1502         max_clocks->pixelClockInKhz =
1503                 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1504         max_clocks->uClockInKhz =
1505                 (unsigned int) sustainable_clocks->uclock * 1000;
1506         max_clocks->socClockInKhz =
1507                 (unsigned int) sustainable_clocks->soc_clock * 1000;
1508         max_clocks->dscClockInKhz = 0;
1509         max_clocks->dppClockInKhz = 0;
1510         max_clocks->fabricClockInKhz = 0;
1511
1512         return 0;
1513 }
1514
1515 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1516 {
1517         int ret = 0;
1518
1519         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1520
1521         return ret;
1522 }
1523
1524 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1525                                              uint64_t event_arg)
1526 {
1527         int ret = 0;
1528
1529         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1530         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1531
1532         return ret;
1533 }
1534
1535 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1536                              uint64_t event_arg)
1537 {
1538         int ret = -EINVAL;
1539
1540         switch (event) {
1541         case SMU_EVENT_RESET_COMPLETE:
1542                 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1543                 break;
1544         default:
1545                 break;
1546         }
1547
1548         return ret;
1549 }
1550
1551 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1552                                     uint32_t *min, uint32_t *max)
1553 {
1554         int ret = 0, clk_id = 0;
1555         uint32_t param = 0;
1556         uint32_t clock_limit;
1557
1558         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1559                 switch (clk_type) {
1560                 case SMU_MCLK:
1561                 case SMU_UCLK:
1562                         clock_limit = smu->smu_table.boot_values.uclk;
1563                         break;
1564                 case SMU_GFXCLK:
1565                 case SMU_SCLK:
1566                         clock_limit = smu->smu_table.boot_values.gfxclk;
1567                         break;
1568                 case SMU_SOCCLK:
1569                         clock_limit = smu->smu_table.boot_values.socclk;
1570                         break;
1571                 default:
1572                         clock_limit = 0;
1573                         break;
1574                 }
1575
1576                 /* clock in Mhz unit */
1577                 if (min)
1578                         *min = clock_limit / 100;
1579                 if (max)
1580                         *max = clock_limit / 100;
1581
1582                 return 0;
1583         }
1584
1585         clk_id = smu_cmn_to_asic_specific_index(smu,
1586                                                 CMN2ASIC_MAPPING_CLK,
1587                                                 clk_type);
1588         if (clk_id < 0) {
1589                 ret = -EINVAL;
1590                 goto failed;
1591         }
1592         param = (clk_id & 0xffff) << 16;
1593
1594         if (max) {
1595                 if (smu->adev->pm.ac_power)
1596                         ret = smu_cmn_send_smc_msg_with_param(smu,
1597                                                               SMU_MSG_GetMaxDpmFreq,
1598                                                               param,
1599                                                               max);
1600                 else
1601                         ret = smu_cmn_send_smc_msg_with_param(smu,
1602                                                               SMU_MSG_GetDcModeMaxDpmFreq,
1603                                                               param,
1604                                                               max);
1605                 if (ret)
1606                         goto failed;
1607         }
1608
1609         if (min) {
1610                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1611                 if (ret)
1612                         goto failed;
1613         }
1614
1615 failed:
1616         return ret;
1617 }
1618
1619 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1620                                           enum smu_clk_type clk_type,
1621                                           uint32_t min,
1622                                           uint32_t max)
1623 {
1624         int ret = 0, clk_id = 0;
1625         uint32_t param;
1626
1627         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1628                 return 0;
1629
1630         clk_id = smu_cmn_to_asic_specific_index(smu,
1631                                                 CMN2ASIC_MAPPING_CLK,
1632                                                 clk_type);
1633         if (clk_id < 0)
1634                 return clk_id;
1635
1636         if (max > 0) {
1637                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1638                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1639                                                       param, NULL);
1640                 if (ret)
1641                         goto out;
1642         }
1643
1644         if (min > 0) {
1645                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1646                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1647                                                       param, NULL);
1648                 if (ret)
1649                         goto out;
1650         }
1651
1652 out:
1653         return ret;
1654 }
1655
1656 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1657                                           enum smu_clk_type clk_type,
1658                                           uint32_t min,
1659                                           uint32_t max)
1660 {
1661         int ret = 0, clk_id = 0;
1662         uint32_t param;
1663
1664         if (min <= 0 && max <= 0)
1665                 return -EINVAL;
1666
1667         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1668                 return 0;
1669
1670         clk_id = smu_cmn_to_asic_specific_index(smu,
1671                                                 CMN2ASIC_MAPPING_CLK,
1672                                                 clk_type);
1673         if (clk_id < 0)
1674                 return clk_id;
1675
1676         if (max > 0) {
1677                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1678                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1679                                                       param, NULL);
1680                 if (ret)
1681                         return ret;
1682         }
1683
1684         if (min > 0) {
1685                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1686                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1687                                                       param, NULL);
1688                 if (ret)
1689                         return ret;
1690         }
1691
1692         return ret;
1693 }
1694
1695 int smu_v13_0_set_performance_level(struct smu_context *smu,
1696                                     enum amd_dpm_forced_level level)
1697 {
1698         struct smu_13_0_dpm_context *dpm_context =
1699                 smu->smu_dpm.dpm_context;
1700         struct smu_13_0_dpm_table *gfx_table =
1701                 &dpm_context->dpm_tables.gfx_table;
1702         struct smu_13_0_dpm_table *mem_table =
1703                 &dpm_context->dpm_tables.uclk_table;
1704         struct smu_13_0_dpm_table *soc_table =
1705                 &dpm_context->dpm_tables.soc_table;
1706         struct smu_13_0_dpm_table *vclk_table =
1707                 &dpm_context->dpm_tables.vclk_table;
1708         struct smu_13_0_dpm_table *dclk_table =
1709                 &dpm_context->dpm_tables.dclk_table;
1710         struct smu_13_0_dpm_table *fclk_table =
1711                 &dpm_context->dpm_tables.fclk_table;
1712         struct smu_umd_pstate_table *pstate_table =
1713                 &smu->pstate_table;
1714         struct amdgpu_device *adev = smu->adev;
1715         uint32_t sclk_min = 0, sclk_max = 0;
1716         uint32_t mclk_min = 0, mclk_max = 0;
1717         uint32_t socclk_min = 0, socclk_max = 0;
1718         uint32_t vclk_min = 0, vclk_max = 0;
1719         uint32_t dclk_min = 0, dclk_max = 0;
1720         uint32_t fclk_min = 0, fclk_max = 0;
1721         int ret = 0, i;
1722
1723         switch (level) {
1724         case AMD_DPM_FORCED_LEVEL_HIGH:
1725                 sclk_min = sclk_max = gfx_table->max;
1726                 mclk_min = mclk_max = mem_table->max;
1727                 socclk_min = socclk_max = soc_table->max;
1728                 vclk_min = vclk_max = vclk_table->max;
1729                 dclk_min = dclk_max = dclk_table->max;
1730                 fclk_min = fclk_max = fclk_table->max;
1731                 break;
1732         case AMD_DPM_FORCED_LEVEL_LOW:
1733                 sclk_min = sclk_max = gfx_table->min;
1734                 mclk_min = mclk_max = mem_table->min;
1735                 socclk_min = socclk_max = soc_table->min;
1736                 vclk_min = vclk_max = vclk_table->min;
1737                 dclk_min = dclk_max = dclk_table->min;
1738                 fclk_min = fclk_max = fclk_table->min;
1739                 break;
1740         case AMD_DPM_FORCED_LEVEL_AUTO:
1741                 sclk_min = gfx_table->min;
1742                 sclk_max = gfx_table->max;
1743                 mclk_min = mem_table->min;
1744                 mclk_max = mem_table->max;
1745                 socclk_min = soc_table->min;
1746                 socclk_max = soc_table->max;
1747                 vclk_min = vclk_table->min;
1748                 vclk_max = vclk_table->max;
1749                 dclk_min = dclk_table->min;
1750                 dclk_max = dclk_table->max;
1751                 fclk_min = fclk_table->min;
1752                 fclk_max = fclk_table->max;
1753                 break;
1754         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1755                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1756                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1757                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1758                 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1759                 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1760                 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1761                 break;
1762         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1763                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1764                 break;
1765         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1766                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1767                 break;
1768         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1769                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1770                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1771                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1772                 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1773                 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1774                 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1775                 break;
1776         case AMD_DPM_FORCED_LEVEL_MANUAL:
1777         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1778                 return 0;
1779         default:
1780                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1781                 return -EINVAL;
1782         }
1783
1784         /*
1785          * Unset those settings for SMU 13.0.2. As soft limits settings
1786          * for those clock domains are not supported.
1787          */
1788         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1789                 mclk_min = mclk_max = 0;
1790                 socclk_min = socclk_max = 0;
1791                 vclk_min = vclk_max = 0;
1792                 dclk_min = dclk_max = 0;
1793                 fclk_min = fclk_max = 0;
1794         }
1795
1796         if (sclk_min && sclk_max) {
1797                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1798                                                             SMU_GFXCLK,
1799                                                             sclk_min,
1800                                                             sclk_max);
1801                 if (ret)
1802                         return ret;
1803
1804                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1805                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1806         }
1807
1808         if (mclk_min && mclk_max) {
1809                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1810                                                             SMU_MCLK,
1811                                                             mclk_min,
1812                                                             mclk_max);
1813                 if (ret)
1814                         return ret;
1815
1816                 pstate_table->uclk_pstate.curr.min = mclk_min;
1817                 pstate_table->uclk_pstate.curr.max = mclk_max;
1818         }
1819
1820         if (socclk_min && socclk_max) {
1821                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1822                                                             SMU_SOCCLK,
1823                                                             socclk_min,
1824                                                             socclk_max);
1825                 if (ret)
1826                         return ret;
1827
1828                 pstate_table->socclk_pstate.curr.min = socclk_min;
1829                 pstate_table->socclk_pstate.curr.max = socclk_max;
1830         }
1831
1832         if (vclk_min && vclk_max) {
1833                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1834                         if (adev->vcn.harvest_config & (1 << i))
1835                                 continue;
1836                         ret = smu_v13_0_set_soft_freq_limited_range(smu,
1837                                                                     i ? SMU_VCLK1 : SMU_VCLK,
1838                                                                     vclk_min,
1839                                                                     vclk_max);
1840                         if (ret)
1841                                 return ret;
1842                 }
1843                 pstate_table->vclk_pstate.curr.min = vclk_min;
1844                 pstate_table->vclk_pstate.curr.max = vclk_max;
1845         }
1846
1847         if (dclk_min && dclk_max) {
1848                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1849                         if (adev->vcn.harvest_config & (1 << i))
1850                                 continue;
1851                         ret = smu_v13_0_set_soft_freq_limited_range(smu,
1852                                                                     i ? SMU_DCLK1 : SMU_DCLK,
1853                                                                     dclk_min,
1854                                                                     dclk_max);
1855                         if (ret)
1856                                 return ret;
1857                 }
1858                 pstate_table->dclk_pstate.curr.min = dclk_min;
1859                 pstate_table->dclk_pstate.curr.max = dclk_max;
1860         }
1861
1862         if (fclk_min && fclk_max) {
1863                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1864                                                             SMU_FCLK,
1865                                                             fclk_min,
1866                                                             fclk_max);
1867                 if (ret)
1868                         return ret;
1869
1870                 pstate_table->fclk_pstate.curr.min = fclk_min;
1871                 pstate_table->fclk_pstate.curr.max = fclk_max;
1872         }
1873
1874         return ret;
1875 }
1876
1877 int smu_v13_0_set_power_source(struct smu_context *smu,
1878                                enum smu_power_src_type power_src)
1879 {
1880         int pwr_source;
1881
1882         pwr_source = smu_cmn_to_asic_specific_index(smu,
1883                                                     CMN2ASIC_MAPPING_PWR,
1884                                                     (uint32_t)power_src);
1885         if (pwr_source < 0)
1886                 return -EINVAL;
1887
1888         return smu_cmn_send_smc_msg_with_param(smu,
1889                                                SMU_MSG_NotifyPowerSource,
1890                                                pwr_source,
1891                                                NULL);
1892 }
1893
1894 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1895                                     enum smu_clk_type clk_type, uint16_t level,
1896                                     uint32_t *value)
1897 {
1898         int ret = 0, clk_id = 0;
1899         uint32_t param;
1900
1901         if (!value)
1902                 return -EINVAL;
1903
1904         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1905                 return 0;
1906
1907         clk_id = smu_cmn_to_asic_specific_index(smu,
1908                                                 CMN2ASIC_MAPPING_CLK,
1909                                                 clk_type);
1910         if (clk_id < 0)
1911                 return clk_id;
1912
1913         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1914
1915         ret = smu_cmn_send_smc_msg_with_param(smu,
1916                                               SMU_MSG_GetDpmFreqByIndex,
1917                                               param,
1918                                               value);
1919         if (ret)
1920                 return ret;
1921
1922         *value = *value & 0x7fffffff;
1923
1924         return ret;
1925 }
1926
1927 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1928                                          enum smu_clk_type clk_type,
1929                                          uint32_t *value)
1930 {
1931         int ret;
1932
1933         ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1934         /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1935         if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1936                 ++(*value);
1937
1938         return ret;
1939 }
1940
1941 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1942                                              enum smu_clk_type clk_type,
1943                                              bool *is_fine_grained_dpm)
1944 {
1945         int ret = 0, clk_id = 0;
1946         uint32_t param;
1947         uint32_t value;
1948
1949         if (!is_fine_grained_dpm)
1950                 return -EINVAL;
1951
1952         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1953                 return 0;
1954
1955         clk_id = smu_cmn_to_asic_specific_index(smu,
1956                                                 CMN2ASIC_MAPPING_CLK,
1957                                                 clk_type);
1958         if (clk_id < 0)
1959                 return clk_id;
1960
1961         param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1962
1963         ret = smu_cmn_send_smc_msg_with_param(smu,
1964                                               SMU_MSG_GetDpmFreqByIndex,
1965                                               param,
1966                                               &value);
1967         if (ret)
1968                 return ret;
1969
1970         /*
1971          * BIT31:  1 - Fine grained DPM, 0 - Dicrete DPM
1972          * now, we un-support it
1973          */
1974         *is_fine_grained_dpm = value & 0x80000000;
1975
1976         return 0;
1977 }
1978
1979 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1980                                    enum smu_clk_type clk_type,
1981                                    struct smu_13_0_dpm_table *single_dpm_table)
1982 {
1983         int ret = 0;
1984         uint32_t clk;
1985         int i;
1986
1987         ret = smu_v13_0_get_dpm_level_count(smu,
1988                                             clk_type,
1989                                             &single_dpm_table->count);
1990         if (ret) {
1991                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1992                 return ret;
1993         }
1994
1995         if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
1996                 ret = smu_v13_0_get_fine_grained_status(smu,
1997                                                         clk_type,
1998                                                         &single_dpm_table->is_fine_grained);
1999                 if (ret) {
2000                         dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2001                         return ret;
2002                 }
2003         }
2004
2005         for (i = 0; i < single_dpm_table->count; i++) {
2006                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2007                                                       clk_type,
2008                                                       i,
2009                                                       &clk);
2010                 if (ret) {
2011                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2012                         return ret;
2013                 }
2014
2015                 single_dpm_table->dpm_levels[i].value = clk;
2016                 single_dpm_table->dpm_levels[i].enabled = true;
2017
2018                 if (i == 0)
2019                         single_dpm_table->min = clk;
2020                 else if (i == single_dpm_table->count - 1)
2021                         single_dpm_table->max = clk;
2022         }
2023
2024         return 0;
2025 }
2026
2027 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2028 {
2029         struct amdgpu_device *adev = smu->adev;
2030
2031         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2032                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2033                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2034 }
2035
2036 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2037 {
2038         uint32_t width_level;
2039
2040         width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2041         if (width_level > LINK_WIDTH_MAX)
2042                 width_level = 0;
2043
2044         return link_width[width_level];
2045 }
2046
2047 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2048 {
2049         struct amdgpu_device *adev = smu->adev;
2050
2051         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2052                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2053                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2054 }
2055
2056 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2057 {
2058         uint32_t speed_level;
2059
2060         speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2061         if (speed_level > LINK_SPEED_MAX)
2062                 speed_level = 0;
2063
2064         return link_speed[speed_level];
2065 }
2066
2067 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2068                              bool enable)
2069 {
2070         struct amdgpu_device *adev = smu->adev;
2071         int i, ret = 0;
2072
2073         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2074                 if (adev->vcn.harvest_config & (1 << i))
2075                         continue;
2076
2077                 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2078                                                       SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2079                                                       i << 16U, NULL);
2080                 if (ret)
2081                         return ret;
2082         }
2083
2084         return ret;
2085 }
2086
2087 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2088                               bool enable)
2089 {
2090         return smu_cmn_send_smc_msg_with_param(smu, enable ?
2091                                                SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2092                                                0, NULL);
2093 }
2094
2095 int smu_v13_0_run_btc(struct smu_context *smu)
2096 {
2097         int res;
2098
2099         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2100         if (res)
2101                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2102
2103         return res;
2104 }
2105
2106 int smu_v13_0_gpo_control(struct smu_context *smu,
2107                           bool enablement)
2108 {
2109         int res;
2110
2111         res = smu_cmn_send_smc_msg_with_param(smu,
2112                                               SMU_MSG_AllowGpo,
2113                                               enablement ? 1 : 0,
2114                                               NULL);
2115         if (res)
2116                 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2117
2118         return res;
2119 }
2120
2121 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2122                                  bool enablement)
2123 {
2124         struct amdgpu_device *adev = smu->adev;
2125         int ret = 0;
2126
2127         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2128                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2129                 if (ret) {
2130                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2131                         return ret;
2132                 }
2133         }
2134
2135         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2136                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2137                 if (ret) {
2138                         dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2139                         return ret;
2140                 }
2141         }
2142
2143         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2144                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2145                 if (ret) {
2146                         dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2147                         return ret;
2148                 }
2149         }
2150
2151         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2152                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2153                 if (ret) {
2154                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2155                         return ret;
2156                 }
2157         }
2158
2159         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2160                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2161                 if (ret) {
2162                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2163                         return ret;
2164                 }
2165         }
2166
2167         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2168                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2169                 if (ret) {
2170                         dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2171                         return ret;
2172                 }
2173         }
2174
2175         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2176                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2177                 if (ret) {
2178                         dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2179                         return ret;
2180                 }
2181         }
2182
2183         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2184                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2185                 if (ret) {
2186                         dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2187                         return ret;
2188                 }
2189         }
2190
2191         return ret;
2192 }
2193
2194 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2195                               bool enablement)
2196 {
2197         int ret = 0;
2198
2199         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2200                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2201
2202         return ret;
2203 }
2204
2205 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2206                                       enum smu_baco_seq baco_seq)
2207 {
2208         struct smu_baco_context *smu_baco = &smu->smu_baco;
2209         int ret;
2210
2211         ret = smu_cmn_send_smc_msg_with_param(smu,
2212                                               SMU_MSG_ArmD3,
2213                                               baco_seq,
2214                                               NULL);
2215         if (ret)
2216                 return ret;
2217
2218         if (baco_seq == BACO_SEQ_BAMACO ||
2219             baco_seq == BACO_SEQ_BACO)
2220                 smu_baco->state = SMU_BACO_STATE_ENTER;
2221         else
2222                 smu_baco->state = SMU_BACO_STATE_EXIT;
2223
2224         return 0;
2225 }
2226
2227 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2228 {
2229         struct smu_baco_context *smu_baco = &smu->smu_baco;
2230
2231         if (amdgpu_sriov_vf(smu->adev) ||
2232             !smu_baco->platform_support)
2233                 return false;
2234
2235         /* return true if ASIC is in BACO state already */
2236         if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2237                 return true;
2238
2239         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2240             !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2241                 return false;
2242
2243         return true;
2244 }
2245
2246 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2247 {
2248         struct smu_baco_context *smu_baco = &smu->smu_baco;
2249
2250         return smu_baco->state;
2251 }
2252
2253 int smu_v13_0_baco_set_state(struct smu_context *smu,
2254                              enum smu_baco_state state)
2255 {
2256         struct smu_baco_context *smu_baco = &smu->smu_baco;
2257         struct amdgpu_device *adev = smu->adev;
2258         int ret = 0;
2259
2260         if (smu_v13_0_baco_get_state(smu) == state)
2261                 return 0;
2262
2263         if (state == SMU_BACO_STATE_ENTER) {
2264                 ret = smu_cmn_send_smc_msg_with_param(smu,
2265                                                       SMU_MSG_EnterBaco,
2266                                                       smu_baco->maco_support ?
2267                                                       BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2268                                                       NULL);
2269         } else {
2270                 ret = smu_cmn_send_smc_msg(smu,
2271                                            SMU_MSG_ExitBaco,
2272                                            NULL);
2273                 if (ret)
2274                         return ret;
2275
2276                 /* clear vbios scratch 6 and 7 for coming asic reinit */
2277                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2278                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2279         }
2280
2281         if (!ret)
2282                 smu_baco->state = state;
2283
2284         return ret;
2285 }
2286
2287 int smu_v13_0_baco_enter(struct smu_context *smu)
2288 {
2289         int ret = 0;
2290
2291         ret = smu_v13_0_baco_set_state(smu,
2292                                        SMU_BACO_STATE_ENTER);
2293         if (ret)
2294                 return ret;
2295
2296         msleep(10);
2297
2298         return ret;
2299 }
2300
2301 int smu_v13_0_baco_exit(struct smu_context *smu)
2302 {
2303         return smu_v13_0_baco_set_state(smu,
2304                                         SMU_BACO_STATE_EXIT);
2305 }
2306
2307 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2308 {
2309         uint16_t index;
2310
2311         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2312                                                SMU_MSG_EnableGfxImu);
2313         /* Param 1 to tell PMFW to enable GFXOFF feature */
2314         return smu_cmn_send_msg_without_waiting(smu, index, 1);
2315 }
2316
2317 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2318                                 enum PP_OD_DPM_TABLE_COMMAND type,
2319                                 long input[], uint32_t size)
2320 {
2321         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2322         int ret = 0;
2323
2324         /* Only allowed in manual mode */
2325         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2326                 return -EINVAL;
2327
2328         switch (type) {
2329         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2330                 if (size != 2) {
2331                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2332                         return -EINVAL;
2333                 }
2334
2335                 if (input[0] == 0) {
2336                         if (input[1] < smu->gfx_default_hard_min_freq) {
2337                                 dev_warn(smu->adev->dev,
2338                                          "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2339                                          input[1], smu->gfx_default_hard_min_freq);
2340                                 return -EINVAL;
2341                         }
2342                         smu->gfx_actual_hard_min_freq = input[1];
2343                 } else if (input[0] == 1) {
2344                         if (input[1] > smu->gfx_default_soft_max_freq) {
2345                                 dev_warn(smu->adev->dev,
2346                                          "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2347                                          input[1], smu->gfx_default_soft_max_freq);
2348                                 return -EINVAL;
2349                         }
2350                         smu->gfx_actual_soft_max_freq = input[1];
2351                 } else {
2352                         return -EINVAL;
2353                 }
2354                 break;
2355         case PP_OD_RESTORE_DEFAULT_TABLE:
2356                 if (size != 0) {
2357                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2358                         return -EINVAL;
2359                 }
2360                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2361                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2362                 break;
2363         case PP_OD_COMMIT_DPM_TABLE:
2364                 if (size != 0) {
2365                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2366                         return -EINVAL;
2367                 }
2368                 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2369                         dev_err(smu->adev->dev,
2370                                 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2371                                 smu->gfx_actual_hard_min_freq,
2372                                 smu->gfx_actual_soft_max_freq);
2373                         return -EINVAL;
2374                 }
2375
2376                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2377                                                       smu->gfx_actual_hard_min_freq,
2378                                                       NULL);
2379                 if (ret) {
2380                         dev_err(smu->adev->dev, "Set hard min sclk failed!");
2381                         return ret;
2382                 }
2383
2384                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2385                                                       smu->gfx_actual_soft_max_freq,
2386                                                       NULL);
2387                 if (ret) {
2388                         dev_err(smu->adev->dev, "Set soft max sclk failed!");
2389                         return ret;
2390                 }
2391                 break;
2392         default:
2393                 return -ENOSYS;
2394         }
2395
2396         return ret;
2397 }
2398
2399 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2400 {
2401         struct smu_table_context *smu_table = &smu->smu_table;
2402
2403         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2404                                     smu_table->clocks_table, false);
2405 }
2406
2407 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2408 {
2409         struct amdgpu_device *adev = smu->adev;
2410
2411         smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2412         smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2413         smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2414 }
2415
2416 int smu_v13_0_mode1_reset(struct smu_context *smu)
2417 {
2418         int ret = 0;
2419
2420         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2421         if (!ret)
2422                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2423
2424         return ret;
2425 }
2426
2427 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2428                                      uint32_t pcie_gen_cap,
2429                                      uint32_t pcie_width_cap)
2430 {
2431         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2432         struct smu_13_0_pcie_table *pcie_table =
2433                                 &dpm_context->dpm_tables.pcie_table;
2434         int num_of_levels = pcie_table->num_of_link_levels;
2435         uint32_t smu_pcie_arg;
2436         int ret, i;
2437
2438         if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2439                 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2440                         pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2441
2442                 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2443                         pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2444
2445                 /* Force all levels to use the same settings */
2446                 for (i = 0; i < num_of_levels; i++) {
2447                         pcie_table->pcie_gen[i] = pcie_gen_cap;
2448                         pcie_table->pcie_lane[i] = pcie_width_cap;
2449                 }
2450         } else {
2451                 for (i = 0; i < num_of_levels; i++) {
2452                         if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2453                                 pcie_table->pcie_gen[i] = pcie_gen_cap;
2454                         if (pcie_table->pcie_lane[i] > pcie_width_cap)
2455                                 pcie_table->pcie_lane[i] = pcie_width_cap;
2456                 }
2457         }
2458
2459         for (i = 0; i < num_of_levels; i++) {
2460                 smu_pcie_arg = i << 16;
2461                 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2462                 smu_pcie_arg |= pcie_table->pcie_lane[i];
2463
2464                 ret = smu_cmn_send_smc_msg_with_param(smu,
2465                                                       SMU_MSG_OverridePcieParameters,
2466                                                       smu_pcie_arg,
2467                                                       NULL);
2468                 if (ret)
2469                         return ret;
2470         }
2471
2472         return 0;
2473 }