drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_13_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v13_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_13_0_2_offset.h"
  43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_13_0_2_offset.h"
  45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
  47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
  61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
  62
  63 #define mmMP1_SMN_C2PMSG_66                                                                            0x0282
  64 #define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
  65
  66 #define mmMP1_SMN_C2PMSG_82                                                                            0x0292
  67 #define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
  68
  69 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
  70 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
  71
  72 #define SMU13_VOLTAGE_SCALE 4
  73
  74 #define LINK_WIDTH_MAX                          6
  75 #define LINK_SPEED_MAX                          3
  76
  77 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  78 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  80 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  81 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  83
  84 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  85 static const int link_speed[] = {25, 50, 80, 160};
  86
  87 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
  88                                                uint32_t pptable_id);
  89
  90 int smu_v13_0_init_microcode(struct smu_context *smu)
  91 {
  92         struct amdgpu_device *adev = smu->adev;
  93         const char *chip_name;
  94         char fw_name[30];
  95         char ucode_prefix[30];
  96         int err = 0;
  97         const struct smc_firmware_header_v1_0 *hdr;
  98         const struct common_firmware_header *header;
  99         struct amdgpu_firmware_info *ucode = NULL;
 100
 101         /* doesn't need to load smu firmware in IOV mode */
 102         if (amdgpu_sriov_vf(adev))
 103                 return 0;
 104
 105         switch (adev->ip_versions[MP1_HWIP][0]) {
 106         case IP_VERSION(13, 0, 2):
 107                 chip_name = "aldebaran_smc";
 108                 break;
 109         default:
 110                 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
 111                 chip_name = ucode_prefix;
 112         }
 113
 114         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
 115
 116         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 117         if (err)
 118                 goto out;
 119         err = amdgpu_ucode_validate(adev->pm.fw);
 120         if (err)
 121                 goto out;
 122
 123         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 124         amdgpu_ucode_print_smc_hdr(&hdr->header);
 125         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 126
 127         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 128                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 129                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 130                 ucode->fw = adev->pm.fw;
 131                 header = (const struct common_firmware_header *)ucode->fw->data;
 132                 adev->firmware.fw_size +=
 133                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 134         }
 135
 136 out:
 137         if (err) {
 138                 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
 139                           fw_name);
 140                 release_firmware(adev->pm.fw);
 141                 adev->pm.fw = NULL;
 142         }
 143         return err;
 144 }
 145
 146 void smu_v13_0_fini_microcode(struct smu_context *smu)
 147 {
 148         struct amdgpu_device *adev = smu->adev;
 149
 150         release_firmware(adev->pm.fw);
 151         adev->pm.fw = NULL;
 152         adev->pm.fw_version = 0;
 153 }
 154
 155 int smu_v13_0_load_microcode(struct smu_context *smu)
 156 {
 157 #if 0
 158         struct amdgpu_device *adev = smu->adev;
 159         const uint32_t *src;
 160         const struct smc_firmware_header_v1_0 *hdr;
 161         uint32_t addr_start = MP1_SRAM;
 162         uint32_t i;
 163         uint32_t smc_fw_size;
 164         uint32_t mp1_fw_flags;
 165
 166         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 167         src = (const uint32_t *)(adev->pm.fw->data +
 168                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 169         smc_fw_size = hdr->header.ucode_size_bytes;
 170
 171         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 172                 WREG32_PCIE(addr_start, src[i]);
 173                 addr_start += 4;
 174         }
 175
 176         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 177                     1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 178         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 179                     1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 180
 181         for (i = 0; i < adev->usec_timeout; i++) {
 182                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 183                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 184                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 185                     MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 186                         break;
 187                 udelay(1);
 188         }
 189
 190         if (i == adev->usec_timeout)
 191                 return -ETIME;
 192 #endif
 193
 194         return 0;
 195 }
 196
 197 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
 198 {
 199         struct amdgpu_device *adev = smu->adev;
 200         struct amdgpu_firmware_info *ucode = NULL;
 201         uint32_t size = 0, pptable_id = 0;
 202         int ret = 0;
 203         void *table;
 204
 205         /* doesn't need to load smu firmware in IOV mode */
 206         if (amdgpu_sriov_vf(adev))
 207                 return 0;
 208
 209         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 210                 return 0;
 211
 212         if (!adev->scpm_enabled)
 213                 return 0;
 214
 215         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7))
 216                 return 0;
 217
 218         /* override pptable_id from driver parameter */
 219         if (amdgpu_smu_pptable_id >= 0) {
 220                 pptable_id = amdgpu_smu_pptable_id;
 221                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 222         } else {
 223                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 224
 225                 /*
 226                  * Temporary solution for SMU V13.0.0 with SCPM enabled:
 227                  *   - use 36831 signed pptable when pp_table_id is 3683
 228                  *   - use 37151 signed pptable when pp_table_id is 3715
 229                  *   - use 36641 signed pptable when pp_table_id is 3664 or 0
 230                  * TODO: drop these when the pptable carried in vbios is ready.
 231                  */
 232                 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
 233                         switch (pptable_id) {
 234                         case 0:
 235                         case 3664:
 236                                 pptable_id = 36641;
 237                                 break;
 238                         case 3683:
 239                                 pptable_id = 36831;
 240                                 break;
 241                         case 3715:
 242                                 pptable_id = 37151;
 243                                 break;
 244                         default:
 245                                 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
 246                                 return -EINVAL;
 247                         }
 248                 }
 249         }
 250
 251         /* "pptable_id == 0" means vbios carries the pptable. */
 252         if (!pptable_id)
 253                 return 0;
 254
 255         ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 256         if (ret)
 257                 return ret;
 258
 259         smu->pptable_firmware.data = table;
 260         smu->pptable_firmware.size = size;
 261
 262         ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
 263         ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
 264         ucode->fw = &smu->pptable_firmware;
 265         adev->firmware.fw_size +=
 266                 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
 267
 268         return 0;
 269 }
 270
 271 int smu_v13_0_check_fw_status(struct smu_context *smu)
 272 {
 273         struct amdgpu_device *adev = smu->adev;
 274         uint32_t mp1_fw_flags;
 275
 276         switch (adev->ip_versions[MP1_HWIP][0]) {
 277         case IP_VERSION(13, 0, 4):
 278                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 279                                            (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
 280                 break;
 281         default:
 282                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 283                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 284                 break;
 285         }
 286
 287         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 288             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 289                 return 0;
 290
 291         return -EIO;
 292 }
 293
 294 int smu_v13_0_check_fw_version(struct smu_context *smu)
 295 {
 296         struct amdgpu_device *adev = smu->adev;
 297         uint32_t if_version = 0xff, smu_version = 0xff;
 298         uint8_t smu_program, smu_major, smu_minor, smu_debug;
 299         int ret = 0;
 300
 301         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 302         if (ret)
 303                 return ret;
 304
 305         smu_program = (smu_version >> 24) & 0xff;
 306         smu_major = (smu_version >> 16) & 0xff;
 307         smu_minor = (smu_version >> 8) & 0xff;
 308         smu_debug = (smu_version >> 0) & 0xff;
 309         if (smu->is_apu)
 310                 adev->pm.fw_version = smu_version;
 311
 312         switch (adev->ip_versions[MP1_HWIP][0]) {
 313         case IP_VERSION(13, 0, 2):
 314                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
 315                 break;
 316         case IP_VERSION(13, 0, 0):
 317                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0;
 318                 break;
 319         case IP_VERSION(13, 0, 7):
 320                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
 321                 break;
 322         case IP_VERSION(13, 0, 1):
 323         case IP_VERSION(13, 0, 3):
 324         case IP_VERSION(13, 0, 8):
 325                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
 326                 break;
 327         case IP_VERSION(13, 0, 4):
 328                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
 329                 break;
 330         case IP_VERSION(13, 0, 5):
 331                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
 332                 break;
 333         default:
 334                 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
 335                         adev->ip_versions[MP1_HWIP][0]);
 336                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
 337                 break;
 338         }
 339
 340         /* only for dGPU w/ SMU13*/
 341         if (adev->pm.fw)
 342                 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
 343                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 344
 345         /*
 346          * 1. if_version mismatch is not critical as our fw is designed
 347          * to be backward compatible.
 348          * 2. New fw usually brings some optimizations. But that's visible
 349          * only on the paired driver.
 350          * Considering above, we just leave user a warning message instead
 351          * of halt driver loading.
 352          */
 353         if (if_version != smu->smc_driver_if_version) {
 354                 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 355                          "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
 356                          smu->smc_driver_if_version, if_version,
 357                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 358                 dev_warn(adev->dev, "SMU driver if version not matched\n");
 359         }
 360
 361         return ret;
 362 }
 363
 364 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 365 {
 366         struct amdgpu_device *adev = smu->adev;
 367         uint32_t ppt_offset_bytes;
 368         const struct smc_firmware_header_v2_0 *v2;
 369
 370         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 371
 372         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 373         *size = le32_to_cpu(v2->ppt_size_bytes);
 374         *table = (uint8_t *)v2 + ppt_offset_bytes;
 375
 376         return 0;
 377 }
 378
 379 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 380                                       uint32_t *size, uint32_t pptable_id)
 381 {
 382         struct amdgpu_device *adev = smu->adev;
 383         const struct smc_firmware_header_v2_1 *v2_1;
 384         struct smc_soft_pptable_entry *entries;
 385         uint32_t pptable_count = 0;
 386         int i = 0;
 387
 388         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 389         entries = (struct smc_soft_pptable_entry *)
 390                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 391         pptable_count = le32_to_cpu(v2_1->pptable_count);
 392         for (i = 0; i < pptable_count; i++) {
 393                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 394                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 395                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 396                         break;
 397                 }
 398         }
 399
 400         if (i == pptable_count)
 401                 return -EINVAL;
 402
 403         return 0;
 404 }
 405
 406 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
 407 {
 408         struct amdgpu_device *adev = smu->adev;
 409         uint16_t atom_table_size;
 410         uint8_t frev, crev;
 411         int ret, index;
 412
 413         dev_info(adev->dev, "use vbios provided pptable\n");
 414         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 415                                             powerplayinfo);
 416
 417         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 418                                              (uint8_t **)table);
 419         if (ret)
 420                 return ret;
 421
 422         if (size)
 423                 *size = atom_table_size;
 424
 425         return 0;
 426 }
 427
 428 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
 429                                                uint32_t pptable_id)
 430 {
 431         const struct smc_firmware_header_v1_0 *hdr;
 432         struct amdgpu_device *adev = smu->adev;
 433         uint16_t version_major, version_minor;
 434         int ret;
 435
 436         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 437         if (!hdr)
 438                 return -EINVAL;
 439
 440         dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
 441
 442         version_major = le16_to_cpu(hdr->header.header_version_major);
 443         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 444         if (version_major != 2) {
 445                 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
 446                         version_major, version_minor);
 447                 return -EINVAL;
 448         }
 449
 450         switch (version_minor) {
 451         case 0:
 452                 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
 453                 break;
 454         case 1:
 455                 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
 456                 break;
 457         default:
 458                 ret = -EINVAL;
 459                 break;
 460         }
 461
 462         return ret;
 463 }
 464
 465 int smu_v13_0_setup_pptable(struct smu_context *smu)
 466 {
 467         struct amdgpu_device *adev = smu->adev;
 468         uint32_t size = 0, pptable_id = 0;
 469         void *table;
 470         int ret = 0;
 471
 472         /* override pptable_id from driver parameter */
 473         if (amdgpu_smu_pptable_id >= 0) {
 474                 pptable_id = amdgpu_smu_pptable_id;
 475                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 476         } else {
 477                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 478
 479                 /*
 480                  * Temporary solution for SMU V13.0.0 with SCPM disabled:
 481                  *   - use 3664, 3683 or 3715 on request
 482                  *   - use 3664 when pptable_id is 0
 483                  * TODO: drop these when the pptable carried in vbios is ready.
 484                  */
 485                 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
 486                         switch (pptable_id) {
 487                         case 0:
 488                                 pptable_id = 3664;
 489                                 break;
 490                         case 3664:
 491                         case 3683:
 492                         case 3715:
 493                                 break;
 494                         default:
 495                                 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
 496                                 return -EINVAL;
 497                         }
 498                 }
 499         }
 500
 501         /* force using vbios pptable in sriov mode */
 502         if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
 503                 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
 504         else
 505                 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 506
 507         if (ret)
 508                 return ret;
 509
 510         if (!smu->smu_table.power_play_table)
 511                 smu->smu_table.power_play_table = table;
 512         if (!smu->smu_table.power_play_table_size)
 513                 smu->smu_table.power_play_table_size = size;
 514
 515         return 0;
 516 }
 517
 518 int smu_v13_0_init_smc_tables(struct smu_context *smu)
 519 {
 520         struct smu_table_context *smu_table = &smu->smu_table;
 521         struct smu_table *tables = smu_table->tables;
 522         int ret = 0;
 523
 524         smu_table->driver_pptable =
 525                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 526         if (!smu_table->driver_pptable) {
 527                 ret = -ENOMEM;
 528                 goto err0_out;
 529         }
 530
 531         smu_table->max_sustainable_clocks =
 532                 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
 533         if (!smu_table->max_sustainable_clocks) {
 534                 ret = -ENOMEM;
 535                 goto err1_out;
 536         }
 537
 538         /* Aldebaran does not support OVERDRIVE */
 539         if (tables[SMU_TABLE_OVERDRIVE].size) {
 540                 smu_table->overdrive_table =
 541                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 542                 if (!smu_table->overdrive_table) {
 543                         ret = -ENOMEM;
 544                         goto err2_out;
 545                 }
 546
 547                 smu_table->boot_overdrive_table =
 548                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 549                 if (!smu_table->boot_overdrive_table) {
 550                         ret = -ENOMEM;
 551                         goto err3_out;
 552                 }
 553         }
 554
 555         smu_table->combo_pptable =
 556                 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
 557         if (!smu_table->combo_pptable) {
 558                 ret = -ENOMEM;
 559                 goto err4_out;
 560         }
 561
 562         return 0;
 563
 564 err4_out:
 565         kfree(smu_table->boot_overdrive_table);
 566 err3_out:
 567         kfree(smu_table->overdrive_table);
 568 err2_out:
 569         kfree(smu_table->max_sustainable_clocks);
 570 err1_out:
 571         kfree(smu_table->driver_pptable);
 572 err0_out:
 573         return ret;
 574 }
 575
 576 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 577 {
 578         struct smu_table_context *smu_table = &smu->smu_table;
 579         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 580
 581         kfree(smu_table->gpu_metrics_table);
 582         kfree(smu_table->combo_pptable);
 583         kfree(smu_table->boot_overdrive_table);
 584         kfree(smu_table->overdrive_table);
 585         kfree(smu_table->max_sustainable_clocks);
 586         kfree(smu_table->driver_pptable);
 587         smu_table->gpu_metrics_table = NULL;
 588         smu_table->combo_pptable = NULL;
 589         smu_table->boot_overdrive_table = NULL;
 590         smu_table->overdrive_table = NULL;
 591         smu_table->max_sustainable_clocks = NULL;
 592         smu_table->driver_pptable = NULL;
 593         kfree(smu_table->hardcode_pptable);
 594         smu_table->hardcode_pptable = NULL;
 595
 596         kfree(smu_table->ecc_table);
 597         kfree(smu_table->metrics_table);
 598         kfree(smu_table->watermarks_table);
 599         smu_table->ecc_table = NULL;
 600         smu_table->metrics_table = NULL;
 601         smu_table->watermarks_table = NULL;
 602         smu_table->metrics_time = 0;
 603
 604         kfree(smu_dpm->dpm_context);
 605         kfree(smu_dpm->golden_dpm_context);
 606         kfree(smu_dpm->dpm_current_power_state);
 607         kfree(smu_dpm->dpm_request_power_state);
 608         smu_dpm->dpm_context = NULL;
 609         smu_dpm->golden_dpm_context = NULL;
 610         smu_dpm->dpm_context_size = 0;
 611         smu_dpm->dpm_current_power_state = NULL;
 612         smu_dpm->dpm_request_power_state = NULL;
 613
 614         return 0;
 615 }
 616
 617 int smu_v13_0_init_power(struct smu_context *smu)
 618 {
 619         struct smu_power_context *smu_power = &smu->smu_power;
 620
 621         if (smu_power->power_context || smu_power->power_context_size != 0)
 622                 return -EINVAL;
 623
 624         smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 625                                            GFP_KERNEL);
 626         if (!smu_power->power_context)
 627                 return -ENOMEM;
 628         smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
 629
 630         return 0;
 631 }
 632
 633 int smu_v13_0_fini_power(struct smu_context *smu)
 634 {
 635         struct smu_power_context *smu_power = &smu->smu_power;
 636
 637         if (!smu_power->power_context || smu_power->power_context_size == 0)
 638                 return -EINVAL;
 639
 640         kfree(smu_power->power_context);
 641         smu_power->power_context = NULL;
 642         smu_power->power_context_size = 0;
 643
 644         return 0;
 645 }
 646
 647 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 648 {
 649         int ret, index;
 650         uint16_t size;
 651         uint8_t frev, crev;
 652         struct atom_common_table_header *header;
 653         struct atom_firmware_info_v3_4 *v_3_4;
 654         struct atom_firmware_info_v3_3 *v_3_3;
 655         struct atom_firmware_info_v3_1 *v_3_1;
 656         struct atom_smu_info_v3_6 *smu_info_v3_6;
 657         struct atom_smu_info_v4_0 *smu_info_v4_0;
 658
 659         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 660                                             firmwareinfo);
 661
 662         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 663                                              (uint8_t **)&header);
 664         if (ret)
 665                 return ret;
 666
 667         if (header->format_revision != 3) {
 668                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 669                 return -EINVAL;
 670         }
 671
 672         switch (header->content_revision) {
 673         case 0:
 674         case 1:
 675         case 2:
 676                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 677                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 678                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 679                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 680                 smu->smu_table.boot_values.socclk = 0;
 681                 smu->smu_table.boot_values.dcefclk = 0;
 682                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 683                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 684                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 685                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 686                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 687                 smu->smu_table.boot_values.pp_table_id = 0;
 688                 break;
 689         case 3:
 690                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 691                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 692                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 693                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 694                 smu->smu_table.boot_values.socclk = 0;
 695                 smu->smu_table.boot_values.dcefclk = 0;
 696                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 697                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 698                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 699                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 700                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 701                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 702                 break;
 703         case 4:
 704         default:
 705                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 706                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 707                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 708                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 709                 smu->smu_table.boot_values.socclk = 0;
 710                 smu->smu_table.boot_values.dcefclk = 0;
 711                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 712                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 713                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 714                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 715                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 716                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 717                 break;
 718         }
 719
 720         smu->smu_table.boot_values.format_revision = header->format_revision;
 721         smu->smu_table.boot_values.content_revision = header->content_revision;
 722
 723         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 724                                             smu_info);
 725         if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 726                                             (uint8_t **)&header)) {
 727
 728                 if ((frev == 3) && (crev == 6)) {
 729                         smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
 730
 731                         smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
 732                         smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
 733                         smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
 734                         smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
 735                 } else if ((frev == 3) && (crev == 1)) {
 736                         return 0;
 737                 } else if ((frev == 4) && (crev == 0)) {
 738                         smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
 739
 740                         smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
 741                         smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
 742                         smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
 743                         smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
 744                         smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
 745                 } else {
 746                         dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
 747                                                 (uint32_t)frev, (uint32_t)crev);
 748                 }
 749         }
 750
 751         return 0;
 752 }
 753
 754
 755 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
 756 {
 757         struct smu_table_context *smu_table = &smu->smu_table;
 758         struct smu_table *memory_pool = &smu_table->memory_pool;
 759         int ret = 0;
 760         uint64_t address;
 761         uint32_t address_low, address_high;
 762
 763         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 764                 return ret;
 765
 766         address = memory_pool->mc_address;
 767         address_high = (uint32_t)upper_32_bits(address);
 768         address_low  = (uint32_t)lower_32_bits(address);
 769
 770         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 771                                               address_high, NULL);
 772         if (ret)
 773                 return ret;
 774         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 775                                               address_low, NULL);
 776         if (ret)
 777                 return ret;
 778         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 779                                               (uint32_t)memory_pool->size, NULL);
 780         if (ret)
 781                 return ret;
 782
 783         return ret;
 784 }
 785
 786 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 787 {
 788         int ret;
 789
 790         ret = smu_cmn_send_smc_msg_with_param(smu,
 791                                               SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 792         if (ret)
 793                 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
 794
 795         return ret;
 796 }
 797
 798 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
 799 {
 800         struct smu_table *driver_table = &smu->smu_table.driver_table;
 801         int ret = 0;
 802
 803         if (driver_table->mc_address) {
 804                 ret = smu_cmn_send_smc_msg_with_param(smu,
 805                                                       SMU_MSG_SetDriverDramAddrHigh,
 806                                                       upper_32_bits(driver_table->mc_address),
 807                                                       NULL);
 808                 if (!ret)
 809                         ret = smu_cmn_send_smc_msg_with_param(smu,
 810                                                               SMU_MSG_SetDriverDramAddrLow,
 811                                                               lower_32_bits(driver_table->mc_address),
 812                                                               NULL);
 813         }
 814
 815         return ret;
 816 }
 817
 818 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
 819 {
 820         int ret = 0;
 821         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 822
 823         if (tool_table->mc_address) {
 824                 ret = smu_cmn_send_smc_msg_with_param(smu,
 825                                                       SMU_MSG_SetToolsDramAddrHigh,
 826                                                       upper_32_bits(tool_table->mc_address),
 827                                                       NULL);
 828                 if (!ret)
 829                         ret = smu_cmn_send_smc_msg_with_param(smu,
 830                                                               SMU_MSG_SetToolsDramAddrLow,
 831                                                               lower_32_bits(tool_table->mc_address),
 832                                                               NULL);
 833         }
 834
 835         return ret;
 836 }
 837
 838 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
 839 {
 840         int ret = 0;
 841
 842         if (!smu->pm_enabled)
 843                 return ret;
 844
 845         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 846
 847         return ret;
 848 }
 849
 850 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
 851 {
 852         struct smu_feature *feature = &smu->smu_feature;
 853         int ret = 0;
 854         uint32_t feature_mask[2];
 855
 856         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
 857             feature->feature_num < 64)
 858                 return -EINVAL;
 859
 860         bitmap_to_arr32(feature_mask, feature->allowed, 64);
 861
 862         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 863                                               feature_mask[1], NULL);
 864         if (ret)
 865                 return ret;
 866
 867         return smu_cmn_send_smc_msg_with_param(smu,
 868                                                SMU_MSG_SetAllowedFeaturesMaskLow,
 869                                                feature_mask[0],
 870                                                NULL);
 871 }
 872
 873 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
 874 {
 875         int ret = 0;
 876         struct amdgpu_device *adev = smu->adev;
 877
 878         switch (adev->ip_versions[MP1_HWIP][0]) {
 879         case IP_VERSION(13, 0, 0):
 880         case IP_VERSION(13, 0, 1):
 881         case IP_VERSION(13, 0, 3):
 882         case IP_VERSION(13, 0, 4):
 883         case IP_VERSION(13, 0, 5):
 884         case IP_VERSION(13, 0, 7):
 885         case IP_VERSION(13, 0, 8):
 886                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 887                         return 0;
 888                 if (enable)
 889                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 890                 else
 891                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 892                 break;
 893         default:
 894                 break;
 895         }
 896
 897         return ret;
 898 }
 899
 900 int smu_v13_0_system_features_control(struct smu_context *smu,
 901                                       bool en)
 902 {
 903         return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 904                                           SMU_MSG_DisableAllSmuFeatures), NULL);
 905 }
 906
 907 int smu_v13_0_notify_display_change(struct smu_context *smu)
 908 {
 909         int ret = 0;
 910
 911         if (!smu->pm_enabled)
 912                 return ret;
 913
 914         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 915             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 916                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 917
 918         return ret;
 919 }
 920
 921         static int
 922 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 923                                     enum smu_clk_type clock_select)
 924 {
 925         int ret = 0;
 926         int clk_id;
 927
 928         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 929             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 930                 return 0;
 931
 932         clk_id = smu_cmn_to_asic_specific_index(smu,
 933                                                 CMN2ASIC_MAPPING_CLK,
 934                                                 clock_select);
 935         if (clk_id < 0)
 936                 return -EINVAL;
 937
 938         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 939                                               clk_id << 16, clock);
 940         if (ret) {
 941                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 942                 return ret;
 943         }
 944
 945         if (*clock != 0)
 946                 return 0;
 947
 948         /* if DC limit is zero, return AC limit */
 949         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 950                                               clk_id << 16, clock);
 951         if (ret) {
 952                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 953                 return ret;
 954         }
 955
 956         return 0;
 957 }
 958
 959 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
 960 {
 961         struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
 962                 smu->smu_table.max_sustainable_clocks;
 963         int ret = 0;
 964
 965         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 966         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 967         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 968         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 969         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 970         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 971
 972         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 973                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 974                                                           &(max_sustainable_clocks->uclock),
 975                                                           SMU_UCLK);
 976                 if (ret) {
 977                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 978                                 __func__);
 979                         return ret;
 980                 }
 981         }
 982
 983         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 984                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 985                                                           &(max_sustainable_clocks->soc_clock),
 986                                                           SMU_SOCCLK);
 987                 if (ret) {
 988                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 989                                 __func__);
 990                         return ret;
 991                 }
 992         }
 993
 994         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 995                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 996                                                           &(max_sustainable_clocks->dcef_clock),
 997                                                           SMU_DCEFCLK);
 998                 if (ret) {
 999                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
1000                                 __func__);
1001                         return ret;
1002                 }
1003
1004                 ret = smu_v13_0_get_max_sustainable_clock(smu,
1005                                                           &(max_sustainable_clocks->display_clock),
1006                                                           SMU_DISPCLK);
1007                 if (ret) {
1008                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
1009                                 __func__);
1010                         return ret;
1011                 }
1012                 ret = smu_v13_0_get_max_sustainable_clock(smu,
1013                                                           &(max_sustainable_clocks->phy_clock),
1014                                                           SMU_PHYCLK);
1015                 if (ret) {
1016                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
1017                                 __func__);
1018                         return ret;
1019                 }
1020                 ret = smu_v13_0_get_max_sustainable_clock(smu,
1021                                                           &(max_sustainable_clocks->pixel_clock),
1022                                                           SMU_PIXCLK);
1023                 if (ret) {
1024                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
1025                                 __func__);
1026                         return ret;
1027                 }
1028         }
1029
1030         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1031                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1032
1033         return 0;
1034 }
1035
1036 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
1037                                       uint32_t *power_limit)
1038 {
1039         int power_src;
1040         int ret = 0;
1041
1042         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1043                 return -EINVAL;
1044
1045         power_src = smu_cmn_to_asic_specific_index(smu,
1046                                                    CMN2ASIC_MAPPING_PWR,
1047                                                    smu->adev->pm.ac_power ?
1048                                                    SMU_POWER_SOURCE_AC :
1049                                                    SMU_POWER_SOURCE_DC);
1050         if (power_src < 0)
1051                 return -EINVAL;
1052
1053         ret = smu_cmn_send_smc_msg_with_param(smu,
1054                                               SMU_MSG_GetPptLimit,
1055                                               power_src << 16,
1056                                               power_limit);
1057         if (ret)
1058                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1059
1060         return ret;
1061 }
1062
1063 int smu_v13_0_set_power_limit(struct smu_context *smu,
1064                               enum smu_ppt_limit_type limit_type,
1065                               uint32_t limit)
1066 {
1067         int ret = 0;
1068
1069         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1070                 return -EINVAL;
1071
1072         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1073                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1074                 return -EOPNOTSUPP;
1075         }
1076
1077         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1078         if (ret) {
1079                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1080                 return ret;
1081         }
1082
1083         smu->current_power_limit = limit;
1084
1085         return 0;
1086 }
1087
1088 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1089 {
1090         return smu_cmn_send_smc_msg(smu,
1091                                     SMU_MSG_AllowIHHostInterrupt,
1092                                     NULL);
1093 }
1094
1095 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1096 {
1097         int ret = 0;
1098
1099         if (smu->dc_controlled_by_gpio &&
1100             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1101                 ret = smu_v13_0_allow_ih_interrupt(smu);
1102
1103         return ret;
1104 }
1105
1106 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1107 {
1108         int ret = 0;
1109
1110         ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1111         if (ret)
1112                 return ret;
1113
1114         return smu_v13_0_process_pending_interrupt(smu);
1115 }
1116
1117 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1118 {
1119         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1120 }
1121
1122 static uint16_t convert_to_vddc(uint8_t vid)
1123 {
1124         return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1125 }
1126
1127 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1128 {
1129         struct amdgpu_device *adev = smu->adev;
1130         uint32_t vdd = 0, val_vid = 0;
1131
1132         if (!value)
1133                 return -EINVAL;
1134         val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1135                    SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1136                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1137
1138         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1139
1140         *value = vdd;
1141
1142         return 0;
1143
1144 }
1145
1146 int
1147 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1148                                         struct pp_display_clock_request
1149                                         *clock_req)
1150 {
1151         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1152         int ret = 0;
1153         enum smu_clk_type clk_select = 0;
1154         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1155
1156         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1157             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1158                 switch (clk_type) {
1159                 case amd_pp_dcef_clock:
1160                         clk_select = SMU_DCEFCLK;
1161                         break;
1162                 case amd_pp_disp_clock:
1163                         clk_select = SMU_DISPCLK;
1164                         break;
1165                 case amd_pp_pixel_clock:
1166                         clk_select = SMU_PIXCLK;
1167                         break;
1168                 case amd_pp_phy_clock:
1169                         clk_select = SMU_PHYCLK;
1170                         break;
1171                 case amd_pp_mem_clock:
1172                         clk_select = SMU_UCLK;
1173                         break;
1174                 default:
1175                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1176                         ret = -EINVAL;
1177                         break;
1178                 }
1179
1180                 if (ret)
1181                         goto failed;
1182
1183                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1184                         return 0;
1185
1186                 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1187
1188                 if(clk_select == SMU_UCLK)
1189                         smu->hard_min_uclk_req_from_dal = clk_freq;
1190         }
1191
1192 failed:
1193         return ret;
1194 }
1195
1196 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1197 {
1198         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1199                 return AMD_FAN_CTRL_MANUAL;
1200         else
1201                 return AMD_FAN_CTRL_AUTO;
1202 }
1203
1204         static int
1205 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1206 {
1207         int ret = 0;
1208
1209         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1210                 return 0;
1211
1212         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1213         if (ret)
1214                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1215                         __func__, (auto_fan_control ? "Start" : "Stop"));
1216
1217         return ret;
1218 }
1219
1220         static int
1221 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1222 {
1223         struct amdgpu_device *adev = smu->adev;
1224
1225         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1226                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1227                                    CG_FDO_CTRL2, TMIN, 0));
1228         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1229                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1230                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1231
1232         return 0;
1233 }
1234
1235 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1236                                 uint32_t speed)
1237 {
1238         struct amdgpu_device *adev = smu->adev;
1239         uint32_t duty100, duty;
1240         uint64_t tmp64;
1241
1242         speed = MIN(speed, 255);
1243
1244         if (smu_v13_0_auto_fan_control(smu, 0))
1245                 return -EINVAL;
1246
1247         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1248                                 CG_FDO_CTRL1, FMAX_DUTY100);
1249         if (!duty100)
1250                 return -EINVAL;
1251
1252         tmp64 = (uint64_t)speed * duty100;
1253         do_div(tmp64, 255);
1254         duty = (uint32_t)tmp64;
1255
1256         WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1257                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1258                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1259
1260         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1261 }
1262
1263         int
1264 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1265                                uint32_t mode)
1266 {
1267         int ret = 0;
1268
1269         switch (mode) {
1270         case AMD_FAN_CTRL_NONE:
1271                 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1272                 break;
1273         case AMD_FAN_CTRL_MANUAL:
1274                 ret = smu_v13_0_auto_fan_control(smu, 0);
1275                 break;
1276         case AMD_FAN_CTRL_AUTO:
1277                 ret = smu_v13_0_auto_fan_control(smu, 1);
1278                 break;
1279         default:
1280                 break;
1281         }
1282
1283         if (ret) {
1284                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1285                 return -EINVAL;
1286         }
1287
1288         return ret;
1289 }
1290
1291 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1292                                 uint32_t speed)
1293 {
1294         struct amdgpu_device *adev = smu->adev;
1295         uint32_t tach_period, crystal_clock_freq;
1296         int ret;
1297
1298         if (!speed)
1299                 return -EINVAL;
1300
1301         ret = smu_v13_0_auto_fan_control(smu, 0);
1302         if (ret)
1303                 return ret;
1304
1305         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1306         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1307         WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1308                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1309                                    CG_TACH_CTRL, TARGET_PERIOD,
1310                                    tach_period));
1311
1312         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1313 }
1314
1315 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1316                               uint32_t pstate)
1317 {
1318         int ret = 0;
1319         ret = smu_cmn_send_smc_msg_with_param(smu,
1320                                               SMU_MSG_SetXgmiMode,
1321                                               pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1322                                               NULL);
1323         return ret;
1324 }
1325
1326 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1327                                    struct amdgpu_irq_src *source,
1328                                    unsigned tyep,
1329                                    enum amdgpu_interrupt_state state)
1330 {
1331         struct smu_context *smu = adev->powerplay.pp_handle;
1332         uint32_t low, high;
1333         uint32_t val = 0;
1334
1335         switch (state) {
1336         case AMDGPU_IRQ_STATE_DISABLE:
1337                 /* For THM irqs */
1338                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1339                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1340                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1341                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1342
1343                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1344
1345                 /* For MP1 SW irqs */
1346                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1347                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1348                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1349
1350                 break;
1351         case AMDGPU_IRQ_STATE_ENABLE:
1352                 /* For THM irqs */
1353                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1354                           smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1355                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1356                            smu->thermal_range.software_shutdown_temp);
1357
1358                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1359                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1360                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1361                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1362                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1363                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1364                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1365                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1366                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1367
1368                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1369                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1370                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1371                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1372
1373                 /* For MP1 SW irqs */
1374                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1375                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1376                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1377                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1378
1379                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1380                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1381                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1382
1383                 break;
1384         default:
1385                 break;
1386         }
1387
1388         return 0;
1389 }
1390
1391 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1392 {
1393         return smu_cmn_send_smc_msg(smu,
1394                                     SMU_MSG_ReenableAcDcInterrupt,
1395                                     NULL);
1396 }
1397
1398 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1399 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1400 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1401
1402 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1403                                  struct amdgpu_irq_src *source,
1404                                  struct amdgpu_iv_entry *entry)
1405 {
1406         struct smu_context *smu = adev->powerplay.pp_handle;
1407         uint32_t client_id = entry->client_id;
1408         uint32_t src_id = entry->src_id;
1409         /*
1410          * ctxid is used to distinguish different
1411          * events for SMCToHost interrupt.
1412          */
1413         uint32_t ctxid = entry->src_data[0];
1414         uint32_t data;
1415
1416         if (client_id == SOC15_IH_CLIENTID_THM) {
1417                 switch (src_id) {
1418                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1419                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1420                         /*
1421                          * SW CTF just occurred.
1422                          * Try to do a graceful shutdown to prevent further damage.
1423                          */
1424                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1425                         orderly_poweroff(true);
1426                         break;
1427                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1428                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1429                         break;
1430                 default:
1431                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1432                                   src_id);
1433                         break;
1434                 }
1435         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1436                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1437                 /*
1438                  * HW CTF just occurred. Shutdown to prevent further damage.
1439                  */
1440                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1441                 orderly_poweroff(true);
1442         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1443                 if (src_id == 0xfe) {
1444                         /* ACK SMUToHost interrupt */
1445                         data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1446                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1447                         WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1448
1449                         switch (ctxid) {
1450                         case 0x3:
1451                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1452                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1453                                 break;
1454                         case 0x4:
1455                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1456                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1457                                 break;
1458                         case 0x7:
1459                                 /*
1460                                  * Increment the throttle interrupt counter
1461                                  */
1462                                 atomic64_inc(&smu->throttle_int_counter);
1463
1464                                 if (!atomic_read(&adev->throttling_logging_enabled))
1465                                         return 0;
1466
1467                                 if (__ratelimit(&adev->throttling_logging_rs))
1468                                         schedule_work(&smu->throttling_logging_work);
1469
1470                                 break;
1471                         }
1472                 }
1473         }
1474
1475         return 0;
1476 }
1477
1478 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1479 {
1480         .set = smu_v13_0_set_irq_state,
1481         .process = smu_v13_0_irq_process,
1482 };
1483
1484 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1485 {
1486         struct amdgpu_device *adev = smu->adev;
1487         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1488         int ret = 0;
1489
1490         irq_src->num_types = 1;
1491         irq_src->funcs = &smu_v13_0_irq_funcs;
1492
1493         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1494                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1495                                 irq_src);
1496         if (ret)
1497                 return ret;
1498
1499         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1500                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1501                                 irq_src);
1502         if (ret)
1503                 return ret;
1504
1505         /* Register CTF(GPIO_19) interrupt */
1506         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1507                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1508                                 irq_src);
1509         if (ret)
1510                 return ret;
1511
1512         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1513                                 0xfe,
1514                                 irq_src);
1515         if (ret)
1516                 return ret;
1517
1518         return ret;
1519 }
1520
1521 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1522                                                struct pp_smu_nv_clock_table *max_clocks)
1523 {
1524         struct smu_table_context *table_context = &smu->smu_table;
1525         struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1526
1527         if (!max_clocks || !table_context->max_sustainable_clocks)
1528                 return -EINVAL;
1529
1530         sustainable_clocks = table_context->max_sustainable_clocks;
1531
1532         max_clocks->dcfClockInKhz =
1533                 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1534         max_clocks->displayClockInKhz =
1535                 (unsigned int) sustainable_clocks->display_clock * 1000;
1536         max_clocks->phyClockInKhz =
1537                 (unsigned int) sustainable_clocks->phy_clock * 1000;
1538         max_clocks->pixelClockInKhz =
1539                 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1540         max_clocks->uClockInKhz =
1541                 (unsigned int) sustainable_clocks->uclock * 1000;
1542         max_clocks->socClockInKhz =
1543                 (unsigned int) sustainable_clocks->soc_clock * 1000;
1544         max_clocks->dscClockInKhz = 0;
1545         max_clocks->dppClockInKhz = 0;
1546         max_clocks->fabricClockInKhz = 0;
1547
1548         return 0;
1549 }
1550
1551 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1552 {
1553         int ret = 0;
1554
1555         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1556
1557         return ret;
1558 }
1559
1560 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1561                                              uint64_t event_arg)
1562 {
1563         int ret = 0;
1564
1565         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1566         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1567
1568         return ret;
1569 }
1570
1571 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1572                              uint64_t event_arg)
1573 {
1574         int ret = -EINVAL;
1575
1576         switch (event) {
1577         case SMU_EVENT_RESET_COMPLETE:
1578                 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1579                 break;
1580         default:
1581                 break;
1582         }
1583
1584         return ret;
1585 }
1586
1587 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1588                                     uint32_t *min, uint32_t *max)
1589 {
1590         int ret = 0, clk_id = 0;
1591         uint32_t param = 0;
1592         uint32_t clock_limit;
1593
1594         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1595                 switch (clk_type) {
1596                 case SMU_MCLK:
1597                 case SMU_UCLK:
1598                         clock_limit = smu->smu_table.boot_values.uclk;
1599                         break;
1600                 case SMU_GFXCLK:
1601                 case SMU_SCLK:
1602                         clock_limit = smu->smu_table.boot_values.gfxclk;
1603                         break;
1604                 case SMU_SOCCLK:
1605                         clock_limit = smu->smu_table.boot_values.socclk;
1606                         break;
1607                 default:
1608                         clock_limit = 0;
1609                         break;
1610                 }
1611
1612                 /* clock in Mhz unit */
1613                 if (min)
1614                         *min = clock_limit / 100;
1615                 if (max)
1616                         *max = clock_limit / 100;
1617
1618                 return 0;
1619         }
1620
1621         clk_id = smu_cmn_to_asic_specific_index(smu,
1622                                                 CMN2ASIC_MAPPING_CLK,
1623                                                 clk_type);
1624         if (clk_id < 0) {
1625                 ret = -EINVAL;
1626                 goto failed;
1627         }
1628         param = (clk_id & 0xffff) << 16;
1629
1630         if (max) {
1631                 if (smu->adev->pm.ac_power)
1632                         ret = smu_cmn_send_smc_msg_with_param(smu,
1633                                                               SMU_MSG_GetMaxDpmFreq,
1634                                                               param,
1635                                                               max);
1636                 else
1637                         ret = smu_cmn_send_smc_msg_with_param(smu,
1638                                                               SMU_MSG_GetDcModeMaxDpmFreq,
1639                                                               param,
1640                                                               max);
1641                 if (ret)
1642                         goto failed;
1643         }
1644
1645         if (min) {
1646                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1647                 if (ret)
1648                         goto failed;
1649         }
1650
1651 failed:
1652         return ret;
1653 }
1654
1655 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1656                                           enum smu_clk_type clk_type,
1657                                           uint32_t min,
1658                                           uint32_t max)
1659 {
1660         int ret = 0, clk_id = 0;
1661         uint32_t param;
1662
1663         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1664                 return 0;
1665
1666         clk_id = smu_cmn_to_asic_specific_index(smu,
1667                                                 CMN2ASIC_MAPPING_CLK,
1668                                                 clk_type);
1669         if (clk_id < 0)
1670                 return clk_id;
1671
1672         if (max > 0) {
1673                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1674                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1675                                                       param, NULL);
1676                 if (ret)
1677                         goto out;
1678         }
1679
1680         if (min > 0) {
1681                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1682                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1683                                                       param, NULL);
1684                 if (ret)
1685                         goto out;
1686         }
1687
1688 out:
1689         return ret;
1690 }
1691
1692 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1693                                           enum smu_clk_type clk_type,
1694                                           uint32_t min,
1695                                           uint32_t max)
1696 {
1697         int ret = 0, clk_id = 0;
1698         uint32_t param;
1699
1700         if (min <= 0 && max <= 0)
1701                 return -EINVAL;
1702
1703         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1704                 return 0;
1705
1706         clk_id = smu_cmn_to_asic_specific_index(smu,
1707                                                 CMN2ASIC_MAPPING_CLK,
1708                                                 clk_type);
1709         if (clk_id < 0)
1710                 return clk_id;
1711
1712         if (max > 0) {
1713                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1714                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1715                                                       param, NULL);
1716                 if (ret)
1717                         return ret;
1718         }
1719
1720         if (min > 0) {
1721                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1722                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1723                                                       param, NULL);
1724                 if (ret)
1725                         return ret;
1726         }
1727
1728         return ret;
1729 }
1730
1731 int smu_v13_0_set_performance_level(struct smu_context *smu,
1732                                     enum amd_dpm_forced_level level)
1733 {
1734         struct smu_13_0_dpm_context *dpm_context =
1735                 smu->smu_dpm.dpm_context;
1736         struct smu_13_0_dpm_table *gfx_table =
1737                 &dpm_context->dpm_tables.gfx_table;
1738         struct smu_13_0_dpm_table *mem_table =
1739                 &dpm_context->dpm_tables.uclk_table;
1740         struct smu_13_0_dpm_table *soc_table =
1741                 &dpm_context->dpm_tables.soc_table;
1742         struct smu_13_0_dpm_table *vclk_table =
1743                 &dpm_context->dpm_tables.vclk_table;
1744         struct smu_13_0_dpm_table *dclk_table =
1745                 &dpm_context->dpm_tables.dclk_table;
1746         struct smu_13_0_dpm_table *fclk_table =
1747                 &dpm_context->dpm_tables.fclk_table;
1748         struct smu_umd_pstate_table *pstate_table =
1749                 &smu->pstate_table;
1750         struct amdgpu_device *adev = smu->adev;
1751         uint32_t sclk_min = 0, sclk_max = 0;
1752         uint32_t mclk_min = 0, mclk_max = 0;
1753         uint32_t socclk_min = 0, socclk_max = 0;
1754         uint32_t vclk_min = 0, vclk_max = 0;
1755         uint32_t dclk_min = 0, dclk_max = 0;
1756         uint32_t fclk_min = 0, fclk_max = 0;
1757         int ret = 0, i;
1758
1759         switch (level) {
1760         case AMD_DPM_FORCED_LEVEL_HIGH:
1761                 sclk_min = sclk_max = gfx_table->max;
1762                 mclk_min = mclk_max = mem_table->max;
1763                 socclk_min = socclk_max = soc_table->max;
1764                 vclk_min = vclk_max = vclk_table->max;
1765                 dclk_min = dclk_max = dclk_table->max;
1766                 fclk_min = fclk_max = fclk_table->max;
1767                 break;
1768         case AMD_DPM_FORCED_LEVEL_LOW:
1769                 sclk_min = sclk_max = gfx_table->min;
1770                 mclk_min = mclk_max = mem_table->min;
1771                 socclk_min = socclk_max = soc_table->min;
1772                 vclk_min = vclk_max = vclk_table->min;
1773                 dclk_min = dclk_max = dclk_table->min;
1774                 fclk_min = fclk_max = fclk_table->min;
1775                 break;
1776         case AMD_DPM_FORCED_LEVEL_AUTO:
1777                 sclk_min = gfx_table->min;
1778                 sclk_max = gfx_table->max;
1779                 mclk_min = mem_table->min;
1780                 mclk_max = mem_table->max;
1781                 socclk_min = soc_table->min;
1782                 socclk_max = soc_table->max;
1783                 vclk_min = vclk_table->min;
1784                 vclk_max = vclk_table->max;
1785                 dclk_min = dclk_table->min;
1786                 dclk_max = dclk_table->max;
1787                 fclk_min = fclk_table->min;
1788                 fclk_max = fclk_table->max;
1789                 break;
1790         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1791                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1792                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1793                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1794                 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1795                 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1796                 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1797                 break;
1798         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1799                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1800                 break;
1801         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1802                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1803                 break;
1804         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1805                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1806                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1807                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1808                 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1809                 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1810                 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1811                 break;
1812         case AMD_DPM_FORCED_LEVEL_MANUAL:
1813         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1814                 return 0;
1815         default:
1816                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1817                 return -EINVAL;
1818         }
1819
1820         /*
1821          * Unset those settings for SMU 13.0.2. As soft limits settings
1822          * for those clock domains are not supported.
1823          */
1824         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1825                 mclk_min = mclk_max = 0;
1826                 socclk_min = socclk_max = 0;
1827                 vclk_min = vclk_max = 0;
1828                 dclk_min = dclk_max = 0;
1829                 fclk_min = fclk_max = 0;
1830         }
1831
1832         if (sclk_min && sclk_max) {
1833                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1834                                                             SMU_GFXCLK,
1835                                                             sclk_min,
1836                                                             sclk_max);
1837                 if (ret)
1838                         return ret;
1839
1840                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1841                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1842         }
1843
1844         if (mclk_min && mclk_max) {
1845                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1846                                                             SMU_MCLK,
1847                                                             mclk_min,
1848                                                             mclk_max);
1849                 if (ret)
1850                         return ret;
1851
1852                 pstate_table->uclk_pstate.curr.min = mclk_min;
1853                 pstate_table->uclk_pstate.curr.max = mclk_max;
1854         }
1855
1856         if (socclk_min && socclk_max) {
1857                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1858                                                             SMU_SOCCLK,
1859                                                             socclk_min,
1860                                                             socclk_max);
1861                 if (ret)
1862                         return ret;
1863
1864                 pstate_table->socclk_pstate.curr.min = socclk_min;
1865                 pstate_table->socclk_pstate.curr.max = socclk_max;
1866         }
1867
1868         if (vclk_min && vclk_max) {
1869                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1870                         if (adev->vcn.harvest_config & (1 << i))
1871                                 continue;
1872                         ret = smu_v13_0_set_soft_freq_limited_range(smu,
1873                                                                     i ? SMU_VCLK1 : SMU_VCLK,
1874                                                                     vclk_min,
1875                                                                     vclk_max);
1876                         if (ret)
1877                                 return ret;
1878                 }
1879                 pstate_table->vclk_pstate.curr.min = vclk_min;
1880                 pstate_table->vclk_pstate.curr.max = vclk_max;
1881         }
1882
1883         if (dclk_min && dclk_max) {
1884                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1885                         if (adev->vcn.harvest_config & (1 << i))
1886                                 continue;
1887                         ret = smu_v13_0_set_soft_freq_limited_range(smu,
1888                                                                     i ? SMU_DCLK1 : SMU_DCLK,
1889                                                                     dclk_min,
1890                                                                     dclk_max);
1891                         if (ret)
1892                                 return ret;
1893                 }
1894                 pstate_table->dclk_pstate.curr.min = dclk_min;
1895                 pstate_table->dclk_pstate.curr.max = dclk_max;
1896         }
1897
1898         if (fclk_min && fclk_max) {
1899                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1900                                                             SMU_FCLK,
1901                                                             fclk_min,
1902                                                             fclk_max);
1903                 if (ret)
1904                         return ret;
1905
1906                 pstate_table->fclk_pstate.curr.min = fclk_min;
1907                 pstate_table->fclk_pstate.curr.max = fclk_max;
1908         }
1909
1910         return ret;
1911 }
1912
1913 int smu_v13_0_set_power_source(struct smu_context *smu,
1914                                enum smu_power_src_type power_src)
1915 {
1916         int pwr_source;
1917
1918         pwr_source = smu_cmn_to_asic_specific_index(smu,
1919                                                     CMN2ASIC_MAPPING_PWR,
1920                                                     (uint32_t)power_src);
1921         if (pwr_source < 0)
1922                 return -EINVAL;
1923
1924         return smu_cmn_send_smc_msg_with_param(smu,
1925                                                SMU_MSG_NotifyPowerSource,
1926                                                pwr_source,
1927                                                NULL);
1928 }
1929
1930 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1931                                            enum smu_clk_type clk_type,
1932                                            uint16_t level,
1933                                            uint32_t *value)
1934 {
1935         int ret = 0, clk_id = 0;
1936         uint32_t param;
1937
1938         if (!value)
1939                 return -EINVAL;
1940
1941         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1942                 return 0;
1943
1944         clk_id = smu_cmn_to_asic_specific_index(smu,
1945                                                 CMN2ASIC_MAPPING_CLK,
1946                                                 clk_type);
1947         if (clk_id < 0)
1948                 return clk_id;
1949
1950         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1951
1952         ret = smu_cmn_send_smc_msg_with_param(smu,
1953                                               SMU_MSG_GetDpmFreqByIndex,
1954                                               param,
1955                                               value);
1956         if (ret)
1957                 return ret;
1958
1959         *value = *value & 0x7fffffff;
1960
1961         return ret;
1962 }
1963
1964 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1965                                          enum smu_clk_type clk_type,
1966                                          uint32_t *value)
1967 {
1968         int ret;
1969
1970         ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1971         /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1972         if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1973                 ++(*value);
1974
1975         return ret;
1976 }
1977
1978 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1979                                              enum smu_clk_type clk_type,
1980                                              bool *is_fine_grained_dpm)
1981 {
1982         int ret = 0, clk_id = 0;
1983         uint32_t param;
1984         uint32_t value;
1985
1986         if (!is_fine_grained_dpm)
1987                 return -EINVAL;
1988
1989         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1990                 return 0;
1991
1992         clk_id = smu_cmn_to_asic_specific_index(smu,
1993                                                 CMN2ASIC_MAPPING_CLK,
1994                                                 clk_type);
1995         if (clk_id < 0)
1996                 return clk_id;
1997
1998         param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1999
2000         ret = smu_cmn_send_smc_msg_with_param(smu,
2001                                               SMU_MSG_GetDpmFreqByIndex,
2002                                               param,
2003                                               &value);
2004         if (ret)
2005                 return ret;
2006
2007         /*
2008          * BIT31:  1 - Fine grained DPM, 0 - Dicrete DPM
2009          * now, we un-support it
2010          */
2011         *is_fine_grained_dpm = value & 0x80000000;
2012
2013         return 0;
2014 }
2015
2016 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
2017                                    enum smu_clk_type clk_type,
2018                                    struct smu_13_0_dpm_table *single_dpm_table)
2019 {
2020         int ret = 0;
2021         uint32_t clk;
2022         int i;
2023
2024         ret = smu_v13_0_get_dpm_level_count(smu,
2025                                             clk_type,
2026                                             &single_dpm_table->count);
2027         if (ret) {
2028                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2029                 return ret;
2030         }
2031
2032         if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
2033                 ret = smu_v13_0_get_fine_grained_status(smu,
2034                                                         clk_type,
2035                                                         &single_dpm_table->is_fine_grained);
2036                 if (ret) {
2037                         dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2038                         return ret;
2039                 }
2040         }
2041
2042         for (i = 0; i < single_dpm_table->count; i++) {
2043                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2044                                                       clk_type,
2045                                                       i,
2046                                                       &clk);
2047                 if (ret) {
2048                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2049                         return ret;
2050                 }
2051
2052                 single_dpm_table->dpm_levels[i].value = clk;
2053                 single_dpm_table->dpm_levels[i].enabled = true;
2054
2055                 if (i == 0)
2056                         single_dpm_table->min = clk;
2057                 else if (i == single_dpm_table->count - 1)
2058                         single_dpm_table->max = clk;
2059         }
2060
2061         return 0;
2062 }
2063
2064 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2065                                   enum smu_clk_type clk_type,
2066                                   uint32_t *min_value,
2067                                   uint32_t *max_value)
2068 {
2069         uint32_t level_count = 0;
2070         int ret = 0;
2071
2072         if (!min_value && !max_value)
2073                 return -EINVAL;
2074
2075         if (min_value) {
2076                 /* by default, level 0 clock value as min value */
2077                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2078                                                       clk_type,
2079                                                       0,
2080                                                       min_value);
2081                 if (ret)
2082                         return ret;
2083         }
2084
2085         if (max_value) {
2086                 ret = smu_v13_0_get_dpm_level_count(smu,
2087                                                     clk_type,
2088                                                     &level_count);
2089                 if (ret)
2090                         return ret;
2091
2092                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2093                                                       clk_type,
2094                                                       level_count - 1,
2095                                                       max_value);
2096                 if (ret)
2097                         return ret;
2098         }
2099
2100         return ret;
2101 }
2102
2103 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2104 {
2105         struct amdgpu_device *adev = smu->adev;
2106
2107         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2108                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2109                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2110 }
2111
2112 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2113 {
2114         uint32_t width_level;
2115
2116         width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2117         if (width_level > LINK_WIDTH_MAX)
2118                 width_level = 0;
2119
2120         return link_width[width_level];
2121 }
2122
2123 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2124 {
2125         struct amdgpu_device *adev = smu->adev;
2126
2127         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2128                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2129                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2130 }
2131
2132 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2133 {
2134         uint32_t speed_level;
2135
2136         speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2137         if (speed_level > LINK_SPEED_MAX)
2138                 speed_level = 0;
2139
2140         return link_speed[speed_level];
2141 }
2142
2143 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2144                              bool enable)
2145 {
2146         struct amdgpu_device *adev = smu->adev;
2147         int i, ret = 0;
2148
2149         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2150                 if (adev->vcn.harvest_config & (1 << i))
2151                         continue;
2152
2153                 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2154                                                       SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2155                                                       i << 16U, NULL);
2156                 if (ret)
2157                         return ret;
2158         }
2159
2160         return ret;
2161 }
2162
2163 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2164                               bool enable)
2165 {
2166         return smu_cmn_send_smc_msg_with_param(smu, enable ?
2167                                                SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2168                                                0, NULL);
2169 }
2170
2171 int smu_v13_0_run_btc(struct smu_context *smu)
2172 {
2173         int res;
2174
2175         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2176         if (res)
2177                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2178
2179         return res;
2180 }
2181
2182 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2183                                  bool enablement)
2184 {
2185         struct amdgpu_device *adev = smu->adev;
2186         int ret = 0;
2187
2188         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2189                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2190                 if (ret) {
2191                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2192                         return ret;
2193                 }
2194         }
2195
2196         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2197                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2198                 if (ret) {
2199                         dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2200                         return ret;
2201                 }
2202         }
2203
2204         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2205                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2206                 if (ret) {
2207                         dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2208                         return ret;
2209                 }
2210         }
2211
2212         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2213                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2214                 if (ret) {
2215                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2216                         return ret;
2217                 }
2218         }
2219
2220         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2221                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2222                 if (ret) {
2223                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2224                         return ret;
2225                 }
2226         }
2227
2228         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2229                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2230                 if (ret) {
2231                         dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2232                         return ret;
2233                 }
2234         }
2235
2236         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2237                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2238                 if (ret) {
2239                         dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2240                         return ret;
2241                 }
2242         }
2243
2244         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2245                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2246                 if (ret) {
2247                         dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2248                         return ret;
2249                 }
2250         }
2251
2252         return ret;
2253 }
2254
2255 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2256                               bool enablement)
2257 {
2258         int ret = 0;
2259
2260         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2261                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2262
2263         return ret;
2264 }
2265
2266 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2267 {
2268         struct smu_baco_context *smu_baco = &smu->smu_baco;
2269
2270         if (amdgpu_sriov_vf(smu->adev) ||
2271             !smu_baco->platform_support)
2272                 return false;
2273
2274         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2275             !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2276                 return false;
2277
2278         return true;
2279 }
2280
2281 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2282 {
2283         struct smu_baco_context *smu_baco = &smu->smu_baco;
2284
2285         return smu_baco->state;
2286 }
2287
2288 int smu_v13_0_baco_set_state(struct smu_context *smu,
2289                              enum smu_baco_state state)
2290 {
2291         struct smu_baco_context *smu_baco = &smu->smu_baco;
2292         struct amdgpu_device *adev = smu->adev;
2293         int ret = 0;
2294
2295         if (smu_v13_0_baco_get_state(smu) == state)
2296                 return 0;
2297
2298         if (state == SMU_BACO_STATE_ENTER) {
2299                 ret = smu_cmn_send_smc_msg_with_param(smu,
2300                                                       SMU_MSG_EnterBaco,
2301                                                       smu_baco->maco_support ?
2302                                                       BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2303                                                       NULL);
2304         } else {
2305                 ret = smu_cmn_send_smc_msg(smu,
2306                                            SMU_MSG_ExitBaco,
2307                                            NULL);
2308                 if (ret)
2309                         return ret;
2310
2311                 /* clear vbios scratch 6 and 7 for coming asic reinit */
2312                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2313                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2314         }
2315
2316         if (!ret)
2317                 smu_baco->state = state;
2318
2319         return ret;
2320 }
2321
2322 int smu_v13_0_baco_enter(struct smu_context *smu)
2323 {
2324         int ret = 0;
2325
2326         ret = smu_v13_0_baco_set_state(smu,
2327                                        SMU_BACO_STATE_ENTER);
2328         if (ret)
2329                 return ret;
2330
2331         msleep(10);
2332
2333         return ret;
2334 }
2335
2336 int smu_v13_0_baco_exit(struct smu_context *smu)
2337 {
2338         return smu_v13_0_baco_set_state(smu,
2339                                         SMU_BACO_STATE_EXIT);
2340 }
2341
2342 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2343 {
2344         uint16_t index;
2345
2346         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2347                                                SMU_MSG_EnableGfxImu);
2348         /* Param 1 to tell PMFW to enable GFXOFF feature */
2349         return smu_cmn_send_msg_without_waiting(smu, index, 1);
2350 }
2351
2352 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2353                                 enum PP_OD_DPM_TABLE_COMMAND type,
2354                                 long input[], uint32_t size)
2355 {
2356         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2357         int ret = 0;
2358
2359         /* Only allowed in manual mode */
2360         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2361                 return -EINVAL;
2362
2363         switch (type) {
2364         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2365                 if (size != 2) {
2366                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2367                         return -EINVAL;
2368                 }
2369
2370                 if (input[0] == 0) {
2371                         if (input[1] < smu->gfx_default_hard_min_freq) {
2372                                 dev_warn(smu->adev->dev,
2373                                          "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2374                                          input[1], smu->gfx_default_hard_min_freq);
2375                                 return -EINVAL;
2376                         }
2377                         smu->gfx_actual_hard_min_freq = input[1];
2378                 } else if (input[0] == 1) {
2379                         if (input[1] > smu->gfx_default_soft_max_freq) {
2380                                 dev_warn(smu->adev->dev,
2381                                          "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2382                                          input[1], smu->gfx_default_soft_max_freq);
2383                                 return -EINVAL;
2384                         }
2385                         smu->gfx_actual_soft_max_freq = input[1];
2386                 } else {
2387                         return -EINVAL;
2388                 }
2389                 break;
2390         case PP_OD_RESTORE_DEFAULT_TABLE:
2391                 if (size != 0) {
2392                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2393                         return -EINVAL;
2394                 }
2395                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2396                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2397                 break;
2398         case PP_OD_COMMIT_DPM_TABLE:
2399                 if (size != 0) {
2400                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2401                         return -EINVAL;
2402                 }
2403                 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2404                         dev_err(smu->adev->dev,
2405                                 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2406                                 smu->gfx_actual_hard_min_freq,
2407                                 smu->gfx_actual_soft_max_freq);
2408                         return -EINVAL;
2409                 }
2410
2411                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2412                                                       smu->gfx_actual_hard_min_freq,
2413                                                       NULL);
2414                 if (ret) {
2415                         dev_err(smu->adev->dev, "Set hard min sclk failed!");
2416                         return ret;
2417                 }
2418
2419                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2420                                                       smu->gfx_actual_soft_max_freq,
2421                                                       NULL);
2422                 if (ret) {
2423                         dev_err(smu->adev->dev, "Set soft max sclk failed!");
2424                         return ret;
2425                 }
2426                 break;
2427         default:
2428                 return -ENOSYS;
2429         }
2430
2431         return ret;
2432 }
2433
2434 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2435 {
2436         struct smu_table_context *smu_table = &smu->smu_table;
2437
2438         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2439                                     smu_table->clocks_table, false);
2440 }
2441
2442 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2443 {
2444         struct amdgpu_device *adev = smu->adev;
2445
2446         smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2447         smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2448         smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2449 }
2450
2451 int smu_v13_0_mode1_reset(struct smu_context *smu)
2452 {
2453         int ret = 0;
2454
2455         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2456         if (!ret)
2457                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2458
2459         return ret;
2460 }