drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_dpm.h"
  29 #include "amdgpu_smu.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_atombios.h"
  33 #include "smu_v13_0.h"
  34 #include "smu13_driver_if_aldebaran.h"
  35 #include "soc15_common.h"
  36 #include "atom.h"
  37 #include "aldebaran_ppt.h"
  38 #include "smu_v13_0_pptable.h"
  39 #include "aldebaran_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/pci.h>
  46 #include "amdgpu_ras.h"
  47 #include "smu_cmn.h"
  48 #include "mp/mp_13_0_2_offset.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
  61         [smu_feature] = {1, (aldebaran_feature)}
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65                           FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
  66                           FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)  | \
  67                           FEATURE_MASK(FEATURE_DPM_UCLK_BIT)    | \
  68                           FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)  | \
  69                           FEATURE_MASK(FEATURE_DPM_FCLK_BIT)    | \
  70                           FEATURE_MASK(FEATURE_DPM_LCLK_BIT)    | \
  71                           FEATURE_MASK(FEATURE_DPM_XGMI_BIT)    | \
  72                           FEATURE_MASK(FEATURE_DPM_VCN_BIT))
  73
  74 /* possible frequency drift (1Mhz) */
  75 #define EPSILON                         1
  76
  77 #define smnPCIE_ESM_CTRL                        0x111003D0
  78
  79 /*
  80  * SMU support ECCTABLE since version 68.42.0,
  81  * use this to check ECCTALE feature whether support
  82  */
  83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00
  84
  85 /*
  86  * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0,
  87  * use this to check mca_ceumc_addr record whether support
  88  */
  89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700
  90
  91 /*
  92  * SMU support BAD CHENNEL info MSG since version 68.51.00,
  93  * use this to check ECCTALE feature whether support
  94  */
  95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300
  96
  97 static const struct smu_temperature_range smu13_thermal_policy[] =
  98 {
  99         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
 100         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
 101 };
 102
 103 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
 104         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
 105         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
 106         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
 107         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
 108         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
 109         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        1),
 110         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       1),
 111         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
 112         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 113         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 114         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 115         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 116         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 117         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 118         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 119         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 120         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 121         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 122         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 123         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 124         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 125         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 126         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 127         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 128         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 129         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 130         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 131         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 132         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 133         MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  0),
 134         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 135         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 136         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 137         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 138         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 139         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 140         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 141         MSG_MAP(SetNumBadHbmPagesRetired,            PPSMC_MSG_SetNumBadHbmPagesRetired,        0),
 142         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 143         MSG_MAP(GetGmiPwrDnHyst,                     PPSMC_MSG_GetGmiPwrDnHyst,                 0),
 144         MSG_MAP(SetGmiPwrDnHyst,                     PPSMC_MSG_SetGmiPwrDnHyst,                 0),
 145         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 146         MSG_MAP(EnterGfxoff,                         PPSMC_MSG_EnterGfxoff,                     0),
 147         MSG_MAP(ExitGfxoff,                          PPSMC_MSG_ExitGfxoff,                      0),
 148         MSG_MAP(SetExecuteDMATest,                   PPSMC_MSG_SetExecuteDMATest,               0),
 149         MSG_MAP(EnableDeterminism,                   PPSMC_MSG_EnableDeterminism,               0),
 150         MSG_MAP(DisableDeterminism,                  PPSMC_MSG_DisableDeterminism,              0),
 151         MSG_MAP(SetUclkDpmMode,                      PPSMC_MSG_SetUclkDpmMode,                  0),
 152         MSG_MAP(GfxDriverResetRecovery,              PPSMC_MSG_GfxDriverResetRecovery,          0),
 153         MSG_MAP(BoardPowerCalibration,               PPSMC_MSG_BoardPowerCalibration,           0),
 154         MSG_MAP(HeavySBR,                            PPSMC_MSG_HeavySBR,                        0),
 155         MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel,   PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0),
 156 };
 157
 158 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
 159         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 160         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 161         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 162         CLK_MAP(FCLK, PPCLK_FCLK),
 163         CLK_MAP(UCLK, PPCLK_UCLK),
 164         CLK_MAP(MCLK, PPCLK_UCLK),
 165         CLK_MAP(DCLK, PPCLK_DCLK),
 166         CLK_MAP(VCLK, PPCLK_VCLK),
 167         CLK_MAP(LCLK,   PPCLK_LCLK),
 168 };
 169
 170 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
 171         ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT,            FEATURE_DATA_CALCULATIONS),
 172         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT,                   FEATURE_DPM_GFXCLK_BIT),
 173         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT,                     FEATURE_DPM_UCLK_BIT),
 174         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,                   FEATURE_DPM_SOCCLK_BIT),
 175         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT,                     FEATURE_DPM_FCLK_BIT),
 176         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT,                     FEATURE_DPM_LCLK_BIT),
 177         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT,                             FEATURE_DPM_XGMI_BIT),
 178         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT,                    FEATURE_DS_GFXCLK_BIT),
 179         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT,                    FEATURE_DS_SOCCLK_BIT),
 180         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT,                              FEATURE_DS_LCLK_BIT),
 181         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT,                              FEATURE_DS_FCLK_BIT),
 182         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,                              FEATURE_DS_UCLK_BIT),
 183         ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT,                               FEATURE_GFX_SS_BIT),
 184         ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT,                              FEATURE_DPM_VCN_BIT),
 185         ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT,                  FEATURE_RSMU_SMN_CG_BIT),
 186         ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT,                              FEATURE_WAFL_CG_BIT),
 187         ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT,                                  FEATURE_PPT_BIT),
 188         ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT,                                  FEATURE_TDC_BIT),
 189         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT,                    FEATURE_APCC_PLUS_BIT),
 190         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT,                    FEATURE_APCC_DFLL_BIT),
 191         ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT,                              FEATURE_FUSE_CG_BIT),
 192         ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT,                               FEATURE_MP1_CG_BIT),
 193         ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT,                     FEATURE_SMUIO_CG_BIT),
 194         ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT,                               FEATURE_THM_CG_BIT),
 195         ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT,                               FEATURE_CLK_CG_BIT),
 196         ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT,                               FEATURE_FW_CTF_BIT),
 197         ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT,                              FEATURE_THERMAL_BIT),
 198         ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,  FEATURE_OUT_OF_BAND_MONITOR_BIT),
 199         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN),
 200         ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT,                    FEATURE_DF_CSTATE),
 201 };
 202
 203 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
 204         TAB_MAP(PPTABLE),
 205         TAB_MAP(AVFS_PSM_DEBUG),
 206         TAB_MAP(AVFS_FUSE_OVERRIDE),
 207         TAB_MAP(PMSTATUSLOG),
 208         TAB_MAP(SMU_METRICS),
 209         TAB_MAP(DRIVER_SMU_CONFIG),
 210         TAB_MAP(I2C_COMMANDS),
 211         TAB_MAP(ECCINFO),
 212 };
 213
 214 static const uint8_t aldebaran_throttler_map[] = {
 215         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 216         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 217         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 218         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 219         [THROTTLER_TDC_HBM_BIT]         = (SMU_THROTTLER_TDC_MEM_BIT),
 220         [THROTTLER_TEMP_GPU_BIT]        = (SMU_THROTTLER_TEMP_GPU_BIT),
 221         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 222         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 223         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 224         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 225         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 226 };
 227
 228 static int aldebaran_tables_init(struct smu_context *smu)
 229 {
 230         struct smu_table_context *smu_table = &smu->smu_table;
 231         struct smu_table *tables = smu_table->tables;
 232
 233         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 234                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 235
 236         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 237                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 238
 239         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 240                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 241
 242         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 243                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 244
 245         SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
 246                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 247
 248         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 249         if (!smu_table->metrics_table)
 250                 return -ENOMEM;
 251         smu_table->metrics_time = 0;
 252
 253         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 254         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 255         if (!smu_table->gpu_metrics_table) {
 256                 kfree(smu_table->metrics_table);
 257                 return -ENOMEM;
 258         }
 259
 260         smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
 261         if (!smu_table->ecc_table) {
 262                 kfree(smu_table->metrics_table);
 263                 kfree(smu_table->gpu_metrics_table);
 264                 return -ENOMEM;
 265         }
 266
 267         return 0;
 268 }
 269
 270 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
 271 {
 272         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 273
 274         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 275                                        GFP_KERNEL);
 276         if (!smu_dpm->dpm_context)
 277                 return -ENOMEM;
 278         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 279
 280         return 0;
 281 }
 282
 283 static int aldebaran_init_smc_tables(struct smu_context *smu)
 284 {
 285         int ret = 0;
 286
 287         ret = aldebaran_tables_init(smu);
 288         if (ret)
 289                 return ret;
 290
 291         ret = aldebaran_allocate_dpm_context(smu);
 292         if (ret)
 293                 return ret;
 294
 295         return smu_v13_0_init_smc_tables(smu);
 296 }
 297
 298 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
 299                                               uint32_t *feature_mask, uint32_t num)
 300 {
 301         if (num > 2)
 302                 return -EINVAL;
 303
 304         /* pptable will handle the features to enable */
 305         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 306
 307         return 0;
 308 }
 309
 310 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
 311 {
 312         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 313         struct smu_13_0_dpm_table *dpm_table = NULL;
 314         PPTable_t *pptable = smu->smu_table.driver_pptable;
 315         int ret = 0;
 316
 317         /* socclk dpm table setup */
 318         dpm_table = &dpm_context->dpm_tables.soc_table;
 319         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 320                 ret = smu_v13_0_set_single_dpm_table(smu,
 321                                                      SMU_SOCCLK,
 322                                                      dpm_table);
 323                 if (ret)
 324                         return ret;
 325         } else {
 326                 dpm_table->count = 1;
 327                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 328                 dpm_table->dpm_levels[0].enabled = true;
 329                 dpm_table->min = dpm_table->dpm_levels[0].value;
 330                 dpm_table->max = dpm_table->dpm_levels[0].value;
 331         }
 332
 333         /* gfxclk dpm table setup */
 334         dpm_table = &dpm_context->dpm_tables.gfx_table;
 335         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 336                 /* in the case of gfxclk, only fine-grained dpm is honored */
 337                 dpm_table->count = 2;
 338                 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
 339                 dpm_table->dpm_levels[0].enabled = true;
 340                 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
 341                 dpm_table->dpm_levels[1].enabled = true;
 342                 dpm_table->min = dpm_table->dpm_levels[0].value;
 343                 dpm_table->max = dpm_table->dpm_levels[1].value;
 344         } else {
 345                 dpm_table->count = 1;
 346                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 347                 dpm_table->dpm_levels[0].enabled = true;
 348                 dpm_table->min = dpm_table->dpm_levels[0].value;
 349                 dpm_table->max = dpm_table->dpm_levels[0].value;
 350         }
 351
 352         /* memclk dpm table setup */
 353         dpm_table = &dpm_context->dpm_tables.uclk_table;
 354         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 355                 ret = smu_v13_0_set_single_dpm_table(smu,
 356                                                      SMU_UCLK,
 357                                                      dpm_table);
 358                 if (ret)
 359                         return ret;
 360         } else {
 361                 dpm_table->count = 1;
 362                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 363                 dpm_table->dpm_levels[0].enabled = true;
 364                 dpm_table->min = dpm_table->dpm_levels[0].value;
 365                 dpm_table->max = dpm_table->dpm_levels[0].value;
 366         }
 367
 368         /* fclk dpm table setup */
 369         dpm_table = &dpm_context->dpm_tables.fclk_table;
 370         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 371                 ret = smu_v13_0_set_single_dpm_table(smu,
 372                                                      SMU_FCLK,
 373                                                      dpm_table);
 374                 if (ret)
 375                         return ret;
 376         } else {
 377                 dpm_table->count = 1;
 378                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 379                 dpm_table->dpm_levels[0].enabled = true;
 380                 dpm_table->min = dpm_table->dpm_levels[0].value;
 381                 dpm_table->max = dpm_table->dpm_levels[0].value;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int aldebaran_check_powerplay_table(struct smu_context *smu)
 388 {
 389         struct smu_table_context *table_context = &smu->smu_table;
 390         struct smu_13_0_powerplay_table *powerplay_table =
 391                 table_context->power_play_table;
 392
 393         table_context->thermal_controller_type =
 394                 powerplay_table->thermal_controller_type;
 395
 396         return 0;
 397 }
 398
 399 static int aldebaran_store_powerplay_table(struct smu_context *smu)
 400 {
 401         struct smu_table_context *table_context = &smu->smu_table;
 402         struct smu_13_0_powerplay_table *powerplay_table =
 403                 table_context->power_play_table;
 404         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 405                sizeof(PPTable_t));
 406
 407         return 0;
 408 }
 409
 410 static int aldebaran_append_powerplay_table(struct smu_context *smu)
 411 {
 412         struct smu_table_context *table_context = &smu->smu_table;
 413         PPTable_t *smc_pptable = table_context->driver_pptable;
 414         struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
 415         int index, ret;
 416
 417         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 418                                            smc_dpm_info);
 419
 420         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 421                                       (uint8_t **)&smc_dpm_table);
 422         if (ret)
 423                 return ret;
 424
 425         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 426                         smc_dpm_table->table_header.format_revision,
 427                         smc_dpm_table->table_header.content_revision);
 428
 429         if ((smc_dpm_table->table_header.format_revision == 4) &&
 430             (smc_dpm_table->table_header.content_revision == 10))
 431                 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
 432                                     smc_dpm_table, GfxMaxCurrent);
 433         return 0;
 434 }
 435
 436 static int aldebaran_setup_pptable(struct smu_context *smu)
 437 {
 438         int ret = 0;
 439
 440         /* VBIOS pptable is the first choice */
 441         smu->smu_table.boot_values.pp_table_id = 0;
 442
 443         ret = smu_v13_0_setup_pptable(smu);
 444         if (ret)
 445                 return ret;
 446
 447         ret = aldebaran_store_powerplay_table(smu);
 448         if (ret)
 449                 return ret;
 450
 451         ret = aldebaran_append_powerplay_table(smu);
 452         if (ret)
 453                 return ret;
 454
 455         ret = aldebaran_check_powerplay_table(smu);
 456         if (ret)
 457                 return ret;
 458
 459         return ret;
 460 }
 461
 462 static bool aldebaran_is_primary(struct smu_context *smu)
 463 {
 464         struct amdgpu_device *adev = smu->adev;
 465
 466         if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
 467                 return adev->smuio.funcs->get_die_id(adev) == 0;
 468
 469         return true;
 470 }
 471
 472 static int aldebaran_run_board_btc(struct smu_context *smu)
 473 {
 474         u32 smu_version;
 475         int ret;
 476
 477         if (!aldebaran_is_primary(smu))
 478                 return 0;
 479
 480         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 481         if (ret) {
 482                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 483                 return ret;
 484         }
 485         if (smu_version <= 0x00441d00)
 486                 return 0;
 487
 488         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
 489         if (ret)
 490                 dev_err(smu->adev->dev, "Board power calibration failed!\n");
 491
 492         return ret;
 493 }
 494
 495 static int aldebaran_run_btc(struct smu_context *smu)
 496 {
 497         int ret;
 498
 499         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 500         if (ret)
 501                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
 502         else
 503                 ret = aldebaran_run_board_btc(smu);
 504
 505         return ret;
 506 }
 507
 508 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
 509 {
 510         struct smu_13_0_dpm_context *dpm_context =
 511                 smu->smu_dpm.dpm_context;
 512         struct smu_13_0_dpm_table *gfx_table =
 513                 &dpm_context->dpm_tables.gfx_table;
 514         struct smu_13_0_dpm_table *mem_table =
 515                 &dpm_context->dpm_tables.uclk_table;
 516         struct smu_13_0_dpm_table *soc_table =
 517                 &dpm_context->dpm_tables.soc_table;
 518         struct smu_umd_pstate_table *pstate_table =
 519                 &smu->pstate_table;
 520
 521         pstate_table->gfxclk_pstate.min = gfx_table->min;
 522         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 523         pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
 524         pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
 525
 526         pstate_table->uclk_pstate.min = mem_table->min;
 527         pstate_table->uclk_pstate.peak = mem_table->max;
 528         pstate_table->uclk_pstate.curr.min = mem_table->min;
 529         pstate_table->uclk_pstate.curr.max = mem_table->max;
 530
 531         pstate_table->socclk_pstate.min = soc_table->min;
 532         pstate_table->socclk_pstate.peak = soc_table->max;
 533         pstate_table->socclk_pstate.curr.min = soc_table->min;
 534         pstate_table->socclk_pstate.curr.max = soc_table->max;
 535
 536         if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
 537             mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
 538             soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
 539                 pstate_table->gfxclk_pstate.standard =
 540                         gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
 541                 pstate_table->uclk_pstate.standard =
 542                         mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
 543                 pstate_table->socclk_pstate.standard =
 544                         soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
 545         } else {
 546                 pstate_table->gfxclk_pstate.standard =
 547                         pstate_table->gfxclk_pstate.min;
 548                 pstate_table->uclk_pstate.standard =
 549                         pstate_table->uclk_pstate.min;
 550                 pstate_table->socclk_pstate.standard =
 551                         pstate_table->socclk_pstate.min;
 552         }
 553
 554         return 0;
 555 }
 556
 557 static int aldebaran_get_clk_table(struct smu_context *smu,
 558                                    struct pp_clock_levels_with_latency *clocks,
 559                                    struct smu_13_0_dpm_table *dpm_table)
 560 {
 561         uint32_t i;
 562
 563         clocks->num_levels = min_t(uint32_t,
 564                                    dpm_table->count,
 565                                    (uint32_t)PP_MAX_CLOCK_LEVELS);
 566
 567         for (i = 0; i < clocks->num_levels; i++) {
 568                 clocks->data[i].clocks_in_khz =
 569                         dpm_table->dpm_levels[i].value * 1000;
 570                 clocks->data[i].latency_in_us = 0;
 571         }
 572
 573         return 0;
 574 }
 575
 576 static int aldebaran_freqs_in_same_level(int32_t frequency1,
 577                                          int32_t frequency2)
 578 {
 579         return (abs(frequency1 - frequency2) <= EPSILON);
 580 }
 581
 582 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 583                                           MetricsMember_t member,
 584                                           uint32_t *value)
 585 {
 586         struct smu_table_context *smu_table= &smu->smu_table;
 587         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 588         int ret = 0;
 589
 590         ret = smu_cmn_get_metrics_table(smu,
 591                                         NULL,
 592                                         false);
 593         if (ret)
 594                 return ret;
 595
 596         switch (member) {
 597         case METRICS_CURR_GFXCLK:
 598                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 599                 break;
 600         case METRICS_CURR_SOCCLK:
 601                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 602                 break;
 603         case METRICS_CURR_UCLK:
 604                 *value = metrics->CurrClock[PPCLK_UCLK];
 605                 break;
 606         case METRICS_CURR_VCLK:
 607                 *value = metrics->CurrClock[PPCLK_VCLK];
 608                 break;
 609         case METRICS_CURR_DCLK:
 610                 *value = metrics->CurrClock[PPCLK_DCLK];
 611                 break;
 612         case METRICS_CURR_FCLK:
 613                 *value = metrics->CurrClock[PPCLK_FCLK];
 614                 break;
 615         case METRICS_AVERAGE_GFXCLK:
 616                 *value = metrics->AverageGfxclkFrequency;
 617                 break;
 618         case METRICS_AVERAGE_SOCCLK:
 619                 *value = metrics->AverageSocclkFrequency;
 620                 break;
 621         case METRICS_AVERAGE_UCLK:
 622                 *value = metrics->AverageUclkFrequency;
 623                 break;
 624         case METRICS_AVERAGE_GFXACTIVITY:
 625                 *value = metrics->AverageGfxActivity;
 626                 break;
 627         case METRICS_AVERAGE_MEMACTIVITY:
 628                 *value = metrics->AverageUclkActivity;
 629                 break;
 630         case METRICS_AVERAGE_SOCKETPOWER:
 631                 /* Valid power data is available only from primary die */
 632                 *value = aldebaran_is_primary(smu) ?
 633                                  metrics->AverageSocketPower << 8 :
 634                                  0;
 635                 break;
 636         case METRICS_TEMPERATURE_EDGE:
 637                 *value = metrics->TemperatureEdge *
 638                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 639                 break;
 640         case METRICS_TEMPERATURE_HOTSPOT:
 641                 *value = metrics->TemperatureHotspot *
 642                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 643                 break;
 644         case METRICS_TEMPERATURE_MEM:
 645                 *value = metrics->TemperatureHBM *
 646                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 647                 break;
 648         case METRICS_TEMPERATURE_VRGFX:
 649                 *value = metrics->TemperatureVrGfx *
 650                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 651                 break;
 652         case METRICS_TEMPERATURE_VRSOC:
 653                 *value = metrics->TemperatureVrSoc *
 654                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 655                 break;
 656         case METRICS_TEMPERATURE_VRMEM:
 657                 *value = metrics->TemperatureVrMem *
 658                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 659                 break;
 660         case METRICS_THROTTLER_STATUS:
 661                 *value = metrics->ThrottlerStatus;
 662                 break;
 663         case METRICS_UNIQUE_ID_UPPER32:
 664                 *value = metrics->PublicSerialNumUpper32;
 665                 break;
 666         case METRICS_UNIQUE_ID_LOWER32:
 667                 *value = metrics->PublicSerialNumLower32;
 668                 break;
 669         default:
 670                 *value = UINT_MAX;
 671                 break;
 672         }
 673
 674         return ret;
 675 }
 676
 677 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
 678                                                    enum smu_clk_type clk_type,
 679                                                    uint32_t *value)
 680 {
 681         MetricsMember_t member_type;
 682         int clk_id = 0;
 683
 684         if (!value)
 685                 return -EINVAL;
 686
 687         clk_id = smu_cmn_to_asic_specific_index(smu,
 688                                                 CMN2ASIC_MAPPING_CLK,
 689                                                 clk_type);
 690         if (clk_id < 0)
 691                 return -EINVAL;
 692
 693         switch (clk_id) {
 694         case PPCLK_GFXCLK:
 695                 /*
 696                  * CurrClock[clk_id] can provide accurate
 697                  *   output only when the dpm feature is enabled.
 698                  * We can use Average_* for dpm disabled case.
 699                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 700                  */
 701                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 702                         member_type = METRICS_CURR_GFXCLK;
 703                 else
 704                         member_type = METRICS_AVERAGE_GFXCLK;
 705                 break;
 706         case PPCLK_UCLK:
 707                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 708                         member_type = METRICS_CURR_UCLK;
 709                 else
 710                         member_type = METRICS_AVERAGE_UCLK;
 711                 break;
 712         case PPCLK_SOCCLK:
 713                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 714                         member_type = METRICS_CURR_SOCCLK;
 715                 else
 716                         member_type = METRICS_AVERAGE_SOCCLK;
 717                 break;
 718         case PPCLK_VCLK:
 719                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 720                         member_type = METRICS_CURR_VCLK;
 721                 else
 722                         member_type = METRICS_AVERAGE_VCLK;
 723                 break;
 724         case PPCLK_DCLK:
 725                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 726                         member_type = METRICS_CURR_DCLK;
 727                 else
 728                         member_type = METRICS_AVERAGE_DCLK;
 729                 break;
 730         case PPCLK_FCLK:
 731                 member_type = METRICS_CURR_FCLK;
 732                 break;
 733         default:
 734                 return -EINVAL;
 735         }
 736
 737         return aldebaran_get_smu_metrics_data(smu,
 738                                               member_type,
 739                                               value);
 740 }
 741
 742 static int aldebaran_print_clk_levels(struct smu_context *smu,
 743                                       enum smu_clk_type type, char *buf)
 744 {
 745         int i, now, size = 0;
 746         int ret = 0;
 747         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 748         struct pp_clock_levels_with_latency clocks;
 749         struct smu_13_0_dpm_table *single_dpm_table;
 750         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 751         struct smu_13_0_dpm_context *dpm_context = NULL;
 752         int display_levels;
 753         uint32_t freq_values[3] = {0};
 754         uint32_t min_clk, max_clk;
 755
 756         smu_cmn_get_sysfs_buf(&buf, &size);
 757
 758         if (amdgpu_ras_intr_triggered()) {
 759                 size += sysfs_emit_at(buf, size, "unavailable\n");
 760                 return size;
 761         }
 762
 763         dpm_context = smu_dpm->dpm_context;
 764
 765         switch (type) {
 766
 767         case SMU_OD_SCLK:
 768                 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK");
 769                 fallthrough;
 770         case SMU_SCLK:
 771                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 772                 if (ret) {
 773                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 774                         return ret;
 775                 }
 776
 777                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 778                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 779                 if (ret) {
 780                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 781                         return ret;
 782                 }
 783
 784                 display_levels = (clocks.num_levels == 1) ? 1 : 2;
 785
 786                 min_clk = pstate_table->gfxclk_pstate.curr.min;
 787                 max_clk = pstate_table->gfxclk_pstate.curr.max;
 788
 789                 freq_values[0] = min_clk;
 790                 freq_values[1] = max_clk;
 791
 792                 /* fine-grained dpm has only 2 levels */
 793                 if (now > min_clk && now < max_clk) {
 794                         display_levels++;
 795                         freq_values[2] = max_clk;
 796                         freq_values[1] = now;
 797                 }
 798
 799                 for (i = 0; i < display_levels; i++)
 800                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 801                                 freq_values[i],
 802                                 (display_levels == 1) ?
 803                                         "*" :
 804                                         (aldebaran_freqs_in_same_level(
 805                                                  freq_values[i], now) ?
 806                                                  "*" :
 807                                                  ""));
 808
 809                 break;
 810
 811         case SMU_OD_MCLK:
 812                 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK");
 813                 fallthrough;
 814         case SMU_MCLK:
 815                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 816                 if (ret) {
 817                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 818                         return ret;
 819                 }
 820
 821                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 822                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 823                 if (ret) {
 824                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 825                         return ret;
 826                 }
 827
 828                 for (i = 0; i < clocks.num_levels; i++)
 829                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 830                                         i, clocks.data[i].clocks_in_khz / 1000,
 831                                         (clocks.num_levels == 1) ? "*" :
 832                                         (aldebaran_freqs_in_same_level(
 833                                                                        clocks.data[i].clocks_in_khz / 1000,
 834                                                                        now) ? "*" : ""));
 835                 break;
 836
 837         case SMU_SOCCLK:
 838                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 839                 if (ret) {
 840                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 841                         return ret;
 842                 }
 843
 844                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 845                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 846                 if (ret) {
 847                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 848                         return ret;
 849                 }
 850
 851                 for (i = 0; i < clocks.num_levels; i++)
 852                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 853                                         i, clocks.data[i].clocks_in_khz / 1000,
 854                                         (clocks.num_levels == 1) ? "*" :
 855                                         (aldebaran_freqs_in_same_level(
 856                                                                        clocks.data[i].clocks_in_khz / 1000,
 857                                                                        now) ? "*" : ""));
 858                 break;
 859
 860         case SMU_FCLK:
 861                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 862                 if (ret) {
 863                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 864                         return ret;
 865                 }
 866
 867                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 868                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 869                 if (ret) {
 870                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 871                         return ret;
 872                 }
 873
 874                 for (i = 0; i < single_dpm_table->count; i++)
 875                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 876                                         i, single_dpm_table->dpm_levels[i].value,
 877                                         (clocks.num_levels == 1) ? "*" :
 878                                         (aldebaran_freqs_in_same_level(
 879                                                                        clocks.data[i].clocks_in_khz / 1000,
 880                                                                        now) ? "*" : ""));
 881                 break;
 882
 883         case SMU_VCLK:
 884                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 885                 if (ret) {
 886                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 887                         return ret;
 888                 }
 889
 890                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 891                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 892                 if (ret) {
 893                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 894                         return ret;
 895                 }
 896
 897                 for (i = 0; i < single_dpm_table->count; i++)
 898                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 899                                         i, single_dpm_table->dpm_levels[i].value,
 900                                         (clocks.num_levels == 1) ? "*" :
 901                                         (aldebaran_freqs_in_same_level(
 902                                                                        clocks.data[i].clocks_in_khz / 1000,
 903                                                                        now) ? "*" : ""));
 904                 break;
 905
 906         case SMU_DCLK:
 907                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 908                 if (ret) {
 909                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 910                         return ret;
 911                 }
 912
 913                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 914                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 915                 if (ret) {
 916                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 917                         return ret;
 918                 }
 919
 920                 for (i = 0; i < single_dpm_table->count; i++)
 921                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 922                                         i, single_dpm_table->dpm_levels[i].value,
 923                                         (clocks.num_levels == 1) ? "*" :
 924                                         (aldebaran_freqs_in_same_level(
 925                                                                        clocks.data[i].clocks_in_khz / 1000,
 926                                                                        now) ? "*" : ""));
 927                 break;
 928
 929         default:
 930                 break;
 931         }
 932
 933         return size;
 934 }
 935
 936 static int aldebaran_upload_dpm_level(struct smu_context *smu,
 937                                       bool max,
 938                                       uint32_t feature_mask,
 939                                       uint32_t level)
 940 {
 941         struct smu_13_0_dpm_context *dpm_context =
 942                 smu->smu_dpm.dpm_context;
 943         uint32_t freq;
 944         int ret = 0;
 945
 946         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 947             (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
 948                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 949                 ret = smu_cmn_send_smc_msg_with_param(smu,
 950                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 951                                                       (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 952                                                       NULL);
 953                 if (ret) {
 954                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 955                                 max ? "max" : "min");
 956                         return ret;
 957                 }
 958         }
 959
 960         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 961             (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
 962                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 963                 ret = smu_cmn_send_smc_msg_with_param(smu,
 964                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 965                                                       (PPCLK_UCLK << 16) | (freq & 0xffff),
 966                                                       NULL);
 967                 if (ret) {
 968                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 969                                 max ? "max" : "min");
 970                         return ret;
 971                 }
 972         }
 973
 974         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 975             (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
 976                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 977                 ret = smu_cmn_send_smc_msg_with_param(smu,
 978                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 979                                                       (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 980                                                       NULL);
 981                 if (ret) {
 982                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 983                                 max ? "max" : "min");
 984                         return ret;
 985                 }
 986         }
 987
 988         return ret;
 989 }
 990
 991 static int aldebaran_force_clk_levels(struct smu_context *smu,
 992                                       enum smu_clk_type type, uint32_t mask)
 993 {
 994         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 995         struct smu_13_0_dpm_table *single_dpm_table = NULL;
 996         uint32_t soft_min_level, soft_max_level;
 997         int ret = 0;
 998
 999         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1000         soft_max_level = mask ? (fls(mask) - 1) : 0;
1001
1002         switch (type) {
1003         case SMU_SCLK:
1004                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1005                 if (soft_max_level >= single_dpm_table->count) {
1006                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1007                                 soft_max_level, single_dpm_table->count - 1);
1008                         ret = -EINVAL;
1009                         break;
1010                 }
1011
1012                 ret = aldebaran_upload_dpm_level(smu,
1013                                                  false,
1014                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1015                                                  soft_min_level);
1016                 if (ret) {
1017                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1018                         break;
1019                 }
1020
1021                 ret = aldebaran_upload_dpm_level(smu,
1022                                                  true,
1023                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1024                                                  soft_max_level);
1025                 if (ret)
1026                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1027
1028                 break;
1029
1030         case SMU_MCLK:
1031         case SMU_SOCCLK:
1032         case SMU_FCLK:
1033                 /*
1034                  * Should not arrive here since aldebaran does not
1035                  * support mclk/socclk/fclk softmin/softmax settings
1036                  */
1037                 ret = -EINVAL;
1038                 break;
1039
1040         default:
1041                 break;
1042         }
1043
1044         return ret;
1045 }
1046
1047 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1048                                                    struct smu_temperature_range *range)
1049 {
1050         struct smu_table_context *table_context = &smu->smu_table;
1051         struct smu_13_0_powerplay_table *powerplay_table =
1052                 table_context->power_play_table;
1053         PPTable_t *pptable = smu->smu_table.driver_pptable;
1054
1055         if (!range)
1056                 return -EINVAL;
1057
1058         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1059
1060         range->hotspot_crit_max = pptable->ThotspotLimit *
1061                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1062         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1063                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1064         range->mem_crit_max = pptable->TmemLimit *
1065                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1066         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1067                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1068         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1069
1070         return 0;
1071 }
1072
1073 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1074                                                   enum amd_pp_sensors sensor,
1075                                                   uint32_t *value)
1076 {
1077         int ret = 0;
1078
1079         if (!value)
1080                 return -EINVAL;
1081
1082         switch (sensor) {
1083         case AMDGPU_PP_SENSOR_GPU_LOAD:
1084                 ret = aldebaran_get_smu_metrics_data(smu,
1085                                                      METRICS_AVERAGE_GFXACTIVITY,
1086                                                      value);
1087                 break;
1088         case AMDGPU_PP_SENSOR_MEM_LOAD:
1089                 ret = aldebaran_get_smu_metrics_data(smu,
1090                                                      METRICS_AVERAGE_MEMACTIVITY,
1091                                                      value);
1092                 break;
1093         default:
1094                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1095                 return -EINVAL;
1096         }
1097
1098         return ret;
1099 }
1100
1101 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value)
1102 {
1103         if (!value)
1104                 return -EINVAL;
1105
1106         return aldebaran_get_smu_metrics_data(smu,
1107                                               METRICS_AVERAGE_SOCKETPOWER,
1108                                               value);
1109 }
1110
1111 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1112                                              enum amd_pp_sensors sensor,
1113                                              uint32_t *value)
1114 {
1115         int ret = 0;
1116
1117         if (!value)
1118                 return -EINVAL;
1119
1120         switch (sensor) {
1121         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1122                 ret = aldebaran_get_smu_metrics_data(smu,
1123                                                      METRICS_TEMPERATURE_HOTSPOT,
1124                                                      value);
1125                 break;
1126         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1127                 ret = aldebaran_get_smu_metrics_data(smu,
1128                                                      METRICS_TEMPERATURE_EDGE,
1129                                                      value);
1130                 break;
1131         case AMDGPU_PP_SENSOR_MEM_TEMP:
1132                 ret = aldebaran_get_smu_metrics_data(smu,
1133                                                      METRICS_TEMPERATURE_MEM,
1134                                                      value);
1135                 break;
1136         default:
1137                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1138                 return -EINVAL;
1139         }
1140
1141         return ret;
1142 }
1143
1144 static int aldebaran_read_sensor(struct smu_context *smu,
1145                                  enum amd_pp_sensors sensor,
1146                                  void *data, uint32_t *size)
1147 {
1148         int ret = 0;
1149
1150         if (amdgpu_ras_intr_triggered())
1151                 return 0;
1152
1153         if (!data || !size)
1154                 return -EINVAL;
1155
1156         switch (sensor) {
1157         case AMDGPU_PP_SENSOR_MEM_LOAD:
1158         case AMDGPU_PP_SENSOR_GPU_LOAD:
1159                 ret = aldebaran_get_current_activity_percent(smu,
1160                                                              sensor,
1161                                                              (uint32_t *)data);
1162                 *size = 4;
1163                 break;
1164         case AMDGPU_PP_SENSOR_GPU_POWER:
1165                 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data);
1166                 *size = 4;
1167                 break;
1168         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1169         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1170         case AMDGPU_PP_SENSOR_MEM_TEMP:
1171                 ret = aldebaran_thermal_get_temperature(smu, sensor,
1172                                                         (uint32_t *)data);
1173                 *size = 4;
1174                 break;
1175         case AMDGPU_PP_SENSOR_GFX_MCLK:
1176                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1177                 /* the output clock frequency in 10K unit */
1178                 *(uint32_t *)data *= 100;
1179                 *size = 4;
1180                 break;
1181         case AMDGPU_PP_SENSOR_GFX_SCLK:
1182                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1183                 *(uint32_t *)data *= 100;
1184                 *size = 4;
1185                 break;
1186         case AMDGPU_PP_SENSOR_VDDGFX:
1187                 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1188                 *size = 4;
1189                 break;
1190         default:
1191                 ret = -EOPNOTSUPP;
1192                 break;
1193         }
1194
1195         return ret;
1196 }
1197
1198 static int aldebaran_get_power_limit(struct smu_context *smu,
1199                                      uint32_t *current_power_limit,
1200                                      uint32_t *default_power_limit,
1201                                      uint32_t *max_power_limit)
1202 {
1203         PPTable_t *pptable = smu->smu_table.driver_pptable;
1204         uint32_t power_limit = 0;
1205         int ret;
1206
1207         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1208                 if (current_power_limit)
1209                         *current_power_limit = 0;
1210                 if (default_power_limit)
1211                         *default_power_limit = 0;
1212                 if (max_power_limit)
1213                         *max_power_limit = 0;
1214
1215                 dev_warn(smu->adev->dev,
1216                         "PPT feature is not enabled, power values can't be fetched.");
1217
1218                 return 0;
1219         }
1220
1221         /* Valid power data is available only from primary die.
1222          * For secondary die show the value as 0.
1223          */
1224         if (aldebaran_is_primary(smu)) {
1225                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1226                                            &power_limit);
1227
1228                 if (ret) {
1229                         /* the last hope to figure out the ppt limit */
1230                         if (!pptable) {
1231                                 dev_err(smu->adev->dev,
1232                                         "Cannot get PPT limit due to pptable missing!");
1233                                 return -EINVAL;
1234                         }
1235                         power_limit = pptable->PptLimit;
1236                 }
1237         }
1238
1239         if (current_power_limit)
1240                 *current_power_limit = power_limit;
1241         if (default_power_limit)
1242                 *default_power_limit = power_limit;
1243
1244         if (max_power_limit) {
1245                 if (pptable)
1246                         *max_power_limit = pptable->PptLimit;
1247         }
1248
1249         return 0;
1250 }
1251
1252 static int aldebaran_set_power_limit(struct smu_context *smu,
1253                                      enum smu_ppt_limit_type limit_type,
1254                                      uint32_t limit)
1255 {
1256         /* Power limit can be set only through primary die */
1257         if (aldebaran_is_primary(smu))
1258                 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1259
1260         return -EINVAL;
1261 }
1262
1263 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1264 {
1265         int ret;
1266
1267         ret = smu_v13_0_system_features_control(smu, enable);
1268         if (!ret && enable)
1269                 ret = aldebaran_run_btc(smu);
1270
1271         return ret;
1272 }
1273
1274 static int aldebaran_set_performance_level(struct smu_context *smu,
1275                                            enum amd_dpm_forced_level level)
1276 {
1277         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1278         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1279         struct smu_13_0_dpm_table *gfx_table =
1280                 &dpm_context->dpm_tables.gfx_table;
1281         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1282
1283         /* Disable determinism if switching to another mode */
1284         if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1285             (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1286                 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1287                 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1288         }
1289
1290         switch (level) {
1291
1292         case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1293                 return 0;
1294
1295         case AMD_DPM_FORCED_LEVEL_HIGH:
1296         case AMD_DPM_FORCED_LEVEL_LOW:
1297         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1298         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1299         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1300         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1301         default:
1302                 break;
1303         }
1304
1305         return smu_v13_0_set_performance_level(smu, level);
1306 }
1307
1308 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1309                                           enum smu_clk_type clk_type,
1310                                           uint32_t min,
1311                                           uint32_t max)
1312 {
1313         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1314         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1315         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1316         struct amdgpu_device *adev = smu->adev;
1317         uint32_t min_clk;
1318         uint32_t max_clk;
1319         int ret = 0;
1320
1321         if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1322                 return -EINVAL;
1323
1324         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1325                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1326                 return -EINVAL;
1327
1328         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1329                 if (min >= max) {
1330                         dev_err(smu->adev->dev,
1331                                 "Minimum GFX clk should be less than the maximum allowed clock\n");
1332                         return -EINVAL;
1333                 }
1334
1335                 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1336                     (max == pstate_table->gfxclk_pstate.curr.max))
1337                         return 0;
1338
1339                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1340                                                             min, max);
1341                 if (!ret) {
1342                         pstate_table->gfxclk_pstate.curr.min = min;
1343                         pstate_table->gfxclk_pstate.curr.max = max;
1344                 }
1345
1346                 return ret;
1347         }
1348
1349         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1350                 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1351                         (max > dpm_context->dpm_tables.gfx_table.max)) {
1352                         dev_warn(adev->dev,
1353                                         "Invalid max frequency %d MHz specified for determinism\n", max);
1354                         return -EINVAL;
1355                 }
1356
1357                 /* Restore default min/max clocks and enable determinism */
1358                 min_clk = dpm_context->dpm_tables.gfx_table.min;
1359                 max_clk = dpm_context->dpm_tables.gfx_table.max;
1360                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1361                 if (!ret) {
1362                         usleep_range(500, 1000);
1363                         ret = smu_cmn_send_smc_msg_with_param(smu,
1364                                         SMU_MSG_EnableDeterminism,
1365                                         max, NULL);
1366                         if (ret) {
1367                                 dev_err(adev->dev,
1368                                                 "Failed to enable determinism at GFX clock %d MHz\n", max);
1369                         } else {
1370                                 pstate_table->gfxclk_pstate.curr.min = min_clk;
1371                                 pstate_table->gfxclk_pstate.curr.max = max;
1372                         }
1373                 }
1374         }
1375
1376         return ret;
1377 }
1378
1379 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1380                                                         long input[], uint32_t size)
1381 {
1382         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1383         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1384         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1385         uint32_t min_clk;
1386         uint32_t max_clk;
1387         int ret = 0;
1388
1389         /* Only allowed in manual or determinism mode */
1390         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1391                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1392                 return -EINVAL;
1393
1394         switch (type) {
1395         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1396                 if (size != 2) {
1397                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1398                         return -EINVAL;
1399                 }
1400
1401                 if (input[0] == 0) {
1402                         if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1403                                 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1404                                         input[1], dpm_context->dpm_tables.gfx_table.min);
1405                                 pstate_table->gfxclk_pstate.custom.min =
1406                                         pstate_table->gfxclk_pstate.curr.min;
1407                                 return -EINVAL;
1408                         }
1409
1410                         pstate_table->gfxclk_pstate.custom.min = input[1];
1411                 } else if (input[0] == 1) {
1412                         if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1413                                 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1414                                         input[1], dpm_context->dpm_tables.gfx_table.max);
1415                                 pstate_table->gfxclk_pstate.custom.max =
1416                                         pstate_table->gfxclk_pstate.curr.max;
1417                                 return -EINVAL;
1418                         }
1419
1420                         pstate_table->gfxclk_pstate.custom.max = input[1];
1421                 } else {
1422                         return -EINVAL;
1423                 }
1424                 break;
1425         case PP_OD_RESTORE_DEFAULT_TABLE:
1426                 if (size != 0) {
1427                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1428                         return -EINVAL;
1429                 } else {
1430                         /* Use the default frequencies for manual and determinism mode */
1431                         min_clk = dpm_context->dpm_tables.gfx_table.min;
1432                         max_clk = dpm_context->dpm_tables.gfx_table.max;
1433
1434                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1435                 }
1436                 break;
1437         case PP_OD_COMMIT_DPM_TABLE:
1438                 if (size != 0) {
1439                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1440                         return -EINVAL;
1441                 } else {
1442                         if (!pstate_table->gfxclk_pstate.custom.min)
1443                                 pstate_table->gfxclk_pstate.custom.min =
1444                                         pstate_table->gfxclk_pstate.curr.min;
1445
1446                         if (!pstate_table->gfxclk_pstate.custom.max)
1447                                 pstate_table->gfxclk_pstate.custom.max =
1448                                         pstate_table->gfxclk_pstate.curr.max;
1449
1450                         min_clk = pstate_table->gfxclk_pstate.custom.min;
1451                         max_clk = pstate_table->gfxclk_pstate.custom.max;
1452
1453                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1454                 }
1455                 break;
1456         default:
1457                 return -ENOSYS;
1458         }
1459
1460         return ret;
1461 }
1462
1463 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1464 {
1465         int ret;
1466         uint64_t feature_enabled;
1467
1468         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1469         if (ret)
1470                 return false;
1471         return !!(feature_enabled & SMC_DPM_FEATURE);
1472 }
1473
1474 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1475                               struct i2c_msg *msg, int num_msgs)
1476 {
1477         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1478         struct amdgpu_device *adev = smu_i2c->adev;
1479         struct smu_context *smu = adev->powerplay.pp_handle;
1480         struct smu_table_context *smu_table = &smu->smu_table;
1481         struct smu_table *table = &smu_table->driver_table;
1482         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1483         int i, j, r, c;
1484         u16 dir;
1485
1486         if (!adev->pm.dpm_enabled)
1487                 return -EBUSY;
1488
1489         req = kzalloc(sizeof(*req), GFP_KERNEL);
1490         if (!req)
1491                 return -ENOMEM;
1492
1493         req->I2CcontrollerPort = smu_i2c->port;
1494         req->I2CSpeed = I2C_SPEED_FAST_400K;
1495         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1496         dir = msg[0].flags & I2C_M_RD;
1497
1498         for (c = i = 0; i < num_msgs; i++) {
1499                 for (j = 0; j < msg[i].len; j++, c++) {
1500                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1501
1502                         if (!(msg[i].flags & I2C_M_RD)) {
1503                                 /* write */
1504                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1505                                 cmd->ReadWriteData = msg[i].buf[j];
1506                         }
1507
1508                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
1509                                 /* The direction changes.
1510                                  */
1511                                 dir = msg[i].flags & I2C_M_RD;
1512                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1513                         }
1514
1515                         req->NumCmds++;
1516
1517                         /*
1518                          * Insert STOP if we are at the last byte of either last
1519                          * message for the transaction or the client explicitly
1520                          * requires a STOP at this particular message.
1521                          */
1522                         if ((j == msg[i].len - 1) &&
1523                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1524                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1525                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1526                         }
1527                 }
1528         }
1529         mutex_lock(&adev->pm.mutex);
1530         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1531         mutex_unlock(&adev->pm.mutex);
1532         if (r)
1533                 goto fail;
1534
1535         for (c = i = 0; i < num_msgs; i++) {
1536                 if (!(msg[i].flags & I2C_M_RD)) {
1537                         c += msg[i].len;
1538                         continue;
1539                 }
1540                 for (j = 0; j < msg[i].len; j++, c++) {
1541                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1542
1543                         msg[i].buf[j] = cmd->ReadWriteData;
1544                 }
1545         }
1546         r = num_msgs;
1547 fail:
1548         kfree(req);
1549         return r;
1550 }
1551
1552 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1553 {
1554         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1555 }
1556
1557
1558 static const struct i2c_algorithm aldebaran_i2c_algo = {
1559         .master_xfer = aldebaran_i2c_xfer,
1560         .functionality = aldebaran_i2c_func,
1561 };
1562
1563 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1564         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1565         .max_read_len  = MAX_SW_I2C_COMMANDS,
1566         .max_write_len = MAX_SW_I2C_COMMANDS,
1567         .max_comb_1st_msg_len = 2,
1568         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1569 };
1570
1571 static int aldebaran_i2c_control_init(struct smu_context *smu)
1572 {
1573         struct amdgpu_device *adev = smu->adev;
1574         struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
1575         struct i2c_adapter *control = &smu_i2c->adapter;
1576         int res;
1577
1578         smu_i2c->adev = adev;
1579         smu_i2c->port = 0;
1580         mutex_init(&smu_i2c->mutex);
1581         control->owner = THIS_MODULE;
1582         control->class = I2C_CLASS_SPD;
1583         control->dev.parent = &adev->pdev->dev;
1584         control->algo = &aldebaran_i2c_algo;
1585         snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0");
1586         control->quirks = &aldebaran_i2c_control_quirks;
1587         i2c_set_adapdata(control, smu_i2c);
1588
1589         res = i2c_add_adapter(control);
1590         if (res) {
1591                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1592                 goto Out_err;
1593         }
1594
1595         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1596         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1597
1598         return 0;
1599 Out_err:
1600         i2c_del_adapter(control);
1601
1602         return res;
1603 }
1604
1605 static void aldebaran_i2c_control_fini(struct smu_context *smu)
1606 {
1607         struct amdgpu_device *adev = smu->adev;
1608         int i;
1609
1610         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1611                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1612                 struct i2c_adapter *control = &smu_i2c->adapter;
1613
1614                 i2c_del_adapter(control);
1615         }
1616         adev->pm.ras_eeprom_i2c_bus = NULL;
1617         adev->pm.fru_eeprom_i2c_bus = NULL;
1618 }
1619
1620 static void aldebaran_get_unique_id(struct smu_context *smu)
1621 {
1622         struct amdgpu_device *adev = smu->adev;
1623         uint32_t upper32 = 0, lower32 = 0;
1624
1625         if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1626                 goto out;
1627         if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1628                 goto out;
1629
1630 out:
1631         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1632         if (adev->serial[0] == '\0')
1633                 sprintf(adev->serial, "%016llx", adev->unique_id);
1634 }
1635
1636 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1637 {
1638         /* aldebaran is not support baco */
1639
1640         return false;
1641 }
1642
1643 static int aldebaran_set_df_cstate(struct smu_context *smu,
1644                                    enum pp_df_cstate state)
1645 {
1646         struct amdgpu_device *adev = smu->adev;
1647
1648         /*
1649          * Aldebaran does not need the cstate disablement
1650          * prerequisite for gpu reset.
1651          */
1652         if (amdgpu_in_reset(adev) || adev->in_suspend)
1653                 return 0;
1654
1655         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1656 }
1657
1658 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1659 {
1660         struct amdgpu_device *adev = smu->adev;
1661
1662         /* The message only works on master die and NACK will be sent
1663            back for other dies, only send it on master die */
1664         if (!adev->smuio.funcs->get_socket_id(adev) &&
1665             !adev->smuio.funcs->get_die_id(adev))
1666                 return smu_cmn_send_smc_msg_with_param(smu,
1667                                    SMU_MSG_GmiPwrDnControl,
1668                                    en ? 0 : 1,
1669                                    NULL);
1670         else
1671                 return 0;
1672 }
1673
1674 static const struct throttling_logging_label {
1675         uint32_t feature_mask;
1676         const char *label;
1677 } logging_label[] = {
1678         {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"},
1679         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1680         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1681         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1682         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1683 };
1684 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1685 {
1686         int ret;
1687         int throttler_idx, throtting_events = 0, buf_idx = 0;
1688         struct amdgpu_device *adev = smu->adev;
1689         uint32_t throttler_status;
1690         char log_buf[256];
1691
1692         ret = aldebaran_get_smu_metrics_data(smu,
1693                                              METRICS_THROTTLER_STATUS,
1694                                              &throttler_status);
1695         if (ret)
1696                 return;
1697
1698         memset(log_buf, 0, sizeof(log_buf));
1699         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1700              throttler_idx++) {
1701                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1702                         throtting_events++;
1703                         buf_idx += snprintf(log_buf + buf_idx,
1704                                             sizeof(log_buf) - buf_idx,
1705                                             "%s%s",
1706                                             throtting_events > 1 ? " and " : "",
1707                                             logging_label[throttler_idx].label);
1708                         if (buf_idx >= sizeof(log_buf)) {
1709                                 dev_err(adev->dev, "buffer overflow!\n");
1710                                 log_buf[sizeof(log_buf) - 1] = '\0';
1711                                 break;
1712                         }
1713                 }
1714         }
1715
1716         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1717                  log_buf);
1718         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1719                 smu_cmn_get_indep_throttler_status(throttler_status,
1720                                                    aldebaran_throttler_map));
1721 }
1722
1723 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1724 {
1725         struct amdgpu_device *adev = smu->adev;
1726         uint32_t esm_ctrl;
1727
1728         /* TODO: confirm this on real target */
1729         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1730         if ((esm_ctrl >> 15) & 0x1FFFF)
1731                 return (((esm_ctrl >> 8) & 0x3F) + 128);
1732
1733         return smu_v13_0_get_current_pcie_link_speed(smu);
1734 }
1735
1736 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1737                                          void **table)
1738 {
1739         struct smu_table_context *smu_table = &smu->smu_table;
1740         struct gpu_metrics_v1_3 *gpu_metrics =
1741                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1742         SmuMetrics_t metrics;
1743         int i, ret = 0;
1744
1745         ret = smu_cmn_get_metrics_table(smu,
1746                                         &metrics,
1747                                         true);
1748         if (ret)
1749                 return ret;
1750
1751         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1752
1753         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1754         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1755         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1756         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1757         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1758         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1759
1760         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1761         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1762         gpu_metrics->average_mm_activity = 0;
1763
1764         /* Valid power data is available only from primary die */
1765         if (aldebaran_is_primary(smu)) {
1766                 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1767                 gpu_metrics->energy_accumulator =
1768                         (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1769                         metrics.EnergyAcc64bitLow;
1770         } else {
1771                 gpu_metrics->average_socket_power = 0;
1772                 gpu_metrics->energy_accumulator = 0;
1773         }
1774
1775         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1776         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1777         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1778         gpu_metrics->average_vclk0_frequency = 0;
1779         gpu_metrics->average_dclk0_frequency = 0;
1780
1781         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1782         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1783         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1784         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1785         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1786
1787         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1788         gpu_metrics->indep_throttle_status =
1789                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1790                                                            aldebaran_throttler_map);
1791
1792         gpu_metrics->current_fan_speed = 0;
1793
1794         gpu_metrics->pcie_link_width =
1795                 smu_v13_0_get_current_pcie_link_width(smu);
1796         gpu_metrics->pcie_link_speed =
1797                 aldebaran_get_current_pcie_link_speed(smu);
1798
1799         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1800
1801         gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1802         gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1803
1804         for (i = 0; i < NUM_HBM_INSTANCES; i++)
1805                 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1806
1807         gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1808                                         metrics.TimeStampLow;
1809
1810         *table = (void *)gpu_metrics;
1811
1812         return sizeof(struct gpu_metrics_v1_3);
1813 }
1814
1815 static int aldebaran_check_ecc_table_support(struct smu_context *smu,
1816                 int *ecctable_version)
1817 {
1818         uint32_t if_version = 0xff, smu_version = 0xff;
1819         int ret = 0;
1820
1821         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
1822         if (ret) {
1823                 /* return not support if failed get smu_version */
1824                 ret = -EOPNOTSUPP;
1825         }
1826
1827         if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
1828                 ret = -EOPNOTSUPP;
1829         else if (smu_version >= SUPPORT_ECCTABLE_SMU_VERSION &&
1830                         smu_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)
1831                 *ecctable_version = 1;
1832         else
1833                 *ecctable_version = 2;
1834
1835         return ret;
1836 }
1837
1838 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
1839                                          void *table)
1840 {
1841         struct smu_table_context *smu_table = &smu->smu_table;
1842         EccInfoTable_t *ecc_table = NULL;
1843         struct ecc_info_per_ch *ecc_info_per_channel = NULL;
1844         int i, ret = 0;
1845         int table_version = 0;
1846         struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
1847
1848         ret = aldebaran_check_ecc_table_support(smu, &table_version);
1849         if (ret)
1850                 return ret;
1851
1852         ret = smu_cmn_update_table(smu,
1853                                SMU_TABLE_ECCINFO,
1854                                0,
1855                                smu_table->ecc_table,
1856                                false);
1857         if (ret) {
1858                 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
1859                 return ret;
1860         }
1861
1862         ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
1863
1864         if (table_version == 1) {
1865                 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1866                         ecc_info_per_channel = &(eccinfo->ecc[i]);
1867                         ecc_info_per_channel->ce_count_lo_chip =
1868                                 ecc_table->EccInfo[i].ce_count_lo_chip;
1869                         ecc_info_per_channel->ce_count_hi_chip =
1870                                 ecc_table->EccInfo[i].ce_count_hi_chip;
1871                         ecc_info_per_channel->mca_umc_status =
1872                                 ecc_table->EccInfo[i].mca_umc_status;
1873                         ecc_info_per_channel->mca_umc_addr =
1874                                 ecc_table->EccInfo[i].mca_umc_addr;
1875                 }
1876         } else if (table_version == 2) {
1877                 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1878                         ecc_info_per_channel = &(eccinfo->ecc[i]);
1879                         ecc_info_per_channel->ce_count_lo_chip =
1880                                 ecc_table->EccInfo_V2[i].ce_count_lo_chip;
1881                         ecc_info_per_channel->ce_count_hi_chip =
1882                                 ecc_table->EccInfo_V2[i].ce_count_hi_chip;
1883                         ecc_info_per_channel->mca_umc_status =
1884                                 ecc_table->EccInfo_V2[i].mca_umc_status;
1885                         ecc_info_per_channel->mca_umc_addr =
1886                                 ecc_table->EccInfo_V2[i].mca_umc_addr;
1887                         ecc_info_per_channel->mca_ceumc_addr =
1888                                 ecc_table->EccInfo_V2[i].mca_ceumc_addr;
1889                 }
1890                 eccinfo->record_ce_addr_supported = 1;
1891         }
1892
1893         return ret;
1894 }
1895
1896 static int aldebaran_mode1_reset(struct smu_context *smu)
1897 {
1898         u32 smu_version, fatal_err, param;
1899         int ret = 0;
1900         struct amdgpu_device *adev = smu->adev;
1901         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1902
1903         fatal_err = 0;
1904         param = SMU_RESET_MODE_1;
1905
1906         /*
1907         * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1908         */
1909         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1910         if (smu_version < 0x00440700) {
1911                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1912         }
1913         else {
1914                 /* fatal error triggered by ras, PMFW supports the flag
1915                    from 68.44.0 */
1916                 if ((smu_version >= 0x00442c00) && ras &&
1917                     atomic_read(&ras->in_recovery))
1918                         fatal_err = 1;
1919
1920                 param |= (fatal_err << 16);
1921                 ret = smu_cmn_send_smc_msg_with_param(smu,
1922                                         SMU_MSG_GfxDeviceDriverReset, param, NULL);
1923         }
1924
1925         if (!ret)
1926                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1927
1928         return ret;
1929 }
1930
1931 static int aldebaran_mode2_reset(struct smu_context *smu)
1932 {
1933         u32 smu_version;
1934         int ret = 0, index;
1935         struct amdgpu_device *adev = smu->adev;
1936         int timeout = 10;
1937
1938         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1939
1940         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1941                                                 SMU_MSG_GfxDeviceDriverReset);
1942
1943         mutex_lock(&smu->message_lock);
1944         if (smu_version >= 0x00441400) {
1945                 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1946                 /* This is similar to FLR, wait till max FLR timeout */
1947                 msleep(100);
1948                 dev_dbg(smu->adev->dev, "restore config space...\n");
1949                 /* Restore the config space saved during init */
1950                 amdgpu_device_load_pci_state(adev->pdev);
1951
1952                 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1953                 while (ret == -ETIME && timeout)  {
1954                         ret = smu_cmn_wait_for_response(smu);
1955                         /* Wait a bit more time for getting ACK */
1956                         if (ret == -ETIME) {
1957                                 --timeout;
1958                                 usleep_range(500, 1000);
1959                                 continue;
1960                         }
1961
1962                         if (ret != 1) {
1963                                 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1964                                                 SMU_RESET_MODE_2, ret);
1965                                 goto out;
1966                         }
1967                 }
1968
1969         } else {
1970                 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1971                                 smu_version);
1972         }
1973
1974         if (ret == 1)
1975                 ret = 0;
1976 out:
1977         mutex_unlock(&smu->message_lock);
1978
1979         return ret;
1980 }
1981
1982 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1983 {
1984         int ret = 0;
1985         ret =  smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
1986
1987         return ret;
1988 }
1989
1990 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1991 {
1992 #if 0
1993         struct amdgpu_device *adev = smu->adev;
1994         u32 smu_version;
1995         uint32_t val;
1996         /**
1997          * PM FW version support mode1 reset from 68.07
1998          */
1999         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2000         if ((smu_version < 0x00440700))
2001                 return false;
2002         /**
2003          * mode1 reset relies on PSP, so we should check if
2004          * PSP is alive.
2005          */
2006         val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
2007
2008         return val != 0x0;
2009 #endif
2010         return true;
2011 }
2012
2013 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
2014 {
2015         return true;
2016 }
2017
2018 static int aldebaran_set_mp1_state(struct smu_context *smu,
2019                                    enum pp_mp1_state mp1_state)
2020 {
2021         switch (mp1_state) {
2022         case PP_MP1_STATE_UNLOAD:
2023                 return smu_cmn_set_mp1_state(smu, mp1_state);
2024         default:
2025                 return 0;
2026         }
2027 }
2028
2029 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
2030                 uint32_t size)
2031 {
2032         int ret = 0;
2033
2034         /* message SMU to update the bad page number on SMUBUS */
2035         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
2036         if (ret)
2037                 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
2038                                 __func__);
2039
2040         return ret;
2041 }
2042
2043 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu)
2044 {
2045         uint32_t if_version = 0xff, smu_version = 0xff;
2046         int ret = 0;
2047
2048         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
2049         if (ret) {
2050                 /* return not support if failed get smu_version */
2051                 ret = -EOPNOTSUPP;
2052         }
2053
2054         if (smu_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION)
2055                 ret = -EOPNOTSUPP;
2056
2057         return ret;
2058 }
2059
2060 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu,
2061                 uint32_t size)
2062 {
2063         int ret = 0;
2064
2065         ret = aldebaran_check_bad_channel_info_support(smu);
2066         if (ret)
2067                 return ret;
2068
2069         /* message SMU to update the bad channel info on SMUBUS */
2070         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL);
2071         if (ret)
2072                 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n",
2073                                 __func__);
2074
2075         return ret;
2076 }
2077
2078 static const struct pptable_funcs aldebaran_ppt_funcs = {
2079         /* init dpm */
2080         .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
2081         /* dpm/clk tables */
2082         .set_default_dpm_table = aldebaran_set_default_dpm_table,
2083         .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
2084         .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
2085         .print_clk_levels = aldebaran_print_clk_levels,
2086         .force_clk_levels = aldebaran_force_clk_levels,
2087         .read_sensor = aldebaran_read_sensor,
2088         .set_performance_level = aldebaran_set_performance_level,
2089         .get_power_limit = aldebaran_get_power_limit,
2090         .is_dpm_running = aldebaran_is_dpm_running,
2091         .get_unique_id = aldebaran_get_unique_id,
2092         .init_microcode = smu_v13_0_init_microcode,
2093         .load_microcode = smu_v13_0_load_microcode,
2094         .fini_microcode = smu_v13_0_fini_microcode,
2095         .init_smc_tables = aldebaran_init_smc_tables,
2096         .fini_smc_tables = smu_v13_0_fini_smc_tables,
2097         .init_power = smu_v13_0_init_power,
2098         .fini_power = smu_v13_0_fini_power,
2099         .check_fw_status = smu_v13_0_check_fw_status,
2100         /* pptable related */
2101         .setup_pptable = aldebaran_setup_pptable,
2102         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2103         .check_fw_version = smu_v13_0_check_fw_version,
2104         .write_pptable = smu_cmn_write_pptable,
2105         .set_driver_table_location = smu_v13_0_set_driver_table_location,
2106         .set_tool_table_location = smu_v13_0_set_tool_table_location,
2107         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2108         .system_features_control = aldebaran_system_features_control,
2109         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2110         .send_smc_msg = smu_cmn_send_smc_msg,
2111         .get_enabled_mask = smu_cmn_get_enabled_mask,
2112         .feature_is_enabled = smu_cmn_feature_is_enabled,
2113         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2114         .set_power_limit = aldebaran_set_power_limit,
2115         .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
2116         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2117         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2118         .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
2119         .register_irq_handler = smu_v13_0_register_irq_handler,
2120         .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
2121         .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
2122         .baco_is_support= aldebaran_is_baco_supported,
2123         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
2124         .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
2125         .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
2126         .set_df_cstate = aldebaran_set_df_cstate,
2127         .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
2128         .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
2129         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2130         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2131         .get_gpu_metrics = aldebaran_get_gpu_metrics,
2132         .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
2133         .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
2134         .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
2135         .mode1_reset = aldebaran_mode1_reset,
2136         .set_mp1_state = aldebaran_set_mp1_state,
2137         .mode2_reset = aldebaran_mode2_reset,
2138         .wait_for_event = smu_v13_0_wait_for_event,
2139         .i2c_init = aldebaran_i2c_control_init,
2140         .i2c_fini = aldebaran_i2c_control_fini,
2141         .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2142         .get_ecc_info = aldebaran_get_ecc_info,
2143         .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag,
2144 };
2145
2146 void aldebaran_set_ppt_funcs(struct smu_context *smu)
2147 {
2148         smu->ppt_funcs = &aldebaran_ppt_funcs;
2149         smu->message_map = aldebaran_message_map;
2150         smu->clock_map = aldebaran_clk_map;
2151         smu->feature_map = aldebaran_feature_mask_map;
2152         smu->table_map = aldebaran_table_map;
2153         smu_v13_0_set_smu_mailbox_registers(smu);
2154 }