2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
26 #include <linux/firmware.h>
28 #include "amdgpu_dpm.h"
29 #include "amdgpu_smu.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_atombios.h"
33 #include "smu_v13_0.h"
34 #include "smu13_driver_if_aldebaran.h"
35 #include "soc15_common.h"
37 #include "aldebaran_ppt.h"
38 #include "smu_v13_0_pptable.h"
39 #include "aldebaran_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
48 #include "mp/mp_13_0_2_offset.h"
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
61 [smu_feature] = {1, (aldebaran_feature)}
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_VCN_BIT))
74 /* possible frequency drift (1Mhz) */
77 #define smnPCIE_ESM_CTRL 0x111003D0
80 * SMU support ECCTABLE since version 68.42.0,
81 * use this to check ECCTALE feature whether support
83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00
86 * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0,
87 * use this to check mca_ceumc_addr record whether support
89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700
92 * SMU support BAD CHENNEL info MSG since version 68.51.00,
93 * use this to check ECCTALE feature whether support
95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300
97 static const struct smu_temperature_range smu13_thermal_policy[] = {
98 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
99 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
102 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
103 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
104 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
105 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
108 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
109 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
110 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
111 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
112 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
113 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
114 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
115 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
116 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
117 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
118 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
119 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
120 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
121 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
122 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
123 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
124 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
125 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
126 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
127 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
128 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
129 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
130 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
132 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0),
133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
139 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
140 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
142 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
143 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
144 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
145 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
146 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
147 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0),
148 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
149 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
150 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
151 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
152 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0),
153 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0),
154 MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel, PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0),
157 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
158 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
159 CLK_MAP(SCLK, PPCLK_GFXCLK),
160 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
161 CLK_MAP(FCLK, PPCLK_FCLK),
162 CLK_MAP(UCLK, PPCLK_UCLK),
163 CLK_MAP(MCLK, PPCLK_UCLK),
164 CLK_MAP(DCLK, PPCLK_DCLK),
165 CLK_MAP(VCLK, PPCLK_VCLK),
166 CLK_MAP(LCLK, PPCLK_LCLK),
169 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS),
171 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT),
172 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT),
173 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT),
174 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT),
175 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT),
176 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
177 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT),
178 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT),
179 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT),
180 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT),
181 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT),
182 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT),
183 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
184 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT),
185 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT),
186 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT),
187 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT),
188 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT),
189 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT),
190 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT),
191 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT),
192 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT),
193 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT),
194 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT),
195 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT),
196 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT),
197 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT),
198 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DWN),
199 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
202 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
204 TAB_MAP(AVFS_PSM_DEBUG),
205 TAB_MAP(AVFS_FUSE_OVERRIDE),
206 TAB_MAP(PMSTATUSLOG),
207 TAB_MAP(SMU_METRICS),
208 TAB_MAP(DRIVER_SMU_CONFIG),
209 TAB_MAP(I2C_COMMANDS),
213 static const uint8_t aldebaran_throttler_map[] = {
214 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
215 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
216 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
217 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
218 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT),
219 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
220 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
221 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
222 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
223 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
224 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
227 static int aldebaran_tables_init(struct smu_context *smu)
229 struct smu_table_context *smu_table = &smu->smu_table;
230 struct smu_table *tables = smu_table->tables;
232 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
233 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
235 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
238 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
239 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
241 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
242 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
244 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
245 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
247 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
248 if (!smu_table->metrics_table)
250 smu_table->metrics_time = 0;
252 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
253 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
254 if (!smu_table->gpu_metrics_table) {
255 kfree(smu_table->metrics_table);
259 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
260 if (!smu_table->ecc_table)
266 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
268 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
270 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
272 if (!smu_dpm->dpm_context)
274 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
279 static int aldebaran_init_smc_tables(struct smu_context *smu)
283 ret = aldebaran_tables_init(smu);
287 ret = aldebaran_allocate_dpm_context(smu);
291 return smu_v13_0_init_smc_tables(smu);
294 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
295 uint32_t *feature_mask, uint32_t num)
300 /* pptable will handle the features to enable */
301 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
306 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
308 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
309 struct smu_13_0_dpm_table *dpm_table = NULL;
310 PPTable_t *pptable = smu->smu_table.driver_pptable;
313 /* socclk dpm table setup */
314 dpm_table = &dpm_context->dpm_tables.soc_table;
315 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
316 ret = smu_v13_0_set_single_dpm_table(smu,
322 dpm_table->count = 1;
323 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
324 dpm_table->dpm_levels[0].enabled = true;
325 dpm_table->min = dpm_table->dpm_levels[0].value;
326 dpm_table->max = dpm_table->dpm_levels[0].value;
329 /* gfxclk dpm table setup */
330 dpm_table = &dpm_context->dpm_tables.gfx_table;
331 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
332 /* in the case of gfxclk, only fine-grained dpm is honored */
333 dpm_table->count = 2;
334 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
335 dpm_table->dpm_levels[0].enabled = true;
336 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
337 dpm_table->dpm_levels[1].enabled = true;
338 dpm_table->min = dpm_table->dpm_levels[0].value;
339 dpm_table->max = dpm_table->dpm_levels[1].value;
341 dpm_table->count = 1;
342 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
343 dpm_table->dpm_levels[0].enabled = true;
344 dpm_table->min = dpm_table->dpm_levels[0].value;
345 dpm_table->max = dpm_table->dpm_levels[0].value;
348 /* memclk dpm table setup */
349 dpm_table = &dpm_context->dpm_tables.uclk_table;
350 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
351 ret = smu_v13_0_set_single_dpm_table(smu,
357 dpm_table->count = 1;
358 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
359 dpm_table->dpm_levels[0].enabled = true;
360 dpm_table->min = dpm_table->dpm_levels[0].value;
361 dpm_table->max = dpm_table->dpm_levels[0].value;
364 /* fclk dpm table setup */
365 dpm_table = &dpm_context->dpm_tables.fclk_table;
366 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
367 ret = smu_v13_0_set_single_dpm_table(smu,
373 dpm_table->count = 1;
374 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
375 dpm_table->dpm_levels[0].enabled = true;
376 dpm_table->min = dpm_table->dpm_levels[0].value;
377 dpm_table->max = dpm_table->dpm_levels[0].value;
383 static int aldebaran_check_powerplay_table(struct smu_context *smu)
385 struct smu_table_context *table_context = &smu->smu_table;
386 struct smu_13_0_powerplay_table *powerplay_table =
387 table_context->power_play_table;
389 table_context->thermal_controller_type =
390 powerplay_table->thermal_controller_type;
395 static int aldebaran_store_powerplay_table(struct smu_context *smu)
397 struct smu_table_context *table_context = &smu->smu_table;
398 struct smu_13_0_powerplay_table *powerplay_table =
399 table_context->power_play_table;
400 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
406 static int aldebaran_append_powerplay_table(struct smu_context *smu)
408 struct smu_table_context *table_context = &smu->smu_table;
409 PPTable_t *smc_pptable = table_context->driver_pptable;
410 struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
413 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
416 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
417 (uint8_t **)&smc_dpm_table);
421 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
422 smc_dpm_table->table_header.format_revision,
423 smc_dpm_table->table_header.content_revision);
425 if ((smc_dpm_table->table_header.format_revision == 4) &&
426 (smc_dpm_table->table_header.content_revision == 10))
427 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
428 smc_dpm_table, GfxMaxCurrent);
432 static int aldebaran_setup_pptable(struct smu_context *smu)
436 /* VBIOS pptable is the first choice */
437 smu->smu_table.boot_values.pp_table_id = 0;
439 ret = smu_v13_0_setup_pptable(smu);
443 ret = aldebaran_store_powerplay_table(smu);
447 ret = aldebaran_append_powerplay_table(smu);
451 ret = aldebaran_check_powerplay_table(smu);
458 static bool aldebaran_is_primary(struct smu_context *smu)
460 struct amdgpu_device *adev = smu->adev;
462 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
463 return adev->smuio.funcs->get_die_id(adev) == 0;
468 static int aldebaran_run_board_btc(struct smu_context *smu)
473 if (!aldebaran_is_primary(smu))
476 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
478 dev_err(smu->adev->dev, "Failed to get smu version!\n");
481 if (smu_version <= 0x00441d00)
484 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
486 dev_err(smu->adev->dev, "Board power calibration failed!\n");
491 static int aldebaran_run_btc(struct smu_context *smu)
495 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
497 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
499 ret = aldebaran_run_board_btc(smu);
504 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
506 struct smu_13_0_dpm_context *dpm_context =
507 smu->smu_dpm.dpm_context;
508 struct smu_13_0_dpm_table *gfx_table =
509 &dpm_context->dpm_tables.gfx_table;
510 struct smu_13_0_dpm_table *mem_table =
511 &dpm_context->dpm_tables.uclk_table;
512 struct smu_13_0_dpm_table *soc_table =
513 &dpm_context->dpm_tables.soc_table;
514 struct smu_umd_pstate_table *pstate_table =
517 pstate_table->gfxclk_pstate.min = gfx_table->min;
518 pstate_table->gfxclk_pstate.peak = gfx_table->max;
519 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
520 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
522 pstate_table->uclk_pstate.min = mem_table->min;
523 pstate_table->uclk_pstate.peak = mem_table->max;
524 pstate_table->uclk_pstate.curr.min = mem_table->min;
525 pstate_table->uclk_pstate.curr.max = mem_table->max;
527 pstate_table->socclk_pstate.min = soc_table->min;
528 pstate_table->socclk_pstate.peak = soc_table->max;
529 pstate_table->socclk_pstate.curr.min = soc_table->min;
530 pstate_table->socclk_pstate.curr.max = soc_table->max;
532 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
533 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
534 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
535 pstate_table->gfxclk_pstate.standard =
536 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
537 pstate_table->uclk_pstate.standard =
538 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
539 pstate_table->socclk_pstate.standard =
540 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
542 pstate_table->gfxclk_pstate.standard =
543 pstate_table->gfxclk_pstate.min;
544 pstate_table->uclk_pstate.standard =
545 pstate_table->uclk_pstate.min;
546 pstate_table->socclk_pstate.standard =
547 pstate_table->socclk_pstate.min;
553 static int aldebaran_get_clk_table(struct smu_context *smu,
554 struct pp_clock_levels_with_latency *clocks,
555 struct smu_13_0_dpm_table *dpm_table)
559 clocks->num_levels = min_t(uint32_t,
561 (uint32_t)PP_MAX_CLOCK_LEVELS);
563 for (i = 0; i < clocks->num_levels; i++) {
564 clocks->data[i].clocks_in_khz =
565 dpm_table->dpm_levels[i].value * 1000;
566 clocks->data[i].latency_in_us = 0;
572 static int aldebaran_freqs_in_same_level(int32_t frequency1,
575 return (abs(frequency1 - frequency2) <= EPSILON);
578 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
579 MetricsMember_t member,
582 struct smu_table_context *smu_table = &smu->smu_table;
583 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
586 ret = smu_cmn_get_metrics_table(smu,
593 case METRICS_CURR_GFXCLK:
594 *value = metrics->CurrClock[PPCLK_GFXCLK];
596 case METRICS_CURR_SOCCLK:
597 *value = metrics->CurrClock[PPCLK_SOCCLK];
599 case METRICS_CURR_UCLK:
600 *value = metrics->CurrClock[PPCLK_UCLK];
602 case METRICS_CURR_VCLK:
603 *value = metrics->CurrClock[PPCLK_VCLK];
605 case METRICS_CURR_DCLK:
606 *value = metrics->CurrClock[PPCLK_DCLK];
608 case METRICS_CURR_FCLK:
609 *value = metrics->CurrClock[PPCLK_FCLK];
611 case METRICS_AVERAGE_GFXCLK:
612 *value = metrics->AverageGfxclkFrequency;
614 case METRICS_AVERAGE_SOCCLK:
615 *value = metrics->AverageSocclkFrequency;
617 case METRICS_AVERAGE_UCLK:
618 *value = metrics->AverageUclkFrequency;
620 case METRICS_AVERAGE_GFXACTIVITY:
621 *value = metrics->AverageGfxActivity;
623 case METRICS_AVERAGE_MEMACTIVITY:
624 *value = metrics->AverageUclkActivity;
626 case METRICS_AVERAGE_SOCKETPOWER:
627 /* Valid power data is available only from primary die */
628 if (aldebaran_is_primary(smu))
629 *value = metrics->AverageSocketPower << 8;
633 case METRICS_TEMPERATURE_EDGE:
634 *value = metrics->TemperatureEdge *
635 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
637 case METRICS_TEMPERATURE_HOTSPOT:
638 *value = metrics->TemperatureHotspot *
639 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
641 case METRICS_TEMPERATURE_MEM:
642 *value = metrics->TemperatureHBM *
643 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
645 case METRICS_TEMPERATURE_VRGFX:
646 *value = metrics->TemperatureVrGfx *
647 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
649 case METRICS_TEMPERATURE_VRSOC:
650 *value = metrics->TemperatureVrSoc *
651 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
653 case METRICS_TEMPERATURE_VRMEM:
654 *value = metrics->TemperatureVrMem *
655 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
657 case METRICS_THROTTLER_STATUS:
658 *value = metrics->ThrottlerStatus;
660 case METRICS_UNIQUE_ID_UPPER32:
661 *value = metrics->PublicSerialNumUpper32;
663 case METRICS_UNIQUE_ID_LOWER32:
664 *value = metrics->PublicSerialNumLower32;
674 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
675 enum smu_clk_type clk_type,
678 MetricsMember_t member_type;
684 clk_id = smu_cmn_to_asic_specific_index(smu,
685 CMN2ASIC_MAPPING_CLK,
693 * CurrClock[clk_id] can provide accurate
694 * output only when the dpm feature is enabled.
695 * We can use Average_* for dpm disabled case.
696 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
698 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
699 member_type = METRICS_CURR_GFXCLK;
701 member_type = METRICS_AVERAGE_GFXCLK;
704 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
705 member_type = METRICS_CURR_UCLK;
707 member_type = METRICS_AVERAGE_UCLK;
710 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
711 member_type = METRICS_CURR_SOCCLK;
713 member_type = METRICS_AVERAGE_SOCCLK;
716 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
717 member_type = METRICS_CURR_VCLK;
719 member_type = METRICS_AVERAGE_VCLK;
722 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
723 member_type = METRICS_CURR_DCLK;
725 member_type = METRICS_AVERAGE_DCLK;
728 member_type = METRICS_CURR_FCLK;
734 return aldebaran_get_smu_metrics_data(smu,
739 static int aldebaran_print_clk_levels(struct smu_context *smu,
740 enum smu_clk_type type, char *buf)
742 int i, now, size = 0;
744 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
745 struct pp_clock_levels_with_latency clocks;
746 struct smu_13_0_dpm_table *single_dpm_table;
747 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
748 struct smu_13_0_dpm_context *dpm_context = NULL;
750 uint32_t freq_values[3] = {0};
751 uint32_t min_clk, max_clk;
753 smu_cmn_get_sysfs_buf(&buf, &size);
755 if (amdgpu_ras_intr_triggered()) {
756 size += sysfs_emit_at(buf, size, "unavailable\n");
760 dpm_context = smu_dpm->dpm_context;
765 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK");
768 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
770 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
774 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
775 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
777 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
781 display_levels = (clocks.num_levels == 1) ? 1 : 2;
783 min_clk = pstate_table->gfxclk_pstate.curr.min;
784 max_clk = pstate_table->gfxclk_pstate.curr.max;
786 freq_values[0] = min_clk;
787 freq_values[1] = max_clk;
789 /* fine-grained dpm has only 2 levels */
790 if (now > min_clk && now < max_clk) {
792 freq_values[2] = max_clk;
793 freq_values[1] = now;
796 for (i = 0; i < display_levels; i++)
797 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
799 (display_levels == 1) ?
801 (aldebaran_freqs_in_same_level(
802 freq_values[i], now) ?
809 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK");
812 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
814 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
818 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
819 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
821 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
825 for (i = 0; i < clocks.num_levels; i++)
826 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
827 i, clocks.data[i].clocks_in_khz / 1000,
828 (clocks.num_levels == 1) ? "*" :
829 (aldebaran_freqs_in_same_level(
830 clocks.data[i].clocks_in_khz / 1000,
835 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
837 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
841 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
842 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
844 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
848 for (i = 0; i < clocks.num_levels; i++)
849 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
850 i, clocks.data[i].clocks_in_khz / 1000,
851 (clocks.num_levels == 1) ? "*" :
852 (aldebaran_freqs_in_same_level(
853 clocks.data[i].clocks_in_khz / 1000,
858 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
860 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
864 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
865 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
867 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
871 for (i = 0; i < single_dpm_table->count; i++)
872 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
873 i, single_dpm_table->dpm_levels[i].value,
874 (clocks.num_levels == 1) ? "*" :
875 (aldebaran_freqs_in_same_level(
876 clocks.data[i].clocks_in_khz / 1000,
881 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
883 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
887 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
888 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
890 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
894 for (i = 0; i < single_dpm_table->count; i++)
895 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
896 i, single_dpm_table->dpm_levels[i].value,
897 (clocks.num_levels == 1) ? "*" :
898 (aldebaran_freqs_in_same_level(
899 clocks.data[i].clocks_in_khz / 1000,
904 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
906 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
910 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
911 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
913 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
917 for (i = 0; i < single_dpm_table->count; i++)
918 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
919 i, single_dpm_table->dpm_levels[i].value,
920 (clocks.num_levels == 1) ? "*" :
921 (aldebaran_freqs_in_same_level(
922 clocks.data[i].clocks_in_khz / 1000,
933 static int aldebaran_upload_dpm_level(struct smu_context *smu,
935 uint32_t feature_mask,
938 struct smu_13_0_dpm_context *dpm_context =
939 smu->smu_dpm.dpm_context;
943 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
944 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
945 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
946 ret = smu_cmn_send_smc_msg_with_param(smu,
947 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
948 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
951 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
952 max ? "max" : "min");
957 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
958 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
959 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
960 ret = smu_cmn_send_smc_msg_with_param(smu,
961 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
962 (PPCLK_UCLK << 16) | (freq & 0xffff),
965 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
966 max ? "max" : "min");
971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
972 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
973 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
974 ret = smu_cmn_send_smc_msg_with_param(smu,
975 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
976 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
979 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
980 max ? "max" : "min");
988 static int aldebaran_force_clk_levels(struct smu_context *smu,
989 enum smu_clk_type type, uint32_t mask)
991 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
992 struct smu_13_0_dpm_table *single_dpm_table = NULL;
993 uint32_t soft_min_level, soft_max_level;
996 soft_min_level = mask ? (ffs(mask) - 1) : 0;
997 soft_max_level = mask ? (fls(mask) - 1) : 0;
1001 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1002 if (soft_max_level >= single_dpm_table->count) {
1003 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1004 soft_max_level, single_dpm_table->count - 1);
1009 ret = aldebaran_upload_dpm_level(smu,
1011 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1014 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1018 ret = aldebaran_upload_dpm_level(smu,
1020 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1023 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1031 * Should not arrive here since aldebaran does not
1032 * support mclk/socclk/fclk softmin/softmax settings
1044 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1045 struct smu_temperature_range *range)
1047 struct smu_table_context *table_context = &smu->smu_table;
1048 struct smu_13_0_powerplay_table *powerplay_table =
1049 table_context->power_play_table;
1050 PPTable_t *pptable = smu->smu_table.driver_pptable;
1055 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1057 range->hotspot_crit_max = pptable->ThotspotLimit *
1058 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1059 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1060 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1061 range->mem_crit_max = pptable->TmemLimit *
1062 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1063 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1064 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1065 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1070 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1071 enum amd_pp_sensors sensor,
1080 case AMDGPU_PP_SENSOR_GPU_LOAD:
1081 ret = aldebaran_get_smu_metrics_data(smu,
1082 METRICS_AVERAGE_GFXACTIVITY,
1085 case AMDGPU_PP_SENSOR_MEM_LOAD:
1086 ret = aldebaran_get_smu_metrics_data(smu,
1087 METRICS_AVERAGE_MEMACTIVITY,
1091 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1098 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1099 enum amd_pp_sensors sensor,
1108 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1109 ret = aldebaran_get_smu_metrics_data(smu,
1110 METRICS_TEMPERATURE_HOTSPOT,
1113 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1114 ret = aldebaran_get_smu_metrics_data(smu,
1115 METRICS_TEMPERATURE_EDGE,
1118 case AMDGPU_PP_SENSOR_MEM_TEMP:
1119 ret = aldebaran_get_smu_metrics_data(smu,
1120 METRICS_TEMPERATURE_MEM,
1124 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1131 static int aldebaran_read_sensor(struct smu_context *smu,
1132 enum amd_pp_sensors sensor,
1133 void *data, uint32_t *size)
1137 if (amdgpu_ras_intr_triggered())
1144 case AMDGPU_PP_SENSOR_MEM_LOAD:
1145 case AMDGPU_PP_SENSOR_GPU_LOAD:
1146 ret = aldebaran_get_current_activity_percent(smu,
1151 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1152 ret = aldebaran_get_smu_metrics_data(smu,
1153 METRICS_AVERAGE_SOCKETPOWER,
1157 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1158 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1159 case AMDGPU_PP_SENSOR_MEM_TEMP:
1160 ret = aldebaran_thermal_get_temperature(smu, sensor,
1164 case AMDGPU_PP_SENSOR_GFX_MCLK:
1165 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1166 /* the output clock frequency in 10K unit */
1167 *(uint32_t *)data *= 100;
1170 case AMDGPU_PP_SENSOR_GFX_SCLK:
1171 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1172 *(uint32_t *)data *= 100;
1175 case AMDGPU_PP_SENSOR_VDDGFX:
1176 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1179 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1188 static int aldebaran_get_power_limit(struct smu_context *smu,
1189 uint32_t *current_power_limit,
1190 uint32_t *default_power_limit,
1191 uint32_t *max_power_limit)
1193 PPTable_t *pptable = smu->smu_table.driver_pptable;
1194 uint32_t power_limit = 0;
1197 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1198 if (current_power_limit)
1199 *current_power_limit = 0;
1200 if (default_power_limit)
1201 *default_power_limit = 0;
1202 if (max_power_limit)
1203 *max_power_limit = 0;
1205 dev_warn(smu->adev->dev,
1206 "PPT feature is not enabled, power values can't be fetched.");
1211 /* Valid power data is available only from primary die.
1212 * For secondary die show the value as 0.
1214 if (aldebaran_is_primary(smu)) {
1215 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1219 /* the last hope to figure out the ppt limit */
1221 dev_err(smu->adev->dev,
1222 "Cannot get PPT limit due to pptable missing!");
1225 power_limit = pptable->PptLimit;
1229 if (current_power_limit)
1230 *current_power_limit = power_limit;
1231 if (default_power_limit)
1232 *default_power_limit = power_limit;
1234 if (max_power_limit) {
1236 *max_power_limit = pptable->PptLimit;
1242 static int aldebaran_set_power_limit(struct smu_context *smu,
1243 enum smu_ppt_limit_type limit_type,
1246 /* Power limit can be set only through primary die */
1247 if (aldebaran_is_primary(smu))
1248 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1253 static int aldebaran_system_features_control(struct smu_context *smu, bool enable)
1257 ret = smu_v13_0_system_features_control(smu, enable);
1259 ret = aldebaran_run_btc(smu);
1264 static int aldebaran_set_performance_level(struct smu_context *smu,
1265 enum amd_dpm_forced_level level)
1267 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1268 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1269 struct smu_13_0_dpm_table *gfx_table =
1270 &dpm_context->dpm_tables.gfx_table;
1271 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1273 /* Disable determinism if switching to another mode */
1274 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1275 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1276 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1277 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1282 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1285 case AMD_DPM_FORCED_LEVEL_HIGH:
1286 case AMD_DPM_FORCED_LEVEL_LOW:
1287 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1288 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1289 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1290 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1295 return smu_v13_0_set_performance_level(smu, level);
1298 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1299 enum smu_clk_type clk_type,
1303 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1304 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1305 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1306 struct amdgpu_device *adev = smu->adev;
1311 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1314 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1315 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1318 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1320 dev_err(smu->adev->dev,
1321 "Minimum GFX clk should be less than the maximum allowed clock\n");
1325 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1326 (max == pstate_table->gfxclk_pstate.curr.max))
1329 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1332 pstate_table->gfxclk_pstate.curr.min = min;
1333 pstate_table->gfxclk_pstate.curr.max = max;
1339 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1340 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1341 (max > dpm_context->dpm_tables.gfx_table.max)) {
1343 "Invalid max frequency %d MHz specified for determinism\n", max);
1347 /* Restore default min/max clocks and enable determinism */
1348 min_clk = dpm_context->dpm_tables.gfx_table.min;
1349 max_clk = dpm_context->dpm_tables.gfx_table.max;
1350 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1352 usleep_range(500, 1000);
1353 ret = smu_cmn_send_smc_msg_with_param(smu,
1354 SMU_MSG_EnableDeterminism,
1358 "Failed to enable determinism at GFX clock %d MHz\n", max);
1360 pstate_table->gfxclk_pstate.curr.min = min_clk;
1361 pstate_table->gfxclk_pstate.curr.max = max;
1369 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1370 long input[], uint32_t size)
1372 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1373 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1374 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1379 /* Only allowed in manual or determinism mode */
1380 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1381 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1385 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1387 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1391 if (input[0] == 0) {
1392 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1393 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1394 input[1], dpm_context->dpm_tables.gfx_table.min);
1395 pstate_table->gfxclk_pstate.custom.min =
1396 pstate_table->gfxclk_pstate.curr.min;
1400 pstate_table->gfxclk_pstate.custom.min = input[1];
1401 } else if (input[0] == 1) {
1402 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1403 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1404 input[1], dpm_context->dpm_tables.gfx_table.max);
1405 pstate_table->gfxclk_pstate.custom.max =
1406 pstate_table->gfxclk_pstate.curr.max;
1410 pstate_table->gfxclk_pstate.custom.max = input[1];
1415 case PP_OD_RESTORE_DEFAULT_TABLE:
1417 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1420 /* Use the default frequencies for manual and determinism mode */
1421 min_clk = dpm_context->dpm_tables.gfx_table.min;
1422 max_clk = dpm_context->dpm_tables.gfx_table.max;
1424 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1427 case PP_OD_COMMIT_DPM_TABLE:
1429 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1432 if (!pstate_table->gfxclk_pstate.custom.min)
1433 pstate_table->gfxclk_pstate.custom.min =
1434 pstate_table->gfxclk_pstate.curr.min;
1436 if (!pstate_table->gfxclk_pstate.custom.max)
1437 pstate_table->gfxclk_pstate.custom.max =
1438 pstate_table->gfxclk_pstate.curr.max;
1440 min_clk = pstate_table->gfxclk_pstate.custom.min;
1441 max_clk = pstate_table->gfxclk_pstate.custom.max;
1443 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1453 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1456 uint64_t feature_enabled;
1458 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1461 return !!(feature_enabled & SMC_DPM_FEATURE);
1464 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1465 struct i2c_msg *msg, int num_msgs)
1467 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1468 struct amdgpu_device *adev = smu_i2c->adev;
1469 struct smu_context *smu = adev->powerplay.pp_handle;
1470 struct smu_table_context *smu_table = &smu->smu_table;
1471 struct smu_table *table = &smu_table->driver_table;
1472 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1476 if (!adev->pm.dpm_enabled)
1479 req = kzalloc(sizeof(*req), GFP_KERNEL);
1483 req->I2CcontrollerPort = smu_i2c->port;
1484 req->I2CSpeed = I2C_SPEED_FAST_400K;
1485 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1486 dir = msg[0].flags & I2C_M_RD;
1488 for (c = i = 0; i < num_msgs; i++) {
1489 for (j = 0; j < msg[i].len; j++, c++) {
1490 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1492 if (!(msg[i].flags & I2C_M_RD)) {
1494 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1495 cmd->ReadWriteData = msg[i].buf[j];
1498 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1499 /* The direction changes.
1501 dir = msg[i].flags & I2C_M_RD;
1502 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1508 * Insert STOP if we are at the last byte of either last
1509 * message for the transaction or the client explicitly
1510 * requires a STOP at this particular message.
1512 if ((j == msg[i].len - 1) &&
1513 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1514 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1515 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1519 mutex_lock(&adev->pm.mutex);
1520 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1524 for (c = i = 0; i < num_msgs; i++) {
1525 if (!(msg[i].flags & I2C_M_RD)) {
1529 for (j = 0; j < msg[i].len; j++, c++) {
1530 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1532 msg[i].buf[j] = cmd->ReadWriteData;
1537 mutex_unlock(&adev->pm.mutex);
1542 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1544 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1548 static const struct i2c_algorithm aldebaran_i2c_algo = {
1549 .master_xfer = aldebaran_i2c_xfer,
1550 .functionality = aldebaran_i2c_func,
1553 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1554 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1555 .max_read_len = MAX_SW_I2C_COMMANDS,
1556 .max_write_len = MAX_SW_I2C_COMMANDS,
1557 .max_comb_1st_msg_len = 2,
1558 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1561 static int aldebaran_i2c_control_init(struct smu_context *smu)
1563 struct amdgpu_device *adev = smu->adev;
1564 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
1565 struct i2c_adapter *control = &smu_i2c->adapter;
1568 smu_i2c->adev = adev;
1570 mutex_init(&smu_i2c->mutex);
1571 control->owner = THIS_MODULE;
1572 control->class = I2C_CLASS_SPD;
1573 control->dev.parent = &adev->pdev->dev;
1574 control->algo = &aldebaran_i2c_algo;
1575 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0");
1576 control->quirks = &aldebaran_i2c_control_quirks;
1577 i2c_set_adapdata(control, smu_i2c);
1579 res = i2c_add_adapter(control);
1581 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1585 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1586 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1590 i2c_del_adapter(control);
1595 static void aldebaran_i2c_control_fini(struct smu_context *smu)
1597 struct amdgpu_device *adev = smu->adev;
1600 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1601 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1602 struct i2c_adapter *control = &smu_i2c->adapter;
1604 i2c_del_adapter(control);
1606 adev->pm.ras_eeprom_i2c_bus = NULL;
1607 adev->pm.fru_eeprom_i2c_bus = NULL;
1610 static void aldebaran_get_unique_id(struct smu_context *smu)
1612 struct amdgpu_device *adev = smu->adev;
1613 uint32_t upper32 = 0, lower32 = 0;
1615 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1617 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1621 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1622 if (adev->serial[0] == '\0')
1623 sprintf(adev->serial, "%016llx", adev->unique_id);
1626 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1628 /* aldebaran is not support baco */
1633 static int aldebaran_set_df_cstate(struct smu_context *smu,
1634 enum pp_df_cstate state)
1636 struct amdgpu_device *adev = smu->adev;
1639 * Aldebaran does not need the cstate disablement
1640 * prerequisite for gpu reset.
1642 if (amdgpu_in_reset(adev) || adev->in_suspend)
1645 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1648 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1650 struct amdgpu_device *adev = smu->adev;
1652 /* The message only works on master die and NACK will be sent
1653 back for other dies, only send it on master die */
1654 if (!adev->smuio.funcs->get_socket_id(adev) &&
1655 !adev->smuio.funcs->get_die_id(adev))
1656 return smu_cmn_send_smc_msg_with_param(smu,
1657 SMU_MSG_GmiPwrDnControl,
1664 static const struct throttling_logging_label {
1665 uint32_t feature_mask;
1667 } logging_label[] = {
1668 {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"},
1669 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1670 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1671 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1672 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1674 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1677 int throttler_idx, throtting_events = 0, buf_idx = 0;
1678 struct amdgpu_device *adev = smu->adev;
1679 uint32_t throttler_status;
1682 ret = aldebaran_get_smu_metrics_data(smu,
1683 METRICS_THROTTLER_STATUS,
1688 memset(log_buf, 0, sizeof(log_buf));
1689 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1691 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1693 buf_idx += snprintf(log_buf + buf_idx,
1694 sizeof(log_buf) - buf_idx,
1696 throtting_events > 1 ? " and " : "",
1697 logging_label[throttler_idx].label);
1698 if (buf_idx >= sizeof(log_buf)) {
1699 dev_err(adev->dev, "buffer overflow!\n");
1700 log_buf[sizeof(log_buf) - 1] = '\0';
1706 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1708 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1709 smu_cmn_get_indep_throttler_status(throttler_status,
1710 aldebaran_throttler_map));
1713 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1715 struct amdgpu_device *adev = smu->adev;
1718 /* TODO: confirm this on real target */
1719 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1720 if ((esm_ctrl >> 15) & 0x1FFFF)
1721 return (((esm_ctrl >> 8) & 0x3F) + 128);
1723 return smu_v13_0_get_current_pcie_link_speed(smu);
1726 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1729 struct smu_table_context *smu_table = &smu->smu_table;
1730 struct gpu_metrics_v1_3 *gpu_metrics =
1731 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1732 SmuMetrics_t metrics;
1735 ret = smu_cmn_get_metrics_table(smu,
1741 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1743 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1744 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1745 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1746 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1747 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1748 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1750 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1751 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1752 gpu_metrics->average_mm_activity = 0;
1754 /* Valid power data is available only from primary die */
1755 if (aldebaran_is_primary(smu)) {
1756 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1757 gpu_metrics->energy_accumulator =
1758 (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1759 metrics.EnergyAcc64bitLow;
1761 gpu_metrics->average_socket_power = 0;
1762 gpu_metrics->energy_accumulator = 0;
1765 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1766 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1767 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1768 gpu_metrics->average_vclk0_frequency = 0;
1769 gpu_metrics->average_dclk0_frequency = 0;
1771 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1772 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1773 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1774 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1775 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1777 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1778 gpu_metrics->indep_throttle_status =
1779 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1780 aldebaran_throttler_map);
1782 gpu_metrics->current_fan_speed = 0;
1784 gpu_metrics->pcie_link_width =
1785 smu_v13_0_get_current_pcie_link_width(smu);
1786 gpu_metrics->pcie_link_speed =
1787 aldebaran_get_current_pcie_link_speed(smu);
1789 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1791 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1792 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1794 for (i = 0; i < NUM_HBM_INSTANCES; i++)
1795 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1797 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1798 metrics.TimeStampLow;
1800 *table = (void *)gpu_metrics;
1802 return sizeof(struct gpu_metrics_v1_3);
1805 static int aldebaran_check_ecc_table_support(struct smu_context *smu,
1806 int *ecctable_version)
1808 uint32_t if_version = 0xff, smu_version = 0xff;
1811 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
1813 /* return not support if failed get smu_version */
1817 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
1819 else if (smu_version >= SUPPORT_ECCTABLE_SMU_VERSION &&
1820 smu_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)
1821 *ecctable_version = 1;
1823 *ecctable_version = 2;
1828 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
1831 struct smu_table_context *smu_table = &smu->smu_table;
1832 EccInfoTable_t *ecc_table = NULL;
1833 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
1835 int table_version = 0;
1836 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
1838 ret = aldebaran_check_ecc_table_support(smu, &table_version);
1842 ret = smu_cmn_update_table(smu,
1845 smu_table->ecc_table,
1848 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
1852 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
1854 if (table_version == 1) {
1855 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1856 ecc_info_per_channel = &(eccinfo->ecc[i]);
1857 ecc_info_per_channel->ce_count_lo_chip =
1858 ecc_table->EccInfo[i].ce_count_lo_chip;
1859 ecc_info_per_channel->ce_count_hi_chip =
1860 ecc_table->EccInfo[i].ce_count_hi_chip;
1861 ecc_info_per_channel->mca_umc_status =
1862 ecc_table->EccInfo[i].mca_umc_status;
1863 ecc_info_per_channel->mca_umc_addr =
1864 ecc_table->EccInfo[i].mca_umc_addr;
1866 } else if (table_version == 2) {
1867 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1868 ecc_info_per_channel = &(eccinfo->ecc[i]);
1869 ecc_info_per_channel->ce_count_lo_chip =
1870 ecc_table->EccInfo_V2[i].ce_count_lo_chip;
1871 ecc_info_per_channel->ce_count_hi_chip =
1872 ecc_table->EccInfo_V2[i].ce_count_hi_chip;
1873 ecc_info_per_channel->mca_umc_status =
1874 ecc_table->EccInfo_V2[i].mca_umc_status;
1875 ecc_info_per_channel->mca_umc_addr =
1876 ecc_table->EccInfo_V2[i].mca_umc_addr;
1877 ecc_info_per_channel->mca_ceumc_addr =
1878 ecc_table->EccInfo_V2[i].mca_ceumc_addr;
1880 eccinfo->record_ce_addr_supported = 1;
1886 static int aldebaran_mode1_reset(struct smu_context *smu)
1888 u32 smu_version, fatal_err, param;
1890 struct amdgpu_device *adev = smu->adev;
1891 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1894 param = SMU_RESET_MODE_1;
1897 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1899 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1900 if (smu_version < 0x00440700) {
1901 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1903 /* fatal error triggered by ras, PMFW supports the flag
1905 if ((smu_version >= 0x00442c00) && ras &&
1906 atomic_read(&ras->in_recovery))
1909 param |= (fatal_err << 16);
1910 ret = smu_cmn_send_smc_msg_with_param(smu,
1911 SMU_MSG_GfxDeviceDriverReset, param, NULL);
1915 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1920 static int aldebaran_mode2_reset(struct smu_context *smu)
1924 struct amdgpu_device *adev = smu->adev;
1927 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1929 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1930 SMU_MSG_GfxDeviceDriverReset);
1932 mutex_lock(&smu->message_lock);
1933 if (smu_version >= 0x00441400) {
1934 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1935 /* This is similar to FLR, wait till max FLR timeout */
1937 dev_dbg(smu->adev->dev, "restore config space...\n");
1938 /* Restore the config space saved during init */
1939 amdgpu_device_load_pci_state(adev->pdev);
1941 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1942 while (ret == -ETIME && timeout) {
1943 ret = smu_cmn_wait_for_response(smu);
1944 /* Wait a bit more time for getting ACK */
1945 if (ret == -ETIME) {
1947 usleep_range(500, 1000);
1952 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1953 SMU_RESET_MODE_2, ret);
1959 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1966 mutex_unlock(&smu->message_lock);
1971 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1974 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
1979 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1982 struct amdgpu_device *adev = smu->adev;
1986 * PM FW version support mode1 reset from 68.07
1988 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1989 if ((smu_version < 0x00440700))
1992 * mode1 reset relies on PSP, so we should check if
1995 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
2002 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
2007 static int aldebaran_set_mp1_state(struct smu_context *smu,
2008 enum pp_mp1_state mp1_state)
2010 switch (mp1_state) {
2011 case PP_MP1_STATE_UNLOAD:
2012 return smu_cmn_set_mp1_state(smu, mp1_state);
2018 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
2023 /* message SMU to update the bad page number on SMUBUS */
2024 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
2026 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
2032 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu)
2034 uint32_t if_version = 0xff, smu_version = 0xff;
2037 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
2039 /* return not support if failed get smu_version */
2043 if (smu_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION)
2049 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu,
2054 ret = aldebaran_check_bad_channel_info_support(smu);
2058 /* message SMU to update the bad channel info on SMUBUS */
2059 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL);
2061 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n",
2067 static const struct pptable_funcs aldebaran_ppt_funcs = {
2069 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
2070 /* dpm/clk tables */
2071 .set_default_dpm_table = aldebaran_set_default_dpm_table,
2072 .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
2073 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
2074 .print_clk_levels = aldebaran_print_clk_levels,
2075 .force_clk_levels = aldebaran_force_clk_levels,
2076 .read_sensor = aldebaran_read_sensor,
2077 .set_performance_level = aldebaran_set_performance_level,
2078 .get_power_limit = aldebaran_get_power_limit,
2079 .is_dpm_running = aldebaran_is_dpm_running,
2080 .get_unique_id = aldebaran_get_unique_id,
2081 .init_microcode = smu_v13_0_init_microcode,
2082 .load_microcode = smu_v13_0_load_microcode,
2083 .fini_microcode = smu_v13_0_fini_microcode,
2084 .init_smc_tables = aldebaran_init_smc_tables,
2085 .fini_smc_tables = smu_v13_0_fini_smc_tables,
2086 .init_power = smu_v13_0_init_power,
2087 .fini_power = smu_v13_0_fini_power,
2088 .check_fw_status = smu_v13_0_check_fw_status,
2089 /* pptable related */
2090 .setup_pptable = aldebaran_setup_pptable,
2091 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2092 .check_fw_version = smu_v13_0_check_fw_version,
2093 .write_pptable = smu_cmn_write_pptable,
2094 .set_driver_table_location = smu_v13_0_set_driver_table_location,
2095 .set_tool_table_location = smu_v13_0_set_tool_table_location,
2096 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2097 .system_features_control = aldebaran_system_features_control,
2098 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2099 .send_smc_msg = smu_cmn_send_smc_msg,
2100 .get_enabled_mask = smu_cmn_get_enabled_mask,
2101 .feature_is_enabled = smu_cmn_feature_is_enabled,
2102 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2103 .set_power_limit = aldebaran_set_power_limit,
2104 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
2105 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2106 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2107 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
2108 .register_irq_handler = smu_v13_0_register_irq_handler,
2109 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
2110 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
2111 .baco_is_support = aldebaran_is_baco_supported,
2112 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
2113 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
2114 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
2115 .set_df_cstate = aldebaran_set_df_cstate,
2116 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
2117 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
2118 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2119 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2120 .get_gpu_metrics = aldebaran_get_gpu_metrics,
2121 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
2122 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
2123 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
2124 .mode1_reset = aldebaran_mode1_reset,
2125 .set_mp1_state = aldebaran_set_mp1_state,
2126 .mode2_reset = aldebaran_mode2_reset,
2127 .wait_for_event = smu_v13_0_wait_for_event,
2128 .i2c_init = aldebaran_i2c_control_init,
2129 .i2c_fini = aldebaran_i2c_control_fini,
2130 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2131 .get_ecc_info = aldebaran_get_ecc_info,
2132 .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag,
2135 void aldebaran_set_ppt_funcs(struct smu_context *smu)
2137 smu->ppt_funcs = &aldebaran_ppt_funcs;
2138 smu->message_map = aldebaran_message_map;
2139 smu->clock_map = aldebaran_clk_map;
2140 smu->feature_map = aldebaran_feature_mask_map;
2141 smu->table_map = aldebaran_table_map;
2142 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
2143 smu_v13_0_set_smu_mailbox_registers(smu);