drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v13_0.h"
  33 #include "smu13_driver_if_aldebaran.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "aldebaran_ppt.h"
  38 #include "smu_v13_0_pptable.h"
  39 #include "aldebaran_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/pci.h>
  46 #include "amdgpu_ras.h"
  47 #include "smu_cmn.h"
  48 #include "mp/mp_13_0_2_offset.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
  63         [smu_feature] = {1, (aldebaran_feature)}
  64
  65 #define FEATURE_MASK(feature) (1ULL << feature)
  66 #define SMC_DPM_FEATURE ( \
  67                           FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
  68                           FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)  | \
  69                           FEATURE_MASK(FEATURE_DPM_UCLK_BIT)    | \
  70                           FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)  | \
  71                           FEATURE_MASK(FEATURE_DPM_FCLK_BIT)    | \
  72                           FEATURE_MASK(FEATURE_DPM_LCLK_BIT)    | \
  73                           FEATURE_MASK(FEATURE_DPM_XGMI_BIT)    | \
  74                           FEATURE_MASK(FEATURE_DPM_VCN_BIT))
  75
  76 /* possible frequency drift (1Mhz) */
  77 #define EPSILON                         1
  78
  79 #define smnPCIE_ESM_CTRL                        0x111003D0
  80
  81 static const struct smu_temperature_range smu13_thermal_policy[] =
  82 {
  83         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
  84         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
  85 };
  86
  87 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
  88         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  89         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  90         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  91         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  92         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  93         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        1),
  94         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       1),
  95         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  96         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
  97         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
  98         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
  99         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 100         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 101         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 102         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 103         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 104         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 105         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 106         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 107         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 108         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 109         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 110         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 111         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 112         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 113         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 114         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 115         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 116         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 117         MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  0),
 118         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 119         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 120         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 121         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 122         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 123         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 124         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 125         MSG_MAP(SetNumBadHbmPagesRetired,            PPSMC_MSG_SetNumBadHbmPagesRetired,        0),
 126         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 127         MSG_MAP(GetGmiPwrDnHyst,                     PPSMC_MSG_GetGmiPwrDnHyst,                 0),
 128         MSG_MAP(SetGmiPwrDnHyst,                     PPSMC_MSG_SetGmiPwrDnHyst,                 0),
 129         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 130         MSG_MAP(EnterGfxoff,                         PPSMC_MSG_EnterGfxoff,                     0),
 131         MSG_MAP(ExitGfxoff,                          PPSMC_MSG_ExitGfxoff,                      0),
 132         MSG_MAP(SetExecuteDMATest,                   PPSMC_MSG_SetExecuteDMATest,               0),
 133         MSG_MAP(EnableDeterminism,                   PPSMC_MSG_EnableDeterminism,               0),
 134         MSG_MAP(DisableDeterminism,                  PPSMC_MSG_DisableDeterminism,              0),
 135         MSG_MAP(SetUclkDpmMode,                      PPSMC_MSG_SetUclkDpmMode,                  0),
 136         MSG_MAP(GfxDriverResetRecovery,              PPSMC_MSG_GfxDriverResetRecovery,          0),
 137         MSG_MAP(BoardPowerCalibration,               PPSMC_MSG_BoardPowerCalibration,           0),
 138 };
 139
 140 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
 141         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 142         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 143         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 144         CLK_MAP(FCLK, PPCLK_FCLK),
 145         CLK_MAP(UCLK, PPCLK_UCLK),
 146         CLK_MAP(MCLK, PPCLK_UCLK),
 147         CLK_MAP(DCLK, PPCLK_DCLK),
 148         CLK_MAP(VCLK, PPCLK_VCLK),
 149         CLK_MAP(LCLK,   PPCLK_LCLK),
 150 };
 151
 152 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
 153         ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT,            FEATURE_DATA_CALCULATIONS),
 154         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT,                   FEATURE_DPM_GFXCLK_BIT),
 155         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT,                     FEATURE_DPM_UCLK_BIT),
 156         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,                   FEATURE_DPM_SOCCLK_BIT),
 157         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT,                     FEATURE_DPM_FCLK_BIT),
 158         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT,                     FEATURE_DPM_LCLK_BIT),
 159         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT,                             FEATURE_DPM_XGMI_BIT),
 160         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT,                    FEATURE_DS_GFXCLK_BIT),
 161         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT,                    FEATURE_DS_SOCCLK_BIT),
 162         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT,                              FEATURE_DS_LCLK_BIT),
 163         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT,                              FEATURE_DS_FCLK_BIT),
 164         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,                              FEATURE_DS_UCLK_BIT),
 165         ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT,                               FEATURE_GFX_SS_BIT),
 166         ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT,                              FEATURE_DPM_VCN_BIT),
 167         ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT,                  FEATURE_RSMU_SMN_CG_BIT),
 168         ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT,                              FEATURE_WAFL_CG_BIT),
 169         ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT,                                  FEATURE_PPT_BIT),
 170         ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT,                                  FEATURE_TDC_BIT),
 171         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT,                    FEATURE_APCC_PLUS_BIT),
 172         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT,                    FEATURE_APCC_DFLL_BIT),
 173         ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT,                              FEATURE_FUSE_CG_BIT),
 174         ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT,                               FEATURE_MP1_CG_BIT),
 175         ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT,                     FEATURE_SMUIO_CG_BIT),
 176         ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT,                               FEATURE_THM_CG_BIT),
 177         ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT,                               FEATURE_CLK_CG_BIT),
 178         ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT,                               FEATURE_FW_CTF_BIT),
 179         ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT,                              FEATURE_THERMAL_BIT),
 180         ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,  FEATURE_OUT_OF_BAND_MONITOR_BIT),
 181         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN),
 182         ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT,                    FEATURE_DF_CSTATE),
 183 };
 184
 185 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
 186         TAB_MAP(PPTABLE),
 187         TAB_MAP(AVFS_PSM_DEBUG),
 188         TAB_MAP(AVFS_FUSE_OVERRIDE),
 189         TAB_MAP(PMSTATUSLOG),
 190         TAB_MAP(SMU_METRICS),
 191         TAB_MAP(DRIVER_SMU_CONFIG),
 192         TAB_MAP(I2C_COMMANDS),
 193 };
 194
 195 static const uint8_t aldebaran_throttler_map[] = {
 196         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 197         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 198         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 199         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 200         [THROTTLER_TDC_HBM_BIT]         = (SMU_THROTTLER_TDC_MEM_BIT),
 201         [THROTTLER_TEMP_GPU_BIT]        = (SMU_THROTTLER_TEMP_GPU_BIT),
 202         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 203         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 204         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 205         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 206         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 207 };
 208
 209 static int aldebaran_tables_init(struct smu_context *smu)
 210 {
 211         struct smu_table_context *smu_table = &smu->smu_table;
 212         struct smu_table *tables = smu_table->tables;
 213
 214         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 215                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 216
 217         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 218                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 219
 220         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 221                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 222
 223         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 224                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 225
 226         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 227         if (!smu_table->metrics_table)
 228                 return -ENOMEM;
 229         smu_table->metrics_time = 0;
 230
 231         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 232         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 233         if (!smu_table->gpu_metrics_table) {
 234                 kfree(smu_table->metrics_table);
 235                 return -ENOMEM;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
 242 {
 243         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 244
 245         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 246                                        GFP_KERNEL);
 247         if (!smu_dpm->dpm_context)
 248                 return -ENOMEM;
 249         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 250
 251         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 252                                                    GFP_KERNEL);
 253         if (!smu_dpm->dpm_current_power_state)
 254                 return -ENOMEM;
 255
 256         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 257                                                    GFP_KERNEL);
 258         if (!smu_dpm->dpm_request_power_state)
 259                 return -ENOMEM;
 260
 261         return 0;
 262 }
 263
 264 static int aldebaran_init_smc_tables(struct smu_context *smu)
 265 {
 266         int ret = 0;
 267
 268         ret = aldebaran_tables_init(smu);
 269         if (ret)
 270                 return ret;
 271
 272         ret = aldebaran_allocate_dpm_context(smu);
 273         if (ret)
 274                 return ret;
 275
 276         return smu_v13_0_init_smc_tables(smu);
 277 }
 278
 279 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
 280                                               uint32_t *feature_mask, uint32_t num)
 281 {
 282         if (num > 2)
 283                 return -EINVAL;
 284
 285         /* pptable will handle the features to enable */
 286         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 287
 288         return 0;
 289 }
 290
 291 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
 292 {
 293         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 294         struct smu_13_0_dpm_table *dpm_table = NULL;
 295         PPTable_t *pptable = smu->smu_table.driver_pptable;
 296         int ret = 0;
 297
 298         /* socclk dpm table setup */
 299         dpm_table = &dpm_context->dpm_tables.soc_table;
 300         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 301                 ret = smu_v13_0_set_single_dpm_table(smu,
 302                                                      SMU_SOCCLK,
 303                                                      dpm_table);
 304                 if (ret)
 305                         return ret;
 306         } else {
 307                 dpm_table->count = 1;
 308                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 309                 dpm_table->dpm_levels[0].enabled = true;
 310                 dpm_table->min = dpm_table->dpm_levels[0].value;
 311                 dpm_table->max = dpm_table->dpm_levels[0].value;
 312         }
 313
 314         /* gfxclk dpm table setup */
 315         dpm_table = &dpm_context->dpm_tables.gfx_table;
 316         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 317                 /* in the case of gfxclk, only fine-grained dpm is honored */
 318                 dpm_table->count = 2;
 319                 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
 320                 dpm_table->dpm_levels[0].enabled = true;
 321                 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
 322                 dpm_table->dpm_levels[1].enabled = true;
 323                 dpm_table->min = dpm_table->dpm_levels[0].value;
 324                 dpm_table->max = dpm_table->dpm_levels[1].value;
 325         } else {
 326                 dpm_table->count = 1;
 327                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 328                 dpm_table->dpm_levels[0].enabled = true;
 329                 dpm_table->min = dpm_table->dpm_levels[0].value;
 330                 dpm_table->max = dpm_table->dpm_levels[0].value;
 331         }
 332
 333         /* memclk dpm table setup */
 334         dpm_table = &dpm_context->dpm_tables.uclk_table;
 335         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 336                 ret = smu_v13_0_set_single_dpm_table(smu,
 337                                                      SMU_UCLK,
 338                                                      dpm_table);
 339                 if (ret)
 340                         return ret;
 341         } else {
 342                 dpm_table->count = 1;
 343                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 344                 dpm_table->dpm_levels[0].enabled = true;
 345                 dpm_table->min = dpm_table->dpm_levels[0].value;
 346                 dpm_table->max = dpm_table->dpm_levels[0].value;
 347         }
 348
 349         /* fclk dpm table setup */
 350         dpm_table = &dpm_context->dpm_tables.fclk_table;
 351         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 352                 ret = smu_v13_0_set_single_dpm_table(smu,
 353                                                      SMU_FCLK,
 354                                                      dpm_table);
 355                 if (ret)
 356                         return ret;
 357         } else {
 358                 dpm_table->count = 1;
 359                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 360                 dpm_table->dpm_levels[0].enabled = true;
 361                 dpm_table->min = dpm_table->dpm_levels[0].value;
 362                 dpm_table->max = dpm_table->dpm_levels[0].value;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static int aldebaran_check_powerplay_table(struct smu_context *smu)
 369 {
 370         struct smu_table_context *table_context = &smu->smu_table;
 371         struct smu_13_0_powerplay_table *powerplay_table =
 372                 table_context->power_play_table;
 373
 374         table_context->thermal_controller_type =
 375                 powerplay_table->thermal_controller_type;
 376
 377         return 0;
 378 }
 379
 380 static int aldebaran_store_powerplay_table(struct smu_context *smu)
 381 {
 382         struct smu_table_context *table_context = &smu->smu_table;
 383         struct smu_13_0_powerplay_table *powerplay_table =
 384                 table_context->power_play_table;
 385         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 386                sizeof(PPTable_t));
 387
 388         return 0;
 389 }
 390
 391 static int aldebaran_append_powerplay_table(struct smu_context *smu)
 392 {
 393         struct smu_table_context *table_context = &smu->smu_table;
 394         PPTable_t *smc_pptable = table_context->driver_pptable;
 395         struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
 396         int index, ret;
 397
 398         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 399                                            smc_dpm_info);
 400
 401         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 402                                       (uint8_t **)&smc_dpm_table);
 403         if (ret)
 404                 return ret;
 405
 406         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 407                         smc_dpm_table->table_header.format_revision,
 408                         smc_dpm_table->table_header.content_revision);
 409
 410         if ((smc_dpm_table->table_header.format_revision == 4) &&
 411             (smc_dpm_table->table_header.content_revision == 10))
 412                 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
 413                                     smc_dpm_table, GfxMaxCurrent);
 414         return 0;
 415 }
 416
 417 static int aldebaran_setup_pptable(struct smu_context *smu)
 418 {
 419         int ret = 0;
 420
 421         /* VBIOS pptable is the first choice */
 422         smu->smu_table.boot_values.pp_table_id = 0;
 423
 424         ret = smu_v13_0_setup_pptable(smu);
 425         if (ret)
 426                 return ret;
 427
 428         ret = aldebaran_store_powerplay_table(smu);
 429         if (ret)
 430                 return ret;
 431
 432         ret = aldebaran_append_powerplay_table(smu);
 433         if (ret)
 434                 return ret;
 435
 436         ret = aldebaran_check_powerplay_table(smu);
 437         if (ret)
 438                 return ret;
 439
 440         return ret;
 441 }
 442
 443 static bool aldebaran_is_primary(struct smu_context *smu)
 444 {
 445         struct amdgpu_device *adev = smu->adev;
 446
 447         if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
 448                 return adev->smuio.funcs->get_die_id(adev) == 0;
 449
 450         return true;
 451 }
 452
 453 static int aldebaran_run_board_btc(struct smu_context *smu)
 454 {
 455         u32 smu_version;
 456         int ret;
 457
 458         if (!aldebaran_is_primary(smu))
 459                 return 0;
 460
 461         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 462         if (ret) {
 463                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 464                 return ret;
 465         }
 466         if (smu_version <= 0x00441d00)
 467                 return 0;
 468
 469         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
 470         if (ret)
 471                 dev_err(smu->adev->dev, "Board power calibration failed!\n");
 472
 473         return ret;
 474 }
 475
 476 static int aldebaran_run_btc(struct smu_context *smu)
 477 {
 478         int ret;
 479
 480         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 481         if (ret)
 482                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
 483         else
 484                 ret = aldebaran_run_board_btc(smu);
 485
 486         return ret;
 487 }
 488
 489 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
 490 {
 491         struct smu_13_0_dpm_context *dpm_context =
 492                 smu->smu_dpm.dpm_context;
 493         struct smu_13_0_dpm_table *gfx_table =
 494                 &dpm_context->dpm_tables.gfx_table;
 495         struct smu_13_0_dpm_table *mem_table =
 496                 &dpm_context->dpm_tables.uclk_table;
 497         struct smu_13_0_dpm_table *soc_table =
 498                 &dpm_context->dpm_tables.soc_table;
 499         struct smu_umd_pstate_table *pstate_table =
 500                 &smu->pstate_table;
 501
 502         pstate_table->gfxclk_pstate.min = gfx_table->min;
 503         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 504         pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
 505         pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
 506
 507         pstate_table->uclk_pstate.min = mem_table->min;
 508         pstate_table->uclk_pstate.peak = mem_table->max;
 509         pstate_table->uclk_pstate.curr.min = mem_table->min;
 510         pstate_table->uclk_pstate.curr.max = mem_table->max;
 511
 512         pstate_table->socclk_pstate.min = soc_table->min;
 513         pstate_table->socclk_pstate.peak = soc_table->max;
 514         pstate_table->socclk_pstate.curr.min = soc_table->min;
 515         pstate_table->socclk_pstate.curr.max = soc_table->max;
 516
 517         if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
 518             mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
 519             soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
 520                 pstate_table->gfxclk_pstate.standard =
 521                         gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
 522                 pstate_table->uclk_pstate.standard =
 523                         mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
 524                 pstate_table->socclk_pstate.standard =
 525                         soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
 526         } else {
 527                 pstate_table->gfxclk_pstate.standard =
 528                         pstate_table->gfxclk_pstate.min;
 529                 pstate_table->uclk_pstate.standard =
 530                         pstate_table->uclk_pstate.min;
 531                 pstate_table->socclk_pstate.standard =
 532                         pstate_table->socclk_pstate.min;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int aldebaran_get_clk_table(struct smu_context *smu,
 539                                    struct pp_clock_levels_with_latency *clocks,
 540                                    struct smu_13_0_dpm_table *dpm_table)
 541 {
 542         int i, count;
 543
 544         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 545         clocks->num_levels = count;
 546
 547         for (i = 0; i < count; i++) {
 548                 clocks->data[i].clocks_in_khz =
 549                         dpm_table->dpm_levels[i].value * 1000;
 550                 clocks->data[i].latency_in_us = 0;
 551         }
 552
 553         return 0;
 554 }
 555
 556 static int aldebaran_freqs_in_same_level(int32_t frequency1,
 557                                          int32_t frequency2)
 558 {
 559         return (abs(frequency1 - frequency2) <= EPSILON);
 560 }
 561
 562 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 563                                           MetricsMember_t member,
 564                                           uint32_t *value)
 565 {
 566         struct smu_table_context *smu_table= &smu->smu_table;
 567         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 568         int ret = 0;
 569
 570         mutex_lock(&smu->metrics_lock);
 571
 572         ret = smu_cmn_get_metrics_table_locked(smu,
 573                                                NULL,
 574                                                false);
 575         if (ret) {
 576                 mutex_unlock(&smu->metrics_lock);
 577                 return ret;
 578         }
 579
 580         switch (member) {
 581         case METRICS_CURR_GFXCLK:
 582                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 583                 break;
 584         case METRICS_CURR_SOCCLK:
 585                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 586                 break;
 587         case METRICS_CURR_UCLK:
 588                 *value = metrics->CurrClock[PPCLK_UCLK];
 589                 break;
 590         case METRICS_CURR_VCLK:
 591                 *value = metrics->CurrClock[PPCLK_VCLK];
 592                 break;
 593         case METRICS_CURR_DCLK:
 594                 *value = metrics->CurrClock[PPCLK_DCLK];
 595                 break;
 596         case METRICS_CURR_FCLK:
 597                 *value = metrics->CurrClock[PPCLK_FCLK];
 598                 break;
 599         case METRICS_AVERAGE_GFXCLK:
 600                 *value = metrics->AverageGfxclkFrequency;
 601                 break;
 602         case METRICS_AVERAGE_SOCCLK:
 603                 *value = metrics->AverageSocclkFrequency;
 604                 break;
 605         case METRICS_AVERAGE_UCLK:
 606                 *value = metrics->AverageUclkFrequency;
 607                 break;
 608         case METRICS_AVERAGE_GFXACTIVITY:
 609                 *value = metrics->AverageGfxActivity;
 610                 break;
 611         case METRICS_AVERAGE_MEMACTIVITY:
 612                 *value = metrics->AverageUclkActivity;
 613                 break;
 614         case METRICS_AVERAGE_SOCKETPOWER:
 615                 /* Valid power data is available only from primary die */
 616                 *value = aldebaran_is_primary(smu) ?
 617                                  metrics->AverageSocketPower << 8 :
 618                                  0;
 619                 break;
 620         case METRICS_TEMPERATURE_EDGE:
 621                 *value = metrics->TemperatureEdge *
 622                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 623                 break;
 624         case METRICS_TEMPERATURE_HOTSPOT:
 625                 *value = metrics->TemperatureHotspot *
 626                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 627                 break;
 628         case METRICS_TEMPERATURE_MEM:
 629                 *value = metrics->TemperatureHBM *
 630                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 631                 break;
 632         case METRICS_TEMPERATURE_VRGFX:
 633                 *value = metrics->TemperatureVrGfx *
 634                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 635                 break;
 636         case METRICS_TEMPERATURE_VRSOC:
 637                 *value = metrics->TemperatureVrSoc *
 638                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 639                 break;
 640         case METRICS_TEMPERATURE_VRMEM:
 641                 *value = metrics->TemperatureVrMem *
 642                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 643                 break;
 644         case METRICS_THROTTLER_STATUS:
 645                 *value = metrics->ThrottlerStatus;
 646                 break;
 647         default:
 648                 *value = UINT_MAX;
 649                 break;
 650         }
 651
 652         mutex_unlock(&smu->metrics_lock);
 653
 654         return ret;
 655 }
 656
 657 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
 658                                                    enum smu_clk_type clk_type,
 659                                                    uint32_t *value)
 660 {
 661         MetricsMember_t member_type;
 662         int clk_id = 0;
 663
 664         if (!value)
 665                 return -EINVAL;
 666
 667         clk_id = smu_cmn_to_asic_specific_index(smu,
 668                                                 CMN2ASIC_MAPPING_CLK,
 669                                                 clk_type);
 670         if (clk_id < 0)
 671                 return -EINVAL;
 672
 673         switch (clk_id) {
 674         case PPCLK_GFXCLK:
 675                 /*
 676                  * CurrClock[clk_id] can provide accurate
 677                  *   output only when the dpm feature is enabled.
 678                  * We can use Average_* for dpm disabled case.
 679                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 680                  */
 681                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 682                         member_type = METRICS_CURR_GFXCLK;
 683                 else
 684                         member_type = METRICS_AVERAGE_GFXCLK;
 685                 break;
 686         case PPCLK_UCLK:
 687                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 688                         member_type = METRICS_CURR_UCLK;
 689                 else
 690                         member_type = METRICS_AVERAGE_UCLK;
 691                 break;
 692         case PPCLK_SOCCLK:
 693                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 694                         member_type = METRICS_CURR_SOCCLK;
 695                 else
 696                         member_type = METRICS_AVERAGE_SOCCLK;
 697                 break;
 698         case PPCLK_VCLK:
 699                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 700                         member_type = METRICS_CURR_VCLK;
 701                 else
 702                         member_type = METRICS_AVERAGE_VCLK;
 703                 break;
 704         case PPCLK_DCLK:
 705                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 706                         member_type = METRICS_CURR_DCLK;
 707                 else
 708                         member_type = METRICS_AVERAGE_DCLK;
 709                 break;
 710         case PPCLK_FCLK:
 711                 member_type = METRICS_CURR_FCLK;
 712                 break;
 713         default:
 714                 return -EINVAL;
 715         }
 716
 717         return aldebaran_get_smu_metrics_data(smu,
 718                                               member_type,
 719                                               value);
 720 }
 721
 722 static int aldebaran_print_clk_levels(struct smu_context *smu,
 723                                       enum smu_clk_type type, char *buf)
 724 {
 725         int i, now, size = 0;
 726         int ret = 0;
 727         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 728         struct pp_clock_levels_with_latency clocks;
 729         struct smu_13_0_dpm_table *single_dpm_table;
 730         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 731         struct smu_13_0_dpm_context *dpm_context = NULL;
 732         uint32_t display_levels;
 733         uint32_t freq_values[3] = {0};
 734         uint32_t min_clk, max_clk;
 735
 736         smu_cmn_get_sysfs_buf(&buf, &size);
 737
 738         if (amdgpu_ras_intr_triggered()) {
 739                 size += sysfs_emit_at(buf, size, "unavailable\n");
 740                 return size;
 741         }
 742
 743         dpm_context = smu_dpm->dpm_context;
 744
 745         switch (type) {
 746
 747         case SMU_OD_SCLK:
 748                 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK");
 749                 fallthrough;
 750         case SMU_SCLK:
 751                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 752                 if (ret) {
 753                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 754                         return ret;
 755                 }
 756
 757                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 758                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 759                 if (ret) {
 760                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 761                         return ret;
 762                 }
 763
 764                 display_levels = clocks.num_levels;
 765
 766                 min_clk = pstate_table->gfxclk_pstate.curr.min;
 767                 max_clk = pstate_table->gfxclk_pstate.curr.max;
 768
 769                 freq_values[0] = min_clk;
 770                 freq_values[1] = max_clk;
 771
 772                 /* fine-grained dpm has only 2 levels */
 773                 if (now > min_clk && now < max_clk) {
 774                         display_levels = clocks.num_levels + 1;
 775                         freq_values[2] = max_clk;
 776                         freq_values[1] = now;
 777                 }
 778
 779                 /*
 780                  * For DPM disabled case, there will be only one clock level.
 781                  * And it's safe to assume that is always the current clock.
 782                  */
 783                 if (display_levels == clocks.num_levels) {
 784                         for (i = 0; i < clocks.num_levels; i++)
 785                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 786                                         freq_values[i],
 787                                         (clocks.num_levels == 1) ?
 788                                                 "*" :
 789                                                 (aldebaran_freqs_in_same_level(
 790                                                          freq_values[i], now) ?
 791                                                          "*" :
 792                                                          ""));
 793                 } else {
 794                         for (i = 0; i < display_levels; i++)
 795                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 796                                                 freq_values[i], i == 1 ? "*" : "");
 797                 }
 798
 799                 break;
 800
 801         case SMU_OD_MCLK:
 802                 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK");
 803                 fallthrough;
 804         case SMU_MCLK:
 805                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 806                 if (ret) {
 807                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 808                         return ret;
 809                 }
 810
 811                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 812                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 813                 if (ret) {
 814                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 815                         return ret;
 816                 }
 817
 818                 for (i = 0; i < clocks.num_levels; i++)
 819                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 820                                         i, clocks.data[i].clocks_in_khz / 1000,
 821                                         (clocks.num_levels == 1) ? "*" :
 822                                         (aldebaran_freqs_in_same_level(
 823                                                                        clocks.data[i].clocks_in_khz / 1000,
 824                                                                        now) ? "*" : ""));
 825                 break;
 826
 827         case SMU_SOCCLK:
 828                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 829                 if (ret) {
 830                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 831                         return ret;
 832                 }
 833
 834                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 835                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 836                 if (ret) {
 837                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 838                         return ret;
 839                 }
 840
 841                 for (i = 0; i < clocks.num_levels; i++)
 842                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 843                                         i, clocks.data[i].clocks_in_khz / 1000,
 844                                         (clocks.num_levels == 1) ? "*" :
 845                                         (aldebaran_freqs_in_same_level(
 846                                                                        clocks.data[i].clocks_in_khz / 1000,
 847                                                                        now) ? "*" : ""));
 848                 break;
 849
 850         case SMU_FCLK:
 851                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 852                 if (ret) {
 853                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 854                         return ret;
 855                 }
 856
 857                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 858                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 859                 if (ret) {
 860                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 861                         return ret;
 862                 }
 863
 864                 for (i = 0; i < single_dpm_table->count; i++)
 865                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 866                                         i, single_dpm_table->dpm_levels[i].value,
 867                                         (clocks.num_levels == 1) ? "*" :
 868                                         (aldebaran_freqs_in_same_level(
 869                                                                        clocks.data[i].clocks_in_khz / 1000,
 870                                                                        now) ? "*" : ""));
 871                 break;
 872
 873         case SMU_VCLK:
 874                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 875                 if (ret) {
 876                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 877                         return ret;
 878                 }
 879
 880                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 881                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 882                 if (ret) {
 883                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 884                         return ret;
 885                 }
 886
 887                 for (i = 0; i < single_dpm_table->count; i++)
 888                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 889                                         i, single_dpm_table->dpm_levels[i].value,
 890                                         (clocks.num_levels == 1) ? "*" :
 891                                         (aldebaran_freqs_in_same_level(
 892                                                                        clocks.data[i].clocks_in_khz / 1000,
 893                                                                        now) ? "*" : ""));
 894                 break;
 895
 896         case SMU_DCLK:
 897                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 898                 if (ret) {
 899                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 900                         return ret;
 901                 }
 902
 903                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 904                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 905                 if (ret) {
 906                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 907                         return ret;
 908                 }
 909
 910                 for (i = 0; i < single_dpm_table->count; i++)
 911                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 912                                         i, single_dpm_table->dpm_levels[i].value,
 913                                         (clocks.num_levels == 1) ? "*" :
 914                                         (aldebaran_freqs_in_same_level(
 915                                                                        clocks.data[i].clocks_in_khz / 1000,
 916                                                                        now) ? "*" : ""));
 917                 break;
 918
 919         default:
 920                 break;
 921         }
 922
 923         return size;
 924 }
 925
 926 static int aldebaran_upload_dpm_level(struct smu_context *smu,
 927                                       bool max,
 928                                       uint32_t feature_mask,
 929                                       uint32_t level)
 930 {
 931         struct smu_13_0_dpm_context *dpm_context =
 932                 smu->smu_dpm.dpm_context;
 933         uint32_t freq;
 934         int ret = 0;
 935
 936         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 937             (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
 938                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 939                 ret = smu_cmn_send_smc_msg_with_param(smu,
 940                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 941                                                       (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 942                                                       NULL);
 943                 if (ret) {
 944                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 945                                 max ? "max" : "min");
 946                         return ret;
 947                 }
 948         }
 949
 950         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 951             (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
 952                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 953                 ret = smu_cmn_send_smc_msg_with_param(smu,
 954                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 955                                                       (PPCLK_UCLK << 16) | (freq & 0xffff),
 956                                                       NULL);
 957                 if (ret) {
 958                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 959                                 max ? "max" : "min");
 960                         return ret;
 961                 }
 962         }
 963
 964         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 965             (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
 966                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 967                 ret = smu_cmn_send_smc_msg_with_param(smu,
 968                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 969                                                       (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 970                                                       NULL);
 971                 if (ret) {
 972                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 973                                 max ? "max" : "min");
 974                         return ret;
 975                 }
 976         }
 977
 978         return ret;
 979 }
 980
 981 static int aldebaran_force_clk_levels(struct smu_context *smu,
 982                                       enum smu_clk_type type, uint32_t mask)
 983 {
 984         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 985         struct smu_13_0_dpm_table *single_dpm_table = NULL;
 986         uint32_t soft_min_level, soft_max_level;
 987         int ret = 0;
 988
 989         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 990         soft_max_level = mask ? (fls(mask) - 1) : 0;
 991
 992         switch (type) {
 993         case SMU_SCLK:
 994                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 995                 if (soft_max_level >= single_dpm_table->count) {
 996                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 997                                 soft_max_level, single_dpm_table->count - 1);
 998                         ret = -EINVAL;
 999                         break;
1000                 }
1001
1002                 ret = aldebaran_upload_dpm_level(smu,
1003                                                  false,
1004                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1005                                                  soft_min_level);
1006                 if (ret) {
1007                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1008                         break;
1009                 }
1010
1011                 ret = aldebaran_upload_dpm_level(smu,
1012                                                  true,
1013                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1014                                                  soft_max_level);
1015                 if (ret)
1016                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1017
1018                 break;
1019
1020         case SMU_MCLK:
1021         case SMU_SOCCLK:
1022         case SMU_FCLK:
1023                 /*
1024                  * Should not arrive here since aldebaran does not
1025                  * support mclk/socclk/fclk softmin/softmax settings
1026                  */
1027                 ret = -EINVAL;
1028                 break;
1029
1030         default:
1031                 break;
1032         }
1033
1034         return ret;
1035 }
1036
1037 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1038                                                    struct smu_temperature_range *range)
1039 {
1040         struct smu_table_context *table_context = &smu->smu_table;
1041         struct smu_13_0_powerplay_table *powerplay_table =
1042                 table_context->power_play_table;
1043         PPTable_t *pptable = smu->smu_table.driver_pptable;
1044
1045         if (!range)
1046                 return -EINVAL;
1047
1048         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1049
1050         range->hotspot_crit_max = pptable->ThotspotLimit *
1051                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1052         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1053                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1054         range->mem_crit_max = pptable->TmemLimit *
1055                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1056         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1057                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1058         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1059
1060         return 0;
1061 }
1062
1063 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1064                                                   enum amd_pp_sensors sensor,
1065                                                   uint32_t *value)
1066 {
1067         int ret = 0;
1068
1069         if (!value)
1070                 return -EINVAL;
1071
1072         switch (sensor) {
1073         case AMDGPU_PP_SENSOR_GPU_LOAD:
1074                 ret = aldebaran_get_smu_metrics_data(smu,
1075                                                      METRICS_AVERAGE_GFXACTIVITY,
1076                                                      value);
1077                 break;
1078         case AMDGPU_PP_SENSOR_MEM_LOAD:
1079                 ret = aldebaran_get_smu_metrics_data(smu,
1080                                                      METRICS_AVERAGE_MEMACTIVITY,
1081                                                      value);
1082                 break;
1083         default:
1084                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1085                 return -EINVAL;
1086         }
1087
1088         return ret;
1089 }
1090
1091 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value)
1092 {
1093         if (!value)
1094                 return -EINVAL;
1095
1096         return aldebaran_get_smu_metrics_data(smu,
1097                                               METRICS_AVERAGE_SOCKETPOWER,
1098                                               value);
1099 }
1100
1101 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1102                                              enum amd_pp_sensors sensor,
1103                                              uint32_t *value)
1104 {
1105         int ret = 0;
1106
1107         if (!value)
1108                 return -EINVAL;
1109
1110         switch (sensor) {
1111         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1112                 ret = aldebaran_get_smu_metrics_data(smu,
1113                                                      METRICS_TEMPERATURE_HOTSPOT,
1114                                                      value);
1115                 break;
1116         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1117                 ret = aldebaran_get_smu_metrics_data(smu,
1118                                                      METRICS_TEMPERATURE_EDGE,
1119                                                      value);
1120                 break;
1121         case AMDGPU_PP_SENSOR_MEM_TEMP:
1122                 ret = aldebaran_get_smu_metrics_data(smu,
1123                                                      METRICS_TEMPERATURE_MEM,
1124                                                      value);
1125                 break;
1126         default:
1127                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1128                 return -EINVAL;
1129         }
1130
1131         return ret;
1132 }
1133
1134 static int aldebaran_read_sensor(struct smu_context *smu,
1135                                  enum amd_pp_sensors sensor,
1136                                  void *data, uint32_t *size)
1137 {
1138         int ret = 0;
1139
1140         if (amdgpu_ras_intr_triggered())
1141                 return 0;
1142
1143         if (!data || !size)
1144                 return -EINVAL;
1145
1146         mutex_lock(&smu->sensor_lock);
1147         switch (sensor) {
1148         case AMDGPU_PP_SENSOR_MEM_LOAD:
1149         case AMDGPU_PP_SENSOR_GPU_LOAD:
1150                 ret = aldebaran_get_current_activity_percent(smu,
1151                                                              sensor,
1152                                                              (uint32_t *)data);
1153                 *size = 4;
1154                 break;
1155         case AMDGPU_PP_SENSOR_GPU_POWER:
1156                 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data);
1157                 *size = 4;
1158                 break;
1159         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1160         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1161         case AMDGPU_PP_SENSOR_MEM_TEMP:
1162                 ret = aldebaran_thermal_get_temperature(smu, sensor,
1163                                                         (uint32_t *)data);
1164                 *size = 4;
1165                 break;
1166         case AMDGPU_PP_SENSOR_GFX_MCLK:
1167                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1168                 /* the output clock frequency in 10K unit */
1169                 *(uint32_t *)data *= 100;
1170                 *size = 4;
1171                 break;
1172         case AMDGPU_PP_SENSOR_GFX_SCLK:
1173                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1174                 *(uint32_t *)data *= 100;
1175                 *size = 4;
1176                 break;
1177         case AMDGPU_PP_SENSOR_VDDGFX:
1178                 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1179                 *size = 4;
1180                 break;
1181         default:
1182                 ret = -EOPNOTSUPP;
1183                 break;
1184         }
1185         mutex_unlock(&smu->sensor_lock);
1186
1187         return ret;
1188 }
1189
1190 static int aldebaran_get_power_limit(struct smu_context *smu,
1191                                      uint32_t *current_power_limit,
1192                                      uint32_t *default_power_limit,
1193                                      uint32_t *max_power_limit)
1194 {
1195         PPTable_t *pptable = smu->smu_table.driver_pptable;
1196         uint32_t power_limit = 0;
1197         int ret;
1198
1199         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1200                 if (current_power_limit)
1201                         *current_power_limit = 0;
1202                 if (default_power_limit)
1203                         *default_power_limit = 0;
1204                 if (max_power_limit)
1205                         *max_power_limit = 0;
1206
1207                 dev_warn(smu->adev->dev,
1208                         "PPT feature is not enabled, power values can't be fetched.");
1209
1210                 return 0;
1211         }
1212
1213         /* Valid power data is available only from primary die.
1214          * For secondary die show the value as 0.
1215          */
1216         if (aldebaran_is_primary(smu)) {
1217                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1218                                            &power_limit);
1219
1220                 if (ret) {
1221                         /* the last hope to figure out the ppt limit */
1222                         if (!pptable) {
1223                                 dev_err(smu->adev->dev,
1224                                         "Cannot get PPT limit due to pptable missing!");
1225                                 return -EINVAL;
1226                         }
1227                         power_limit = pptable->PptLimit;
1228                 }
1229         }
1230
1231         if (current_power_limit)
1232                 *current_power_limit = power_limit;
1233         if (default_power_limit)
1234                 *default_power_limit = power_limit;
1235
1236         if (max_power_limit) {
1237                 if (pptable)
1238                         *max_power_limit = pptable->PptLimit;
1239         }
1240
1241         return 0;
1242 }
1243
1244 static int aldebaran_set_power_limit(struct smu_context *smu, uint32_t n)
1245 {
1246         /* Power limit can be set only through primary die */
1247         if (aldebaran_is_primary(smu))
1248                 return smu_v13_0_set_power_limit(smu, n);
1249
1250         return -EINVAL;
1251 }
1252
1253 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1254 {
1255         int ret;
1256
1257         ret = smu_v13_0_system_features_control(smu, enable);
1258         if (!ret && enable)
1259                 ret = aldebaran_run_btc(smu);
1260
1261         return ret;
1262 }
1263
1264 static int aldebaran_set_performance_level(struct smu_context *smu,
1265                                            enum amd_dpm_forced_level level)
1266 {
1267         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1268         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1269         struct smu_13_0_dpm_table *gfx_table =
1270                 &dpm_context->dpm_tables.gfx_table;
1271         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1272
1273         /* Disable determinism if switching to another mode */
1274         if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1275             (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1276                 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1277                 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1278         }
1279
1280         switch (level) {
1281
1282         case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1283                 return 0;
1284
1285         case AMD_DPM_FORCED_LEVEL_HIGH:
1286         case AMD_DPM_FORCED_LEVEL_LOW:
1287         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1288         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1289         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1290         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1291         default:
1292                 break;
1293         }
1294
1295         return smu_v13_0_set_performance_level(smu, level);
1296 }
1297
1298 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1299                                           enum smu_clk_type clk_type,
1300                                           uint32_t min,
1301                                           uint32_t max)
1302 {
1303         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1304         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1305         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1306         struct amdgpu_device *adev = smu->adev;
1307         uint32_t min_clk;
1308         uint32_t max_clk;
1309         int ret = 0;
1310
1311         if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1312                 return -EINVAL;
1313
1314         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1315                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1316                 return -EINVAL;
1317
1318         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1319                 if (min >= max) {
1320                         dev_err(smu->adev->dev,
1321                                 "Minimum GFX clk should be less than the maximum allowed clock\n");
1322                         return -EINVAL;
1323                 }
1324
1325                 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1326                     (max == pstate_table->gfxclk_pstate.curr.max))
1327                         return 0;
1328
1329                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1330                                                             min, max);
1331                 if (!ret) {
1332                         pstate_table->gfxclk_pstate.curr.min = min;
1333                         pstate_table->gfxclk_pstate.curr.max = max;
1334                 }
1335
1336                 return ret;
1337         }
1338
1339         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1340                 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1341                         (max > dpm_context->dpm_tables.gfx_table.max)) {
1342                         dev_warn(adev->dev,
1343                                         "Invalid max frequency %d MHz specified for determinism\n", max);
1344                         return -EINVAL;
1345                 }
1346
1347                 /* Restore default min/max clocks and enable determinism */
1348                 min_clk = dpm_context->dpm_tables.gfx_table.min;
1349                 max_clk = dpm_context->dpm_tables.gfx_table.max;
1350                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1351                 if (!ret) {
1352                         usleep_range(500, 1000);
1353                         ret = smu_cmn_send_smc_msg_with_param(smu,
1354                                         SMU_MSG_EnableDeterminism,
1355                                         max, NULL);
1356                         if (ret) {
1357                                 dev_err(adev->dev,
1358                                                 "Failed to enable determinism at GFX clock %d MHz\n", max);
1359                         } else {
1360                                 pstate_table->gfxclk_pstate.curr.min = min_clk;
1361                                 pstate_table->gfxclk_pstate.curr.max = max;
1362                         }
1363                 }
1364         }
1365
1366         return ret;
1367 }
1368
1369 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1370                                                         long input[], uint32_t size)
1371 {
1372         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1373         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1374         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1375         uint32_t min_clk;
1376         uint32_t max_clk;
1377         int ret = 0;
1378
1379         /* Only allowed in manual or determinism mode */
1380         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1381                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1382                 return -EINVAL;
1383
1384         switch (type) {
1385         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1386                 if (size != 2) {
1387                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1388                         return -EINVAL;
1389                 }
1390
1391                 if (input[0] == 0) {
1392                         if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1393                                 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1394                                         input[1], dpm_context->dpm_tables.gfx_table.min);
1395                                 pstate_table->gfxclk_pstate.custom.min =
1396                                         pstate_table->gfxclk_pstate.curr.min;
1397                                 return -EINVAL;
1398                         }
1399
1400                         pstate_table->gfxclk_pstate.custom.min = input[1];
1401                 } else if (input[0] == 1) {
1402                         if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1403                                 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1404                                         input[1], dpm_context->dpm_tables.gfx_table.max);
1405                                 pstate_table->gfxclk_pstate.custom.max =
1406                                         pstate_table->gfxclk_pstate.curr.max;
1407                                 return -EINVAL;
1408                         }
1409
1410                         pstate_table->gfxclk_pstate.custom.max = input[1];
1411                 } else {
1412                         return -EINVAL;
1413                 }
1414                 break;
1415         case PP_OD_RESTORE_DEFAULT_TABLE:
1416                 if (size != 0) {
1417                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1418                         return -EINVAL;
1419                 } else {
1420                         /* Use the default frequencies for manual and determinism mode */
1421                         min_clk = dpm_context->dpm_tables.gfx_table.min;
1422                         max_clk = dpm_context->dpm_tables.gfx_table.max;
1423
1424                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1425                 }
1426                 break;
1427         case PP_OD_COMMIT_DPM_TABLE:
1428                 if (size != 0) {
1429                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1430                         return -EINVAL;
1431                 } else {
1432                         if (!pstate_table->gfxclk_pstate.custom.min)
1433                                 pstate_table->gfxclk_pstate.custom.min =
1434                                         pstate_table->gfxclk_pstate.curr.min;
1435
1436                         if (!pstate_table->gfxclk_pstate.custom.max)
1437                                 pstate_table->gfxclk_pstate.custom.max =
1438                                         pstate_table->gfxclk_pstate.curr.max;
1439
1440                         min_clk = pstate_table->gfxclk_pstate.custom.min;
1441                         max_clk = pstate_table->gfxclk_pstate.custom.max;
1442
1443                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1444                 }
1445                 break;
1446         default:
1447                 return -ENOSYS;
1448         }
1449
1450         return ret;
1451 }
1452
1453 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1454 {
1455         int ret;
1456         uint32_t feature_mask[2];
1457         unsigned long feature_enabled;
1458
1459         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1460         if (ret)
1461                 return false;
1462         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1463                                           ((uint64_t)feature_mask[1] << 32));
1464         return !!(feature_enabled & SMC_DPM_FEATURE);
1465 }
1466
1467 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1468                               struct i2c_msg *msg, int num_msgs)
1469 {
1470         struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
1471         struct smu_table_context *smu_table = &adev->smu.smu_table;
1472         struct smu_table *table = &smu_table->driver_table;
1473         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1474         int i, j, r, c;
1475         u16 dir;
1476
1477         req = kzalloc(sizeof(*req), GFP_KERNEL);
1478         if (!req)
1479                 return -ENOMEM;
1480
1481         req->I2CcontrollerPort = 0;
1482         req->I2CSpeed = I2C_SPEED_FAST_400K;
1483         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1484         dir = msg[0].flags & I2C_M_RD;
1485
1486         for (c = i = 0; i < num_msgs; i++) {
1487                 for (j = 0; j < msg[i].len; j++, c++) {
1488                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1489
1490                         if (!(msg[i].flags & I2C_M_RD)) {
1491                                 /* write */
1492                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1493                                 cmd->ReadWriteData = msg[i].buf[j];
1494                         }
1495
1496                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
1497                                 /* The direction changes.
1498                                  */
1499                                 dir = msg[i].flags & I2C_M_RD;
1500                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1501                         }
1502
1503                         req->NumCmds++;
1504
1505                         /*
1506                          * Insert STOP if we are at the last byte of either last
1507                          * message for the transaction or the client explicitly
1508                          * requires a STOP at this particular message.
1509                          */
1510                         if ((j == msg[i].len - 1) &&
1511                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1512                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1513                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1514                         }
1515                 }
1516         }
1517         mutex_lock(&adev->smu.mutex);
1518         r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1519         mutex_unlock(&adev->smu.mutex);
1520         if (r)
1521                 goto fail;
1522
1523         for (c = i = 0; i < num_msgs; i++) {
1524                 if (!(msg[i].flags & I2C_M_RD)) {
1525                         c += msg[i].len;
1526                         continue;
1527                 }
1528                 for (j = 0; j < msg[i].len; j++, c++) {
1529                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1530
1531                         msg[i].buf[j] = cmd->ReadWriteData;
1532                 }
1533         }
1534         r = num_msgs;
1535 fail:
1536         kfree(req);
1537         return r;
1538 }
1539
1540 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1541 {
1542         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1543 }
1544
1545
1546 static const struct i2c_algorithm aldebaran_i2c_algo = {
1547         .master_xfer = aldebaran_i2c_xfer,
1548         .functionality = aldebaran_i2c_func,
1549 };
1550
1551 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1552         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1553         .max_read_len  = MAX_SW_I2C_COMMANDS,
1554         .max_write_len = MAX_SW_I2C_COMMANDS,
1555         .max_comb_1st_msg_len = 2,
1556         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1557 };
1558
1559 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
1560 {
1561         struct amdgpu_device *adev = to_amdgpu_device(control);
1562         int res;
1563
1564         control->owner = THIS_MODULE;
1565         control->class = I2C_CLASS_SPD;
1566         control->dev.parent = &adev->pdev->dev;
1567         control->algo = &aldebaran_i2c_algo;
1568         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
1569         control->quirks = &aldebaran_i2c_control_quirks;
1570
1571         res = i2c_add_adapter(control);
1572         if (res)
1573                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1574
1575         return res;
1576 }
1577
1578 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
1579 {
1580         i2c_del_adapter(control);
1581 }
1582
1583 static void aldebaran_get_unique_id(struct smu_context *smu)
1584 {
1585         struct amdgpu_device *adev = smu->adev;
1586         SmuMetrics_t *metrics = smu->smu_table.metrics_table;
1587         uint32_t upper32 = 0, lower32 = 0;
1588         int ret;
1589
1590         mutex_lock(&smu->metrics_lock);
1591         ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
1592         if (ret)
1593                 goto out_unlock;
1594
1595         upper32 = metrics->PublicSerialNumUpper32;
1596         lower32 = metrics->PublicSerialNumLower32;
1597
1598 out_unlock:
1599         mutex_unlock(&smu->metrics_lock);
1600
1601         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1602         sprintf(adev->serial, "%016llx", adev->unique_id);
1603 }
1604
1605 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1606 {
1607         /* aldebaran is not support baco */
1608
1609         return false;
1610 }
1611
1612 static int aldebaran_set_df_cstate(struct smu_context *smu,
1613                                    enum pp_df_cstate state)
1614 {
1615         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1616 }
1617
1618 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1619 {
1620         return smu_cmn_send_smc_msg_with_param(smu,
1621                                                SMU_MSG_GmiPwrDnControl,
1622                                                en ? 1 : 0,
1623                                                NULL);
1624 }
1625
1626 static const struct throttling_logging_label {
1627         uint32_t feature_mask;
1628         const char *label;
1629 } logging_label[] = {
1630         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1631         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1632         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1633         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1634 };
1635 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1636 {
1637         int ret;
1638         int throttler_idx, throtting_events = 0, buf_idx = 0;
1639         struct amdgpu_device *adev = smu->adev;
1640         uint32_t throttler_status;
1641         char log_buf[256];
1642
1643         ret = aldebaran_get_smu_metrics_data(smu,
1644                                              METRICS_THROTTLER_STATUS,
1645                                              &throttler_status);
1646         if (ret)
1647                 return;
1648
1649         memset(log_buf, 0, sizeof(log_buf));
1650         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1651              throttler_idx++) {
1652                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1653                         throtting_events++;
1654                         buf_idx += snprintf(log_buf + buf_idx,
1655                                             sizeof(log_buf) - buf_idx,
1656                                             "%s%s",
1657                                             throtting_events > 1 ? " and " : "",
1658                                             logging_label[throttler_idx].label);
1659                         if (buf_idx >= sizeof(log_buf)) {
1660                                 dev_err(adev->dev, "buffer overflow!\n");
1661                                 log_buf[sizeof(log_buf) - 1] = '\0';
1662                                 break;
1663                         }
1664                 }
1665         }
1666
1667         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1668                  log_buf);
1669         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1670                 smu_cmn_get_indep_throttler_status(throttler_status,
1671                                                    aldebaran_throttler_map));
1672 }
1673
1674 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1675 {
1676         struct amdgpu_device *adev = smu->adev;
1677         uint32_t esm_ctrl;
1678
1679         /* TODO: confirm this on real target */
1680         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1681         if ((esm_ctrl >> 15) & 0x1FFFF)
1682                 return (((esm_ctrl >> 8) & 0x3F) + 128);
1683
1684         return smu_v13_0_get_current_pcie_link_speed(smu);
1685 }
1686
1687 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1688                                          void **table)
1689 {
1690         struct smu_table_context *smu_table = &smu->smu_table;
1691         struct gpu_metrics_v1_3 *gpu_metrics =
1692                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1693         SmuMetrics_t metrics;
1694         int i, ret = 0;
1695
1696         ret = smu_cmn_get_metrics_table(smu,
1697                                         &metrics,
1698                                         true);
1699         if (ret)
1700                 return ret;
1701
1702         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1703
1704         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1705         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1706         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1707         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1708         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1709         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1710
1711         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1712         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1713         gpu_metrics->average_mm_activity = 0;
1714
1715         /* Valid power data is available only from primary die */
1716         if (aldebaran_is_primary(smu)) {
1717                 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1718                 gpu_metrics->energy_accumulator =
1719                         (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1720                         metrics.EnergyAcc64bitLow;
1721         } else {
1722                 gpu_metrics->average_socket_power = 0;
1723                 gpu_metrics->energy_accumulator = 0;
1724         }
1725
1726         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1727         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1728         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1729         gpu_metrics->average_vclk0_frequency = 0;
1730         gpu_metrics->average_dclk0_frequency = 0;
1731
1732         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1733         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1734         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1735         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1736         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1737
1738         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1739         gpu_metrics->indep_throttle_status =
1740                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1741                                                            aldebaran_throttler_map);
1742
1743         gpu_metrics->current_fan_speed = 0;
1744
1745         gpu_metrics->pcie_link_width =
1746                 smu_v13_0_get_current_pcie_link_width(smu);
1747         gpu_metrics->pcie_link_speed =
1748                 aldebaran_get_current_pcie_link_speed(smu);
1749
1750         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1751
1752         gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1753         gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1754
1755         for (i = 0; i < NUM_HBM_INSTANCES; i++)
1756                 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1757
1758         gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1759                                         metrics.TimeStampLow;
1760
1761         *table = (void *)gpu_metrics;
1762
1763         return sizeof(struct gpu_metrics_v1_3);
1764 }
1765
1766 static int aldebaran_mode2_reset(struct smu_context *smu)
1767 {
1768         u32 smu_version;
1769         int ret = 0, index;
1770         struct amdgpu_device *adev = smu->adev;
1771         int timeout = 10;
1772
1773         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1774
1775         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1776                                                 SMU_MSG_GfxDeviceDriverReset);
1777
1778         mutex_lock(&smu->message_lock);
1779         if (smu_version >= 0x00441400) {
1780                 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1781                 /* This is similar to FLR, wait till max FLR timeout */
1782                 msleep(100);
1783                 dev_dbg(smu->adev->dev, "restore config space...\n");
1784                 /* Restore the config space saved during init */
1785                 amdgpu_device_load_pci_state(adev->pdev);
1786
1787                 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1788                 while (ret == -ETIME && timeout)  {
1789                         ret = smu_cmn_wait_for_response(smu);
1790                         /* Wait a bit more time for getting ACK */
1791                         if (ret == -ETIME) {
1792                                 --timeout;
1793                                 usleep_range(500, 1000);
1794                                 continue;
1795                         }
1796
1797                         if (ret != 1) {
1798                                 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1799                                                 SMU_RESET_MODE_2, ret);
1800                                 goto out;
1801                         }
1802                 }
1803
1804         } else {
1805                 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1806                                 smu_version);
1807         }
1808
1809         if (ret == 1)
1810                 ret = 0;
1811 out:
1812         mutex_unlock(&smu->message_lock);
1813
1814         return ret;
1815 }
1816
1817 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1818 {
1819 #if 0
1820         struct amdgpu_device *adev = smu->adev;
1821         u32 smu_version;
1822         uint32_t val;
1823         /**
1824          * PM FW version support mode1 reset from 68.07
1825          */
1826         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1827         if ((smu_version < 0x00440700))
1828                 return false;
1829         /**
1830          * mode1 reset relies on PSP, so we should check if
1831          * PSP is alive.
1832          */
1833         val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1834
1835         return val != 0x0;
1836 #endif
1837         return true;
1838 }
1839
1840 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1841 {
1842         return true;
1843 }
1844
1845 static int aldebaran_set_mp1_state(struct smu_context *smu,
1846                                    enum pp_mp1_state mp1_state)
1847 {
1848         switch (mp1_state) {
1849         case PP_MP1_STATE_UNLOAD:
1850                 return smu_cmn_set_mp1_state(smu, mp1_state);
1851         default:
1852                 return 0;
1853         }
1854 }
1855
1856 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1857                 uint32_t size)
1858 {
1859         int ret = 0;
1860
1861         /* message SMU to update the bad page number on SMUBUS */
1862         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1863         if (ret)
1864                 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1865                                 __func__);
1866
1867         return ret;
1868 }
1869
1870 static const struct pptable_funcs aldebaran_ppt_funcs = {
1871         /* init dpm */
1872         .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
1873         /* dpm/clk tables */
1874         .set_default_dpm_table = aldebaran_set_default_dpm_table,
1875         .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
1876         .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
1877         .print_clk_levels = aldebaran_print_clk_levels,
1878         .force_clk_levels = aldebaran_force_clk_levels,
1879         .read_sensor = aldebaran_read_sensor,
1880         .set_performance_level = aldebaran_set_performance_level,
1881         .get_power_limit = aldebaran_get_power_limit,
1882         .is_dpm_running = aldebaran_is_dpm_running,
1883         .get_unique_id = aldebaran_get_unique_id,
1884         .init_microcode = smu_v13_0_init_microcode,
1885         .load_microcode = smu_v13_0_load_microcode,
1886         .fini_microcode = smu_v13_0_fini_microcode,
1887         .init_smc_tables = aldebaran_init_smc_tables,
1888         .fini_smc_tables = smu_v13_0_fini_smc_tables,
1889         .init_power = smu_v13_0_init_power,
1890         .fini_power = smu_v13_0_fini_power,
1891         .check_fw_status = smu_v13_0_check_fw_status,
1892         /* pptable related */
1893         .setup_pptable = aldebaran_setup_pptable,
1894         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1895         .check_fw_version = smu_v13_0_check_fw_version,
1896         .write_pptable = smu_cmn_write_pptable,
1897         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1898         .set_tool_table_location = smu_v13_0_set_tool_table_location,
1899         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1900         .system_features_control = aldebaran_system_features_control,
1901         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1902         .send_smc_msg = smu_cmn_send_smc_msg,
1903         .get_enabled_mask = smu_cmn_get_enabled_mask,
1904         .feature_is_enabled = smu_cmn_feature_is_enabled,
1905         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1906         .set_power_limit = aldebaran_set_power_limit,
1907         .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
1908         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1909         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1910         .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
1911         .register_irq_handler = smu_v13_0_register_irq_handler,
1912         .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
1913         .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
1914         .baco_is_support= aldebaran_is_baco_supported,
1915         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1916         .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
1917         .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
1918         .set_df_cstate = aldebaran_set_df_cstate,
1919         .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
1920         .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
1921         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1922         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1923         .get_gpu_metrics = aldebaran_get_gpu_metrics,
1924         .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
1925         .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
1926         .mode1_reset = smu_v13_0_mode1_reset,
1927         .set_mp1_state = aldebaran_set_mp1_state,
1928         .mode2_reset = aldebaran_mode2_reset,
1929         .wait_for_event = smu_v13_0_wait_for_event,
1930         .i2c_init = aldebaran_i2c_control_init,
1931         .i2c_fini = aldebaran_i2c_control_fini,
1932         .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
1933 };
1934
1935 void aldebaran_set_ppt_funcs(struct smu_context *smu)
1936 {
1937         smu->ppt_funcs = &aldebaran_ppt_funcs;
1938         smu->message_map = aldebaran_message_map;
1939         smu->clock_map = aldebaran_clk_map;
1940         smu->feature_map = aldebaran_feature_mask_map;
1941         smu->table_map = aldebaran_table_map;
1942 }