2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
30 #include "amdgpu_dpm.h"
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "smu_v11_0.h"
36 #include "smu11_driver_if_sienna_cichlid.h"
37 #include "soc15_common.h"
39 #include "sienna_cichlid_ppt.h"
40 #include "smu_v11_0_7_pptable.h"
41 #include "smu_v11_0_7_ppsmc.h"
42 #include "nbio/nbio_2_3_offset.h"
43 #include "nbio/nbio_2_3_sh_mask.h"
44 #include "thm/thm_11_0_2_offset.h"
45 #include "thm/thm_11_0_2_sh_mask.h"
46 #include "mp/mp_11_0_offset.h"
47 #include "mp/mp_11_0_sh_mask.h"
49 #include "asic_reg/mp/mp_11_0_sh_mask.h"
50 #include "amdgpu_ras.h"
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
76 #define GET_PPTABLE_MEMBER(field, member) do {\
77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
83 /* STB FIFO depth is in 64bit units */
84 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
87 * SMU support ECCTABLE since version 58.70.0,
88 * use this to check whether ECCTABLE feature is supported.
90 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
92 static int get_table_size(struct smu_context *smu)
94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
95 return sizeof(PPTable_beige_goby_t);
97 return sizeof(PPTable_t);
100 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
114 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
115 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
123 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
132 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
133 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
134 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
135 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
136 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
137 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
138 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
139 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
140 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
144 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
145 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
146 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
147 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
148 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
149 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
150 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
151 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
152 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
153 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
154 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
155 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
156 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
157 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
160 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
161 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
162 CLK_MAP(SCLK, PPCLK_GFXCLK),
163 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
164 CLK_MAP(FCLK, PPCLK_FCLK),
165 CLK_MAP(UCLK, PPCLK_UCLK),
166 CLK_MAP(MCLK, PPCLK_UCLK),
167 CLK_MAP(DCLK, PPCLK_DCLK_0),
168 CLK_MAP(DCLK1, PPCLK_DCLK_1),
169 CLK_MAP(VCLK, PPCLK_VCLK_0),
170 CLK_MAP(VCLK1, PPCLK_VCLK_1),
171 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
172 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
173 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
174 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
177 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
178 FEA_MAP(DPM_PREFETCHER),
180 FEA_MAP(DPM_GFX_GPO),
186 FEA_MAP(DPM_DCEFCLK),
188 FEA_MAP(MEM_VDDCI_SCALING),
189 FEA_MAP(MEM_MVDD_SCALING),
201 FEA_MAP(RSMU_SMN_CG),
210 FEA_MAP(FAN_CONTROL),
214 FEA_MAP(LED_DISPLAY),
216 FEA_MAP(OUT_OF_BAND_MONITOR),
217 FEA_MAP(TEMP_DEPENDENT_VMIN),
223 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
226 TAB_MAP(AVFS_PSM_DEBUG),
227 TAB_MAP(AVFS_FUSE_OVERRIDE),
228 TAB_MAP(PMSTATUSLOG),
229 TAB_MAP(SMU_METRICS),
230 TAB_MAP(DRIVER_SMU_CONFIG),
231 TAB_MAP(ACTIVITY_MONITOR_COEFF),
233 TAB_MAP(I2C_COMMANDS),
238 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
243 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
253 static const uint8_t sienna_cichlid_throttler_map[] = {
254 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
255 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
256 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
257 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
260 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
261 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
262 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
263 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
264 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
265 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
266 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
267 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
268 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
269 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
270 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
271 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
275 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
276 uint32_t *feature_mask, uint32_t num)
278 struct amdgpu_device *adev = smu->adev;
283 memset(feature_mask, 0, sizeof(uint32_t) * num);
285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
286 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
287 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
288 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
289 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
290 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
291 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
292 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
293 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
294 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
295 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
296 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
297 | FEATURE_MASK(FEATURE_PPT_BIT)
298 | FEATURE_MASK(FEATURE_TDC_BIT)
299 | FEATURE_MASK(FEATURE_BACO_BIT)
300 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
301 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
302 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
303 | FEATURE_MASK(FEATURE_THERMAL_BIT)
304 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
312 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
313 !(adev->flags & AMD_IS_APU))
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
316 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
318 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
319 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
321 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
324 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
327 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
330 if (adev->pm.pp_feature & PP_ULV_MASK)
331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
333 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
336 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
339 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
342 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
345 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
346 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
349 if (smu->dc_controlled_by_gpio)
350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
352 if (amdgpu_device_should_use_aspm(adev))
353 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
358 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
360 struct smu_table_context *table_context = &smu->smu_table;
361 struct smu_11_0_7_powerplay_table *powerplay_table =
362 table_context->power_play_table;
363 struct smu_baco_context *smu_baco = &smu->smu_baco;
364 struct amdgpu_device *adev = smu->adev;
367 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
368 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
369 smu_baco->platform_support =
370 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
374 * Disable BACO entry/exit completely on below SKUs to
375 * avoid hardware intermittent failures.
377 if (((adev->pdev->device == 0x73A1) &&
378 (adev->pdev->revision == 0x00)) ||
379 ((adev->pdev->device == 0x73BF) &&
380 (adev->pdev->revision == 0xCF)) ||
381 ((adev->pdev->device == 0x7422) &&
382 (adev->pdev->revision == 0x00)) ||
383 ((adev->pdev->device == 0x73A3) &&
384 (adev->pdev->revision == 0x00)) ||
385 ((adev->pdev->device == 0x73E3) &&
386 (adev->pdev->revision == 0x00)))
387 smu_baco->platform_support = false;
392 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
394 struct smu_table_context *table_context = &smu->smu_table;
395 PPTable_t *pptable = table_context->driver_pptable;
396 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
398 /* Fan control is not possible if PPTable has it disabled */
399 smu->adev->pm.no_fan =
400 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
401 if (smu->adev->pm.no_fan)
402 dev_info_once(smu->adev->dev,
403 "PMFW based fan control disabled");
406 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
408 struct smu_table_context *table_context = &smu->smu_table;
409 struct smu_11_0_7_powerplay_table *powerplay_table =
410 table_context->power_play_table;
412 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
413 smu->dc_controlled_by_gpio = true;
415 sienna_cichlid_check_bxco_support(smu);
416 sienna_cichlid_check_fan_support(smu);
418 table_context->thermal_controller_type =
419 powerplay_table->thermal_controller_type;
422 * Instead of having its own buffer space and get overdrive_table copied,
423 * smu->od_settings just points to the actual overdrive_table
425 smu->od_settings = &powerplay_table->overdrive_table;
430 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
432 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
434 PPTable_beige_goby_t *ppt_beige_goby;
437 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
438 ppt_beige_goby = smu->smu_table.driver_pptable;
440 ppt = smu->smu_table.driver_pptable;
442 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
445 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
446 (uint8_t **)&smc_dpm_table);
450 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
451 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
452 smc_dpm_table, I2cControllers);
454 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
455 smc_dpm_table, I2cControllers);
460 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
462 struct smu_table_context *table_context = &smu->smu_table;
463 struct smu_11_0_7_powerplay_table *powerplay_table =
464 table_context->power_play_table;
467 table_size = get_table_size(smu);
468 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
474 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
476 struct amdgpu_device *adev = smu->adev;
477 uint32_t *board_reserved;
478 uint16_t *freq_table_gfx;
481 /* Fix some OEM SKU specific stability issues */
482 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
483 if ((adev->pdev->device == 0x73DF) &&
484 (adev->pdev->revision == 0XC3) &&
485 (adev->pdev->subsystem_device == 0x16C2) &&
486 (adev->pdev->subsystem_vendor == 0x1043))
487 board_reserved[0] = 1387;
489 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
490 if ((adev->pdev->device == 0x73DF) &&
491 (adev->pdev->revision == 0XC3) &&
492 ((adev->pdev->subsystem_device == 0x16C2) ||
493 (adev->pdev->subsystem_device == 0x133C)) &&
494 (adev->pdev->subsystem_vendor == 0x1043)) {
495 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
496 if (freq_table_gfx[i] > 2500)
497 freq_table_gfx[i] = 2500;
504 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
508 ret = smu_v11_0_setup_pptable(smu);
512 ret = sienna_cichlid_store_powerplay_table(smu);
516 ret = sienna_cichlid_append_powerplay_table(smu);
520 ret = sienna_cichlid_check_powerplay_table(smu);
524 return sienna_cichlid_patch_pptable_quirk(smu);
527 static int sienna_cichlid_tables_init(struct smu_context *smu)
529 struct smu_table_context *smu_table = &smu->smu_table;
530 struct smu_table *tables = smu_table->tables;
533 table_size = get_table_size(smu);
534 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
535 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
536 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
537 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
538 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
540 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
542 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
544 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
546 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
547 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
548 AMDGPU_GEM_DOMAIN_VRAM);
549 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
550 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
551 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
552 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
554 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
555 if (!smu_table->metrics_table)
557 smu_table->metrics_time = 0;
559 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
560 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
561 if (!smu_table->gpu_metrics_table)
564 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
565 if (!smu_table->watermarks_table)
568 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
569 if (!smu_table->ecc_table)
572 smu_table->driver_smu_config_table =
573 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
574 if (!smu_table->driver_smu_config_table)
580 kfree(smu_table->ecc_table);
582 kfree(smu_table->watermarks_table);
584 kfree(smu_table->gpu_metrics_table);
586 kfree(smu_table->metrics_table);
591 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
593 struct smu_table_context *smu_table= &smu->smu_table;
594 SmuMetricsExternal_t *metrics_ext =
595 (SmuMetricsExternal_t *)(smu_table->metrics_table);
596 uint32_t throttler_status = 0;
599 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
600 (smu->smc_fw_version >= 0x3A4900)) {
601 for (i = 0; i < THROTTLER_COUNT; i++)
603 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
604 } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
605 (smu->smc_fw_version >= 0x3A4300)) {
606 for (i = 0; i < THROTTLER_COUNT; i++)
608 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
610 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
613 return throttler_status;
616 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
617 uint32_t *current_power_limit,
618 uint32_t *default_power_limit,
619 uint32_t *max_power_limit)
621 struct smu_11_0_7_powerplay_table *powerplay_table =
622 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
623 uint32_t power_limit, od_percent;
624 uint16_t *table_member;
626 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
628 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
630 table_member[PPT_THROTTLER_PPT0];
633 if (current_power_limit)
634 *current_power_limit = power_limit;
635 if (default_power_limit)
636 *default_power_limit = power_limit;
638 if (max_power_limit) {
639 if (smu->od_enabled) {
641 le32_to_cpu(powerplay_table->overdrive_table.max[
642 SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
644 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
645 od_percent, power_limit);
647 power_limit *= (100 + od_percent);
650 *max_power_limit = power_limit;
656 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
657 uint32_t *apu_percent,
658 uint32_t *dgpu_percent)
660 struct smu_table_context *smu_table = &smu->smu_table;
661 SmuMetrics_V4_t *metrics_v4 =
662 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
663 uint16_t powerRatio = 0;
664 uint16_t apu_power_limit = 0;
665 uint16_t dgpu_power_limit = 0;
666 uint32_t apu_boost = 0;
667 uint32_t dgpu_boost = 0;
668 uint32_t cur_power_limit;
670 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
671 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
672 apu_power_limit = metrics_v4->ApuSTAPMLimit;
673 dgpu_power_limit = cur_power_limit;
674 powerRatio = (((apu_power_limit +
675 dgpu_power_limit) * 100) /
676 metrics_v4->ApuSTAPMSmartShiftLimit);
677 if (powerRatio > 100) {
678 apu_power_limit = (apu_power_limit * 100) /
680 dgpu_power_limit = (dgpu_power_limit * 100) /
683 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
684 apu_power_limit != 0) {
685 apu_boost = ((metrics_v4->AverageApuSocketPower -
686 apu_power_limit) * 100) /
692 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
693 dgpu_power_limit != 0) {
694 dgpu_boost = ((metrics_v4->AverageSocketPower -
695 dgpu_power_limit) * 100) /
697 if (dgpu_boost > 100)
701 if (dgpu_boost >= apu_boost)
706 *apu_percent = apu_boost;
707 *dgpu_percent = dgpu_boost;
710 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
711 MetricsMember_t member,
714 struct smu_table_context *smu_table= &smu->smu_table;
715 SmuMetrics_t *metrics =
716 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
717 SmuMetrics_V2_t *metrics_v2 =
718 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
719 SmuMetrics_V3_t *metrics_v3 =
720 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
721 bool use_metrics_v2 = false;
722 bool use_metrics_v3 = false;
723 uint16_t average_gfx_activity;
725 uint32_t apu_percent = 0;
726 uint32_t dgpu_percent = 0;
728 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
729 case IP_VERSION(11, 0, 7):
730 if (smu->smc_fw_version >= 0x3A4900)
731 use_metrics_v3 = true;
732 else if (smu->smc_fw_version >= 0x3A4300)
733 use_metrics_v2 = true;
735 case IP_VERSION(11, 0, 11):
736 if (smu->smc_fw_version >= 0x412D00)
737 use_metrics_v2 = true;
739 case IP_VERSION(11, 0, 12):
740 if (smu->smc_fw_version >= 0x3B2300)
741 use_metrics_v2 = true;
743 case IP_VERSION(11, 0, 13):
744 if (smu->smc_fw_version >= 0x491100)
745 use_metrics_v2 = true;
751 ret = smu_cmn_get_metrics_table(smu,
758 case METRICS_CURR_GFXCLK:
759 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
760 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
761 metrics->CurrClock[PPCLK_GFXCLK];
763 case METRICS_CURR_SOCCLK:
764 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
765 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
766 metrics->CurrClock[PPCLK_SOCCLK];
768 case METRICS_CURR_UCLK:
769 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
770 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
771 metrics->CurrClock[PPCLK_UCLK];
773 case METRICS_CURR_VCLK:
774 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
775 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
776 metrics->CurrClock[PPCLK_VCLK_0];
778 case METRICS_CURR_VCLK1:
779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
781 metrics->CurrClock[PPCLK_VCLK_1];
783 case METRICS_CURR_DCLK:
784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
786 metrics->CurrClock[PPCLK_DCLK_0];
788 case METRICS_CURR_DCLK1:
789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
791 metrics->CurrClock[PPCLK_DCLK_1];
793 case METRICS_CURR_DCEFCLK:
794 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
796 metrics->CurrClock[PPCLK_DCEFCLK];
798 case METRICS_CURR_FCLK:
799 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
800 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
801 metrics->CurrClock[PPCLK_FCLK];
803 case METRICS_AVERAGE_GFXCLK:
804 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
805 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
806 metrics->AverageGfxActivity;
807 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
808 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
809 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
810 metrics->AverageGfxclkFrequencyPostDs;
812 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
813 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
814 metrics->AverageGfxclkFrequencyPreDs;
816 case METRICS_AVERAGE_FCLK:
817 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
818 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
819 metrics->AverageFclkFrequencyPostDs;
821 case METRICS_AVERAGE_UCLK:
822 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
823 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
824 metrics->AverageUclkFrequencyPostDs;
826 case METRICS_AVERAGE_GFXACTIVITY:
827 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
828 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
829 metrics->AverageGfxActivity;
831 case METRICS_AVERAGE_MEMACTIVITY:
832 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
833 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
834 metrics->AverageUclkActivity;
836 case METRICS_AVERAGE_SOCKETPOWER:
837 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
838 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
839 metrics->AverageSocketPower << 8;
841 case METRICS_TEMPERATURE_EDGE:
842 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
843 use_metrics_v2 ? metrics_v2->TemperatureEdge :
844 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
846 case METRICS_TEMPERATURE_HOTSPOT:
847 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
848 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
849 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
851 case METRICS_TEMPERATURE_MEM:
852 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
853 use_metrics_v2 ? metrics_v2->TemperatureMem :
854 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
856 case METRICS_TEMPERATURE_VRGFX:
857 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
858 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
859 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
861 case METRICS_TEMPERATURE_VRSOC:
862 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
863 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
864 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
866 case METRICS_THROTTLER_STATUS:
867 *value = sienna_cichlid_get_throttler_status_locked(smu);
869 case METRICS_CURR_FANSPEED:
870 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
871 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
873 case METRICS_UNIQUE_ID_UPPER32:
874 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
875 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
877 case METRICS_UNIQUE_ID_LOWER32:
878 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
879 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
881 case METRICS_SS_APU_SHARE:
882 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
883 *value = apu_percent;
885 case METRICS_SS_DGPU_SHARE:
886 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
887 *value = dgpu_percent;
899 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
901 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
903 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
905 if (!smu_dpm->dpm_context)
908 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
913 static void sienna_cichlid_stb_init(struct smu_context *smu);
915 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
917 struct amdgpu_device *adev = smu->adev;
920 ret = sienna_cichlid_tables_init(smu);
924 ret = sienna_cichlid_allocate_dpm_context(smu);
928 if (!amdgpu_sriov_vf(adev))
929 sienna_cichlid_stb_init(smu);
931 return smu_v11_0_init_smc_tables(smu);
934 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
936 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
937 struct smu_11_0_dpm_table *dpm_table;
938 struct amdgpu_device *adev = smu->adev;
940 DpmDescriptor_t *table_member;
942 /* socclk dpm table setup */
943 dpm_table = &dpm_context->dpm_tables.soc_table;
944 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
945 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
946 ret = smu_v11_0_set_single_dpm_table(smu,
951 dpm_table->is_fine_grained =
952 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
954 dpm_table->count = 1;
955 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
956 dpm_table->dpm_levels[0].enabled = true;
957 dpm_table->min = dpm_table->dpm_levels[0].value;
958 dpm_table->max = dpm_table->dpm_levels[0].value;
961 /* gfxclk dpm table setup */
962 dpm_table = &dpm_context->dpm_tables.gfx_table;
963 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
964 ret = smu_v11_0_set_single_dpm_table(smu,
969 dpm_table->is_fine_grained =
970 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
972 dpm_table->count = 1;
973 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
974 dpm_table->dpm_levels[0].enabled = true;
975 dpm_table->min = dpm_table->dpm_levels[0].value;
976 dpm_table->max = dpm_table->dpm_levels[0].value;
979 /* uclk dpm table setup */
980 dpm_table = &dpm_context->dpm_tables.uclk_table;
981 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
982 ret = smu_v11_0_set_single_dpm_table(smu,
987 dpm_table->is_fine_grained =
988 !table_member[PPCLK_UCLK].SnapToDiscrete;
990 dpm_table->count = 1;
991 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
992 dpm_table->dpm_levels[0].enabled = true;
993 dpm_table->min = dpm_table->dpm_levels[0].value;
994 dpm_table->max = dpm_table->dpm_levels[0].value;
997 /* fclk dpm table setup */
998 dpm_table = &dpm_context->dpm_tables.fclk_table;
999 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
1000 ret = smu_v11_0_set_single_dpm_table(smu,
1005 dpm_table->is_fine_grained =
1006 !table_member[PPCLK_FCLK].SnapToDiscrete;
1008 dpm_table->count = 1;
1009 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1010 dpm_table->dpm_levels[0].enabled = true;
1011 dpm_table->min = dpm_table->dpm_levels[0].value;
1012 dpm_table->max = dpm_table->dpm_levels[0].value;
1015 /* vclk0/1 dpm table setup */
1016 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1017 if (adev->vcn.harvest_config & (1 << i))
1020 dpm_table = &dpm_context->dpm_tables.vclk_table;
1021 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1022 ret = smu_v11_0_set_single_dpm_table(smu,
1023 i ? SMU_VCLK1 : SMU_VCLK,
1027 dpm_table->is_fine_grained =
1028 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1030 dpm_table->count = 1;
1031 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1032 dpm_table->dpm_levels[0].enabled = true;
1033 dpm_table->min = dpm_table->dpm_levels[0].value;
1034 dpm_table->max = dpm_table->dpm_levels[0].value;
1038 /* dclk0/1 dpm table setup */
1039 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1040 if (adev->vcn.harvest_config & (1 << i))
1042 dpm_table = &dpm_context->dpm_tables.dclk_table;
1043 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1044 ret = smu_v11_0_set_single_dpm_table(smu,
1045 i ? SMU_DCLK1 : SMU_DCLK,
1049 dpm_table->is_fine_grained =
1050 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1052 dpm_table->count = 1;
1053 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1054 dpm_table->dpm_levels[0].enabled = true;
1055 dpm_table->min = dpm_table->dpm_levels[0].value;
1056 dpm_table->max = dpm_table->dpm_levels[0].value;
1060 /* dcefclk dpm table setup */
1061 dpm_table = &dpm_context->dpm_tables.dcef_table;
1062 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1063 ret = smu_v11_0_set_single_dpm_table(smu,
1068 dpm_table->is_fine_grained =
1069 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1071 dpm_table->count = 1;
1072 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1073 dpm_table->dpm_levels[0].enabled = true;
1074 dpm_table->min = dpm_table->dpm_levels[0].value;
1075 dpm_table->max = dpm_table->dpm_levels[0].value;
1078 /* pixelclk dpm table setup */
1079 dpm_table = &dpm_context->dpm_tables.pixel_table;
1080 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1081 ret = smu_v11_0_set_single_dpm_table(smu,
1086 dpm_table->is_fine_grained =
1087 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1089 dpm_table->count = 1;
1090 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1091 dpm_table->dpm_levels[0].enabled = true;
1092 dpm_table->min = dpm_table->dpm_levels[0].value;
1093 dpm_table->max = dpm_table->dpm_levels[0].value;
1096 /* displayclk dpm table setup */
1097 dpm_table = &dpm_context->dpm_tables.display_table;
1098 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1099 ret = smu_v11_0_set_single_dpm_table(smu,
1104 dpm_table->is_fine_grained =
1105 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1107 dpm_table->count = 1;
1108 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1109 dpm_table->dpm_levels[0].enabled = true;
1110 dpm_table->min = dpm_table->dpm_levels[0].value;
1111 dpm_table->max = dpm_table->dpm_levels[0].value;
1114 /* phyclk dpm table setup */
1115 dpm_table = &dpm_context->dpm_tables.phy_table;
1116 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1117 ret = smu_v11_0_set_single_dpm_table(smu,
1122 dpm_table->is_fine_grained =
1123 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1125 dpm_table->count = 1;
1126 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1127 dpm_table->dpm_levels[0].enabled = true;
1128 dpm_table->min = dpm_table->dpm_levels[0].value;
1129 dpm_table->max = dpm_table->dpm_levels[0].value;
1135 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1137 struct amdgpu_device *adev = smu->adev;
1140 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1141 if (adev->vcn.harvest_config & (1 << i))
1143 /* vcn dpm on is a prerequisite for vcn power gate messages */
1144 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1145 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1146 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1156 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1161 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1162 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1167 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1168 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1177 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1178 enum smu_clk_type clk_type,
1181 MetricsMember_t member_type;
1184 clk_id = smu_cmn_to_asic_specific_index(smu,
1185 CMN2ASIC_MAPPING_CLK,
1192 member_type = METRICS_CURR_GFXCLK;
1195 member_type = METRICS_CURR_UCLK;
1198 member_type = METRICS_CURR_SOCCLK;
1201 member_type = METRICS_CURR_FCLK;
1204 member_type = METRICS_CURR_VCLK;
1207 member_type = METRICS_CURR_VCLK1;
1210 member_type = METRICS_CURR_DCLK;
1213 member_type = METRICS_CURR_DCLK1;
1216 member_type = METRICS_CURR_DCEFCLK;
1222 return sienna_cichlid_get_smu_metrics_data(smu,
1228 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1230 DpmDescriptor_t *dpm_desc = NULL;
1231 DpmDescriptor_t *table_member;
1232 uint32_t clk_index = 0;
1234 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1235 clk_index = smu_cmn_to_asic_specific_index(smu,
1236 CMN2ASIC_MAPPING_CLK,
1238 dpm_desc = &table_member[clk_index];
1240 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1241 return dpm_desc->SnapToDiscrete == 0;
1244 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1245 enum SMU_11_0_7_ODFEATURE_CAP cap)
1247 return od_table->cap[cap];
1250 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1251 enum SMU_11_0_7_ODSETTING_ID setting,
1252 uint32_t *min, uint32_t *max)
1255 *min = od_table->min[setting];
1257 *max = od_table->max[setting];
1260 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1261 enum smu_clk_type clk_type, char *buf)
1263 struct amdgpu_device *adev = smu->adev;
1264 struct smu_table_context *table_context = &smu->smu_table;
1265 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1266 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1267 uint16_t *table_member;
1269 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1270 OverDriveTable_t *od_table =
1271 (OverDriveTable_t *)table_context->overdrive_table;
1272 int i, size = 0, ret = 0;
1273 uint32_t cur_value = 0, value = 0, count = 0;
1274 uint32_t freq_values[3] = {0};
1275 uint32_t mark_index = 0;
1276 uint32_t gen_speed, lane_width;
1277 uint32_t min_value, max_value;
1278 uint32_t smu_version;
1280 smu_cmn_get_sysfs_buf(&buf, &size);
1294 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1298 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1302 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1303 for (i = 0; i < count; i++) {
1304 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1308 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1309 cur_value == value ? "*" : "");
1312 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1315 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1319 freq_values[1] = cur_value;
1320 mark_index = cur_value == freq_values[0] ? 0 :
1321 cur_value == freq_values[2] ? 2 : 1;
1324 if (mark_index != 1) {
1326 freq_values[1] = freq_values[2];
1329 for (i = 0; i < count; i++) {
1330 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1331 cur_value == freq_values[i] ? "*" : "");
1337 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1338 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1339 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1340 for (i = 0; i < NUM_LINK_LEVELS; i++)
1341 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1342 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1343 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1344 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1345 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1346 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1347 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1348 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1349 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1350 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1351 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1353 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1354 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1358 if (!smu->od_enabled || !od_table || !od_settings)
1361 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1364 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1365 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1369 if (!smu->od_enabled || !od_table || !od_settings)
1372 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1375 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1376 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1379 case SMU_OD_VDDGFX_OFFSET:
1380 if (!smu->od_enabled || !od_table || !od_settings)
1384 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1385 * and onwards SMU firmwares.
1387 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1388 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
1389 (smu_version < 0x003a2900))
1392 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1393 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1397 if (!smu->od_enabled || !od_table || !od_settings)
1400 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1402 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1403 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1405 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1407 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1408 min_value, max_value);
1411 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1412 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1414 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1416 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1417 min_value, max_value);
1429 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1430 enum smu_clk_type clk_type, uint32_t mask)
1433 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1435 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1436 soft_max_level = mask ? (fls(mask) - 1) : 0;
1445 /* There is only 2 levels for fine grained DPM */
1446 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1447 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1448 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1451 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1453 goto forec_level_out;
1455 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1457 goto forec_level_out;
1459 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1461 goto forec_level_out;
1464 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1474 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1476 struct smu_11_0_dpm_context *dpm_context =
1477 smu->smu_dpm.dpm_context;
1478 struct smu_11_0_dpm_table *gfx_table =
1479 &dpm_context->dpm_tables.gfx_table;
1480 struct smu_11_0_dpm_table *mem_table =
1481 &dpm_context->dpm_tables.uclk_table;
1482 struct smu_11_0_dpm_table *soc_table =
1483 &dpm_context->dpm_tables.soc_table;
1484 struct smu_umd_pstate_table *pstate_table =
1486 struct amdgpu_device *adev = smu->adev;
1488 pstate_table->gfxclk_pstate.min = gfx_table->min;
1489 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1491 pstate_table->uclk_pstate.min = mem_table->min;
1492 pstate_table->uclk_pstate.peak = mem_table->max;
1494 pstate_table->socclk_pstate.min = soc_table->min;
1495 pstate_table->socclk_pstate.peak = soc_table->max;
1497 switch (adev->ip_versions[MP1_HWIP][0]) {
1498 case IP_VERSION(11, 0, 7):
1499 case IP_VERSION(11, 0, 11):
1500 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1501 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1502 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1504 case IP_VERSION(11, 0, 12):
1505 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1506 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1507 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1509 case IP_VERSION(11, 0, 13):
1510 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1511 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1512 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1521 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1524 uint32_t max_freq = 0;
1526 /* Sienna_Cichlid do not support to change display num currently */
1529 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1534 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1535 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1538 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1546 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1550 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1551 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1552 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1554 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1555 smu->display_config->num_display,
1565 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1568 uint64_t feature_enabled;
1570 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1574 return !!(feature_enabled & SMC_DPM_FEATURE);
1577 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1584 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1585 * by pmfw is always trustable(even when the fan control feature
1586 * disabled or 0 RPM kicked in).
1588 return sienna_cichlid_get_smu_metrics_data(smu,
1589 METRICS_CURR_FANSPEED,
1593 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1595 uint16_t *table_member;
1597 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1598 smu->fan_max_rpm = *table_member;
1603 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1605 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1606 DpmActivityMonitorCoeffInt_t *activity_monitor =
1607 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1608 uint32_t i, size = 0;
1609 int16_t workload_type = 0;
1610 static const char *title[] = {
1611 "PROFILE_INDEX(NAME)",
1615 "MinActiveFreqType",
1620 "PD_Data_error_coeff",
1621 "PD_Data_error_rate_coeff"};
1627 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1628 title[0], title[1], title[2], title[3], title[4], title[5],
1629 title[6], title[7], title[8], title[9], title[10]);
1631 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1632 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1633 workload_type = smu_cmn_to_asic_specific_index(smu,
1634 CMN2ASIC_MAPPING_WORKLOAD,
1636 if (workload_type < 0)
1639 result = smu_cmn_update_table(smu,
1640 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1641 (void *)(&activity_monitor_external), false);
1643 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1647 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1648 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1650 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1654 activity_monitor->Gfx_FPS,
1655 activity_monitor->Gfx_MinFreqStep,
1656 activity_monitor->Gfx_MinActiveFreqType,
1657 activity_monitor->Gfx_MinActiveFreq,
1658 activity_monitor->Gfx_BoosterFreqType,
1659 activity_monitor->Gfx_BoosterFreq,
1660 activity_monitor->Gfx_PD_Data_limit_c,
1661 activity_monitor->Gfx_PD_Data_error_coeff,
1662 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1664 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1668 activity_monitor->Fclk_FPS,
1669 activity_monitor->Fclk_MinFreqStep,
1670 activity_monitor->Fclk_MinActiveFreqType,
1671 activity_monitor->Fclk_MinActiveFreq,
1672 activity_monitor->Fclk_BoosterFreqType,
1673 activity_monitor->Fclk_BoosterFreq,
1674 activity_monitor->Fclk_PD_Data_limit_c,
1675 activity_monitor->Fclk_PD_Data_error_coeff,
1676 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1678 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1682 activity_monitor->Mem_FPS,
1683 activity_monitor->Mem_MinFreqStep,
1684 activity_monitor->Mem_MinActiveFreqType,
1685 activity_monitor->Mem_MinActiveFreq,
1686 activity_monitor->Mem_BoosterFreqType,
1687 activity_monitor->Mem_BoosterFreq,
1688 activity_monitor->Mem_PD_Data_limit_c,
1689 activity_monitor->Mem_PD_Data_error_coeff,
1690 activity_monitor->Mem_PD_Data_error_rate_coeff);
1696 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1699 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1700 DpmActivityMonitorCoeffInt_t *activity_monitor =
1701 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1702 int workload_type, ret = 0;
1704 smu->power_profile_mode = input[size];
1706 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1707 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1711 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1713 ret = smu_cmn_update_table(smu,
1714 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1715 (void *)(&activity_monitor_external), false);
1717 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1722 case 0: /* Gfxclk */
1723 activity_monitor->Gfx_FPS = input[1];
1724 activity_monitor->Gfx_MinFreqStep = input[2];
1725 activity_monitor->Gfx_MinActiveFreqType = input[3];
1726 activity_monitor->Gfx_MinActiveFreq = input[4];
1727 activity_monitor->Gfx_BoosterFreqType = input[5];
1728 activity_monitor->Gfx_BoosterFreq = input[6];
1729 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1730 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1731 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1733 case 1: /* Socclk */
1734 activity_monitor->Fclk_FPS = input[1];
1735 activity_monitor->Fclk_MinFreqStep = input[2];
1736 activity_monitor->Fclk_MinActiveFreqType = input[3];
1737 activity_monitor->Fclk_MinActiveFreq = input[4];
1738 activity_monitor->Fclk_BoosterFreqType = input[5];
1739 activity_monitor->Fclk_BoosterFreq = input[6];
1740 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1741 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1742 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1745 activity_monitor->Mem_FPS = input[1];
1746 activity_monitor->Mem_MinFreqStep = input[2];
1747 activity_monitor->Mem_MinActiveFreqType = input[3];
1748 activity_monitor->Mem_MinActiveFreq = input[4];
1749 activity_monitor->Mem_BoosterFreqType = input[5];
1750 activity_monitor->Mem_BoosterFreq = input[6];
1751 activity_monitor->Mem_PD_Data_limit_c = input[7];
1752 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1753 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1757 ret = smu_cmn_update_table(smu,
1758 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1759 (void *)(&activity_monitor_external), true);
1761 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1766 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1767 workload_type = smu_cmn_to_asic_specific_index(smu,
1768 CMN2ASIC_MAPPING_WORKLOAD,
1769 smu->power_profile_mode);
1770 if (workload_type < 0)
1772 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1773 1 << workload_type, NULL);
1778 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1780 struct smu_clocks min_clocks = {0};
1781 struct pp_display_clock_request clock_req;
1784 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1785 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1786 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1788 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1789 clock_req.clock_type = amd_pp_dcef_clock;
1790 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1792 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1794 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1795 ret = smu_cmn_send_smc_msg_with_param(smu,
1796 SMU_MSG_SetMinDeepSleepDcefclk,
1797 min_clocks.dcef_clock_in_sr/100,
1800 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1805 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1809 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1810 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1812 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1820 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1821 struct pp_smu_wm_range_sets *clock_ranges)
1823 Watermarks_t *table = smu->smu_table.watermarks_table;
1828 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1829 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1832 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1833 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1834 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1835 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1836 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1837 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1838 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1839 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1840 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1842 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1843 clock_ranges->reader_wm_sets[i].wm_inst;
1846 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1847 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1848 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1849 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1850 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1851 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1852 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1853 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1854 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1856 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1857 clock_ranges->writer_wm_sets[i].wm_inst;
1860 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1863 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1864 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1865 ret = smu_cmn_write_watermarks_table(smu);
1867 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1870 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1876 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1877 enum amd_pp_sensors sensor,
1878 void *data, uint32_t *size)
1882 struct amdgpu_device *adev = smu->adev;
1888 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1889 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1890 *(uint16_t *)data = *temp;
1893 case AMDGPU_PP_SENSOR_MEM_LOAD:
1894 ret = sienna_cichlid_get_smu_metrics_data(smu,
1895 METRICS_AVERAGE_MEMACTIVITY,
1899 case AMDGPU_PP_SENSOR_GPU_LOAD:
1900 ret = sienna_cichlid_get_smu_metrics_data(smu,
1901 METRICS_AVERAGE_GFXACTIVITY,
1905 case AMDGPU_PP_SENSOR_GPU_POWER:
1906 ret = sienna_cichlid_get_smu_metrics_data(smu,
1907 METRICS_AVERAGE_SOCKETPOWER,
1911 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1912 ret = sienna_cichlid_get_smu_metrics_data(smu,
1913 METRICS_TEMPERATURE_HOTSPOT,
1917 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1918 ret = sienna_cichlid_get_smu_metrics_data(smu,
1919 METRICS_TEMPERATURE_EDGE,
1923 case AMDGPU_PP_SENSOR_MEM_TEMP:
1924 ret = sienna_cichlid_get_smu_metrics_data(smu,
1925 METRICS_TEMPERATURE_MEM,
1929 case AMDGPU_PP_SENSOR_GFX_MCLK:
1930 ret = sienna_cichlid_get_smu_metrics_data(smu,
1933 *(uint32_t *)data *= 100;
1936 case AMDGPU_PP_SENSOR_GFX_SCLK:
1937 ret = sienna_cichlid_get_smu_metrics_data(smu,
1938 METRICS_AVERAGE_GFXCLK,
1940 *(uint32_t *)data *= 100;
1943 case AMDGPU_PP_SENSOR_VDDGFX:
1944 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1947 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1948 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1949 ret = sienna_cichlid_get_smu_metrics_data(smu,
1950 METRICS_SS_APU_SHARE, (uint32_t *)data);
1956 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1957 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1958 ret = sienna_cichlid_get_smu_metrics_data(smu,
1959 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1973 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1975 struct amdgpu_device *adev = smu->adev;
1976 uint32_t upper32 = 0, lower32 = 0;
1978 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1979 if (smu->smc_fw_version < 0x3A5300 ||
1980 smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1983 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1985 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1990 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1991 if (adev->serial[0] == '\0')
1992 sprintf(adev->serial, "%016llx", adev->unique_id);
1995 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1997 uint32_t num_discrete_levels = 0;
1998 uint16_t *dpm_levels = NULL;
2000 struct smu_table_context *table_context = &smu->smu_table;
2001 DpmDescriptor_t *table_member1;
2002 uint16_t *table_member2;
2004 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2007 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
2008 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
2009 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
2010 dpm_levels = table_member2;
2012 if (num_discrete_levels == 0 || dpm_levels == NULL)
2015 *num_states = num_discrete_levels;
2016 for (i = 0; i < num_discrete_levels; i++) {
2017 /* convert to khz */
2018 *clocks_in_khz = (*dpm_levels) * 1000;
2026 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2027 struct smu_temperature_range *range)
2029 struct smu_table_context *table_context = &smu->smu_table;
2030 struct smu_11_0_7_powerplay_table *powerplay_table =
2031 table_context->power_play_table;
2032 uint16_t *table_member;
2033 uint16_t temp_edge, temp_hotspot, temp_mem;
2038 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2040 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2041 temp_edge = table_member[TEMP_EDGE];
2042 temp_hotspot = table_member[TEMP_HOTSPOT];
2043 temp_mem = table_member[TEMP_MEM];
2045 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2046 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2047 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2048 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2049 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2050 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2051 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2052 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2053 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2055 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2060 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2061 bool disable_memory_clock_switch)
2064 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2065 (struct smu_11_0_max_sustainable_clocks *)
2066 smu->smu_table.max_sustainable_clocks;
2067 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2068 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2070 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2073 if(disable_memory_clock_switch)
2074 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2076 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2079 smu->disable_uclk_switch = disable_memory_clock_switch;
2084 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2085 uint32_t pcie_gen_cap,
2086 uint32_t pcie_width_cap)
2088 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2089 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2093 /* PCIE gen speed and lane width override */
2094 if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2095 if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap)
2096 pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1];
2098 if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap)
2099 pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1];
2101 /* Force all levels to use the same settings */
2102 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2103 pcie_table->pcie_gen[i] = pcie_gen_cap;
2104 pcie_table->pcie_lane[i] = pcie_width_cap;
2107 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2108 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2109 pcie_table->pcie_gen[i] = pcie_gen_cap;
2110 if (pcie_table->pcie_lane[i] > pcie_width_cap)
2111 pcie_table->pcie_lane[i] = pcie_width_cap;
2115 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2116 smu_pcie_arg = (i << 16 |
2117 pcie_table->pcie_gen[i] << 8 |
2118 pcie_table->pcie_lane[i]);
2120 ret = smu_cmn_send_smc_msg_with_param(smu,
2121 SMU_MSG_OverridePcieParameters,
2131 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2132 enum smu_clk_type clk_type,
2133 uint32_t *min, uint32_t *max)
2135 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2138 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2139 OverDriveTable_t *od_table)
2141 struct amdgpu_device *adev = smu->adev;
2142 uint32_t smu_version;
2144 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2145 od_table->GfxclkFmax);
2146 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2147 od_table->UclkFmax);
2149 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2150 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2151 (smu_version < 0x003a2900)))
2152 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2155 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2157 OverDriveTable_t *od_table =
2158 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2159 OverDriveTable_t *boot_od_table =
2160 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2161 OverDriveTable_t *user_od_table =
2162 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2163 OverDriveTable_t user_od_table_bak;
2166 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2167 0, (void *)boot_od_table, false);
2169 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2173 sienna_cichlid_dump_od_table(smu, boot_od_table);
2175 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2178 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2179 * but we have to preserve user defined values in "user_od_table".
2181 if (!smu->adev->in_suspend) {
2182 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2183 smu->user_dpm_profile.user_od = false;
2184 } else if (smu->user_dpm_profile.user_od) {
2185 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2186 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2187 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2188 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2189 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2190 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2191 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2197 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2198 struct smu_11_0_7_overdrive_table *od_table,
2199 enum SMU_11_0_7_ODSETTING_ID setting,
2202 if (value < od_table->min[setting]) {
2203 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2204 setting, value, od_table->min[setting]);
2207 if (value > od_table->max[setting]) {
2208 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2209 setting, value, od_table->max[setting]);
2216 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2217 enum PP_OD_DPM_TABLE_COMMAND type,
2218 long input[], uint32_t size)
2220 struct smu_table_context *table_context = &smu->smu_table;
2221 OverDriveTable_t *od_table =
2222 (OverDriveTable_t *)table_context->overdrive_table;
2223 struct smu_11_0_7_overdrive_table *od_settings =
2224 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2225 struct amdgpu_device *adev = smu->adev;
2226 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2229 uint32_t smu_version;
2231 if (!smu->od_enabled) {
2232 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2236 if (!smu->od_settings) {
2237 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2241 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2242 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2247 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2248 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2249 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2250 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2254 for (i = 0; i < size; i += 2) {
2256 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2262 if (input[i + 1] > od_table->GfxclkFmax) {
2263 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2264 input[i + 1], od_table->GfxclkFmax);
2268 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2269 freq_ptr = &od_table->GfxclkFmin;
2273 if (input[i + 1] < od_table->GfxclkFmin) {
2274 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2275 input[i + 1], od_table->GfxclkFmin);
2279 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2280 freq_ptr = &od_table->GfxclkFmax;
2284 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2285 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2289 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2290 freq_setting, input[i + 1]);
2294 *freq_ptr = (uint16_t)input[i + 1];
2298 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2299 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2300 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2304 for (i = 0; i < size; i += 2) {
2306 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2312 if (input[i + 1] > od_table->UclkFmax) {
2313 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2314 input[i + 1], od_table->UclkFmax);
2318 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2319 freq_ptr = &od_table->UclkFmin;
2323 if (input[i + 1] < od_table->UclkFmin) {
2324 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2325 input[i + 1], od_table->UclkFmin);
2329 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2330 freq_ptr = &od_table->UclkFmax;
2334 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2335 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2339 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2340 freq_setting, input[i + 1]);
2344 *freq_ptr = (uint16_t)input[i + 1];
2348 case PP_OD_RESTORE_DEFAULT_TABLE:
2349 memcpy(table_context->overdrive_table,
2350 table_context->boot_overdrive_table,
2351 sizeof(OverDriveTable_t));
2354 case PP_OD_COMMIT_DPM_TABLE:
2355 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2356 sienna_cichlid_dump_od_table(smu, od_table);
2357 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2359 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2362 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2363 smu->user_dpm_profile.user_od = true;
2365 if (!memcmp(table_context->user_overdrive_table,
2366 table_context->boot_overdrive_table,
2367 sizeof(OverDriveTable_t)))
2368 smu->user_dpm_profile.user_od = false;
2372 case PP_OD_EDIT_VDDGFX_OFFSET:
2374 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2379 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2380 * and onwards SMU firmwares.
2382 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2383 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2384 (smu_version < 0x003a2900)) {
2385 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2386 "only by 58.41.0 and onwards SMU firmwares!\n");
2390 od_table->VddGfxOffset = (int16_t)input[0];
2392 sienna_cichlid_dump_od_table(smu, od_table);
2402 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2404 struct smu_table_context *table_context = &smu->smu_table;
2405 OverDriveTable_t *od_table = table_context->overdrive_table;
2406 OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2409 res = smu_v11_0_restore_user_od_settings(smu);
2411 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2416 static int sienna_cichlid_run_btc(struct smu_context *smu)
2420 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2422 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2427 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2429 struct amdgpu_device *adev = smu->adev;
2431 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2432 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2434 return smu_v11_0_baco_enter(smu);
2437 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2439 struct amdgpu_device *adev = smu->adev;
2441 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2442 /* Wait for PMFW handling for the Dstate change */
2444 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2446 return smu_v11_0_baco_exit(smu);
2450 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2452 struct amdgpu_device *adev = smu->adev;
2457 * SRIOV env will not support SMU mode1 reset
2458 * PM FW support mode1 reset from 58.26
2460 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2461 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2465 * mode1 reset relies on PSP, so we should check if
2468 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2472 static void beige_goby_dump_pptable(struct smu_context *smu)
2474 struct smu_table_context *table_context = &smu->smu_table;
2475 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2478 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2480 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2481 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2482 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2484 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2485 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2486 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2487 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2488 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2491 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2492 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2493 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2496 for (i = 0; i < TEMP_COUNT; i++) {
2497 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2500 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2501 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2502 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2503 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2504 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2506 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2507 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2508 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2509 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2511 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2513 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2515 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2516 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2517 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2518 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2520 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2522 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2524 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2525 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2526 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2527 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2529 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2530 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2532 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2533 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2534 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2535 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2536 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2537 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2538 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2539 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2541 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2542 " .VoltageMode = 0x%02x\n"
2543 " .SnapToDiscrete = 0x%02x\n"
2544 " .NumDiscreteLevels = 0x%02x\n"
2545 " .padding = 0x%02x\n"
2546 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2547 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2548 " .SsFmin = 0x%04x\n"
2549 " .Padding_16 = 0x%04x\n",
2550 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2551 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2552 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2553 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2554 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2555 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2556 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2557 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2558 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2559 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2560 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2562 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2563 " .VoltageMode = 0x%02x\n"
2564 " .SnapToDiscrete = 0x%02x\n"
2565 " .NumDiscreteLevels = 0x%02x\n"
2566 " .padding = 0x%02x\n"
2567 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2568 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2569 " .SsFmin = 0x%04x\n"
2570 " .Padding_16 = 0x%04x\n",
2571 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2572 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2573 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2574 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2575 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2576 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2577 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2578 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2579 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2580 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2581 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2583 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2584 " .VoltageMode = 0x%02x\n"
2585 " .SnapToDiscrete = 0x%02x\n"
2586 " .NumDiscreteLevels = 0x%02x\n"
2587 " .padding = 0x%02x\n"
2588 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2589 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2590 " .SsFmin = 0x%04x\n"
2591 " .Padding_16 = 0x%04x\n",
2592 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2593 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2594 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2595 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2596 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2597 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2598 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2599 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2600 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2601 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2602 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2604 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2605 " .VoltageMode = 0x%02x\n"
2606 " .SnapToDiscrete = 0x%02x\n"
2607 " .NumDiscreteLevels = 0x%02x\n"
2608 " .padding = 0x%02x\n"
2609 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2610 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2611 " .SsFmin = 0x%04x\n"
2612 " .Padding_16 = 0x%04x\n",
2613 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2614 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2615 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2616 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2617 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2618 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2619 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2620 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2621 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2622 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2623 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2625 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2626 " .VoltageMode = 0x%02x\n"
2627 " .SnapToDiscrete = 0x%02x\n"
2628 " .NumDiscreteLevels = 0x%02x\n"
2629 " .padding = 0x%02x\n"
2630 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2631 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2632 " .SsFmin = 0x%04x\n"
2633 " .Padding_16 = 0x%04x\n",
2634 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2635 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2636 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2637 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2638 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2639 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2640 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2641 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2642 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2643 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2644 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2646 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2647 " .VoltageMode = 0x%02x\n"
2648 " .SnapToDiscrete = 0x%02x\n"
2649 " .NumDiscreteLevels = 0x%02x\n"
2650 " .padding = 0x%02x\n"
2651 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2652 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2653 " .SsFmin = 0x%04x\n"
2654 " .Padding_16 = 0x%04x\n",
2655 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2656 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2657 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2658 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2659 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2660 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2661 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2662 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2663 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2664 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2665 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2667 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2668 " .VoltageMode = 0x%02x\n"
2669 " .SnapToDiscrete = 0x%02x\n"
2670 " .NumDiscreteLevels = 0x%02x\n"
2671 " .padding = 0x%02x\n"
2672 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2673 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2674 " .SsFmin = 0x%04x\n"
2675 " .Padding_16 = 0x%04x\n",
2676 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2677 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2678 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2679 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2680 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2681 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2682 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2683 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2684 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2685 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2686 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2688 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2689 " .VoltageMode = 0x%02x\n"
2690 " .SnapToDiscrete = 0x%02x\n"
2691 " .NumDiscreteLevels = 0x%02x\n"
2692 " .padding = 0x%02x\n"
2693 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2694 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2695 " .SsFmin = 0x%04x\n"
2696 " .Padding_16 = 0x%04x\n",
2697 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2698 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2699 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2700 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2701 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2702 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2703 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2704 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2705 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2706 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2707 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2709 dev_info(smu->adev->dev, "FreqTableGfx\n");
2710 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2711 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2713 dev_info(smu->adev->dev, "FreqTableVclk\n");
2714 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2715 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2717 dev_info(smu->adev->dev, "FreqTableDclk\n");
2718 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2719 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2721 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2722 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2723 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2725 dev_info(smu->adev->dev, "FreqTableUclk\n");
2726 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2727 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2729 dev_info(smu->adev->dev, "FreqTableFclk\n");
2730 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2731 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2733 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2734 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2735 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2736 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2737 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2738 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2739 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2740 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2741 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2743 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2744 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2745 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2747 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2748 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2750 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2751 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2752 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2754 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2755 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2756 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2758 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2759 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2760 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2762 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2763 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2764 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2766 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2767 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2768 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2769 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2770 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2772 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2774 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2775 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2776 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2777 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2778 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2779 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2780 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2781 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2782 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2783 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2784 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2786 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2787 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2788 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2789 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2790 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2791 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2793 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2794 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2795 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2796 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2797 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2799 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2800 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2801 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2803 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2804 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2805 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2806 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2808 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2809 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2810 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2812 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2813 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2814 pptable->UclkDpmSrcFreqRange.Fmin);
2815 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2816 pptable->UclkDpmSrcFreqRange.Fmax);
2817 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2818 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2819 pptable->UclkDpmTargFreqRange.Fmin);
2820 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2821 pptable->UclkDpmTargFreqRange.Fmax);
2822 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2823 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2825 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2826 for (i = 0; i < NUM_LINK_LEVELS; i++)
2827 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2829 dev_info(smu->adev->dev, "PcieLaneCount\n");
2830 for (i = 0; i < NUM_LINK_LEVELS; i++)
2831 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2833 dev_info(smu->adev->dev, "LclkFreq\n");
2834 for (i = 0; i < NUM_LINK_LEVELS; i++)
2835 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2837 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2838 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2840 dev_info(smu->adev->dev, "FanGain\n");
2841 for (i = 0; i < TEMP_COUNT; i++)
2842 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2844 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2845 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2846 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2847 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2848 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2849 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2850 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2851 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2852 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2853 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2854 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2855 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2857 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2858 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2859 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2860 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2862 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2863 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2864 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2865 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2867 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2868 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2869 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2870 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2871 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2872 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2873 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2874 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2875 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2876 pptable->dBtcGbGfxPll.a,
2877 pptable->dBtcGbGfxPll.b,
2878 pptable->dBtcGbGfxPll.c);
2879 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2880 pptable->dBtcGbGfxDfll.a,
2881 pptable->dBtcGbGfxDfll.b,
2882 pptable->dBtcGbGfxDfll.c);
2883 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2884 pptable->dBtcGbSoc.a,
2885 pptable->dBtcGbSoc.b,
2886 pptable->dBtcGbSoc.c);
2887 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2888 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2889 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2890 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2891 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2892 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2894 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2895 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2896 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2897 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2898 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2899 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2902 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2903 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2904 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2905 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2906 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2907 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2908 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2909 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2911 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2912 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2914 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2915 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2916 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2917 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2919 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2920 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2921 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2922 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2924 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2925 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2927 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2928 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2929 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2930 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2931 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2933 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2934 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2935 pptable->ReservedEquation0.a,
2936 pptable->ReservedEquation0.b,
2937 pptable->ReservedEquation0.c);
2938 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2939 pptable->ReservedEquation1.a,
2940 pptable->ReservedEquation1.b,
2941 pptable->ReservedEquation1.c);
2942 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2943 pptable->ReservedEquation2.a,
2944 pptable->ReservedEquation2.b,
2945 pptable->ReservedEquation2.c);
2946 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2947 pptable->ReservedEquation3.a,
2948 pptable->ReservedEquation3.b,
2949 pptable->ReservedEquation3.c);
2951 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2952 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2953 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2954 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2955 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2956 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2957 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2958 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2960 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2961 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2962 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2963 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2964 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2965 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2967 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2968 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2969 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2970 pptable->I2cControllers[i].Enabled);
2971 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2972 pptable->I2cControllers[i].Speed);
2973 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2974 pptable->I2cControllers[i].SlaveAddress);
2975 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2976 pptable->I2cControllers[i].ControllerPort);
2977 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2978 pptable->I2cControllers[i].ControllerName);
2979 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2980 pptable->I2cControllers[i].ThermalThrotter);
2981 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2982 pptable->I2cControllers[i].I2cProtocol);
2983 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2984 pptable->I2cControllers[i].PaddingConfig);
2987 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2988 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2989 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2990 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2992 dev_info(smu->adev->dev, "Board Parameters:\n");
2993 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2994 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2995 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2996 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2997 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2998 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2999 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3000 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3002 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3003 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3004 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3006 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3007 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3008 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3010 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3011 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3012 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3014 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3015 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3016 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3018 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3020 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3021 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3022 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3023 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3024 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3025 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3026 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3027 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3028 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3029 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3030 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3031 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3032 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3033 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3034 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3035 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3037 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3038 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3039 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3041 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3042 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3043 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3045 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3046 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3048 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3049 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3050 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3052 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3053 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3054 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3055 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3056 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3058 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3059 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3061 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3062 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3063 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3064 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3065 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3066 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3067 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3068 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3069 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3070 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3071 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3072 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3074 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3075 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3076 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3077 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3079 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3080 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3081 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3082 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3083 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3084 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3085 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3086 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3087 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3088 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3089 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3091 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3092 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3093 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3094 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3095 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3096 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3097 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3098 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3101 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3103 struct smu_table_context *table_context = &smu->smu_table;
3104 PPTable_t *pptable = table_context->driver_pptable;
3107 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
3108 beige_goby_dump_pptable(smu);
3112 dev_info(smu->adev->dev, "Dumped PPTable:\n");
3114 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3115 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3116 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3118 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3119 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3120 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3121 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3122 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3125 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3126 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3127 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3130 for (i = 0; i < TEMP_COUNT; i++) {
3131 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3134 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3135 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3136 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3137 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3138 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3140 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3141 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3142 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3143 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3145 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3147 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3149 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3150 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3151 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3152 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3154 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3155 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3157 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3158 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3159 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3160 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3162 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3163 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3164 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3165 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3167 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3168 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3170 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3171 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3172 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3173 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3174 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3175 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3176 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3177 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3179 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3180 " .VoltageMode = 0x%02x\n"
3181 " .SnapToDiscrete = 0x%02x\n"
3182 " .NumDiscreteLevels = 0x%02x\n"
3183 " .padding = 0x%02x\n"
3184 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3185 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3186 " .SsFmin = 0x%04x\n"
3187 " .Padding_16 = 0x%04x\n",
3188 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3189 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3190 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3191 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3192 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3193 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3194 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3195 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3196 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3197 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3198 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3200 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3201 " .VoltageMode = 0x%02x\n"
3202 " .SnapToDiscrete = 0x%02x\n"
3203 " .NumDiscreteLevels = 0x%02x\n"
3204 " .padding = 0x%02x\n"
3205 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3206 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3207 " .SsFmin = 0x%04x\n"
3208 " .Padding_16 = 0x%04x\n",
3209 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3210 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3211 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3212 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3213 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3214 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3215 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3216 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3217 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3218 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3219 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3221 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3222 " .VoltageMode = 0x%02x\n"
3223 " .SnapToDiscrete = 0x%02x\n"
3224 " .NumDiscreteLevels = 0x%02x\n"
3225 " .padding = 0x%02x\n"
3226 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3227 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3228 " .SsFmin = 0x%04x\n"
3229 " .Padding_16 = 0x%04x\n",
3230 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3231 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3232 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3233 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3234 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3235 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3236 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3237 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3238 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3239 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3240 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3242 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3243 " .VoltageMode = 0x%02x\n"
3244 " .SnapToDiscrete = 0x%02x\n"
3245 " .NumDiscreteLevels = 0x%02x\n"
3246 " .padding = 0x%02x\n"
3247 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3248 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3249 " .SsFmin = 0x%04x\n"
3250 " .Padding_16 = 0x%04x\n",
3251 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3252 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3253 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3254 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3255 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3256 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3257 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3258 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3259 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3260 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3261 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3263 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3264 " .VoltageMode = 0x%02x\n"
3265 " .SnapToDiscrete = 0x%02x\n"
3266 " .NumDiscreteLevels = 0x%02x\n"
3267 " .padding = 0x%02x\n"
3268 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3269 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3270 " .SsFmin = 0x%04x\n"
3271 " .Padding_16 = 0x%04x\n",
3272 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3273 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3274 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3275 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3276 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3277 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3278 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3279 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3280 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3281 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3282 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3284 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3285 " .VoltageMode = 0x%02x\n"
3286 " .SnapToDiscrete = 0x%02x\n"
3287 " .NumDiscreteLevels = 0x%02x\n"
3288 " .padding = 0x%02x\n"
3289 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3290 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3291 " .SsFmin = 0x%04x\n"
3292 " .Padding_16 = 0x%04x\n",
3293 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3294 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3295 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3296 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3297 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3298 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3299 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3300 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3301 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3302 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3303 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3305 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3306 " .VoltageMode = 0x%02x\n"
3307 " .SnapToDiscrete = 0x%02x\n"
3308 " .NumDiscreteLevels = 0x%02x\n"
3309 " .padding = 0x%02x\n"
3310 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3311 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3312 " .SsFmin = 0x%04x\n"
3313 " .Padding_16 = 0x%04x\n",
3314 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3315 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3316 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3317 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3318 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3319 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3320 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3321 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3322 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3323 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3324 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3326 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3327 " .VoltageMode = 0x%02x\n"
3328 " .SnapToDiscrete = 0x%02x\n"
3329 " .NumDiscreteLevels = 0x%02x\n"
3330 " .padding = 0x%02x\n"
3331 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3332 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3333 " .SsFmin = 0x%04x\n"
3334 " .Padding_16 = 0x%04x\n",
3335 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3336 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3337 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3338 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3339 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3340 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3341 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3342 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3343 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3344 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3345 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3347 dev_info(smu->adev->dev, "FreqTableGfx\n");
3348 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3349 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3351 dev_info(smu->adev->dev, "FreqTableVclk\n");
3352 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3353 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3355 dev_info(smu->adev->dev, "FreqTableDclk\n");
3356 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3357 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3359 dev_info(smu->adev->dev, "FreqTableSocclk\n");
3360 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3361 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3363 dev_info(smu->adev->dev, "FreqTableUclk\n");
3364 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3365 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3367 dev_info(smu->adev->dev, "FreqTableFclk\n");
3368 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3369 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3371 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3372 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3373 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3374 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3375 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3376 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3377 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3378 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3379 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3381 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3382 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3383 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3385 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3386 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3388 dev_info(smu->adev->dev, "Mp0clkFreq\n");
3389 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3390 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3392 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3393 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3394 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3396 dev_info(smu->adev->dev, "MemVddciVoltage\n");
3397 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3398 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3400 dev_info(smu->adev->dev, "MemMvddVoltage\n");
3401 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3402 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3404 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3405 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3406 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3407 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3408 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3410 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3412 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3413 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3414 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3415 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3416 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3417 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3418 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3419 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3420 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3421 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3422 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3424 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3425 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3426 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3427 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3428 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3429 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3431 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3432 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3433 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3434 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3435 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3437 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3438 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3439 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3441 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3442 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3443 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3444 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3446 dev_info(smu->adev->dev, "UclkDpmPstates\n");
3447 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3448 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3450 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3451 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3452 pptable->UclkDpmSrcFreqRange.Fmin);
3453 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3454 pptable->UclkDpmSrcFreqRange.Fmax);
3455 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3456 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3457 pptable->UclkDpmTargFreqRange.Fmin);
3458 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3459 pptable->UclkDpmTargFreqRange.Fmax);
3460 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3461 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3463 dev_info(smu->adev->dev, "PcieGenSpeed\n");
3464 for (i = 0; i < NUM_LINK_LEVELS; i++)
3465 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3467 dev_info(smu->adev->dev, "PcieLaneCount\n");
3468 for (i = 0; i < NUM_LINK_LEVELS; i++)
3469 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3471 dev_info(smu->adev->dev, "LclkFreq\n");
3472 for (i = 0; i < NUM_LINK_LEVELS; i++)
3473 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3475 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3476 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3478 dev_info(smu->adev->dev, "FanGain\n");
3479 for (i = 0; i < TEMP_COUNT; i++)
3480 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3482 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3483 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3484 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3485 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3486 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3487 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3488 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3489 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3490 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3491 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3492 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3493 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3495 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3496 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3497 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3498 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3500 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3501 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3502 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3503 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3505 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3506 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3507 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3508 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3509 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3510 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3511 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3512 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3513 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3514 pptable->dBtcGbGfxPll.a,
3515 pptable->dBtcGbGfxPll.b,
3516 pptable->dBtcGbGfxPll.c);
3517 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3518 pptable->dBtcGbGfxDfll.a,
3519 pptable->dBtcGbGfxDfll.b,
3520 pptable->dBtcGbGfxDfll.c);
3521 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3522 pptable->dBtcGbSoc.a,
3523 pptable->dBtcGbSoc.b,
3524 pptable->dBtcGbSoc.c);
3525 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3526 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3527 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3528 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3529 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3530 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3532 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3533 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3534 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
3535 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3536 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
3537 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3540 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3541 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3542 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3543 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3544 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3545 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3546 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3547 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3549 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3550 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3552 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3553 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3554 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3555 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3557 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3558 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3559 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3560 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3562 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3563 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3565 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3566 for (i = 0; i < NUM_XGMI_LEVELS; i++)
3567 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3568 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3569 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3571 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3572 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3573 pptable->ReservedEquation0.a,
3574 pptable->ReservedEquation0.b,
3575 pptable->ReservedEquation0.c);
3576 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3577 pptable->ReservedEquation1.a,
3578 pptable->ReservedEquation1.b,
3579 pptable->ReservedEquation1.c);
3580 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3581 pptable->ReservedEquation2.a,
3582 pptable->ReservedEquation2.b,
3583 pptable->ReservedEquation2.c);
3584 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3585 pptable->ReservedEquation3.a,
3586 pptable->ReservedEquation3.b,
3587 pptable->ReservedEquation3.c);
3589 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3590 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3591 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3592 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3593 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3594 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3595 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3596 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3598 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3599 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3600 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3601 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3602 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3603 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3605 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3606 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3607 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3608 pptable->I2cControllers[i].Enabled);
3609 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3610 pptable->I2cControllers[i].Speed);
3611 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3612 pptable->I2cControllers[i].SlaveAddress);
3613 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3614 pptable->I2cControllers[i].ControllerPort);
3615 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3616 pptable->I2cControllers[i].ControllerName);
3617 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3618 pptable->I2cControllers[i].ThermalThrotter);
3619 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3620 pptable->I2cControllers[i].I2cProtocol);
3621 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3622 pptable->I2cControllers[i].PaddingConfig);
3625 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3626 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3627 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3628 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3630 dev_info(smu->adev->dev, "Board Parameters:\n");
3631 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3632 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3633 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3634 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3635 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3636 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3637 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3638 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3640 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3641 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3642 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3644 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3645 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3646 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3648 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3649 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3650 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3652 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3653 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3654 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3656 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3658 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3659 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3660 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3661 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3662 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3663 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3664 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3665 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3666 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3667 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3668 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3669 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3670 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3671 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3672 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3673 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3675 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3676 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3677 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3679 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3680 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3681 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3683 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3684 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3686 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3687 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3688 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3690 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3691 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3692 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3693 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3694 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3696 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3697 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3699 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3700 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3701 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3702 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3703 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3704 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3705 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3706 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3707 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3708 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3709 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3710 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3712 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3713 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3714 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3715 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3717 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3718 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3719 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3720 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3721 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3722 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3723 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3724 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3725 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3726 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3727 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3729 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3730 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3731 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3732 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3733 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3734 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3735 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3736 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3739 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3740 struct i2c_msg *msg, int num_msgs)
3742 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3743 struct amdgpu_device *adev = smu_i2c->adev;
3744 struct smu_context *smu = adev->powerplay.pp_handle;
3745 struct smu_table_context *smu_table = &smu->smu_table;
3746 struct smu_table *table = &smu_table->driver_table;
3747 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3751 if (!adev->pm.dpm_enabled)
3754 req = kzalloc(sizeof(*req), GFP_KERNEL);
3758 req->I2CcontrollerPort = smu_i2c->port;
3759 req->I2CSpeed = I2C_SPEED_FAST_400K;
3760 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3761 dir = msg[0].flags & I2C_M_RD;
3763 for (c = i = 0; i < num_msgs; i++) {
3764 for (j = 0; j < msg[i].len; j++, c++) {
3765 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3767 if (!(msg[i].flags & I2C_M_RD)) {
3769 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3770 cmd->ReadWriteData = msg[i].buf[j];
3773 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3774 /* The direction changes.
3776 dir = msg[i].flags & I2C_M_RD;
3777 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3783 * Insert STOP if we are at the last byte of either last
3784 * message for the transaction or the client explicitly
3785 * requires a STOP at this particular message.
3787 if ((j == msg[i].len - 1) &&
3788 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3789 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3790 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3794 mutex_lock(&adev->pm.mutex);
3795 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3799 for (c = i = 0; i < num_msgs; i++) {
3800 if (!(msg[i].flags & I2C_M_RD)) {
3804 for (j = 0; j < msg[i].len; j++, c++) {
3805 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3807 msg[i].buf[j] = cmd->ReadWriteData;
3812 mutex_unlock(&adev->pm.mutex);
3817 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3819 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3823 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3824 .master_xfer = sienna_cichlid_i2c_xfer,
3825 .functionality = sienna_cichlid_i2c_func,
3828 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3829 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3830 .max_read_len = MAX_SW_I2C_COMMANDS,
3831 .max_write_len = MAX_SW_I2C_COMMANDS,
3832 .max_comb_1st_msg_len = 2,
3833 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3836 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3838 struct amdgpu_device *adev = smu->adev;
3841 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3842 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3843 struct i2c_adapter *control = &smu_i2c->adapter;
3845 smu_i2c->adev = adev;
3847 mutex_init(&smu_i2c->mutex);
3848 control->owner = THIS_MODULE;
3849 control->class = I2C_CLASS_HWMON;
3850 control->dev.parent = &adev->pdev->dev;
3851 control->algo = &sienna_cichlid_i2c_algo;
3852 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3853 control->quirks = &sienna_cichlid_i2c_control_quirks;
3854 i2c_set_adapdata(control, smu_i2c);
3856 res = i2c_add_adapter(control);
3858 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3862 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3863 /* XXX ideally this would be something in a vbios data table */
3864 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3865 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3869 for ( ; i >= 0; i--) {
3870 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3871 struct i2c_adapter *control = &smu_i2c->adapter;
3873 i2c_del_adapter(control);
3878 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3880 struct amdgpu_device *adev = smu->adev;
3883 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3884 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3885 struct i2c_adapter *control = &smu_i2c->adapter;
3887 i2c_del_adapter(control);
3889 adev->pm.ras_eeprom_i2c_bus = NULL;
3890 adev->pm.fru_eeprom_i2c_bus = NULL;
3893 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3896 struct smu_table_context *smu_table = &smu->smu_table;
3897 struct gpu_metrics_v1_3 *gpu_metrics =
3898 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3899 SmuMetricsExternal_t metrics_external;
3900 SmuMetrics_t *metrics =
3901 &(metrics_external.SmuMetrics);
3902 SmuMetrics_V2_t *metrics_v2 =
3903 &(metrics_external.SmuMetrics_V2);
3904 SmuMetrics_V3_t *metrics_v3 =
3905 &(metrics_external.SmuMetrics_V3);
3906 struct amdgpu_device *adev = smu->adev;
3907 bool use_metrics_v2 = false;
3908 bool use_metrics_v3 = false;
3909 uint16_t average_gfx_activity;
3912 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3913 case IP_VERSION(11, 0, 7):
3914 if (smu->smc_fw_version >= 0x3A4900)
3915 use_metrics_v3 = true;
3916 else if (smu->smc_fw_version >= 0x3A4300)
3917 use_metrics_v2 = true;
3919 case IP_VERSION(11, 0, 11):
3920 if (smu->smc_fw_version >= 0x412D00)
3921 use_metrics_v2 = true;
3923 case IP_VERSION(11, 0, 12):
3924 if (smu->smc_fw_version >= 0x3B2300)
3925 use_metrics_v2 = true;
3927 case IP_VERSION(11, 0, 13):
3928 if (smu->smc_fw_version >= 0x491100)
3929 use_metrics_v2 = true;
3935 ret = smu_cmn_get_metrics_table(smu,
3941 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3943 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3944 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3945 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3946 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3947 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3948 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3949 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3950 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3951 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3952 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3953 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3954 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3956 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3957 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3958 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3959 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3960 gpu_metrics->average_mm_activity = use_metrics_v3 ?
3961 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3962 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3964 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3965 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3966 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3967 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3969 if (metrics->CurrGfxVoltageOffset)
3970 gpu_metrics->voltage_gfx =
3971 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3972 if (metrics->CurrMemVidOffset)
3973 gpu_metrics->voltage_mem =
3974 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3975 if (metrics->CurrSocVoltageOffset)
3976 gpu_metrics->voltage_soc =
3977 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3979 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3980 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3981 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3982 gpu_metrics->average_gfxclk_frequency =
3983 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3984 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3985 metrics->AverageGfxclkFrequencyPostDs;
3987 gpu_metrics->average_gfxclk_frequency =
3988 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3989 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3990 metrics->AverageGfxclkFrequencyPreDs;
3992 gpu_metrics->average_uclk_frequency =
3993 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3994 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3995 metrics->AverageUclkFrequencyPostDs;
3996 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
3997 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3998 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
3999 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
4000 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
4001 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
4002 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
4003 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
4005 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
4006 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
4007 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
4008 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
4009 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
4010 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
4011 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
4012 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
4013 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
4014 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
4015 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
4016 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
4017 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
4018 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
4020 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
4021 gpu_metrics->indep_throttle_status =
4022 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
4023 sienna_cichlid_throttler_map);
4025 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
4026 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
4028 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
4029 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
4030 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
4031 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
4032 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
4033 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
4035 gpu_metrics->pcie_link_width =
4036 smu_v11_0_get_current_pcie_link_width(smu);
4037 gpu_metrics->pcie_link_speed =
4038 smu_v11_0_get_current_pcie_link_speed(smu);
4041 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4043 *table = (void *)gpu_metrics;
4045 return sizeof(struct gpu_metrics_v1_3);
4048 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4050 uint32_t if_version = 0xff, smu_version = 0xff;
4053 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
4057 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4063 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4066 struct smu_table_context *smu_table = &smu->smu_table;
4067 EccInfoTable_t *ecc_table = NULL;
4068 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4070 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4072 ret = sienna_cichlid_check_ecc_table_support(smu);
4076 ret = smu_cmn_update_table(smu,
4079 smu_table->ecc_table,
4082 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4086 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4088 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4089 ecc_info_per_channel = &(eccinfo->ecc[i]);
4090 ecc_info_per_channel->ce_count_lo_chip =
4091 ecc_table->EccInfo[i].ce_count_lo_chip;
4092 ecc_info_per_channel->ce_count_hi_chip =
4093 ecc_table->EccInfo[i].ce_count_hi_chip;
4094 ecc_info_per_channel->mca_umc_status =
4095 ecc_table->EccInfo[i].mca_umc_status;
4096 ecc_info_per_channel->mca_umc_addr =
4097 ecc_table->EccInfo[i].mca_umc_addr;
4102 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4104 uint16_t *mgpu_fan_boost_limit_rpm;
4106 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4108 * Skip the MGpuFanBoost setting for those ASICs
4109 * which do not support it
4111 if (*mgpu_fan_boost_limit_rpm == 0)
4114 return smu_cmn_send_smc_msg_with_param(smu,
4115 SMU_MSG_SetMGpuFanBoostLimitRpm,
4120 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4123 uint32_t smu_version;
4127 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4128 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4133 if (smu_version < 0x003a2500) {
4134 ret = smu_cmn_send_smc_msg_with_param(smu,
4135 SMU_MSG_SetGpoFeaturePMask,
4136 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4139 ret = smu_cmn_send_smc_msg_with_param(smu,
4140 SMU_MSG_DisallowGpo,
4145 if (smu_version < 0x003a2500) {
4146 ret = smu_cmn_send_smc_msg_with_param(smu,
4147 SMU_MSG_SetGpoFeaturePMask,
4151 ret = smu_cmn_send_smc_msg_with_param(smu,
4152 SMU_MSG_DisallowGpo,
4162 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4164 uint32_t smu_version;
4167 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4172 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4175 if (smu_version < 0x003A2D00)
4178 return smu_cmn_send_smc_msg_with_param(smu,
4179 SMU_MSG_Enable2ndUSB20Port,
4180 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4185 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4191 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4196 return smu_v11_0_system_features_control(smu, en);
4199 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4200 enum pp_mp1_state mp1_state)
4204 switch (mp1_state) {
4205 case PP_MP1_STATE_UNLOAD:
4206 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4216 static void sienna_cichlid_stb_init(struct smu_context *smu)
4218 struct amdgpu_device *adev = smu->adev;
4221 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4222 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4224 /* STB is disabled */
4225 if (!smu->stb_context.enabled)
4228 spin_lock_init(&smu->stb_context.lock);
4230 /* STB buffer size in bytes as function of FIFO depth */
4231 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4232 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4233 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4235 dev_info(smu->adev->dev, "STB initialized to %d entries",
4236 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4240 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4241 struct config_table_setting *table)
4243 struct amdgpu_device *adev = smu->adev;
4248 table->gfxclk_average_tau = 10;
4249 table->socclk_average_tau = 10;
4250 table->fclk_average_tau = 10;
4251 table->uclk_average_tau = 10;
4252 table->gfx_activity_average_tau = 10;
4253 table->mem_activity_average_tau = 10;
4254 table->socket_power_average_tau = 100;
4255 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
4256 table->apu_socket_power_average_tau = 100;
4261 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4262 struct config_table_setting *table)
4264 DriverSmuConfigExternal_t driver_smu_config_table;
4269 memset(&driver_smu_config_table,
4271 sizeof(driver_smu_config_table));
4272 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4273 table->gfxclk_average_tau;
4274 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4275 table->fclk_average_tau;
4276 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4277 table->uclk_average_tau;
4278 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4279 table->gfx_activity_average_tau;
4280 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4281 table->mem_activity_average_tau;
4282 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4283 table->socket_power_average_tau;
4285 return smu_cmn_update_table(smu,
4286 SMU_TABLE_DRIVER_SMU_CONFIG,
4288 (void *)&driver_smu_config_table,
4292 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4297 struct amdgpu_device *adev = smu->adev;
4299 /* No need to disable interrupts for now as we don't lock it yet from ISR */
4300 spin_lock(&smu->stb_context.lock);
4303 * Read the STB FIFO in units of 32bit since this is the accessor window
4304 * (register width) we have.
4306 buf = ((char *) buf) + size;
4307 while ((void *)p < buf)
4308 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4310 spin_unlock(&smu->stb_context.lock);
4315 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4320 static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4324 struct amdgpu_device *adev = smu->adev;
4327 smu_cmn_get_smc_version(smu, NULL, &smu_version);
4329 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4330 SMU_MSG_DriverMode2Reset);
4332 mutex_lock(&smu->message_lock);
4334 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4337 ret = smu_cmn_wait_for_response(smu);
4338 while (ret != 0 && timeout) {
4339 ret = smu_cmn_wait_for_response(smu);
4340 /* Wait a bit more time for getting ACK */
4343 usleep_range(500, 1000);
4352 "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4353 SMU_RESET_MODE_2, ret);
4357 dev_info(smu->adev->dev, "restore config space...\n");
4358 /* Restore the config space saved during init */
4359 amdgpu_device_load_pci_state(adev->pdev);
4361 mutex_unlock(&smu->message_lock);
4366 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4367 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4368 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4369 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4370 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4371 .i2c_init = sienna_cichlid_i2c_control_init,
4372 .i2c_fini = sienna_cichlid_i2c_control_fini,
4373 .print_clk_levels = sienna_cichlid_print_clk_levels,
4374 .force_clk_levels = sienna_cichlid_force_clk_levels,
4375 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4376 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4377 .display_config_changed = sienna_cichlid_display_config_changed,
4378 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4379 .is_dpm_running = sienna_cichlid_is_dpm_running,
4380 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4381 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4382 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4383 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4384 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4385 .read_sensor = sienna_cichlid_read_sensor,
4386 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4387 .set_performance_level = smu_v11_0_set_performance_level,
4388 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4389 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4390 .get_power_limit = sienna_cichlid_get_power_limit,
4391 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4392 .dump_pptable = sienna_cichlid_dump_pptable,
4393 .init_microcode = smu_v11_0_init_microcode,
4394 .load_microcode = smu_v11_0_load_microcode,
4395 .fini_microcode = smu_v11_0_fini_microcode,
4396 .init_smc_tables = sienna_cichlid_init_smc_tables,
4397 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4398 .init_power = smu_v11_0_init_power,
4399 .fini_power = smu_v11_0_fini_power,
4400 .check_fw_status = smu_v11_0_check_fw_status,
4401 .setup_pptable = sienna_cichlid_setup_pptable,
4402 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4403 .check_fw_version = smu_v11_0_check_fw_version,
4404 .write_pptable = smu_cmn_write_pptable,
4405 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4406 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4407 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4408 .system_features_control = sienna_cichlid_system_features_control,
4409 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4410 .send_smc_msg = smu_cmn_send_smc_msg,
4411 .init_display_count = NULL,
4412 .set_allowed_mask = smu_v11_0_set_allowed_mask,
4413 .get_enabled_mask = smu_cmn_get_enabled_mask,
4414 .feature_is_enabled = smu_cmn_feature_is_enabled,
4415 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4416 .notify_display_change = NULL,
4417 .set_power_limit = smu_v11_0_set_power_limit,
4418 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4419 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4420 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4421 .set_min_dcef_deep_sleep = NULL,
4422 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4423 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4424 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4425 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4426 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4427 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4428 .gfx_off_control = smu_v11_0_gfx_off_control,
4429 .register_irq_handler = smu_v11_0_register_irq_handler,
4430 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4431 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4432 .baco_is_support = smu_v11_0_baco_is_support,
4433 .baco_get_state = smu_v11_0_baco_get_state,
4434 .baco_set_state = smu_v11_0_baco_set_state,
4435 .baco_enter = sienna_cichlid_baco_enter,
4436 .baco_exit = sienna_cichlid_baco_exit,
4437 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4438 .mode1_reset = smu_v11_0_mode1_reset,
4439 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4440 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4441 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4442 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4443 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
4444 .run_btc = sienna_cichlid_run_btc,
4445 .set_power_source = smu_v11_0_set_power_source,
4446 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4447 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4448 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4449 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4450 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4451 .deep_sleep_control = smu_v11_0_deep_sleep_control,
4452 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4453 .interrupt_work = smu_v11_0_interrupt_work,
4454 .gpo_control = sienna_cichlid_gpo_control,
4455 .set_mp1_state = sienna_cichlid_set_mp1_state,
4456 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4457 .get_ecc_info = sienna_cichlid_get_ecc_info,
4458 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4459 .set_config_table = sienna_cichlid_set_config_table,
4460 .get_unique_id = sienna_cichlid_get_unique_id,
4461 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4462 .mode2_reset = sienna_cichlid_mode2_reset,
4465 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4467 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4468 smu->message_map = sienna_cichlid_message_map;
4469 smu->clock_map = sienna_cichlid_clk_map;
4470 smu->feature_map = sienna_cichlid_feature_mask_map;
4471 smu->table_map = sienna_cichlid_table_map;
4472 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4473 smu->workload_map = sienna_cichlid_workload_map;
4474 smu_v11_0_set_smu_mailbox_registers(smu);