2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "soc15_common.h"
35 #include "smu_v11_0.h"
36 #include "smu11_driver_if_navi10.h"
38 #include "navi10_ppt.h"
39 #include "smu_v11_0_pptable.h"
40 #include "smu_v11_0_ppsmc.h"
41 #include "nbio/nbio_2_3_offset.h"
42 #include "nbio/nbio_2_3_sh_mask.h"
43 #include "thm/thm_11_0_2_offset.h"
44 #include "thm/thm_11_0_2_sh_mask.h"
46 #include "asic_reg/mp/mp_11_0_sh_mask.h"
48 #include "smu_11_0_cdr_table.h"
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
73 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
75 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0),
84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0),
85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
98 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
99 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0),
100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
108 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0),
109 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
110 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
111 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
112 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
113 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0),
114 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
115 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
116 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
117 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
118 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
119 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
120 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
121 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
122 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0),
123 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0),
124 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
125 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
126 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
127 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
128 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
129 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
130 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
131 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
132 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
133 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
134 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
135 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
136 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
137 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
138 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
139 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
140 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange, 0),
141 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
142 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
143 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
146 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
147 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0),
150 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_SOCCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK),
158 CLK_MAP(VCLK, PPCLK_VCLK),
159 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
160 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
161 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
162 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
165 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
166 FEA_MAP(DPM_PREFETCHER),
168 FEA_MAP(DPM_GFX_PACE),
173 FEA_MAP(DPM_DCEFCLK),
174 FEA_MAP(MEM_VDDCI_SCALING),
175 FEA_MAP(MEM_MVDD_SCALING),
188 FEA_MAP(RSMU_SMN_CG),
198 FEA_MAP(FAN_CONTROL),
202 FEA_MAP(LED_DISPLAY),
204 FEA_MAP(OUT_OF_BAND_MONITOR),
205 FEA_MAP(TEMP_DEPENDENT_VMIN),
211 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
215 TAB_MAP(AVFS_PSM_DEBUG),
216 TAB_MAP(AVFS_FUSE_OVERRIDE),
217 TAB_MAP(PMSTATUSLOG),
218 TAB_MAP(SMU_METRICS),
219 TAB_MAP(DRIVER_SMU_CONFIG),
220 TAB_MAP(ACTIVITY_MONITOR_COEFF),
222 TAB_MAP(I2C_COMMANDS),
226 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
231 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
241 static const uint8_t navi1x_throttler_map[] = {
242 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
243 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
244 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
245 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
246 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
247 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
248 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
249 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
250 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
251 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
252 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
253 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
254 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
255 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
256 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
257 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
258 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
259 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
263 static bool is_asic_secure(struct smu_context *smu)
265 struct amdgpu_device *adev = smu->adev;
266 bool is_secure = true;
267 uint32_t mp0_fw_intf;
269 mp0_fw_intf = RREG32_PCIE(MP0_Public |
270 (smnMP0_FW_INTF & 0xffffffff));
272 if (!(mp0_fw_intf & (1 << 19)))
279 navi10_get_allowed_feature_mask(struct smu_context *smu,
280 uint32_t *feature_mask, uint32_t num)
282 struct amdgpu_device *adev = smu->adev;
287 memset(feature_mask, 0, sizeof(uint32_t) * num);
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
291 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
292 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293 | FEATURE_MASK(FEATURE_PPT_BIT)
294 | FEATURE_MASK(FEATURE_TDC_BIT)
295 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
296 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
297 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
298 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
299 | FEATURE_MASK(FEATURE_THERMAL_BIT)
300 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
301 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
302 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
303 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
304 | FEATURE_MASK(FEATURE_BACO_BIT)
305 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
306 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
307 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
308 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
337 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
340 if (smu->dc_controlled_by_gpio)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
343 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
346 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
347 if (!(is_asic_secure(smu) &&
348 (adev->asic_type == CHIP_NAVI10) &&
349 (adev->rev_id == 0)) &&
350 (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
352 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
353 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
355 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
356 if (is_asic_secure(smu) &&
357 (adev->asic_type == CHIP_NAVI10) &&
359 *(uint64_t *)feature_mask &=
360 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
365 static void navi10_check_bxco_support(struct smu_context *smu)
367 struct smu_table_context *table_context = &smu->smu_table;
368 struct smu_11_0_powerplay_table *powerplay_table =
369 table_context->power_play_table;
370 struct smu_baco_context *smu_baco = &smu->smu_baco;
371 struct amdgpu_device *adev = smu->adev;
374 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
375 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
376 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
377 smu_baco->platform_support =
378 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
383 static int navi10_check_powerplay_table(struct smu_context *smu)
385 struct smu_table_context *table_context = &smu->smu_table;
386 struct smu_11_0_powerplay_table *powerplay_table =
387 table_context->power_play_table;
389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
390 smu->dc_controlled_by_gpio = true;
392 navi10_check_bxco_support(smu);
394 table_context->thermal_controller_type =
395 powerplay_table->thermal_controller_type;
398 * Instead of having its own buffer space and get overdrive_table copied,
399 * smu->od_settings just points to the actual overdrive_table
401 smu->od_settings = &powerplay_table->overdrive_table;
406 static int navi10_append_powerplay_table(struct smu_context *smu)
408 struct amdgpu_device *adev = smu->adev;
409 struct smu_table_context *table_context = &smu->smu_table;
410 PPTable_t *smc_pptable = table_context->driver_pptable;
411 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
412 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
415 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
418 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
419 (uint8_t **)&smc_dpm_table);
423 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
424 smc_dpm_table->table_header.format_revision,
425 smc_dpm_table->table_header.content_revision);
427 if (smc_dpm_table->table_header.format_revision != 4) {
428 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
432 switch (smc_dpm_table->table_header.content_revision) {
433 case 5: /* nv10 and nv14 */
434 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
435 smc_dpm_table, I2cControllers);
438 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
439 (uint8_t **)&smc_dpm_table_v4_7);
442 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
443 smc_dpm_table_v4_7, I2cControllers);
446 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
447 smc_dpm_table->table_header.content_revision);
451 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
452 /* TODO: remove it once SMU fw fix it */
453 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
459 static int navi10_store_powerplay_table(struct smu_context *smu)
461 struct smu_table_context *table_context = &smu->smu_table;
462 struct smu_11_0_powerplay_table *powerplay_table =
463 table_context->power_play_table;
465 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
471 static int navi10_setup_pptable(struct smu_context *smu)
475 ret = smu_v11_0_setup_pptable(smu);
479 ret = navi10_store_powerplay_table(smu);
483 ret = navi10_append_powerplay_table(smu);
487 ret = navi10_check_powerplay_table(smu);
494 static int navi10_tables_init(struct smu_context *smu)
496 struct smu_table_context *smu_table = &smu->smu_table;
497 struct smu_table *tables = smu_table->tables;
499 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
500 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
501 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
505 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
507 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
509 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
511 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
512 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
513 AMDGPU_GEM_DOMAIN_VRAM);
515 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
517 if (!smu_table->metrics_table)
519 smu_table->metrics_time = 0;
521 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
522 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
523 if (!smu_table->gpu_metrics_table)
526 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
527 if (!smu_table->watermarks_table)
533 kfree(smu_table->gpu_metrics_table);
535 kfree(smu_table->metrics_table);
540 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
541 MetricsMember_t member,
544 struct smu_table_context *smu_table= &smu->smu_table;
545 SmuMetrics_legacy_t *metrics =
546 (SmuMetrics_legacy_t *)smu_table->metrics_table;
549 mutex_lock(&smu->metrics_lock);
551 ret = smu_cmn_get_metrics_table_locked(smu,
555 mutex_unlock(&smu->metrics_lock);
560 case METRICS_CURR_GFXCLK:
561 *value = metrics->CurrClock[PPCLK_GFXCLK];
563 case METRICS_CURR_SOCCLK:
564 *value = metrics->CurrClock[PPCLK_SOCCLK];
566 case METRICS_CURR_UCLK:
567 *value = metrics->CurrClock[PPCLK_UCLK];
569 case METRICS_CURR_VCLK:
570 *value = metrics->CurrClock[PPCLK_VCLK];
572 case METRICS_CURR_DCLK:
573 *value = metrics->CurrClock[PPCLK_DCLK];
575 case METRICS_CURR_DCEFCLK:
576 *value = metrics->CurrClock[PPCLK_DCEFCLK];
578 case METRICS_AVERAGE_GFXCLK:
579 *value = metrics->AverageGfxclkFrequency;
581 case METRICS_AVERAGE_SOCCLK:
582 *value = metrics->AverageSocclkFrequency;
584 case METRICS_AVERAGE_UCLK:
585 *value = metrics->AverageUclkFrequency;
587 case METRICS_AVERAGE_GFXACTIVITY:
588 *value = metrics->AverageGfxActivity;
590 case METRICS_AVERAGE_MEMACTIVITY:
591 *value = metrics->AverageUclkActivity;
593 case METRICS_AVERAGE_SOCKETPOWER:
594 *value = metrics->AverageSocketPower << 8;
596 case METRICS_TEMPERATURE_EDGE:
597 *value = metrics->TemperatureEdge *
598 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
600 case METRICS_TEMPERATURE_HOTSPOT:
601 *value = metrics->TemperatureHotspot *
602 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
604 case METRICS_TEMPERATURE_MEM:
605 *value = metrics->TemperatureMem *
606 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
608 case METRICS_TEMPERATURE_VRGFX:
609 *value = metrics->TemperatureVrGfx *
610 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
612 case METRICS_TEMPERATURE_VRSOC:
613 *value = metrics->TemperatureVrSoc *
614 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
616 case METRICS_THROTTLER_STATUS:
617 *value = metrics->ThrottlerStatus;
619 case METRICS_CURR_FANSPEED:
620 *value = metrics->CurrFanSpeed;
627 mutex_unlock(&smu->metrics_lock);
632 static int navi10_get_smu_metrics_data(struct smu_context *smu,
633 MetricsMember_t member,
636 struct smu_table_context *smu_table= &smu->smu_table;
637 SmuMetrics_t *metrics =
638 (SmuMetrics_t *)smu_table->metrics_table;
641 mutex_lock(&smu->metrics_lock);
643 ret = smu_cmn_get_metrics_table_locked(smu,
647 mutex_unlock(&smu->metrics_lock);
652 case METRICS_CURR_GFXCLK:
653 *value = metrics->CurrClock[PPCLK_GFXCLK];
655 case METRICS_CURR_SOCCLK:
656 *value = metrics->CurrClock[PPCLK_SOCCLK];
658 case METRICS_CURR_UCLK:
659 *value = metrics->CurrClock[PPCLK_UCLK];
661 case METRICS_CURR_VCLK:
662 *value = metrics->CurrClock[PPCLK_VCLK];
664 case METRICS_CURR_DCLK:
665 *value = metrics->CurrClock[PPCLK_DCLK];
667 case METRICS_CURR_DCEFCLK:
668 *value = metrics->CurrClock[PPCLK_DCEFCLK];
670 case METRICS_AVERAGE_GFXCLK:
671 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
672 *value = metrics->AverageGfxclkFrequencyPreDs;
674 *value = metrics->AverageGfxclkFrequencyPostDs;
676 case METRICS_AVERAGE_SOCCLK:
677 *value = metrics->AverageSocclkFrequency;
679 case METRICS_AVERAGE_UCLK:
680 *value = metrics->AverageUclkFrequencyPostDs;
682 case METRICS_AVERAGE_GFXACTIVITY:
683 *value = metrics->AverageGfxActivity;
685 case METRICS_AVERAGE_MEMACTIVITY:
686 *value = metrics->AverageUclkActivity;
688 case METRICS_AVERAGE_SOCKETPOWER:
689 *value = metrics->AverageSocketPower << 8;
691 case METRICS_TEMPERATURE_EDGE:
692 *value = metrics->TemperatureEdge *
693 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
695 case METRICS_TEMPERATURE_HOTSPOT:
696 *value = metrics->TemperatureHotspot *
697 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
699 case METRICS_TEMPERATURE_MEM:
700 *value = metrics->TemperatureMem *
701 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
703 case METRICS_TEMPERATURE_VRGFX:
704 *value = metrics->TemperatureVrGfx *
705 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
707 case METRICS_TEMPERATURE_VRSOC:
708 *value = metrics->TemperatureVrSoc *
709 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
711 case METRICS_THROTTLER_STATUS:
712 *value = metrics->ThrottlerStatus;
714 case METRICS_CURR_FANSPEED:
715 *value = metrics->CurrFanSpeed;
722 mutex_unlock(&smu->metrics_lock);
727 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
728 MetricsMember_t member,
731 struct smu_table_context *smu_table= &smu->smu_table;
732 SmuMetrics_NV12_legacy_t *metrics =
733 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
736 mutex_lock(&smu->metrics_lock);
738 ret = smu_cmn_get_metrics_table_locked(smu,
742 mutex_unlock(&smu->metrics_lock);
747 case METRICS_CURR_GFXCLK:
748 *value = metrics->CurrClock[PPCLK_GFXCLK];
750 case METRICS_CURR_SOCCLK:
751 *value = metrics->CurrClock[PPCLK_SOCCLK];
753 case METRICS_CURR_UCLK:
754 *value = metrics->CurrClock[PPCLK_UCLK];
756 case METRICS_CURR_VCLK:
757 *value = metrics->CurrClock[PPCLK_VCLK];
759 case METRICS_CURR_DCLK:
760 *value = metrics->CurrClock[PPCLK_DCLK];
762 case METRICS_CURR_DCEFCLK:
763 *value = metrics->CurrClock[PPCLK_DCEFCLK];
765 case METRICS_AVERAGE_GFXCLK:
766 *value = metrics->AverageGfxclkFrequency;
768 case METRICS_AVERAGE_SOCCLK:
769 *value = metrics->AverageSocclkFrequency;
771 case METRICS_AVERAGE_UCLK:
772 *value = metrics->AverageUclkFrequency;
774 case METRICS_AVERAGE_GFXACTIVITY:
775 *value = metrics->AverageGfxActivity;
777 case METRICS_AVERAGE_MEMACTIVITY:
778 *value = metrics->AverageUclkActivity;
780 case METRICS_AVERAGE_SOCKETPOWER:
781 *value = metrics->AverageSocketPower << 8;
783 case METRICS_TEMPERATURE_EDGE:
784 *value = metrics->TemperatureEdge *
785 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
787 case METRICS_TEMPERATURE_HOTSPOT:
788 *value = metrics->TemperatureHotspot *
789 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
791 case METRICS_TEMPERATURE_MEM:
792 *value = metrics->TemperatureMem *
793 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
795 case METRICS_TEMPERATURE_VRGFX:
796 *value = metrics->TemperatureVrGfx *
797 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
799 case METRICS_TEMPERATURE_VRSOC:
800 *value = metrics->TemperatureVrSoc *
801 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
803 case METRICS_THROTTLER_STATUS:
804 *value = metrics->ThrottlerStatus;
806 case METRICS_CURR_FANSPEED:
807 *value = metrics->CurrFanSpeed;
814 mutex_unlock(&smu->metrics_lock);
819 static int navi12_get_smu_metrics_data(struct smu_context *smu,
820 MetricsMember_t member,
823 struct smu_table_context *smu_table= &smu->smu_table;
824 SmuMetrics_NV12_t *metrics =
825 (SmuMetrics_NV12_t *)smu_table->metrics_table;
828 mutex_lock(&smu->metrics_lock);
830 ret = smu_cmn_get_metrics_table_locked(smu,
834 mutex_unlock(&smu->metrics_lock);
839 case METRICS_CURR_GFXCLK:
840 *value = metrics->CurrClock[PPCLK_GFXCLK];
842 case METRICS_CURR_SOCCLK:
843 *value = metrics->CurrClock[PPCLK_SOCCLK];
845 case METRICS_CURR_UCLK:
846 *value = metrics->CurrClock[PPCLK_UCLK];
848 case METRICS_CURR_VCLK:
849 *value = metrics->CurrClock[PPCLK_VCLK];
851 case METRICS_CURR_DCLK:
852 *value = metrics->CurrClock[PPCLK_DCLK];
854 case METRICS_CURR_DCEFCLK:
855 *value = metrics->CurrClock[PPCLK_DCEFCLK];
857 case METRICS_AVERAGE_GFXCLK:
858 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
859 *value = metrics->AverageGfxclkFrequencyPreDs;
861 *value = metrics->AverageGfxclkFrequencyPostDs;
863 case METRICS_AVERAGE_SOCCLK:
864 *value = metrics->AverageSocclkFrequency;
866 case METRICS_AVERAGE_UCLK:
867 *value = metrics->AverageUclkFrequencyPostDs;
869 case METRICS_AVERAGE_GFXACTIVITY:
870 *value = metrics->AverageGfxActivity;
872 case METRICS_AVERAGE_MEMACTIVITY:
873 *value = metrics->AverageUclkActivity;
875 case METRICS_AVERAGE_SOCKETPOWER:
876 *value = metrics->AverageSocketPower << 8;
878 case METRICS_TEMPERATURE_EDGE:
879 *value = metrics->TemperatureEdge *
880 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
882 case METRICS_TEMPERATURE_HOTSPOT:
883 *value = metrics->TemperatureHotspot *
884 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
886 case METRICS_TEMPERATURE_MEM:
887 *value = metrics->TemperatureMem *
888 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
890 case METRICS_TEMPERATURE_VRGFX:
891 *value = metrics->TemperatureVrGfx *
892 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
894 case METRICS_TEMPERATURE_VRSOC:
895 *value = metrics->TemperatureVrSoc *
896 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
898 case METRICS_THROTTLER_STATUS:
899 *value = metrics->ThrottlerStatus;
901 case METRICS_CURR_FANSPEED:
902 *value = metrics->CurrFanSpeed;
909 mutex_unlock(&smu->metrics_lock);
914 static int navi1x_get_smu_metrics_data(struct smu_context *smu,
915 MetricsMember_t member,
918 struct amdgpu_device *adev = smu->adev;
919 uint32_t smu_version;
922 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
924 dev_err(adev->dev, "Failed to get smu version!\n");
928 switch (adev->asic_type) {
930 if (smu_version > 0x00341C00)
931 ret = navi12_get_smu_metrics_data(smu, member, value);
933 ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
938 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
939 ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
940 ret = navi10_get_smu_metrics_data(smu, member, value);
942 ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
949 static int navi10_allocate_dpm_context(struct smu_context *smu)
951 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
953 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
955 if (!smu_dpm->dpm_context)
958 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
963 static int navi10_init_smc_tables(struct smu_context *smu)
967 ret = navi10_tables_init(smu);
971 ret = navi10_allocate_dpm_context(smu);
975 return smu_v11_0_init_smc_tables(smu);
978 static int navi10_set_default_dpm_table(struct smu_context *smu)
980 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
981 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
982 struct smu_11_0_dpm_table *dpm_table;
985 /* socclk dpm table setup */
986 dpm_table = &dpm_context->dpm_tables.soc_table;
987 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
988 ret = smu_v11_0_set_single_dpm_table(smu,
993 dpm_table->is_fine_grained =
994 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
996 dpm_table->count = 1;
997 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
998 dpm_table->dpm_levels[0].enabled = true;
999 dpm_table->min = dpm_table->dpm_levels[0].value;
1000 dpm_table->max = dpm_table->dpm_levels[0].value;
1003 /* gfxclk dpm table setup */
1004 dpm_table = &dpm_context->dpm_tables.gfx_table;
1005 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1006 ret = smu_v11_0_set_single_dpm_table(smu,
1011 dpm_table->is_fine_grained =
1012 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
1014 dpm_table->count = 1;
1015 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1016 dpm_table->dpm_levels[0].enabled = true;
1017 dpm_table->min = dpm_table->dpm_levels[0].value;
1018 dpm_table->max = dpm_table->dpm_levels[0].value;
1021 /* uclk dpm table setup */
1022 dpm_table = &dpm_context->dpm_tables.uclk_table;
1023 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1024 ret = smu_v11_0_set_single_dpm_table(smu,
1029 dpm_table->is_fine_grained =
1030 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
1032 dpm_table->count = 1;
1033 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1034 dpm_table->dpm_levels[0].enabled = true;
1035 dpm_table->min = dpm_table->dpm_levels[0].value;
1036 dpm_table->max = dpm_table->dpm_levels[0].value;
1039 /* vclk dpm table setup */
1040 dpm_table = &dpm_context->dpm_tables.vclk_table;
1041 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1042 ret = smu_v11_0_set_single_dpm_table(smu,
1047 dpm_table->is_fine_grained =
1048 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1050 dpm_table->count = 1;
1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1052 dpm_table->dpm_levels[0].enabled = true;
1053 dpm_table->min = dpm_table->dpm_levels[0].value;
1054 dpm_table->max = dpm_table->dpm_levels[0].value;
1057 /* dclk dpm table setup */
1058 dpm_table = &dpm_context->dpm_tables.dclk_table;
1059 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1060 ret = smu_v11_0_set_single_dpm_table(smu,
1065 dpm_table->is_fine_grained =
1066 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1068 dpm_table->count = 1;
1069 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1070 dpm_table->dpm_levels[0].enabled = true;
1071 dpm_table->min = dpm_table->dpm_levels[0].value;
1072 dpm_table->max = dpm_table->dpm_levels[0].value;
1075 /* dcefclk dpm table setup */
1076 dpm_table = &dpm_context->dpm_tables.dcef_table;
1077 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1078 ret = smu_v11_0_set_single_dpm_table(smu,
1083 dpm_table->is_fine_grained =
1084 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1086 dpm_table->count = 1;
1087 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1088 dpm_table->dpm_levels[0].enabled = true;
1089 dpm_table->min = dpm_table->dpm_levels[0].value;
1090 dpm_table->max = dpm_table->dpm_levels[0].value;
1093 /* pixelclk dpm table setup */
1094 dpm_table = &dpm_context->dpm_tables.pixel_table;
1095 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1096 ret = smu_v11_0_set_single_dpm_table(smu,
1101 dpm_table->is_fine_grained =
1102 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1104 dpm_table->count = 1;
1105 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1106 dpm_table->dpm_levels[0].enabled = true;
1107 dpm_table->min = dpm_table->dpm_levels[0].value;
1108 dpm_table->max = dpm_table->dpm_levels[0].value;
1111 /* displayclk dpm table setup */
1112 dpm_table = &dpm_context->dpm_tables.display_table;
1113 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1114 ret = smu_v11_0_set_single_dpm_table(smu,
1119 dpm_table->is_fine_grained =
1120 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1122 dpm_table->count = 1;
1123 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1124 dpm_table->dpm_levels[0].enabled = true;
1125 dpm_table->min = dpm_table->dpm_levels[0].value;
1126 dpm_table->max = dpm_table->dpm_levels[0].value;
1129 /* phyclk dpm table setup */
1130 dpm_table = &dpm_context->dpm_tables.phy_table;
1131 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1132 ret = smu_v11_0_set_single_dpm_table(smu,
1137 dpm_table->is_fine_grained =
1138 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1140 dpm_table->count = 1;
1141 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1142 dpm_table->dpm_levels[0].enabled = true;
1143 dpm_table->min = dpm_table->dpm_levels[0].value;
1144 dpm_table->max = dpm_table->dpm_levels[0].value;
1150 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1155 /* vcn dpm on is a prerequisite for vcn power gate messages */
1156 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1157 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1162 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1163 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1172 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1177 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1178 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1183 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1184 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1193 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1194 enum smu_clk_type clk_type,
1197 MetricsMember_t member_type;
1200 clk_id = smu_cmn_to_asic_specific_index(smu,
1201 CMN2ASIC_MAPPING_CLK,
1208 member_type = METRICS_CURR_GFXCLK;
1211 member_type = METRICS_CURR_UCLK;
1214 member_type = METRICS_CURR_SOCCLK;
1217 member_type = METRICS_CURR_VCLK;
1220 member_type = METRICS_CURR_DCLK;
1223 member_type = METRICS_CURR_DCEFCLK;
1229 return navi1x_get_smu_metrics_data(smu,
1234 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1236 PPTable_t *pptable = smu->smu_table.driver_pptable;
1237 DpmDescriptor_t *dpm_desc = NULL;
1238 uint32_t clk_index = 0;
1240 clk_index = smu_cmn_to_asic_specific_index(smu,
1241 CMN2ASIC_MAPPING_CLK,
1243 dpm_desc = &pptable->DpmDescriptor[clk_index];
1245 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1246 return dpm_desc->SnapToDiscrete == 0;
1249 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1251 return od_table->cap[cap];
1254 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1255 enum SMU_11_0_ODSETTING_ID setting,
1256 uint32_t *min, uint32_t *max)
1259 *min = od_table->min[setting];
1261 *max = od_table->max[setting];
1264 static int navi10_print_clk_levels(struct smu_context *smu,
1265 enum smu_clk_type clk_type, char *buf)
1267 uint16_t *curve_settings;
1268 int i, size = 0, ret = 0;
1269 uint32_t cur_value = 0, value = 0, count = 0;
1270 uint32_t freq_values[3] = {0};
1271 uint32_t mark_index = 0;
1272 struct smu_table_context *table_context = &smu->smu_table;
1273 uint32_t gen_speed, lane_width;
1274 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1275 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1276 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1277 OverDriveTable_t *od_table =
1278 (OverDriveTable_t *)table_context->overdrive_table;
1279 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1280 uint32_t min_value, max_value;
1282 smu_cmn_get_sysfs_buf(&buf, &size);
1294 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1298 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1302 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1303 for (i = 0; i < count; i++) {
1304 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1308 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1309 cur_value == value ? "*" : "");
1312 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1315 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1319 freq_values[1] = cur_value;
1320 mark_index = cur_value == freq_values[0] ? 0 :
1321 cur_value == freq_values[2] ? 2 : 1;
1322 if (mark_index != 1)
1323 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
1325 for (i = 0; i < 3; i++) {
1326 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1327 i == mark_index ? "*" : "");
1333 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1334 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1335 for (i = 0; i < NUM_LINK_LEVELS; i++)
1336 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1337 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1338 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1339 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1340 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1341 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1342 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1343 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1344 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1345 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1346 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1347 pptable->LclkFreq[i],
1348 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1349 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1353 if (!smu->od_enabled || !od_table || !od_settings)
1355 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1357 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1358 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1359 od_table->GfxclkFmin, od_table->GfxclkFmax);
1362 if (!smu->od_enabled || !od_table || !od_settings)
1364 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1366 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1367 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax);
1369 case SMU_OD_VDDC_CURVE:
1370 if (!smu->od_enabled || !od_table || !od_settings)
1372 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1374 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
1375 for (i = 0; i < 3; i++) {
1378 curve_settings = &od_table->GfxclkFreq1;
1381 curve_settings = &od_table->GfxclkFreq2;
1384 curve_settings = &od_table->GfxclkFreq3;
1389 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n",
1390 i, curve_settings[0],
1391 curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1395 if (!smu->od_enabled || !od_table || !od_settings)
1397 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1399 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1400 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1402 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1404 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1405 min_value, max_value);
1408 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1409 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1410 &min_value, &max_value);
1411 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1412 min_value, max_value);
1415 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1416 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1417 &min_value, &max_value);
1418 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1419 min_value, max_value);
1420 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1421 &min_value, &max_value);
1422 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1423 min_value, max_value);
1424 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1425 &min_value, &max_value);
1426 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1427 min_value, max_value);
1428 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1429 &min_value, &max_value);
1430 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1431 min_value, max_value);
1432 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1433 &min_value, &max_value);
1434 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1435 min_value, max_value);
1436 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1437 &min_value, &max_value);
1438 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1439 min_value, max_value);
1450 static int navi10_force_clk_levels(struct smu_context *smu,
1451 enum smu_clk_type clk_type, uint32_t mask)
1454 int ret = 0, size = 0;
1455 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1457 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1458 soft_max_level = mask ? (fls(mask) - 1) : 0;
1467 /* There is only 2 levels for fine grained DPM */
1468 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1469 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1470 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1473 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1477 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1481 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1486 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1496 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1498 struct smu_11_0_dpm_context *dpm_context =
1499 smu->smu_dpm.dpm_context;
1500 struct smu_11_0_dpm_table *gfx_table =
1501 &dpm_context->dpm_tables.gfx_table;
1502 struct smu_11_0_dpm_table *mem_table =
1503 &dpm_context->dpm_tables.uclk_table;
1504 struct smu_11_0_dpm_table *soc_table =
1505 &dpm_context->dpm_tables.soc_table;
1506 struct smu_umd_pstate_table *pstate_table =
1508 struct amdgpu_device *adev = smu->adev;
1511 pstate_table->gfxclk_pstate.min = gfx_table->min;
1512 switch (adev->asic_type) {
1514 switch (adev->pdev->revision) {
1515 case 0xf0: /* XTX */
1517 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1521 sclk_freq = NAVI10_PEAK_SCLK_XT;
1524 sclk_freq = NAVI10_PEAK_SCLK_XL;
1529 switch (adev->pdev->revision) {
1532 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1534 case 0xc1: /* XTM */
1536 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1538 case 0xc3: /* XLM */
1540 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1542 case 0xc5: /* XTX */
1544 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1547 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1552 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1555 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1558 pstate_table->gfxclk_pstate.peak = sclk_freq;
1560 pstate_table->uclk_pstate.min = mem_table->min;
1561 pstate_table->uclk_pstate.peak = mem_table->max;
1563 pstate_table->socclk_pstate.min = soc_table->min;
1564 pstate_table->socclk_pstate.peak = soc_table->max;
1566 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1567 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1568 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1569 pstate_table->gfxclk_pstate.standard =
1570 NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1571 pstate_table->uclk_pstate.standard =
1572 NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1573 pstate_table->socclk_pstate.standard =
1574 NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1576 pstate_table->gfxclk_pstate.standard =
1577 pstate_table->gfxclk_pstate.min;
1578 pstate_table->uclk_pstate.standard =
1579 pstate_table->uclk_pstate.min;
1580 pstate_table->socclk_pstate.standard =
1581 pstate_table->socclk_pstate.min;
1587 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1588 enum smu_clk_type clk_type,
1589 struct pp_clock_levels_with_latency *clocks)
1592 uint32_t level_count = 0, freq = 0;
1600 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1604 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1605 clocks->num_levels = level_count;
1607 for (i = 0; i < level_count; i++) {
1608 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1612 clocks->data[i].clocks_in_khz = freq * 1000;
1613 clocks->data[i].latency_in_us = 0;
1623 static int navi10_pre_display_config_changed(struct smu_context *smu)
1626 uint32_t max_freq = 0;
1628 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1632 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1633 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1636 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1644 static int navi10_display_config_changed(struct smu_context *smu)
1648 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1649 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1650 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1651 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1652 smu->display_config->num_display,
1661 static bool navi10_is_dpm_running(struct smu_context *smu)
1664 uint32_t feature_mask[2];
1665 uint64_t feature_enabled;
1667 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1671 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1673 return !!(feature_enabled & SMC_DPM_FEATURE);
1676 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1684 switch (smu_v11_0_get_fan_control_mode(smu)) {
1685 case AMD_FAN_CTRL_AUTO:
1686 ret = navi10_get_smu_metrics_data(smu,
1687 METRICS_CURR_FANSPEED,
1691 ret = smu_v11_0_get_fan_speed_rpm(smu,
1699 static int navi10_get_fan_parameters(struct smu_context *smu)
1701 PPTable_t *pptable = smu->smu_table.driver_pptable;
1703 smu->fan_max_rpm = pptable->FanMaximumRpm;
1708 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1710 DpmActivityMonitorCoeffInt_t activity_monitor;
1711 uint32_t i, size = 0;
1712 int16_t workload_type = 0;
1713 static const char *profile_name[] = {
1721 static const char *title[] = {
1722 "PROFILE_INDEX(NAME)",
1726 "MinActiveFreqType",
1731 "PD_Data_error_coeff",
1732 "PD_Data_error_rate_coeff"};
1738 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1739 title[0], title[1], title[2], title[3], title[4], title[5],
1740 title[6], title[7], title[8], title[9], title[10]);
1742 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1743 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1744 workload_type = smu_cmn_to_asic_specific_index(smu,
1745 CMN2ASIC_MAPPING_WORKLOAD,
1747 if (workload_type < 0)
1750 result = smu_cmn_update_table(smu,
1751 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1752 (void *)(&activity_monitor), false);
1754 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1758 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1759 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1761 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1765 activity_monitor.Gfx_FPS,
1766 activity_monitor.Gfx_MinFreqStep,
1767 activity_monitor.Gfx_MinActiveFreqType,
1768 activity_monitor.Gfx_MinActiveFreq,
1769 activity_monitor.Gfx_BoosterFreqType,
1770 activity_monitor.Gfx_BoosterFreq,
1771 activity_monitor.Gfx_PD_Data_limit_c,
1772 activity_monitor.Gfx_PD_Data_error_coeff,
1773 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1775 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1779 activity_monitor.Soc_FPS,
1780 activity_monitor.Soc_MinFreqStep,
1781 activity_monitor.Soc_MinActiveFreqType,
1782 activity_monitor.Soc_MinActiveFreq,
1783 activity_monitor.Soc_BoosterFreqType,
1784 activity_monitor.Soc_BoosterFreq,
1785 activity_monitor.Soc_PD_Data_limit_c,
1786 activity_monitor.Soc_PD_Data_error_coeff,
1787 activity_monitor.Soc_PD_Data_error_rate_coeff);
1789 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1793 activity_monitor.Mem_FPS,
1794 activity_monitor.Mem_MinFreqStep,
1795 activity_monitor.Mem_MinActiveFreqType,
1796 activity_monitor.Mem_MinActiveFreq,
1797 activity_monitor.Mem_BoosterFreqType,
1798 activity_monitor.Mem_BoosterFreq,
1799 activity_monitor.Mem_PD_Data_limit_c,
1800 activity_monitor.Mem_PD_Data_error_coeff,
1801 activity_monitor.Mem_PD_Data_error_rate_coeff);
1807 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1809 DpmActivityMonitorCoeffInt_t activity_monitor;
1810 int workload_type, ret = 0;
1812 smu->power_profile_mode = input[size];
1814 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1815 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1819 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1821 ret = smu_cmn_update_table(smu,
1822 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1823 (void *)(&activity_monitor), false);
1825 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1830 case 0: /* Gfxclk */
1831 activity_monitor.Gfx_FPS = input[1];
1832 activity_monitor.Gfx_MinFreqStep = input[2];
1833 activity_monitor.Gfx_MinActiveFreqType = input[3];
1834 activity_monitor.Gfx_MinActiveFreq = input[4];
1835 activity_monitor.Gfx_BoosterFreqType = input[5];
1836 activity_monitor.Gfx_BoosterFreq = input[6];
1837 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1838 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1839 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1841 case 1: /* Socclk */
1842 activity_monitor.Soc_FPS = input[1];
1843 activity_monitor.Soc_MinFreqStep = input[2];
1844 activity_monitor.Soc_MinActiveFreqType = input[3];
1845 activity_monitor.Soc_MinActiveFreq = input[4];
1846 activity_monitor.Soc_BoosterFreqType = input[5];
1847 activity_monitor.Soc_BoosterFreq = input[6];
1848 activity_monitor.Soc_PD_Data_limit_c = input[7];
1849 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1850 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1853 activity_monitor.Mem_FPS = input[1];
1854 activity_monitor.Mem_MinFreqStep = input[2];
1855 activity_monitor.Mem_MinActiveFreqType = input[3];
1856 activity_monitor.Mem_MinActiveFreq = input[4];
1857 activity_monitor.Mem_BoosterFreqType = input[5];
1858 activity_monitor.Mem_BoosterFreq = input[6];
1859 activity_monitor.Mem_PD_Data_limit_c = input[7];
1860 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1861 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1865 ret = smu_cmn_update_table(smu,
1866 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1867 (void *)(&activity_monitor), true);
1869 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1874 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1875 workload_type = smu_cmn_to_asic_specific_index(smu,
1876 CMN2ASIC_MAPPING_WORKLOAD,
1877 smu->power_profile_mode);
1878 if (workload_type < 0)
1880 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1881 1 << workload_type, NULL);
1886 static int navi10_notify_smc_display_config(struct smu_context *smu)
1888 struct smu_clocks min_clocks = {0};
1889 struct pp_display_clock_request clock_req;
1892 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1893 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1894 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1896 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1897 clock_req.clock_type = amd_pp_dcef_clock;
1898 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1900 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1902 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1903 ret = smu_cmn_send_smc_msg_with_param(smu,
1904 SMU_MSG_SetMinDeepSleepDcefclk,
1905 min_clocks.dcef_clock_in_sr/100,
1908 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1913 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1917 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1918 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1920 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1928 static int navi10_set_watermarks_table(struct smu_context *smu,
1929 struct pp_smu_wm_range_sets *clock_ranges)
1931 Watermarks_t *table = smu->smu_table.watermarks_table;
1936 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1937 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1940 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1941 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1942 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1943 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1944 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1945 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1946 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1947 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1948 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1950 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1951 clock_ranges->reader_wm_sets[i].wm_inst;
1954 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1955 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1956 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1957 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1958 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1959 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1960 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1961 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1962 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1964 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1965 clock_ranges->writer_wm_sets[i].wm_inst;
1968 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1971 /* pass data to smu controller */
1972 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1973 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1974 ret = smu_cmn_write_watermarks_table(smu);
1976 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1979 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1985 static int navi10_read_sensor(struct smu_context *smu,
1986 enum amd_pp_sensors sensor,
1987 void *data, uint32_t *size)
1990 struct smu_table_context *table_context = &smu->smu_table;
1991 PPTable_t *pptable = table_context->driver_pptable;
1996 mutex_lock(&smu->sensor_lock);
1998 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1999 *(uint32_t *)data = pptable->FanMaximumRpm;
2002 case AMDGPU_PP_SENSOR_MEM_LOAD:
2003 ret = navi1x_get_smu_metrics_data(smu,
2004 METRICS_AVERAGE_MEMACTIVITY,
2008 case AMDGPU_PP_SENSOR_GPU_LOAD:
2009 ret = navi1x_get_smu_metrics_data(smu,
2010 METRICS_AVERAGE_GFXACTIVITY,
2014 case AMDGPU_PP_SENSOR_GPU_POWER:
2015 ret = navi1x_get_smu_metrics_data(smu,
2016 METRICS_AVERAGE_SOCKETPOWER,
2020 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2021 ret = navi1x_get_smu_metrics_data(smu,
2022 METRICS_TEMPERATURE_HOTSPOT,
2026 case AMDGPU_PP_SENSOR_EDGE_TEMP:
2027 ret = navi1x_get_smu_metrics_data(smu,
2028 METRICS_TEMPERATURE_EDGE,
2032 case AMDGPU_PP_SENSOR_MEM_TEMP:
2033 ret = navi1x_get_smu_metrics_data(smu,
2034 METRICS_TEMPERATURE_MEM,
2038 case AMDGPU_PP_SENSOR_GFX_MCLK:
2039 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
2040 *(uint32_t *)data *= 100;
2043 case AMDGPU_PP_SENSOR_GFX_SCLK:
2044 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
2045 *(uint32_t *)data *= 100;
2048 case AMDGPU_PP_SENSOR_VDDGFX:
2049 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2056 mutex_unlock(&smu->sensor_lock);
2061 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2063 uint32_t num_discrete_levels = 0;
2064 uint16_t *dpm_levels = NULL;
2066 struct smu_table_context *table_context = &smu->smu_table;
2067 PPTable_t *driver_ppt = NULL;
2069 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2072 driver_ppt = table_context->driver_pptable;
2073 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2074 dpm_levels = driver_ppt->FreqTableUclk;
2076 if (num_discrete_levels == 0 || dpm_levels == NULL)
2079 *num_states = num_discrete_levels;
2080 for (i = 0; i < num_discrete_levels; i++) {
2081 /* convert to khz */
2082 *clocks_in_khz = (*dpm_levels) * 1000;
2090 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2091 struct smu_temperature_range *range)
2093 struct smu_table_context *table_context = &smu->smu_table;
2094 struct smu_11_0_powerplay_table *powerplay_table =
2095 table_context->power_play_table;
2096 PPTable_t *pptable = smu->smu_table.driver_pptable;
2101 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2103 range->max = pptable->TedgeLimit *
2104 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2105 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2106 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2107 range->hotspot_crit_max = pptable->ThotspotLimit *
2108 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2109 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2110 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2111 range->mem_crit_max = pptable->TmemLimit *
2112 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2113 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2114 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2115 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2120 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2121 bool disable_memory_clock_switch)
2124 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2125 (struct smu_11_0_max_sustainable_clocks *)
2126 smu->smu_table.max_sustainable_clocks;
2127 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2128 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2130 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2133 if(disable_memory_clock_switch)
2134 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2136 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2139 smu->disable_uclk_switch = disable_memory_clock_switch;
2144 static int navi10_get_power_limit(struct smu_context *smu,
2145 uint32_t *current_power_limit,
2146 uint32_t *default_power_limit,
2147 uint32_t *max_power_limit)
2149 struct smu_11_0_powerplay_table *powerplay_table =
2150 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2151 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2152 PPTable_t *pptable = smu->smu_table.driver_pptable;
2153 uint32_t power_limit, od_percent;
2155 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2156 /* the last hope to figure out the ppt limit */
2158 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2162 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2165 if (current_power_limit)
2166 *current_power_limit = power_limit;
2167 if (default_power_limit)
2168 *default_power_limit = power_limit;
2170 if (max_power_limit) {
2171 if (smu->od_enabled &&
2172 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2173 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2175 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
2177 power_limit *= (100 + od_percent);
2181 *max_power_limit = power_limit;
2187 static int navi10_update_pcie_parameters(struct smu_context *smu,
2188 uint32_t pcie_gen_cap,
2189 uint32_t pcie_width_cap)
2191 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2192 PPTable_t *pptable = smu->smu_table.driver_pptable;
2193 uint32_t smu_pcie_arg;
2196 /* lclk dpm table setup */
2197 for (i = 0; i < MAX_PCIE_CONF; i++) {
2198 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2199 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2202 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2203 smu_pcie_arg = (i << 16) |
2204 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2205 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2206 pptable->PcieLaneCount[i] : pcie_width_cap);
2207 ret = smu_cmn_send_smc_msg_with_param(smu,
2208 SMU_MSG_OverridePcieParameters,
2215 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2216 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2217 if (pptable->PcieLaneCount[i] > pcie_width_cap)
2218 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2224 static inline void navi10_dump_od_table(struct smu_context *smu,
2225 OverDriveTable_t *od_table)
2227 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2228 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2229 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2230 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2231 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2232 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2235 static int navi10_od_setting_check_range(struct smu_context *smu,
2236 struct smu_11_0_overdrive_table *od_table,
2237 enum SMU_11_0_ODSETTING_ID setting,
2240 if (value < od_table->min[setting]) {
2241 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2244 if (value > od_table->max[setting]) {
2245 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2251 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2255 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2259 ret = smu_cmn_send_smc_msg_with_param(smu,
2260 SMU_MSG_GetVoltageByDpm,
2264 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2268 *voltage = (uint16_t)value;
2273 static int navi10_baco_enter(struct smu_context *smu)
2275 struct amdgpu_device *adev = smu->adev;
2278 * This aims the case below:
2279 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded
2281 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To
2282 * make that possible, PMFW needs to acknowledge the dstate transition
2283 * process for both gfx(function 0) and audio(function 1) function of
2286 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the
2287 * device representing the audio function of the ASIC. And that means
2288 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still
2289 * possible runpm suspend kicked on the ASIC. However without the dstate
2290 * transition notification from audio function, pmfw cannot handle the
2291 * BACO in/exit correctly. And that will cause driver hang on runpm
2294 * To address this, we revert to legacy message way(driver masters the
2295 * timing for BACO in/exit) on sound driver missing.
2297 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2298 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2300 return smu_v11_0_baco_enter(smu);
2303 static int navi10_baco_exit(struct smu_context *smu)
2305 struct amdgpu_device *adev = smu->adev;
2307 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2308 /* Wait for PMFW handling for the Dstate change */
2310 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2312 return smu_v11_0_baco_exit(smu);
2316 static int navi10_set_default_od_settings(struct smu_context *smu)
2318 OverDriveTable_t *od_table =
2319 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2320 OverDriveTable_t *boot_od_table =
2321 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2322 OverDriveTable_t *user_od_table =
2323 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2327 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2328 * - either they already have the default OD settings got during cold bootup
2329 * - or they have some user customized OD settings which cannot be overwritten
2331 if (smu->adev->in_suspend)
2334 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false);
2336 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2340 if (!boot_od_table->GfxclkVolt1) {
2341 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2342 &boot_od_table->GfxclkVolt1,
2343 boot_od_table->GfxclkFreq1);
2348 if (!boot_od_table->GfxclkVolt2) {
2349 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2350 &boot_od_table->GfxclkVolt2,
2351 boot_od_table->GfxclkFreq2);
2356 if (!boot_od_table->GfxclkVolt3) {
2357 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2358 &boot_od_table->GfxclkVolt3,
2359 boot_od_table->GfxclkFreq3);
2364 navi10_dump_od_table(smu, boot_od_table);
2366 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2367 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2372 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2375 struct smu_table_context *table_context = &smu->smu_table;
2376 OverDriveTable_t *od_table;
2377 struct smu_11_0_overdrive_table *od_settings;
2378 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2379 uint16_t *freq_ptr, *voltage_ptr;
2380 od_table = (OverDriveTable_t *)table_context->overdrive_table;
2382 if (!smu->od_enabled) {
2383 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2387 if (!smu->od_settings) {
2388 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2392 od_settings = smu->od_settings;
2395 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2396 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2397 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2400 if (!table_context->overdrive_table) {
2401 dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2404 for (i = 0; i < size; i += 2) {
2406 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2411 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2412 freq_ptr = &od_table->GfxclkFmin;
2413 if (input[i + 1] > od_table->GfxclkFmax) {
2414 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2416 od_table->GfxclkFmin);
2421 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2422 freq_ptr = &od_table->GfxclkFmax;
2423 if (input[i + 1] < od_table->GfxclkFmin) {
2424 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2426 od_table->GfxclkFmax);
2431 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2432 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2435 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2438 *freq_ptr = input[i + 1];
2441 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2442 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2443 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2447 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2450 if (input[0] != 1) {
2451 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2452 dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2455 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2458 od_table->UclkFmax = input[1];
2460 case PP_OD_RESTORE_DEFAULT_TABLE:
2461 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2462 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2465 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2467 case PP_OD_COMMIT_DPM_TABLE:
2468 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2469 navi10_dump_od_table(smu, od_table);
2470 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2472 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2475 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2476 smu->user_dpm_profile.user_od = true;
2478 if (!memcmp(table_context->user_overdrive_table,
2479 table_context->boot_overdrive_table,
2480 sizeof(OverDriveTable_t)))
2481 smu->user_dpm_profile.user_od = false;
2484 case PP_OD_EDIT_VDDC_CURVE:
2485 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2486 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2490 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2494 dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2500 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2501 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2502 freq_ptr = &od_table->GfxclkFreq1;
2503 voltage_ptr = &od_table->GfxclkVolt1;
2506 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2507 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2508 freq_ptr = &od_table->GfxclkFreq2;
2509 voltage_ptr = &od_table->GfxclkVolt2;
2512 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2513 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2514 freq_ptr = &od_table->GfxclkFreq3;
2515 voltage_ptr = &od_table->GfxclkVolt3;
2518 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2519 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2522 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2525 // Allow setting zero to disable the OverDrive VDDC curve
2526 if (input[2] != 0) {
2527 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2530 *freq_ptr = input[1];
2531 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2532 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2534 // If setting 0, disable all voltage curve settings
2535 od_table->GfxclkVolt1 = 0;
2536 od_table->GfxclkVolt2 = 0;
2537 od_table->GfxclkVolt3 = 0;
2539 navi10_dump_od_table(smu, od_table);
2547 static int navi10_run_btc(struct smu_context *smu)
2551 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2553 dev_err(smu->adev->dev, "RunBtc failed!\n");
2558 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2560 struct amdgpu_device *adev = smu->adev;
2562 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2565 if (adev->asic_type == CHIP_NAVI10 ||
2566 adev->asic_type == CHIP_NAVI14)
2572 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2574 uint32_t uclk_count, uclk_min, uclk_max;
2577 /* This workaround can be applied only with uclk dpm enabled */
2578 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2581 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2585 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2590 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2591 * This workaround is needed only when the max uclk frequency
2592 * not greater than that.
2594 if (uclk_max > 0x2EE)
2597 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2601 /* Force UCLK out of the highest DPM */
2602 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2606 /* Revert the UCLK Hardmax */
2607 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2612 * In this case, SMU already disabled dummy pstate during enablement
2613 * of UCLK DPM, we have to re-enabled it.
2615 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2618 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2620 struct smu_table_context *smu_table = &smu->smu_table;
2621 struct smu_table *dummy_read_table =
2622 &smu_table->dummy_read_1_table;
2623 char *dummy_table = dummy_read_table->cpu_addr;
2627 for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2628 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2629 dummy_table += 0x1000;
2630 memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2631 dummy_table += 0x1000;
2634 amdgpu_asic_flush_hdp(smu->adev, NULL);
2636 ret = smu_cmn_send_smc_msg_with_param(smu,
2637 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2638 upper_32_bits(dummy_read_table->mc_address),
2643 return smu_cmn_send_smc_msg_with_param(smu,
2644 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2645 lower_32_bits(dummy_read_table->mc_address),
2649 static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2651 struct amdgpu_device *adev = smu->adev;
2652 uint8_t umc_fw_greater_than_v136 = false;
2653 uint8_t umc_fw_disable_cdr = false;
2654 uint32_t pmfw_version;
2658 if (!navi10_need_umc_cdr_workaround(smu))
2661 ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
2663 dev_err(adev->dev, "Failed to get smu version!\n");
2668 * The messages below are only supported by Navi10 42.53.0 and later
2669 * PMFWs and Navi14 53.29.0 and later PMFWs.
2670 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2671 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2672 * - PPSMC_MSG_GetUMCFWWA
2674 if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) ||
2675 ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) {
2676 ret = smu_cmn_send_smc_msg_with_param(smu,
2677 SMU_MSG_GET_UMC_FW_WA,
2683 /* First bit indicates if the UMC f/w is above v137 */
2684 umc_fw_greater_than_v136 = param & 0x1;
2686 /* Second bit indicates if hybrid-cdr is disabled */
2687 umc_fw_disable_cdr = param & 0x2;
2689 /* w/a only allowed if UMC f/w is <= 136 */
2690 if (umc_fw_greater_than_v136)
2693 if (umc_fw_disable_cdr) {
2694 if (adev->asic_type == CHIP_NAVI10)
2695 return navi10_umc_hybrid_cdr_workaround(smu);
2697 return navi10_set_dummy_pstates_table_location(smu);
2700 if (adev->asic_type == CHIP_NAVI10)
2701 return navi10_umc_hybrid_cdr_workaround(smu);
2707 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2710 struct smu_table_context *smu_table = &smu->smu_table;
2711 struct gpu_metrics_v1_3 *gpu_metrics =
2712 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2713 SmuMetrics_legacy_t metrics;
2716 mutex_lock(&smu->metrics_lock);
2718 ret = smu_cmn_get_metrics_table_locked(smu,
2722 mutex_unlock(&smu->metrics_lock);
2726 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2728 mutex_unlock(&smu->metrics_lock);
2730 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2732 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2733 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2734 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2735 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2736 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2737 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2739 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2740 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2742 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2744 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2745 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2746 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2748 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2749 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2750 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2751 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2752 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2754 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2755 gpu_metrics->indep_throttle_status =
2756 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2757 navi1x_throttler_map);
2759 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2761 gpu_metrics->pcie_link_width =
2762 smu_v11_0_get_current_pcie_link_width(smu);
2763 gpu_metrics->pcie_link_speed =
2764 smu_v11_0_get_current_pcie_link_speed(smu);
2766 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2768 if (metrics.CurrGfxVoltageOffset)
2769 gpu_metrics->voltage_gfx =
2770 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2771 if (metrics.CurrMemVidOffset)
2772 gpu_metrics->voltage_mem =
2773 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2774 if (metrics.CurrSocVoltageOffset)
2775 gpu_metrics->voltage_soc =
2776 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2778 *table = (void *)gpu_metrics;
2780 return sizeof(struct gpu_metrics_v1_3);
2783 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2784 struct i2c_msg *msg, int num_msgs)
2786 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
2787 struct smu_table_context *smu_table = &adev->smu.smu_table;
2788 struct smu_table *table = &smu_table->driver_table;
2789 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2793 req = kzalloc(sizeof(*req), GFP_KERNEL);
2797 req->I2CcontrollerPort = 0;
2798 req->I2CSpeed = I2C_SPEED_FAST_400K;
2799 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2800 dir = msg[0].flags & I2C_M_RD;
2802 for (c = i = 0; i < num_msgs; i++) {
2803 for (j = 0; j < msg[i].len; j++, c++) {
2804 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2806 if (!(msg[i].flags & I2C_M_RD)) {
2808 cmd->Cmd = I2C_CMD_WRITE;
2809 cmd->RegisterAddr = msg[i].buf[j];
2812 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2813 /* The direction changes.
2815 dir = msg[i].flags & I2C_M_RD;
2816 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2822 * Insert STOP if we are at the last byte of either last
2823 * message for the transaction or the client explicitly
2824 * requires a STOP at this particular message.
2826 if ((j == msg[i].len - 1) &&
2827 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2828 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2829 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2833 mutex_lock(&adev->smu.mutex);
2834 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2835 mutex_unlock(&adev->smu.mutex);
2839 for (c = i = 0; i < num_msgs; i++) {
2840 if (!(msg[i].flags & I2C_M_RD)) {
2844 for (j = 0; j < msg[i].len; j++, c++) {
2845 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2847 msg[i].buf[j] = cmd->Data;
2856 static u32 navi10_i2c_func(struct i2c_adapter *adap)
2858 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2862 static const struct i2c_algorithm navi10_i2c_algo = {
2863 .master_xfer = navi10_i2c_xfer,
2864 .functionality = navi10_i2c_func,
2867 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
2868 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2869 .max_read_len = MAX_SW_I2C_COMMANDS,
2870 .max_write_len = MAX_SW_I2C_COMMANDS,
2871 .max_comb_1st_msg_len = 2,
2872 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2875 static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2877 struct amdgpu_device *adev = to_amdgpu_device(control);
2880 control->owner = THIS_MODULE;
2881 control->class = I2C_CLASS_HWMON;
2882 control->dev.parent = &adev->pdev->dev;
2883 control->algo = &navi10_i2c_algo;
2884 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2885 control->quirks = &navi10_i2c_control_quirks;
2887 res = i2c_add_adapter(control);
2889 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2894 static void navi10_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2896 i2c_del_adapter(control);
2899 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
2902 struct smu_table_context *smu_table = &smu->smu_table;
2903 struct gpu_metrics_v1_3 *gpu_metrics =
2904 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2905 SmuMetrics_t metrics;
2908 mutex_lock(&smu->metrics_lock);
2910 ret = smu_cmn_get_metrics_table_locked(smu,
2914 mutex_unlock(&smu->metrics_lock);
2918 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
2920 mutex_unlock(&smu->metrics_lock);
2922 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2924 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2925 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2926 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2927 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2928 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2929 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2931 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2932 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2934 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2936 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
2937 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2939 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2941 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2942 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2944 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2945 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2946 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2947 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2948 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2950 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2951 gpu_metrics->indep_throttle_status =
2952 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2953 navi1x_throttler_map);
2955 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2957 gpu_metrics->pcie_link_width = metrics.PcieWidth;
2958 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
2960 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2962 if (metrics.CurrGfxVoltageOffset)
2963 gpu_metrics->voltage_gfx =
2964 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2965 if (metrics.CurrMemVidOffset)
2966 gpu_metrics->voltage_mem =
2967 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2968 if (metrics.CurrSocVoltageOffset)
2969 gpu_metrics->voltage_soc =
2970 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2972 *table = (void *)gpu_metrics;
2974 return sizeof(struct gpu_metrics_v1_3);
2977 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
2980 struct smu_table_context *smu_table = &smu->smu_table;
2981 struct gpu_metrics_v1_3 *gpu_metrics =
2982 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2983 SmuMetrics_NV12_legacy_t metrics;
2986 mutex_lock(&smu->metrics_lock);
2988 ret = smu_cmn_get_metrics_table_locked(smu,
2992 mutex_unlock(&smu->metrics_lock);
2996 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
2998 mutex_unlock(&smu->metrics_lock);
3000 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3002 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3003 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3004 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3005 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3006 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3007 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3009 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3010 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3012 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3014 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
3015 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3016 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
3018 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3019 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3020 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3021 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3023 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3024 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3025 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3026 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3027 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3029 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3030 gpu_metrics->indep_throttle_status =
3031 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3032 navi1x_throttler_map);
3034 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3036 gpu_metrics->pcie_link_width =
3037 smu_v11_0_get_current_pcie_link_width(smu);
3038 gpu_metrics->pcie_link_speed =
3039 smu_v11_0_get_current_pcie_link_speed(smu);
3041 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3043 if (metrics.CurrGfxVoltageOffset)
3044 gpu_metrics->voltage_gfx =
3045 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3046 if (metrics.CurrMemVidOffset)
3047 gpu_metrics->voltage_mem =
3048 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3049 if (metrics.CurrSocVoltageOffset)
3050 gpu_metrics->voltage_soc =
3051 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3053 *table = (void *)gpu_metrics;
3055 return sizeof(struct gpu_metrics_v1_3);
3058 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
3061 struct smu_table_context *smu_table = &smu->smu_table;
3062 struct gpu_metrics_v1_3 *gpu_metrics =
3063 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3064 SmuMetrics_NV12_t metrics;
3067 mutex_lock(&smu->metrics_lock);
3069 ret = smu_cmn_get_metrics_table_locked(smu,
3073 mutex_unlock(&smu->metrics_lock);
3077 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
3079 mutex_unlock(&smu->metrics_lock);
3081 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3083 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3084 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3085 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3086 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3087 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3088 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3090 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3091 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3093 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3095 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3096 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3098 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3100 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3101 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3103 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3104 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3105 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3106 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3108 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3109 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3110 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3111 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3112 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3114 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3115 gpu_metrics->indep_throttle_status =
3116 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3117 navi1x_throttler_map);
3119 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3121 gpu_metrics->pcie_link_width = metrics.PcieWidth;
3122 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3124 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3126 if (metrics.CurrGfxVoltageOffset)
3127 gpu_metrics->voltage_gfx =
3128 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3129 if (metrics.CurrMemVidOffset)
3130 gpu_metrics->voltage_mem =
3131 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3132 if (metrics.CurrSocVoltageOffset)
3133 gpu_metrics->voltage_soc =
3134 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3136 *table = (void *)gpu_metrics;
3138 return sizeof(struct gpu_metrics_v1_3);
3141 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
3144 struct amdgpu_device *adev = smu->adev;
3145 uint32_t smu_version;
3148 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3150 dev_err(adev->dev, "Failed to get smu version!\n");
3154 switch (adev->asic_type) {
3156 if (smu_version > 0x00341C00)
3157 ret = navi12_get_gpu_metrics(smu, table);
3159 ret = navi12_get_legacy_gpu_metrics(smu, table);
3164 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
3165 ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
3166 ret = navi10_get_gpu_metrics(smu, table);
3168 ret =navi10_get_legacy_gpu_metrics(smu, table);
3175 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
3177 struct smu_table_context *table_context = &smu->smu_table;
3178 PPTable_t *smc_pptable = table_context->driver_pptable;
3179 struct amdgpu_device *adev = smu->adev;
3182 /* Navi12 does not support this */
3183 if (adev->asic_type == CHIP_NAVI12)
3187 * Skip the MGpuFanBoost setting for those ASICs
3188 * which do not support it
3190 if (!smc_pptable->MGpuFanBoostLimitRpm)
3193 /* Workaround for WS SKU */
3194 if (adev->pdev->device == 0x7312 &&
3195 adev->pdev->revision == 0)
3198 return smu_cmn_send_smc_msg_with_param(smu,
3199 SMU_MSG_SetMGpuFanBoostLimitRpm,
3204 static int navi10_post_smu_init(struct smu_context *smu)
3206 struct amdgpu_device *adev = smu->adev;
3209 if (amdgpu_sriov_vf(adev))
3212 ret = navi10_run_umc_cdr_workaround(smu);
3214 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
3218 if (!smu->dc_controlled_by_gpio) {
3220 * For Navi1X, manually switch it to AC mode as PMFW
3221 * may boot it with DC mode.
3223 ret = smu_v11_0_set_power_source(smu,
3225 SMU_POWER_SOURCE_AC :
3226 SMU_POWER_SOURCE_DC);
3228 dev_err(adev->dev, "Failed to switch to %s mode!\n",
3229 adev->pm.ac_power ? "AC" : "DC");
3237 static const struct pptable_funcs navi10_ppt_funcs = {
3238 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3239 .set_default_dpm_table = navi10_set_default_dpm_table,
3240 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
3241 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
3242 .i2c_init = navi10_i2c_control_init,
3243 .i2c_fini = navi10_i2c_control_fini,
3244 .print_clk_levels = navi10_print_clk_levels,
3245 .force_clk_levels = navi10_force_clk_levels,
3246 .populate_umd_state_clk = navi10_populate_umd_state_clk,
3247 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
3248 .pre_display_config_changed = navi10_pre_display_config_changed,
3249 .display_config_changed = navi10_display_config_changed,
3250 .notify_smc_display_config = navi10_notify_smc_display_config,
3251 .is_dpm_running = navi10_is_dpm_running,
3252 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3253 .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
3254 .get_power_profile_mode = navi10_get_power_profile_mode,
3255 .set_power_profile_mode = navi10_set_power_profile_mode,
3256 .set_watermarks_table = navi10_set_watermarks_table,
3257 .read_sensor = navi10_read_sensor,
3258 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
3259 .set_performance_level = smu_v11_0_set_performance_level,
3260 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
3261 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
3262 .get_power_limit = navi10_get_power_limit,
3263 .update_pcie_parameters = navi10_update_pcie_parameters,
3264 .init_microcode = smu_v11_0_init_microcode,
3265 .load_microcode = smu_v11_0_load_microcode,
3266 .fini_microcode = smu_v11_0_fini_microcode,
3267 .init_smc_tables = navi10_init_smc_tables,
3268 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3269 .init_power = smu_v11_0_init_power,
3270 .fini_power = smu_v11_0_fini_power,
3271 .check_fw_status = smu_v11_0_check_fw_status,
3272 .setup_pptable = navi10_setup_pptable,
3273 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3274 .check_fw_version = smu_v11_0_check_fw_version,
3275 .write_pptable = smu_cmn_write_pptable,
3276 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3277 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3278 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3279 .system_features_control = smu_v11_0_system_features_control,
3280 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3281 .send_smc_msg = smu_cmn_send_smc_msg,
3282 .init_display_count = smu_v11_0_init_display_count,
3283 .set_allowed_mask = smu_v11_0_set_allowed_mask,
3284 .get_enabled_mask = smu_cmn_get_enabled_mask,
3285 .feature_is_enabled = smu_cmn_feature_is_enabled,
3286 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3287 .notify_display_change = smu_v11_0_notify_display_change,
3288 .set_power_limit = smu_v11_0_set_power_limit,
3289 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3290 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3291 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3292 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3293 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3294 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3295 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3296 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3297 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3298 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3299 .gfx_off_control = smu_v11_0_gfx_off_control,
3300 .register_irq_handler = smu_v11_0_register_irq_handler,
3301 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3302 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3303 .baco_is_support = smu_v11_0_baco_is_support,
3304 .baco_get_state = smu_v11_0_baco_get_state,
3305 .baco_set_state = smu_v11_0_baco_set_state,
3306 .baco_enter = navi10_baco_enter,
3307 .baco_exit = navi10_baco_exit,
3308 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3309 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3310 .set_default_od_settings = navi10_set_default_od_settings,
3311 .od_edit_dpm_table = navi10_od_edit_dpm_table,
3312 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3313 .run_btc = navi10_run_btc,
3314 .set_power_source = smu_v11_0_set_power_source,
3315 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3316 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3317 .get_gpu_metrics = navi1x_get_gpu_metrics,
3318 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3319 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3320 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3321 .get_fan_parameters = navi10_get_fan_parameters,
3322 .post_init = navi10_post_smu_init,
3323 .interrupt_work = smu_v11_0_interrupt_work,
3324 .set_mp1_state = smu_cmn_set_mp1_state,
3327 void navi10_set_ppt_funcs(struct smu_context *smu)
3329 smu->ppt_funcs = &navi10_ppt_funcs;
3330 smu->message_map = navi10_message_map;
3331 smu->clock_map = navi10_clk_map;
3332 smu->feature_map = navi10_feature_mask_map;
3333 smu->table_map = navi10_table_map;
3334 smu->pwr_src_map = navi10_pwr_src_map;
3335 smu->workload_map = navi10_workload_map;