drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_dpm.h"
  31 #include "amdgpu_smu.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_atombios.h"
  35 #include "soc15_common.h"
  36 #include "smu_v11_0.h"
  37 #include "smu11_driver_if_navi10.h"
  38 #include "atom.h"
  39 #include "navi10_ppt.h"
  40 #include "smu_v11_0_pptable.h"
  41 #include "smu_v11_0_ppsmc.h"
  42 #include "nbio/nbio_2_3_offset.h"
  43 #include "nbio/nbio_2_3_sh_mask.h"
  44 #include "thm/thm_11_0_2_offset.h"
  45 #include "thm/thm_11_0_2_sh_mask.h"
  46
  47 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  48 #include "smu_cmn.h"
  49 #include "smu_11_0_cdr_table.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define FEATURE_MASK(feature) (1ULL << feature)
  62 #define SMC_DPM_FEATURE ( \
  63         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  64         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  65         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  66         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  67         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  68         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  69         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  70         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  71
  72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
  73
  74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  75         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  76         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  77         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  78         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,    0),
  79         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,   0),
  80         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,         0),
  81         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,        0),
  82         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,         0),
  83         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,        0),
  84         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,        0),
  85         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,       0),
  86         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow,     1),
  87         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh,    1),
  88         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,              0),
  89         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                  0),
  90         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        1),
  91         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         1),
  92         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,         0),
  93         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,          0),
  94         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        1),
  95         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        0),
  96         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,            0),
  97         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable,             0),
  98         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc,                       0),
  99         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                    0),
 100         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,             1),
 101         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,             1),
 102         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,             0),
 103         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,             0),
 104         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,                1),
 105         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,                1),
 106         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,            1),
 107         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig,       0),
 108         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,                0),
 109         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,        0),
 110         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,         0),
 111         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,       0),
 112         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk,       0),
 113         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,        0),
 114         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,            0),
 115         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,            0),
 116         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  0),
 117         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,          1),
 118         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,       0),
 119         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,        0),
 120         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,           0),
 121         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt,             0),
 122         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays,                0),
 123         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
 124         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow,  0),
 125         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                  0),
 126         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               0),
 127         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                  0),
 128         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,          1),
 129         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData,                 0),
 130         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                     0),
 131         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset,           0),
 132         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown,        0),
 133         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   0),
 134         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 0),
 135         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  0),
 136         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                0),
 137         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,               0),
 138         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                        0),
 139         MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALDisableDummyPstateChange, 0),
 140         MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange,   0),
 141         MSG_MAP(GetVoltageByDpm,                PPSMC_MSG_GetVoltageByDpm,              0),
 142         MSG_MAP(GetVoltageByDpmOverdrive,       PPSMC_MSG_GetVoltageByDpmOverdrive,     0),
 143         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,      0),
 144         MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
 145         MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
 146         MSG_MAP(GET_UMC_FW_WA,                  PPSMC_MSG_GetUMCFWWA,                   0),
 147 };
 148
 149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 150         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 151         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 152         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 153         CLK_MAP(FCLK, PPCLK_SOCCLK),
 154         CLK_MAP(UCLK, PPCLK_UCLK),
 155         CLK_MAP(MCLK, PPCLK_UCLK),
 156         CLK_MAP(DCLK, PPCLK_DCLK),
 157         CLK_MAP(VCLK, PPCLK_VCLK),
 158         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 159         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 160         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 161         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 162 };
 163
 164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 165         FEA_MAP(DPM_PREFETCHER),
 166         FEA_MAP(DPM_GFXCLK),
 167         FEA_MAP(DPM_GFX_PACE),
 168         FEA_MAP(DPM_UCLK),
 169         FEA_MAP(DPM_SOCCLK),
 170         FEA_MAP(DPM_MP0CLK),
 171         FEA_MAP(DPM_LINK),
 172         FEA_MAP(DPM_DCEFCLK),
 173         FEA_MAP(MEM_VDDCI_SCALING),
 174         FEA_MAP(MEM_MVDD_SCALING),
 175         FEA_MAP(DS_GFXCLK),
 176         FEA_MAP(DS_SOCCLK),
 177         FEA_MAP(DS_LCLK),
 178         FEA_MAP(DS_DCEFCLK),
 179         FEA_MAP(DS_UCLK),
 180         FEA_MAP(GFX_ULV),
 181         FEA_MAP(FW_DSTATE),
 182         FEA_MAP(GFXOFF),
 183         FEA_MAP(BACO),
 184         FEA_MAP(VCN_PG),
 185         FEA_MAP(JPEG_PG),
 186         FEA_MAP(USB_PG),
 187         FEA_MAP(RSMU_SMN_CG),
 188         FEA_MAP(PPT),
 189         FEA_MAP(TDC),
 190         FEA_MAP(GFX_EDC),
 191         FEA_MAP(APCC_PLUS),
 192         FEA_MAP(GTHR),
 193         FEA_MAP(ACDC),
 194         FEA_MAP(VR0HOT),
 195         FEA_MAP(VR1HOT),
 196         FEA_MAP(FW_CTF),
 197         FEA_MAP(FAN_CONTROL),
 198         FEA_MAP(THERMAL),
 199         FEA_MAP(GFX_DCS),
 200         FEA_MAP(RM),
 201         FEA_MAP(LED_DISPLAY),
 202         FEA_MAP(GFX_SS),
 203         FEA_MAP(OUT_OF_BAND_MONITOR),
 204         FEA_MAP(TEMP_DEPENDENT_VMIN),
 205         FEA_MAP(MMHUB_PG),
 206         FEA_MAP(ATHUB_PG),
 207         FEA_MAP(APCC_DFLL),
 208 };
 209
 210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 211         TAB_MAP(PPTABLE),
 212         TAB_MAP(WATERMARKS),
 213         TAB_MAP(AVFS),
 214         TAB_MAP(AVFS_PSM_DEBUG),
 215         TAB_MAP(AVFS_FUSE_OVERRIDE),
 216         TAB_MAP(PMSTATUSLOG),
 217         TAB_MAP(SMU_METRICS),
 218         TAB_MAP(DRIVER_SMU_CONFIG),
 219         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 220         TAB_MAP(OVERDRIVE),
 221         TAB_MAP(I2C_COMMANDS),
 222         TAB_MAP(PACE),
 223 };
 224
 225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 226         PWR_MAP(AC),
 227         PWR_MAP(DC),
 228 };
 229
 230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 231         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 232         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 233         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 234         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 235         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 236         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 237         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 238 };
 239
 240 static const uint8_t navi1x_throttler_map[] = {
 241         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 242         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 243         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 244         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 245         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 246         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 247         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 248         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 249         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 250         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 251         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 252         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 253         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 254         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 255         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 256         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 257         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 258         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 259 };
 260
 261
 262 static bool is_asic_secure(struct smu_context *smu)
 263 {
 264         struct amdgpu_device *adev = smu->adev;
 265         bool is_secure = true;
 266         uint32_t mp0_fw_intf;
 267
 268         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 269                                    (smnMP0_FW_INTF & 0xffffffff));
 270
 271         if (!(mp0_fw_intf & (1 << 19)))
 272                 is_secure = false;
 273
 274         return is_secure;
 275 }
 276
 277 static int
 278 navi10_get_allowed_feature_mask(struct smu_context *smu,
 279                                   uint32_t *feature_mask, uint32_t num)
 280 {
 281         struct amdgpu_device *adev = smu->adev;
 282
 283         if (num > 2)
 284                 return -EINVAL;
 285
 286         memset(feature_mask, 0, sizeof(uint32_t) * num);
 287
 288         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 289                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 290                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 291                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 292                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 293                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 294                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 295                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 296                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 297                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 298                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 299                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 300                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 301                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 302                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 303                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 304                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 305                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 306                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 307                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)
 308                                 | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);
 309
 310         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 311                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 312
 313         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 314                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 315
 316         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 317                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 318
 319         if (adev->pm.pp_feature & PP_ULV_MASK)
 320                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 321
 322         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 323                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 324
 325         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 326                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 327
 328         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 329                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 330
 331         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 332                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 333
 334         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 335                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 336
 337         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 338                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 339
 340         if (smu->dc_controlled_by_gpio)
 341                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 342
 343         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 344                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 345
 346         /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
 347         if (!(is_asic_secure(smu) &&
 348              (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
 349              (adev->rev_id == 0)) &&
 350             (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
 351                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 352                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 353                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 354
 355         /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
 356         if (is_asic_secure(smu) &&
 357             (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
 358             (adev->rev_id == 0))
 359                 *(uint64_t *)feature_mask &=
 360                                 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 361
 362         return 0;
 363 }
 364
 365 static void navi10_check_bxco_support(struct smu_context *smu)
 366 {
 367         struct smu_table_context *table_context = &smu->smu_table;
 368         struct smu_11_0_powerplay_table *powerplay_table =
 369                 table_context->power_play_table;
 370         struct smu_baco_context *smu_baco = &smu->smu_baco;
 371         struct amdgpu_device *adev = smu->adev;
 372         uint32_t val;
 373
 374         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 375             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 376                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 377                 smu_baco->platform_support =
 378                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 379                                                                         false;
 380         }
 381 }
 382
 383 static int navi10_check_powerplay_table(struct smu_context *smu)
 384 {
 385         struct smu_table_context *table_context = &smu->smu_table;
 386         struct smu_11_0_powerplay_table *powerplay_table =
 387                 table_context->power_play_table;
 388
 389         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
 390                 smu->dc_controlled_by_gpio = true;
 391
 392         navi10_check_bxco_support(smu);
 393
 394         table_context->thermal_controller_type =
 395                 powerplay_table->thermal_controller_type;
 396
 397         /*
 398          * Instead of having its own buffer space and get overdrive_table copied,
 399          * smu->od_settings just points to the actual overdrive_table
 400          */
 401         smu->od_settings = &powerplay_table->overdrive_table;
 402
 403         return 0;
 404 }
 405
 406 static int navi10_append_powerplay_table(struct smu_context *smu)
 407 {
 408         struct amdgpu_device *adev = smu->adev;
 409         struct smu_table_context *table_context = &smu->smu_table;
 410         PPTable_t *smc_pptable = table_context->driver_pptable;
 411         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 412         struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
 413         int index, ret;
 414
 415         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 416                                            smc_dpm_info);
 417
 418         ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
 419                                       (uint8_t **)&smc_dpm_table);
 420         if (ret)
 421                 return ret;
 422
 423         dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 424                         smc_dpm_table->table_header.format_revision,
 425                         smc_dpm_table->table_header.content_revision);
 426
 427         if (smc_dpm_table->table_header.format_revision != 4) {
 428                 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
 429                 return -EINVAL;
 430         }
 431
 432         switch (smc_dpm_table->table_header.content_revision) {
 433         case 5: /* nv10 and nv14 */
 434                 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
 435                                     smc_dpm_table, I2cControllers);
 436                 break;
 437         case 7: /* nv12 */
 438                 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
 439                                               (uint8_t **)&smc_dpm_table_v4_7);
 440                 if (ret)
 441                         return ret;
 442                 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
 443                                     smc_dpm_table_v4_7, I2cControllers);
 444                 break;
 445         default:
 446                 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
 447                                 smc_dpm_table->table_header.content_revision);
 448                 return -EINVAL;
 449         }
 450
 451         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 452                 /* TODO: remove it once SMU fw fix it */
 453                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int navi10_store_powerplay_table(struct smu_context *smu)
 460 {
 461         struct smu_table_context *table_context = &smu->smu_table;
 462         struct smu_11_0_powerplay_table *powerplay_table =
 463                 table_context->power_play_table;
 464
 465         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 466                sizeof(PPTable_t));
 467
 468         return 0;
 469 }
 470
 471 static int navi10_setup_pptable(struct smu_context *smu)
 472 {
 473         int ret = 0;
 474
 475         ret = smu_v11_0_setup_pptable(smu);
 476         if (ret)
 477                 return ret;
 478
 479         ret = navi10_store_powerplay_table(smu);
 480         if (ret)
 481                 return ret;
 482
 483         ret = navi10_append_powerplay_table(smu);
 484         if (ret)
 485                 return ret;
 486
 487         ret = navi10_check_powerplay_table(smu);
 488         if (ret)
 489                 return ret;
 490
 491         return ret;
 492 }
 493
 494 static int navi10_tables_init(struct smu_context *smu)
 495 {
 496         struct smu_table_context *smu_table = &smu->smu_table;
 497         struct smu_table *tables = smu_table->tables;
 498         struct smu_table *dummy_read_1_table =
 499                         &smu_table->dummy_read_1_table;
 500
 501         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 502                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 503         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 504                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 505         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
 506                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 507         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 508                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 509         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 510                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 511         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 512                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 513         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 514                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 515                        AMDGPU_GEM_DOMAIN_VRAM);
 516         SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t),
 517                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 518
 519         dummy_read_1_table->size = 0x40000;
 520         dummy_read_1_table->align = PAGE_SIZE;
 521         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 522
 523         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
 524                                            GFP_KERNEL);
 525         if (!smu_table->metrics_table)
 526                 goto err0_out;
 527         smu_table->metrics_time = 0;
 528
 529         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 530         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 531         if (!smu_table->gpu_metrics_table)
 532                 goto err1_out;
 533
 534         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 535         if (!smu_table->watermarks_table)
 536                 goto err2_out;
 537
 538         smu_table->driver_smu_config_table =
 539                 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
 540         if (!smu_table->driver_smu_config_table)
 541                 goto err3_out;
 542
 543         return 0;
 544
 545 err3_out:
 546         kfree(smu_table->watermarks_table);
 547 err2_out:
 548         kfree(smu_table->gpu_metrics_table);
 549 err1_out:
 550         kfree(smu_table->metrics_table);
 551 err0_out:
 552         return -ENOMEM;
 553 }
 554
 555 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
 556                                               MetricsMember_t member,
 557                                               uint32_t *value)
 558 {
 559         struct smu_table_context *smu_table = &smu->smu_table;
 560         SmuMetrics_legacy_t *metrics =
 561                 (SmuMetrics_legacy_t *)smu_table->metrics_table;
 562         int ret = 0;
 563
 564         ret = smu_cmn_get_metrics_table(smu,
 565                                         NULL,
 566                                         false);
 567         if (ret)
 568                 return ret;
 569
 570         switch (member) {
 571         case METRICS_CURR_GFXCLK:
 572                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 573                 break;
 574         case METRICS_CURR_SOCCLK:
 575                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 576                 break;
 577         case METRICS_CURR_UCLK:
 578                 *value = metrics->CurrClock[PPCLK_UCLK];
 579                 break;
 580         case METRICS_CURR_VCLK:
 581                 *value = metrics->CurrClock[PPCLK_VCLK];
 582                 break;
 583         case METRICS_CURR_DCLK:
 584                 *value = metrics->CurrClock[PPCLK_DCLK];
 585                 break;
 586         case METRICS_CURR_DCEFCLK:
 587                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 588                 break;
 589         case METRICS_AVERAGE_GFXCLK:
 590                 *value = metrics->AverageGfxclkFrequency;
 591                 break;
 592         case METRICS_AVERAGE_SOCCLK:
 593                 *value = metrics->AverageSocclkFrequency;
 594                 break;
 595         case METRICS_AVERAGE_UCLK:
 596                 *value = metrics->AverageUclkFrequency;
 597                 break;
 598         case METRICS_AVERAGE_GFXACTIVITY:
 599                 *value = metrics->AverageGfxActivity;
 600                 break;
 601         case METRICS_AVERAGE_MEMACTIVITY:
 602                 *value = metrics->AverageUclkActivity;
 603                 break;
 604         case METRICS_AVERAGE_SOCKETPOWER:
 605                 *value = metrics->AverageSocketPower << 8;
 606                 break;
 607         case METRICS_TEMPERATURE_EDGE:
 608                 *value = metrics->TemperatureEdge *
 609                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 610                 break;
 611         case METRICS_TEMPERATURE_HOTSPOT:
 612                 *value = metrics->TemperatureHotspot *
 613                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 614                 break;
 615         case METRICS_TEMPERATURE_MEM:
 616                 *value = metrics->TemperatureMem *
 617                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 618                 break;
 619         case METRICS_TEMPERATURE_VRGFX:
 620                 *value = metrics->TemperatureVrGfx *
 621                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 622                 break;
 623         case METRICS_TEMPERATURE_VRSOC:
 624                 *value = metrics->TemperatureVrSoc *
 625                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 626                 break;
 627         case METRICS_THROTTLER_STATUS:
 628                 *value = metrics->ThrottlerStatus;
 629                 break;
 630         case METRICS_CURR_FANSPEED:
 631                 *value = metrics->CurrFanSpeed;
 632                 break;
 633         default:
 634                 *value = UINT_MAX;
 635                 break;
 636         }
 637
 638         return ret;
 639 }
 640
 641 static int navi10_get_smu_metrics_data(struct smu_context *smu,
 642                                        MetricsMember_t member,
 643                                        uint32_t *value)
 644 {
 645         struct smu_table_context *smu_table = &smu->smu_table;
 646         SmuMetrics_t *metrics =
 647                 (SmuMetrics_t *)smu_table->metrics_table;
 648         int ret = 0;
 649
 650         ret = smu_cmn_get_metrics_table(smu,
 651                                         NULL,
 652                                         false);
 653         if (ret)
 654                 return ret;
 655
 656         switch (member) {
 657         case METRICS_CURR_GFXCLK:
 658                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 659                 break;
 660         case METRICS_CURR_SOCCLK:
 661                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 662                 break;
 663         case METRICS_CURR_UCLK:
 664                 *value = metrics->CurrClock[PPCLK_UCLK];
 665                 break;
 666         case METRICS_CURR_VCLK:
 667                 *value = metrics->CurrClock[PPCLK_VCLK];
 668                 break;
 669         case METRICS_CURR_DCLK:
 670                 *value = metrics->CurrClock[PPCLK_DCLK];
 671                 break;
 672         case METRICS_CURR_DCEFCLK:
 673                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 674                 break;
 675         case METRICS_AVERAGE_GFXCLK:
 676                 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
 677                         *value = metrics->AverageGfxclkFrequencyPreDs;
 678                 else
 679                         *value = metrics->AverageGfxclkFrequencyPostDs;
 680                 break;
 681         case METRICS_AVERAGE_SOCCLK:
 682                 *value = metrics->AverageSocclkFrequency;
 683                 break;
 684         case METRICS_AVERAGE_UCLK:
 685                 *value = metrics->AverageUclkFrequencyPostDs;
 686                 break;
 687         case METRICS_AVERAGE_GFXACTIVITY:
 688                 *value = metrics->AverageGfxActivity;
 689                 break;
 690         case METRICS_AVERAGE_MEMACTIVITY:
 691                 *value = metrics->AverageUclkActivity;
 692                 break;
 693         case METRICS_AVERAGE_SOCKETPOWER:
 694                 *value = metrics->AverageSocketPower << 8;
 695                 break;
 696         case METRICS_TEMPERATURE_EDGE:
 697                 *value = metrics->TemperatureEdge *
 698                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 699                 break;
 700         case METRICS_TEMPERATURE_HOTSPOT:
 701                 *value = metrics->TemperatureHotspot *
 702                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 703                 break;
 704         case METRICS_TEMPERATURE_MEM:
 705                 *value = metrics->TemperatureMem *
 706                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 707                 break;
 708         case METRICS_TEMPERATURE_VRGFX:
 709                 *value = metrics->TemperatureVrGfx *
 710                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 711                 break;
 712         case METRICS_TEMPERATURE_VRSOC:
 713                 *value = metrics->TemperatureVrSoc *
 714                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 715                 break;
 716         case METRICS_THROTTLER_STATUS:
 717                 *value = metrics->ThrottlerStatus;
 718                 break;
 719         case METRICS_CURR_FANSPEED:
 720                 *value = metrics->CurrFanSpeed;
 721                 break;
 722         default:
 723                 *value = UINT_MAX;
 724                 break;
 725         }
 726
 727         return ret;
 728 }
 729
 730 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
 731                                               MetricsMember_t member,
 732                                               uint32_t *value)
 733 {
 734         struct smu_table_context *smu_table = &smu->smu_table;
 735         SmuMetrics_NV12_legacy_t *metrics =
 736                 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
 737         int ret = 0;
 738
 739         ret = smu_cmn_get_metrics_table(smu,
 740                                         NULL,
 741                                         false);
 742         if (ret)
 743                 return ret;
 744
 745         switch (member) {
 746         case METRICS_CURR_GFXCLK:
 747                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 748                 break;
 749         case METRICS_CURR_SOCCLK:
 750                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 751                 break;
 752         case METRICS_CURR_UCLK:
 753                 *value = metrics->CurrClock[PPCLK_UCLK];
 754                 break;
 755         case METRICS_CURR_VCLK:
 756                 *value = metrics->CurrClock[PPCLK_VCLK];
 757                 break;
 758         case METRICS_CURR_DCLK:
 759                 *value = metrics->CurrClock[PPCLK_DCLK];
 760                 break;
 761         case METRICS_CURR_DCEFCLK:
 762                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 763                 break;
 764         case METRICS_AVERAGE_GFXCLK:
 765                 *value = metrics->AverageGfxclkFrequency;
 766                 break;
 767         case METRICS_AVERAGE_SOCCLK:
 768                 *value = metrics->AverageSocclkFrequency;
 769                 break;
 770         case METRICS_AVERAGE_UCLK:
 771                 *value = metrics->AverageUclkFrequency;
 772                 break;
 773         case METRICS_AVERAGE_GFXACTIVITY:
 774                 *value = metrics->AverageGfxActivity;
 775                 break;
 776         case METRICS_AVERAGE_MEMACTIVITY:
 777                 *value = metrics->AverageUclkActivity;
 778                 break;
 779         case METRICS_AVERAGE_SOCKETPOWER:
 780                 *value = metrics->AverageSocketPower << 8;
 781                 break;
 782         case METRICS_TEMPERATURE_EDGE:
 783                 *value = metrics->TemperatureEdge *
 784                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 785                 break;
 786         case METRICS_TEMPERATURE_HOTSPOT:
 787                 *value = metrics->TemperatureHotspot *
 788                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 789                 break;
 790         case METRICS_TEMPERATURE_MEM:
 791                 *value = metrics->TemperatureMem *
 792                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 793                 break;
 794         case METRICS_TEMPERATURE_VRGFX:
 795                 *value = metrics->TemperatureVrGfx *
 796                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 797                 break;
 798         case METRICS_TEMPERATURE_VRSOC:
 799                 *value = metrics->TemperatureVrSoc *
 800                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 801                 break;
 802         case METRICS_THROTTLER_STATUS:
 803                 *value = metrics->ThrottlerStatus;
 804                 break;
 805         case METRICS_CURR_FANSPEED:
 806                 *value = metrics->CurrFanSpeed;
 807                 break;
 808         default:
 809                 *value = UINT_MAX;
 810                 break;
 811         }
 812
 813         return ret;
 814 }
 815
 816 static int navi12_get_smu_metrics_data(struct smu_context *smu,
 817                                        MetricsMember_t member,
 818                                        uint32_t *value)
 819 {
 820         struct smu_table_context *smu_table = &smu->smu_table;
 821         SmuMetrics_NV12_t *metrics =
 822                 (SmuMetrics_NV12_t *)smu_table->metrics_table;
 823         int ret = 0;
 824
 825         ret = smu_cmn_get_metrics_table(smu,
 826                                         NULL,
 827                                         false);
 828         if (ret)
 829                 return ret;
 830
 831         switch (member) {
 832         case METRICS_CURR_GFXCLK:
 833                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 834                 break;
 835         case METRICS_CURR_SOCCLK:
 836                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 837                 break;
 838         case METRICS_CURR_UCLK:
 839                 *value = metrics->CurrClock[PPCLK_UCLK];
 840                 break;
 841         case METRICS_CURR_VCLK:
 842                 *value = metrics->CurrClock[PPCLK_VCLK];
 843                 break;
 844         case METRICS_CURR_DCLK:
 845                 *value = metrics->CurrClock[PPCLK_DCLK];
 846                 break;
 847         case METRICS_CURR_DCEFCLK:
 848                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 849                 break;
 850         case METRICS_AVERAGE_GFXCLK:
 851                 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
 852                         *value = metrics->AverageGfxclkFrequencyPreDs;
 853                 else
 854                         *value = metrics->AverageGfxclkFrequencyPostDs;
 855                 break;
 856         case METRICS_AVERAGE_SOCCLK:
 857                 *value = metrics->AverageSocclkFrequency;
 858                 break;
 859         case METRICS_AVERAGE_UCLK:
 860                 *value = metrics->AverageUclkFrequencyPostDs;
 861                 break;
 862         case METRICS_AVERAGE_GFXACTIVITY:
 863                 *value = metrics->AverageGfxActivity;
 864                 break;
 865         case METRICS_AVERAGE_MEMACTIVITY:
 866                 *value = metrics->AverageUclkActivity;
 867                 break;
 868         case METRICS_AVERAGE_SOCKETPOWER:
 869                 *value = metrics->AverageSocketPower << 8;
 870                 break;
 871         case METRICS_TEMPERATURE_EDGE:
 872                 *value = metrics->TemperatureEdge *
 873                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 874                 break;
 875         case METRICS_TEMPERATURE_HOTSPOT:
 876                 *value = metrics->TemperatureHotspot *
 877                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 878                 break;
 879         case METRICS_TEMPERATURE_MEM:
 880                 *value = metrics->TemperatureMem *
 881                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 882                 break;
 883         case METRICS_TEMPERATURE_VRGFX:
 884                 *value = metrics->TemperatureVrGfx *
 885                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 886                 break;
 887         case METRICS_TEMPERATURE_VRSOC:
 888                 *value = metrics->TemperatureVrSoc *
 889                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 890                 break;
 891         case METRICS_THROTTLER_STATUS:
 892                 *value = metrics->ThrottlerStatus;
 893                 break;
 894         case METRICS_CURR_FANSPEED:
 895                 *value = metrics->CurrFanSpeed;
 896                 break;
 897         default:
 898                 *value = UINT_MAX;
 899                 break;
 900         }
 901
 902         return ret;
 903 }
 904
 905 static int navi1x_get_smu_metrics_data(struct smu_context *smu,
 906                                        MetricsMember_t member,
 907                                        uint32_t *value)
 908 {
 909         struct amdgpu_device *adev = smu->adev;
 910         uint32_t smu_version;
 911         int ret = 0;
 912
 913         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 914         if (ret) {
 915                 dev_err(adev->dev, "Failed to get smu version!\n");
 916                 return ret;
 917         }
 918
 919         switch (adev->ip_versions[MP1_HWIP][0]) {
 920         case IP_VERSION(11, 0, 9):
 921                 if (smu_version > 0x00341C00)
 922                         ret = navi12_get_smu_metrics_data(smu, member, value);
 923                 else
 924                         ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
 925                 break;
 926         case IP_VERSION(11, 0, 0):
 927         case IP_VERSION(11, 0, 5):
 928         default:
 929                 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
 930                       ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
 931                         ret = navi10_get_smu_metrics_data(smu, member, value);
 932                 else
 933                         ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
 934                 break;
 935         }
 936
 937         return ret;
 938 }
 939
 940 static int navi10_allocate_dpm_context(struct smu_context *smu)
 941 {
 942         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 943
 944         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 945                                        GFP_KERNEL);
 946         if (!smu_dpm->dpm_context)
 947                 return -ENOMEM;
 948
 949         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 950
 951         return 0;
 952 }
 953
 954 static int navi10_init_smc_tables(struct smu_context *smu)
 955 {
 956         int ret = 0;
 957
 958         ret = navi10_tables_init(smu);
 959         if (ret)
 960                 return ret;
 961
 962         ret = navi10_allocate_dpm_context(smu);
 963         if (ret)
 964                 return ret;
 965
 966         return smu_v11_0_init_smc_tables(smu);
 967 }
 968
 969 static int navi10_set_default_dpm_table(struct smu_context *smu)
 970 {
 971         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 972         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 973         struct smu_11_0_dpm_table *dpm_table;
 974         int ret = 0;
 975
 976         /* socclk dpm table setup */
 977         dpm_table = &dpm_context->dpm_tables.soc_table;
 978         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 979                 ret = smu_v11_0_set_single_dpm_table(smu,
 980                                                      SMU_SOCCLK,
 981                                                      dpm_table);
 982                 if (ret)
 983                         return ret;
 984                 dpm_table->is_fine_grained =
 985                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 986         } else {
 987                 dpm_table->count = 1;
 988                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 989                 dpm_table->dpm_levels[0].enabled = true;
 990                 dpm_table->min = dpm_table->dpm_levels[0].value;
 991                 dpm_table->max = dpm_table->dpm_levels[0].value;
 992         }
 993
 994         /* gfxclk dpm table setup */
 995         dpm_table = &dpm_context->dpm_tables.gfx_table;
 996         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 997                 ret = smu_v11_0_set_single_dpm_table(smu,
 998                                                      SMU_GFXCLK,
 999                                                      dpm_table);
1000                 if (ret)
1001                         return ret;
1002                 dpm_table->is_fine_grained =
1003                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
1004         } else {
1005                 dpm_table->count = 1;
1006                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1007                 dpm_table->dpm_levels[0].enabled = true;
1008                 dpm_table->min = dpm_table->dpm_levels[0].value;
1009                 dpm_table->max = dpm_table->dpm_levels[0].value;
1010         }
1011
1012         /* uclk dpm table setup */
1013         dpm_table = &dpm_context->dpm_tables.uclk_table;
1014         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1015                 ret = smu_v11_0_set_single_dpm_table(smu,
1016                                                      SMU_UCLK,
1017                                                      dpm_table);
1018                 if (ret)
1019                         return ret;
1020                 dpm_table->is_fine_grained =
1021                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
1022         } else {
1023                 dpm_table->count = 1;
1024                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1025                 dpm_table->dpm_levels[0].enabled = true;
1026                 dpm_table->min = dpm_table->dpm_levels[0].value;
1027                 dpm_table->max = dpm_table->dpm_levels[0].value;
1028         }
1029
1030         /* vclk dpm table setup */
1031         dpm_table = &dpm_context->dpm_tables.vclk_table;
1032         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1033                 ret = smu_v11_0_set_single_dpm_table(smu,
1034                                                      SMU_VCLK,
1035                                                      dpm_table);
1036                 if (ret)
1037                         return ret;
1038                 dpm_table->is_fine_grained =
1039                         !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1040         } else {
1041                 dpm_table->count = 1;
1042                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1043                 dpm_table->dpm_levels[0].enabled = true;
1044                 dpm_table->min = dpm_table->dpm_levels[0].value;
1045                 dpm_table->max = dpm_table->dpm_levels[0].value;
1046         }
1047
1048         /* dclk dpm table setup */
1049         dpm_table = &dpm_context->dpm_tables.dclk_table;
1050         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1051                 ret = smu_v11_0_set_single_dpm_table(smu,
1052                                                      SMU_DCLK,
1053                                                      dpm_table);
1054                 if (ret)
1055                         return ret;
1056                 dpm_table->is_fine_grained =
1057                         !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1058         } else {
1059                 dpm_table->count = 1;
1060                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1061                 dpm_table->dpm_levels[0].enabled = true;
1062                 dpm_table->min = dpm_table->dpm_levels[0].value;
1063                 dpm_table->max = dpm_table->dpm_levels[0].value;
1064         }
1065
1066         /* dcefclk dpm table setup */
1067         dpm_table = &dpm_context->dpm_tables.dcef_table;
1068         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1069                 ret = smu_v11_0_set_single_dpm_table(smu,
1070                                                      SMU_DCEFCLK,
1071                                                      dpm_table);
1072                 if (ret)
1073                         return ret;
1074                 dpm_table->is_fine_grained =
1075                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1076         } else {
1077                 dpm_table->count = 1;
1078                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1079                 dpm_table->dpm_levels[0].enabled = true;
1080                 dpm_table->min = dpm_table->dpm_levels[0].value;
1081                 dpm_table->max = dpm_table->dpm_levels[0].value;
1082         }
1083
1084         /* pixelclk dpm table setup */
1085         dpm_table = &dpm_context->dpm_tables.pixel_table;
1086         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1087                 ret = smu_v11_0_set_single_dpm_table(smu,
1088                                                      SMU_PIXCLK,
1089                                                      dpm_table);
1090                 if (ret)
1091                         return ret;
1092                 dpm_table->is_fine_grained =
1093                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1094         } else {
1095                 dpm_table->count = 1;
1096                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1097                 dpm_table->dpm_levels[0].enabled = true;
1098                 dpm_table->min = dpm_table->dpm_levels[0].value;
1099                 dpm_table->max = dpm_table->dpm_levels[0].value;
1100         }
1101
1102         /* displayclk dpm table setup */
1103         dpm_table = &dpm_context->dpm_tables.display_table;
1104         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1105                 ret = smu_v11_0_set_single_dpm_table(smu,
1106                                                      SMU_DISPCLK,
1107                                                      dpm_table);
1108                 if (ret)
1109                         return ret;
1110                 dpm_table->is_fine_grained =
1111                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1112         } else {
1113                 dpm_table->count = 1;
1114                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1115                 dpm_table->dpm_levels[0].enabled = true;
1116                 dpm_table->min = dpm_table->dpm_levels[0].value;
1117                 dpm_table->max = dpm_table->dpm_levels[0].value;
1118         }
1119
1120         /* phyclk dpm table setup */
1121         dpm_table = &dpm_context->dpm_tables.phy_table;
1122         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1123                 ret = smu_v11_0_set_single_dpm_table(smu,
1124                                                      SMU_PHYCLK,
1125                                                      dpm_table);
1126                 if (ret)
1127                         return ret;
1128                 dpm_table->is_fine_grained =
1129                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1130         } else {
1131                 dpm_table->count = 1;
1132                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1133                 dpm_table->dpm_levels[0].enabled = true;
1134                 dpm_table->min = dpm_table->dpm_levels[0].value;
1135                 dpm_table->max = dpm_table->dpm_levels[0].value;
1136         }
1137
1138         return 0;
1139 }
1140
1141 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1142 {
1143         int ret = 0;
1144
1145         if (enable) {
1146                 /* vcn dpm on is a prerequisite for vcn power gate messages */
1147                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1148                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1149                         if (ret)
1150                                 return ret;
1151                 }
1152         } else {
1153                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1154                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1155                         if (ret)
1156                                 return ret;
1157                 }
1158         }
1159
1160         return ret;
1161 }
1162
1163 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1164 {
1165         int ret = 0;
1166
1167         if (enable) {
1168                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1169                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1170                         if (ret)
1171                                 return ret;
1172                 }
1173         } else {
1174                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1175                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1176                         if (ret)
1177                                 return ret;
1178                 }
1179         }
1180
1181         return ret;
1182 }
1183
1184 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1185                                        enum smu_clk_type clk_type,
1186                                        uint32_t *value)
1187 {
1188         MetricsMember_t member_type;
1189         int clk_id = 0;
1190
1191         clk_id = smu_cmn_to_asic_specific_index(smu,
1192                                                 CMN2ASIC_MAPPING_CLK,
1193                                                 clk_type);
1194         if (clk_id < 0)
1195                 return clk_id;
1196
1197         switch (clk_id) {
1198         case PPCLK_GFXCLK:
1199                 member_type = METRICS_CURR_GFXCLK;
1200                 break;
1201         case PPCLK_UCLK:
1202                 member_type = METRICS_CURR_UCLK;
1203                 break;
1204         case PPCLK_SOCCLK:
1205                 member_type = METRICS_CURR_SOCCLK;
1206                 break;
1207         case PPCLK_VCLK:
1208                 member_type = METRICS_CURR_VCLK;
1209                 break;
1210         case PPCLK_DCLK:
1211                 member_type = METRICS_CURR_DCLK;
1212                 break;
1213         case PPCLK_DCEFCLK:
1214                 member_type = METRICS_CURR_DCEFCLK;
1215                 break;
1216         default:
1217                 return -EINVAL;
1218         }
1219
1220         return navi1x_get_smu_metrics_data(smu,
1221                                            member_type,
1222                                            value);
1223 }
1224
1225 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1226 {
1227         PPTable_t *pptable = smu->smu_table.driver_pptable;
1228         DpmDescriptor_t *dpm_desc = NULL;
1229         uint32_t clk_index = 0;
1230
1231         clk_index = smu_cmn_to_asic_specific_index(smu,
1232                                                    CMN2ASIC_MAPPING_CLK,
1233                                                    clk_type);
1234         dpm_desc = &pptable->DpmDescriptor[clk_index];
1235
1236         /* 0 - Fine grained DPM, 1 - Discrete DPM */
1237         return dpm_desc->SnapToDiscrete == 0;
1238 }
1239
1240 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1241 {
1242         return od_table->cap[cap];
1243 }
1244
1245 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1246                                         enum SMU_11_0_ODSETTING_ID setting,
1247                                         uint32_t *min, uint32_t *max)
1248 {
1249         if (min)
1250                 *min = od_table->min[setting];
1251         if (max)
1252                 *max = od_table->max[setting];
1253 }
1254
1255 static int navi10_emit_clk_levels(struct smu_context *smu,
1256                                   enum smu_clk_type clk_type,
1257                                   char *buf,
1258                                   int *offset)
1259 {
1260         uint16_t *curve_settings;
1261         int ret = 0;
1262         uint32_t cur_value = 0, value = 0;
1263         uint32_t freq_values[3] = {0};
1264         uint32_t i, levels, mark_index = 0, count = 0;
1265         struct smu_table_context *table_context = &smu->smu_table;
1266         uint32_t gen_speed, lane_width;
1267         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1268         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1269         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1270         OverDriveTable_t *od_table =
1271                 (OverDriveTable_t *)table_context->overdrive_table;
1272         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1273         uint32_t min_value, max_value;
1274
1275         switch (clk_type) {
1276         case SMU_GFXCLK:
1277         case SMU_SCLK:
1278         case SMU_SOCCLK:
1279         case SMU_MCLK:
1280         case SMU_UCLK:
1281         case SMU_FCLK:
1282         case SMU_VCLK:
1283         case SMU_DCLK:
1284         case SMU_DCEFCLK:
1285                 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1286                 if (ret)
1287                         return ret;
1288
1289                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1290                 if (ret)
1291                         return ret;
1292
1293                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1294                         for (i = 0; i < count; i++) {
1295                                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1296                                                                       clk_type, i, &value);
1297                                 if (ret)
1298                                         return ret;
1299
1300                                 *offset += sysfs_emit_at(buf, *offset,
1301                                                 "%d: %uMhz %s\n",
1302                                                 i, value,
1303                                                 cur_value == value ? "*" : "");
1304                         }
1305                 } else {
1306                         ret = smu_v11_0_get_dpm_freq_by_index(smu,
1307                                                               clk_type, 0, &freq_values[0]);
1308                         if (ret)
1309                                 return ret;
1310                         ret = smu_v11_0_get_dpm_freq_by_index(smu,
1311                                                               clk_type,
1312                                                               count - 1,
1313                                                               &freq_values[2]);
1314                         if (ret)
1315                                 return ret;
1316
1317                         freq_values[1] = cur_value;
1318                         mark_index = cur_value == freq_values[0] ? 0 :
1319                                      cur_value == freq_values[2] ? 2 : 1;
1320
1321                         levels = 3;
1322                         if (mark_index != 1) {
1323                                 levels = 2;
1324                                 freq_values[1] = freq_values[2];
1325                         }
1326
1327                         for (i = 0; i < levels; i++) {
1328                                 *offset += sysfs_emit_at(buf, *offset,
1329                                                 "%d: %uMhz %s\n",
1330                                                 i, freq_values[i],
1331                                                 i == mark_index ? "*" : "");
1332                         }
1333                 }
1334                 break;
1335         case SMU_PCIE:
1336                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1337                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1338                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1339                         *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i,
1340                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1341                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1342                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1343                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1344                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1345                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1346                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1347                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1348                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1349                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1350                                         pptable->LclkFreq[i],
1351                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1352                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1353                                         "*" : "");
1354                 }
1355                 break;
1356         case SMU_OD_SCLK:
1357                 if (!smu->od_enabled || !od_table || !od_settings)
1358                         return -EOPNOTSUPP;
1359                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1360                         break;
1361                 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n",
1362                                           od_table->GfxclkFmin, od_table->GfxclkFmax);
1363                 break;
1364         case SMU_OD_MCLK:
1365                 if (!smu->od_enabled || !od_table || !od_settings)
1366                         return -EOPNOTSUPP;
1367                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1368                         break;
1369                 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax);
1370                 break;
1371         case SMU_OD_VDDC_CURVE:
1372                 if (!smu->od_enabled || !od_table || !od_settings)
1373                         return -EOPNOTSUPP;
1374                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1375                         break;
1376                 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n");
1377                 for (i = 0; i < 3; i++) {
1378                         switch (i) {
1379                         case 0:
1380                                 curve_settings = &od_table->GfxclkFreq1;
1381                                 break;
1382                         case 1:
1383                                 curve_settings = &od_table->GfxclkFreq2;
1384                                 break;
1385                         case 2:
1386                                 curve_settings = &od_table->GfxclkFreq3;
1387                                 break;
1388                         default:
1389                                 break;
1390                         }
1391                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n",
1392                                                   i, curve_settings[0],
1393                                         curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1394                 }
1395                 break;
1396         case SMU_OD_RANGE:
1397                 if (!smu->od_enabled || !od_table || !od_settings)
1398                         return -EOPNOTSUPP;
1399                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
1400
1401                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1402                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1403                                                     &min_value, NULL);
1404                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1405                                                     NULL, &max_value);
1406                         *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n",
1407                                         min_value, max_value);
1408                 }
1409
1410                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1411                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1412                                                     &min_value, &max_value);
1413                         *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n",
1414                                         min_value, max_value);
1415                 }
1416
1417                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1418                         navi10_od_setting_get_range(od_settings,
1419                                                     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1420                                                     &min_value, &max_value);
1421                         *offset += sysfs_emit_at(buf, *offset,
1422                                                  "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1423                                                  min_value, max_value);
1424                         navi10_od_setting_get_range(od_settings,
1425                                                     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1426                                                     &min_value, &max_value);
1427                         *offset += sysfs_emit_at(buf, *offset,
1428                                                  "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1429                                                  min_value, max_value);
1430                         navi10_od_setting_get_range(od_settings,
1431                                                     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1432                                                     &min_value, &max_value);
1433                         *offset += sysfs_emit_at(buf, *offset,
1434                                                  "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1435                                                  min_value, max_value);
1436                         navi10_od_setting_get_range(od_settings,
1437                                                     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1438                                                     &min_value, &max_value);
1439                         *offset += sysfs_emit_at(buf, *offset,
1440                                                  "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1441                                                  min_value, max_value);
1442                         navi10_od_setting_get_range(od_settings,
1443                                                     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1444                                                     &min_value, &max_value);
1445                         *offset += sysfs_emit_at(buf, *offset,
1446                                                  "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1447                                                  min_value, max_value);
1448                         navi10_od_setting_get_range(od_settings,
1449                                                     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1450                                                     &min_value, &max_value);
1451                         *offset += sysfs_emit_at(buf, *offset,
1452                                                  "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1453                                                  min_value, max_value);
1454                 }
1455
1456                 break;
1457         default:
1458                 break;
1459         }
1460
1461         return 0;
1462 }
1463
1464 static int navi10_print_clk_levels(struct smu_context *smu,
1465                         enum smu_clk_type clk_type, char *buf)
1466 {
1467         uint16_t *curve_settings;
1468         int i, levels, size = 0, ret = 0;
1469         uint32_t cur_value = 0, value = 0, count = 0;
1470         uint32_t freq_values[3] = {0};
1471         uint32_t mark_index = 0;
1472         struct smu_table_context *table_context = &smu->smu_table;
1473         uint32_t gen_speed, lane_width;
1474         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1475         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1476         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1477         OverDriveTable_t *od_table =
1478                 (OverDriveTable_t *)table_context->overdrive_table;
1479         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1480         uint32_t min_value, max_value;
1481
1482         smu_cmn_get_sysfs_buf(&buf, &size);
1483
1484         switch (clk_type) {
1485         case SMU_GFXCLK:
1486         case SMU_SCLK:
1487         case SMU_SOCCLK:
1488         case SMU_MCLK:
1489         case SMU_UCLK:
1490         case SMU_FCLK:
1491         case SMU_VCLK:
1492         case SMU_DCLK:
1493         case SMU_DCEFCLK:
1494                 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1495                 if (ret)
1496                         return size;
1497
1498                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1499                 if (ret)
1500                         return size;
1501
1502                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1503                         for (i = 0; i < count; i++) {
1504                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1505                                 if (ret)
1506                                         return size;
1507
1508                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1509                                                 cur_value == value ? "*" : "");
1510                         }
1511                 } else {
1512                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1513                         if (ret)
1514                                 return size;
1515                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1516                         if (ret)
1517                                 return size;
1518
1519                         freq_values[1] = cur_value;
1520                         mark_index = cur_value == freq_values[0] ? 0 :
1521                                      cur_value == freq_values[2] ? 2 : 1;
1522
1523                         levels = 3;
1524                         if (mark_index != 1) {
1525                                 levels = 2;
1526                                 freq_values[1] = freq_values[2];
1527                         }
1528
1529                         for (i = 0; i < levels; i++) {
1530                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1531                                                 i == mark_index ? "*" : "");
1532                         }
1533                 }
1534                 break;
1535         case SMU_PCIE:
1536                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1537                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1538                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1539                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1540                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1541                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1542                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1543                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1544                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1545                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1546                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1547                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1548                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1549                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1550                                         pptable->LclkFreq[i],
1551                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1552                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1553                                         "*" : "");
1554                 break;
1555         case SMU_OD_SCLK:
1556                 if (!smu->od_enabled || !od_table || !od_settings)
1557                         break;
1558                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1559                         break;
1560                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1561                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1562                                       od_table->GfxclkFmin, od_table->GfxclkFmax);
1563                 break;
1564         case SMU_OD_MCLK:
1565                 if (!smu->od_enabled || !od_table || !od_settings)
1566                         break;
1567                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1568                         break;
1569                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1570                 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax);
1571                 break;
1572         case SMU_OD_VDDC_CURVE:
1573                 if (!smu->od_enabled || !od_table || !od_settings)
1574                         break;
1575                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1576                         break;
1577                 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
1578                 for (i = 0; i < 3; i++) {
1579                         switch (i) {
1580                         case 0:
1581                                 curve_settings = &od_table->GfxclkFreq1;
1582                                 break;
1583                         case 1:
1584                                 curve_settings = &od_table->GfxclkFreq2;
1585                                 break;
1586                         case 2:
1587                                 curve_settings = &od_table->GfxclkFreq3;
1588                                 break;
1589                         default:
1590                                 break;
1591                         }
1592                         size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n",
1593                                               i, curve_settings[0],
1594                                         curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1595                 }
1596                 break;
1597         case SMU_OD_RANGE:
1598                 if (!smu->od_enabled || !od_table || !od_settings)
1599                         break;
1600                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1601
1602                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1603                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1604                                                     &min_value, NULL);
1605                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1606                                                     NULL, &max_value);
1607                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1608                                         min_value, max_value);
1609                 }
1610
1611                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1612                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1613                                                     &min_value, &max_value);
1614                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1615                                         min_value, max_value);
1616                 }
1617
1618                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1619                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1620                                                     &min_value, &max_value);
1621                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1622                                               min_value, max_value);
1623                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1624                                                     &min_value, &max_value);
1625                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1626                                               min_value, max_value);
1627                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1628                                                     &min_value, &max_value);
1629                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1630                                               min_value, max_value);
1631                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1632                                                     &min_value, &max_value);
1633                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1634                                               min_value, max_value);
1635                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1636                                                     &min_value, &max_value);
1637                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1638                                               min_value, max_value);
1639                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1640                                                     &min_value, &max_value);
1641                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1642                                               min_value, max_value);
1643                 }
1644
1645                 break;
1646         default:
1647                 break;
1648         }
1649
1650         return size;
1651 }
1652
1653 static int navi10_force_clk_levels(struct smu_context *smu,
1654                                    enum smu_clk_type clk_type, uint32_t mask)
1655 {
1656
1657         int ret = 0;
1658         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1659
1660         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1661         soft_max_level = mask ? (fls(mask) - 1) : 0;
1662
1663         switch (clk_type) {
1664         case SMU_GFXCLK:
1665         case SMU_SCLK:
1666         case SMU_SOCCLK:
1667         case SMU_MCLK:
1668         case SMU_UCLK:
1669         case SMU_FCLK:
1670                 /* There is only 2 levels for fine grained DPM */
1671                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1672                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1673                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1674                 }
1675
1676                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1677                 if (ret)
1678                         return 0;
1679
1680                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1681                 if (ret)
1682                         return 0;
1683
1684                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1685                 if (ret)
1686                         return 0;
1687                 break;
1688         case SMU_DCEFCLK:
1689                 dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n");
1690                 break;
1691
1692         default:
1693                 break;
1694         }
1695
1696         return 0;
1697 }
1698
1699 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1700 {
1701         struct smu_11_0_dpm_context *dpm_context =
1702                                 smu->smu_dpm.dpm_context;
1703         struct smu_11_0_dpm_table *gfx_table =
1704                                 &dpm_context->dpm_tables.gfx_table;
1705         struct smu_11_0_dpm_table *mem_table =
1706                                 &dpm_context->dpm_tables.uclk_table;
1707         struct smu_11_0_dpm_table *soc_table =
1708                                 &dpm_context->dpm_tables.soc_table;
1709         struct smu_umd_pstate_table *pstate_table =
1710                                 &smu->pstate_table;
1711         struct amdgpu_device *adev = smu->adev;
1712         uint32_t sclk_freq;
1713
1714         pstate_table->gfxclk_pstate.min = gfx_table->min;
1715         switch (adev->ip_versions[MP1_HWIP][0]) {
1716         case IP_VERSION(11, 0, 0):
1717                 switch (adev->pdev->revision) {
1718                 case 0xf0: /* XTX */
1719                 case 0xc0:
1720                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1721                         break;
1722                 case 0xf1: /* XT */
1723                 case 0xc1:
1724                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1725                         break;
1726                 default: /* XL */
1727                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1728                         break;
1729                 }
1730                 break;
1731         case IP_VERSION(11, 0, 5):
1732                 switch (adev->pdev->revision) {
1733                 case 0xc7: /* XT */
1734                 case 0xf4:
1735                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1736                         break;
1737                 case 0xc1: /* XTM */
1738                 case 0xf2:
1739                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1740                         break;
1741                 case 0xc3: /* XLM */
1742                 case 0xf3:
1743                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1744                         break;
1745                 case 0xc5: /* XTX */
1746                 case 0xf6:
1747                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1748                         break;
1749                 default: /* XL */
1750                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1751                         break;
1752                 }
1753                 break;
1754         case IP_VERSION(11, 0, 9):
1755                 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1756                 break;
1757         default:
1758                 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1759                 break;
1760         }
1761         pstate_table->gfxclk_pstate.peak = sclk_freq;
1762
1763         pstate_table->uclk_pstate.min = mem_table->min;
1764         pstate_table->uclk_pstate.peak = mem_table->max;
1765
1766         pstate_table->socclk_pstate.min = soc_table->min;
1767         pstate_table->socclk_pstate.peak = soc_table->max;
1768
1769         if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1770             mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1771             soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1772                 pstate_table->gfxclk_pstate.standard =
1773                         NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1774                 pstate_table->uclk_pstate.standard =
1775                         NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1776                 pstate_table->socclk_pstate.standard =
1777                         NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1778         } else {
1779                 pstate_table->gfxclk_pstate.standard =
1780                         pstate_table->gfxclk_pstate.min;
1781                 pstate_table->uclk_pstate.standard =
1782                         pstate_table->uclk_pstate.min;
1783                 pstate_table->socclk_pstate.standard =
1784                         pstate_table->socclk_pstate.min;
1785         }
1786
1787         return 0;
1788 }
1789
1790 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1791                                                  enum smu_clk_type clk_type,
1792                                                  struct pp_clock_levels_with_latency *clocks)
1793 {
1794         int ret = 0, i = 0;
1795         uint32_t level_count = 0, freq = 0;
1796
1797         switch (clk_type) {
1798         case SMU_GFXCLK:
1799         case SMU_DCEFCLK:
1800         case SMU_SOCCLK:
1801         case SMU_MCLK:
1802         case SMU_UCLK:
1803                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1804                 if (ret)
1805                         return ret;
1806
1807                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1808                 clocks->num_levels = level_count;
1809
1810                 for (i = 0; i < level_count; i++) {
1811                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1812                         if (ret)
1813                                 return ret;
1814
1815                         clocks->data[i].clocks_in_khz = freq * 1000;
1816                         clocks->data[i].latency_in_us = 0;
1817                 }
1818                 break;
1819         default:
1820                 break;
1821         }
1822
1823         return ret;
1824 }
1825
1826 static int navi10_pre_display_config_changed(struct smu_context *smu)
1827 {
1828         int ret = 0;
1829         uint32_t max_freq = 0;
1830
1831         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1832         if (ret)
1833                 return ret;
1834
1835         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1836                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1837                 if (ret)
1838                         return ret;
1839                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1840                 if (ret)
1841                         return ret;
1842         }
1843
1844         return ret;
1845 }
1846
1847 static int navi10_display_config_changed(struct smu_context *smu)
1848 {
1849         int ret = 0;
1850
1851         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1852             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1853             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1854                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1855                                                   smu->display_config->num_display,
1856                                                   NULL);
1857                 if (ret)
1858                         return ret;
1859         }
1860
1861         return ret;
1862 }
1863
1864 static bool navi10_is_dpm_running(struct smu_context *smu)
1865 {
1866         int ret = 0;
1867         uint64_t feature_enabled;
1868
1869         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1870         if (ret)
1871                 return false;
1872
1873         return !!(feature_enabled & SMC_DPM_FEATURE);
1874 }
1875
1876 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1877                                     uint32_t *speed)
1878 {
1879         int ret = 0;
1880
1881         if (!speed)
1882                 return -EINVAL;
1883
1884         switch (smu_v11_0_get_fan_control_mode(smu)) {
1885         case AMD_FAN_CTRL_AUTO:
1886                 ret = navi10_get_smu_metrics_data(smu,
1887                                                   METRICS_CURR_FANSPEED,
1888                                                   speed);
1889                 break;
1890         default:
1891                 ret = smu_v11_0_get_fan_speed_rpm(smu,
1892                                                   speed);
1893                 break;
1894         }
1895
1896         return ret;
1897 }
1898
1899 static int navi10_get_fan_parameters(struct smu_context *smu)
1900 {
1901         PPTable_t *pptable = smu->smu_table.driver_pptable;
1902
1903         smu->fan_max_rpm = pptable->FanMaximumRpm;
1904
1905         return 0;
1906 }
1907
1908 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1909 {
1910         DpmActivityMonitorCoeffInt_t activity_monitor;
1911         uint32_t i, size = 0;
1912         int16_t workload_type = 0;
1913         static const char *title[] = {
1914                         "PROFILE_INDEX(NAME)",
1915                         "CLOCK_TYPE(NAME)",
1916                         "FPS",
1917                         "MinFreqType",
1918                         "MinActiveFreqType",
1919                         "MinActiveFreq",
1920                         "BoosterFreqType",
1921                         "BoosterFreq",
1922                         "PD_Data_limit_c",
1923                         "PD_Data_error_coeff",
1924                         "PD_Data_error_rate_coeff"};
1925         int result = 0;
1926
1927         if (!buf)
1928                 return -EINVAL;
1929
1930         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1931                         title[0], title[1], title[2], title[3], title[4], title[5],
1932                         title[6], title[7], title[8], title[9], title[10]);
1933
1934         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1935                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1936                 workload_type = smu_cmn_to_asic_specific_index(smu,
1937                                                                CMN2ASIC_MAPPING_WORKLOAD,
1938                                                                i);
1939                 if (workload_type < 0)
1940                         return -EINVAL;
1941
1942                 result = smu_cmn_update_table(smu,
1943                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1944                                           (void *)(&activity_monitor), false);
1945                 if (result) {
1946                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1947                         return result;
1948                 }
1949
1950                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1951                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1952
1953                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1954                         " ",
1955                         0,
1956                         "GFXCLK",
1957                         activity_monitor.Gfx_FPS,
1958                         activity_monitor.Gfx_MinFreqStep,
1959                         activity_monitor.Gfx_MinActiveFreqType,
1960                         activity_monitor.Gfx_MinActiveFreq,
1961                         activity_monitor.Gfx_BoosterFreqType,
1962                         activity_monitor.Gfx_BoosterFreq,
1963                         activity_monitor.Gfx_PD_Data_limit_c,
1964                         activity_monitor.Gfx_PD_Data_error_coeff,
1965                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1966
1967                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1968                         " ",
1969                         1,
1970                         "SOCCLK",
1971                         activity_monitor.Soc_FPS,
1972                         activity_monitor.Soc_MinFreqStep,
1973                         activity_monitor.Soc_MinActiveFreqType,
1974                         activity_monitor.Soc_MinActiveFreq,
1975                         activity_monitor.Soc_BoosterFreqType,
1976                         activity_monitor.Soc_BoosterFreq,
1977                         activity_monitor.Soc_PD_Data_limit_c,
1978                         activity_monitor.Soc_PD_Data_error_coeff,
1979                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1980
1981                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1982                         " ",
1983                         2,
1984                         "MEMLK",
1985                         activity_monitor.Mem_FPS,
1986                         activity_monitor.Mem_MinFreqStep,
1987                         activity_monitor.Mem_MinActiveFreqType,
1988                         activity_monitor.Mem_MinActiveFreq,
1989                         activity_monitor.Mem_BoosterFreqType,
1990                         activity_monitor.Mem_BoosterFreq,
1991                         activity_monitor.Mem_PD_Data_limit_c,
1992                         activity_monitor.Mem_PD_Data_error_coeff,
1993                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1994         }
1995
1996         return size;
1997 }
1998
1999 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
2000 {
2001         DpmActivityMonitorCoeffInt_t activity_monitor;
2002         int workload_type, ret = 0;
2003
2004         smu->power_profile_mode = input[size];
2005
2006         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
2007                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
2008                 return -EINVAL;
2009         }
2010
2011         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
2012
2013                 ret = smu_cmn_update_table(smu,
2014                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2015                                        (void *)(&activity_monitor), false);
2016                 if (ret) {
2017                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2018                         return ret;
2019                 }
2020
2021                 switch (input[0]) {
2022                 case 0: /* Gfxclk */
2023                         activity_monitor.Gfx_FPS = input[1];
2024                         activity_monitor.Gfx_MinFreqStep = input[2];
2025                         activity_monitor.Gfx_MinActiveFreqType = input[3];
2026                         activity_monitor.Gfx_MinActiveFreq = input[4];
2027                         activity_monitor.Gfx_BoosterFreqType = input[5];
2028                         activity_monitor.Gfx_BoosterFreq = input[6];
2029                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
2030                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
2031                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
2032                         break;
2033                 case 1: /* Socclk */
2034                         activity_monitor.Soc_FPS = input[1];
2035                         activity_monitor.Soc_MinFreqStep = input[2];
2036                         activity_monitor.Soc_MinActiveFreqType = input[3];
2037                         activity_monitor.Soc_MinActiveFreq = input[4];
2038                         activity_monitor.Soc_BoosterFreqType = input[5];
2039                         activity_monitor.Soc_BoosterFreq = input[6];
2040                         activity_monitor.Soc_PD_Data_limit_c = input[7];
2041                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
2042                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
2043                         break;
2044                 case 2: /* Memlk */
2045                         activity_monitor.Mem_FPS = input[1];
2046                         activity_monitor.Mem_MinFreqStep = input[2];
2047                         activity_monitor.Mem_MinActiveFreqType = input[3];
2048                         activity_monitor.Mem_MinActiveFreq = input[4];
2049                         activity_monitor.Mem_BoosterFreqType = input[5];
2050                         activity_monitor.Mem_BoosterFreq = input[6];
2051                         activity_monitor.Mem_PD_Data_limit_c = input[7];
2052                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
2053                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
2054                         break;
2055                 }
2056
2057                 ret = smu_cmn_update_table(smu,
2058                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2059                                        (void *)(&activity_monitor), true);
2060                 if (ret) {
2061                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2062                         return ret;
2063                 }
2064         }
2065
2066         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2067         workload_type = smu_cmn_to_asic_specific_index(smu,
2068                                                        CMN2ASIC_MAPPING_WORKLOAD,
2069                                                        smu->power_profile_mode);
2070         if (workload_type < 0)
2071                 return -EINVAL;
2072         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2073                                     1 << workload_type, NULL);
2074
2075         return ret;
2076 }
2077
2078 static int navi10_notify_smc_display_config(struct smu_context *smu)
2079 {
2080         struct smu_clocks min_clocks = {0};
2081         struct pp_display_clock_request clock_req;
2082         int ret = 0;
2083
2084         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2085         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2086         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2087
2088         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2089                 clock_req.clock_type = amd_pp_dcef_clock;
2090                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2091
2092                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
2093                 if (!ret) {
2094                         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2095                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2096                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
2097                                                                   min_clocks.dcef_clock_in_sr/100,
2098                                                                   NULL);
2099                                 if (ret) {
2100                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
2101                                         return ret;
2102                                 }
2103                         }
2104                 } else {
2105                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
2106                 }
2107         }
2108
2109         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2110                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
2111                 if (ret) {
2112                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
2113                         return ret;
2114                 }
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int navi10_set_watermarks_table(struct smu_context *smu,
2121                                        struct pp_smu_wm_range_sets *clock_ranges)
2122 {
2123         Watermarks_t *table = smu->smu_table.watermarks_table;
2124         int ret = 0;
2125         int i;
2126
2127         if (clock_ranges) {
2128                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
2129                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
2130                         return -EINVAL;
2131
2132                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
2133                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
2134                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
2135                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
2136                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
2137                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
2138                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
2139                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
2140                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
2141
2142                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
2143                                 clock_ranges->reader_wm_sets[i].wm_inst;
2144                 }
2145
2146                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
2147                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
2148                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
2149                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
2150                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
2151                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
2152                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
2153                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
2154                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
2155
2156                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
2157                                 clock_ranges->writer_wm_sets[i].wm_inst;
2158                 }
2159
2160                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
2161         }
2162
2163         /* pass data to smu controller */
2164         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2165              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2166                 ret = smu_cmn_write_watermarks_table(smu);
2167                 if (ret) {
2168                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
2169                         return ret;
2170                 }
2171                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2172         }
2173
2174         return 0;
2175 }
2176
2177 static int navi10_read_sensor(struct smu_context *smu,
2178                                  enum amd_pp_sensors sensor,
2179                                  void *data, uint32_t *size)
2180 {
2181         int ret = 0;
2182         struct smu_table_context *table_context = &smu->smu_table;
2183         PPTable_t *pptable = table_context->driver_pptable;
2184
2185         if (!data || !size)
2186                 return -EINVAL;
2187
2188         switch (sensor) {
2189         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
2190                 *(uint32_t *)data = pptable->FanMaximumRpm;
2191                 *size = 4;
2192                 break;
2193         case AMDGPU_PP_SENSOR_MEM_LOAD:
2194                 ret = navi1x_get_smu_metrics_data(smu,
2195                                                   METRICS_AVERAGE_MEMACTIVITY,
2196                                                   (uint32_t *)data);
2197                 *size = 4;
2198                 break;
2199         case AMDGPU_PP_SENSOR_GPU_LOAD:
2200                 ret = navi1x_get_smu_metrics_data(smu,
2201                                                   METRICS_AVERAGE_GFXACTIVITY,
2202                                                   (uint32_t *)data);
2203                 *size = 4;
2204                 break;
2205         case AMDGPU_PP_SENSOR_GPU_POWER:
2206                 ret = navi1x_get_smu_metrics_data(smu,
2207                                                   METRICS_AVERAGE_SOCKETPOWER,
2208                                                   (uint32_t *)data);
2209                 *size = 4;
2210                 break;
2211         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2212                 ret = navi1x_get_smu_metrics_data(smu,
2213                                                   METRICS_TEMPERATURE_HOTSPOT,
2214                                                   (uint32_t *)data);
2215                 *size = 4;
2216                 break;
2217         case AMDGPU_PP_SENSOR_EDGE_TEMP:
2218                 ret = navi1x_get_smu_metrics_data(smu,
2219                                                   METRICS_TEMPERATURE_EDGE,
2220                                                   (uint32_t *)data);
2221                 *size = 4;
2222                 break;
2223         case AMDGPU_PP_SENSOR_MEM_TEMP:
2224                 ret = navi1x_get_smu_metrics_data(smu,
2225                                                   METRICS_TEMPERATURE_MEM,
2226                                                   (uint32_t *)data);
2227                 *size = 4;
2228                 break;
2229         case AMDGPU_PP_SENSOR_GFX_MCLK:
2230                 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
2231                 *(uint32_t *)data *= 100;
2232                 *size = 4;
2233                 break;
2234         case AMDGPU_PP_SENSOR_GFX_SCLK:
2235                 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
2236                 *(uint32_t *)data *= 100;
2237                 *size = 4;
2238                 break;
2239         case AMDGPU_PP_SENSOR_VDDGFX:
2240                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2241                 *size = 4;
2242                 break;
2243         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2244         default:
2245                 ret = -EOPNOTSUPP;
2246                 break;
2247         }
2248
2249         return ret;
2250 }
2251
2252 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2253 {
2254         uint32_t num_discrete_levels = 0;
2255         uint16_t *dpm_levels = NULL;
2256         uint16_t i = 0;
2257         struct smu_table_context *table_context = &smu->smu_table;
2258         PPTable_t *driver_ppt = NULL;
2259
2260         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2261                 return -EINVAL;
2262
2263         driver_ppt = table_context->driver_pptable;
2264         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2265         dpm_levels = driver_ppt->FreqTableUclk;
2266
2267         if (num_discrete_levels == 0 || dpm_levels == NULL)
2268                 return -EINVAL;
2269
2270         *num_states = num_discrete_levels;
2271         for (i = 0; i < num_discrete_levels; i++) {
2272                 /* convert to khz */
2273                 *clocks_in_khz = (*dpm_levels) * 1000;
2274                 clocks_in_khz++;
2275                 dpm_levels++;
2276         }
2277
2278         return 0;
2279 }
2280
2281 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2282                                                 struct smu_temperature_range *range)
2283 {
2284         struct smu_table_context *table_context = &smu->smu_table;
2285         struct smu_11_0_powerplay_table *powerplay_table =
2286                                 table_context->power_play_table;
2287         PPTable_t *pptable = smu->smu_table.driver_pptable;
2288
2289         if (!range)
2290                 return -EINVAL;
2291
2292         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2293
2294         range->max = pptable->TedgeLimit *
2295                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2296         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2297                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2298         range->hotspot_crit_max = pptable->ThotspotLimit *
2299                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2300         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2301                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2302         range->mem_crit_max = pptable->TmemLimit *
2303                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2304         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2305                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2306         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2307
2308         return 0;
2309 }
2310
2311 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2312                                                 bool disable_memory_clock_switch)
2313 {
2314         int ret = 0;
2315         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2316                 (struct smu_11_0_max_sustainable_clocks *)
2317                         smu->smu_table.max_sustainable_clocks;
2318         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2319         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2320
2321         if (smu->disable_uclk_switch == disable_memory_clock_switch)
2322                 return 0;
2323
2324         if (disable_memory_clock_switch)
2325                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2326         else
2327                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2328
2329         if (!ret)
2330                 smu->disable_uclk_switch = disable_memory_clock_switch;
2331
2332         return ret;
2333 }
2334
2335 static int navi10_get_power_limit(struct smu_context *smu,
2336                                   uint32_t *current_power_limit,
2337                                   uint32_t *default_power_limit,
2338                                   uint32_t *max_power_limit)
2339 {
2340         struct smu_11_0_powerplay_table *powerplay_table =
2341                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2342         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2343         PPTable_t *pptable = smu->smu_table.driver_pptable;
2344         uint32_t power_limit, od_percent;
2345
2346         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2347                 /* the last hope to figure out the ppt limit */
2348                 if (!pptable) {
2349                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2350                         return -EINVAL;
2351                 }
2352                 power_limit =
2353                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2354         }
2355
2356         if (current_power_limit)
2357                 *current_power_limit = power_limit;
2358         if (default_power_limit)
2359                 *default_power_limit = power_limit;
2360
2361         if (max_power_limit) {
2362                 if (smu->od_enabled &&
2363                     navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2364                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2365
2366                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
2367
2368                         power_limit *= (100 + od_percent);
2369                         power_limit /= 100;
2370                 }
2371
2372                 *max_power_limit = power_limit;
2373         }
2374
2375         return 0;
2376 }
2377
2378 static int navi10_update_pcie_parameters(struct smu_context *smu,
2379                                      uint32_t pcie_gen_cap,
2380                                      uint32_t pcie_width_cap)
2381 {
2382         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2383         PPTable_t *pptable = smu->smu_table.driver_pptable;
2384         uint32_t smu_pcie_arg;
2385         int ret, i;
2386
2387         /* lclk dpm table setup */
2388         for (i = 0; i < MAX_PCIE_CONF; i++) {
2389                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2390                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2391         }
2392
2393         for (i = 0; i < NUM_LINK_LEVELS; i++) {
2394                 smu_pcie_arg = (i << 16) |
2395                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2396                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2397                                         pptable->PcieLaneCount[i] : pcie_width_cap);
2398                 ret = smu_cmn_send_smc_msg_with_param(smu,
2399                                           SMU_MSG_OverridePcieParameters,
2400                                           smu_pcie_arg,
2401                                           NULL);
2402
2403                 if (ret)
2404                         return ret;
2405
2406                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2407                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2408                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
2409                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2410         }
2411
2412         return 0;
2413 }
2414
2415 static inline void navi10_dump_od_table(struct smu_context *smu,
2416                                         OverDriveTable_t *od_table)
2417 {
2418         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2419         dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2420         dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2421         dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2422         dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2423         dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2424 }
2425
2426 static int navi10_od_setting_check_range(struct smu_context *smu,
2427                                          struct smu_11_0_overdrive_table *od_table,
2428                                          enum SMU_11_0_ODSETTING_ID setting,
2429                                          uint32_t value)
2430 {
2431         if (value < od_table->min[setting]) {
2432                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2433                 return -EINVAL;
2434         }
2435         if (value > od_table->max[setting]) {
2436                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2437                 return -EINVAL;
2438         }
2439         return 0;
2440 }
2441
2442 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2443                                                      uint16_t *voltage,
2444                                                      uint32_t freq)
2445 {
2446         uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2447         uint32_t value = 0;
2448         int ret;
2449
2450         ret = smu_cmn_send_smc_msg_with_param(smu,
2451                                           SMU_MSG_GetVoltageByDpm,
2452                                           param,
2453                                           &value);
2454         if (ret) {
2455                 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2456                 return ret;
2457         }
2458
2459         *voltage = (uint16_t)value;
2460
2461         return 0;
2462 }
2463
2464 static int navi10_baco_enter(struct smu_context *smu)
2465 {
2466         struct amdgpu_device *adev = smu->adev;
2467
2468         /*
2469          * This aims the case below:
2470          *   amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded
2471          *
2472          * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To
2473          * make that possible, PMFW needs to acknowledge the dstate transition
2474          * process for both gfx(function 0) and audio(function 1) function of
2475          * the ASIC.
2476          *
2477          * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the
2478          * device representing the audio function of the ASIC. And that means
2479          * even if the sound driver(snd_hda_intel) was not loaded yet, it's still
2480          * possible runpm suspend kicked on the ASIC. However without the dstate
2481          * transition notification from audio function, pmfw cannot handle the
2482          * BACO in/exit correctly. And that will cause driver hang on runpm
2483          * resuming.
2484          *
2485          * To address this, we revert to legacy message way(driver masters the
2486          * timing for BACO in/exit) on sound driver missing.
2487          */
2488         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2489                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2490         else
2491                 return smu_v11_0_baco_enter(smu);
2492 }
2493
2494 static int navi10_baco_exit(struct smu_context *smu)
2495 {
2496         struct amdgpu_device *adev = smu->adev;
2497
2498         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2499                 /* Wait for PMFW handling for the Dstate change */
2500                 msleep(10);
2501                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2502         } else {
2503                 return smu_v11_0_baco_exit(smu);
2504         }
2505 }
2506
2507 static int navi10_set_default_od_settings(struct smu_context *smu)
2508 {
2509         OverDriveTable_t *od_table =
2510                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2511         OverDriveTable_t *boot_od_table =
2512                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2513         OverDriveTable_t *user_od_table =
2514                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2515         int ret = 0;
2516
2517         /*
2518          * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2519          *   - either they already have the default OD settings got during cold bootup
2520          *   - or they have some user customized OD settings which cannot be overwritten
2521          */
2522         if (smu->adev->in_suspend)
2523                 return 0;
2524
2525         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false);
2526         if (ret) {
2527                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2528                 return ret;
2529         }
2530
2531         if (!boot_od_table->GfxclkVolt1) {
2532                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2533                                                                 &boot_od_table->GfxclkVolt1,
2534                                                                 boot_od_table->GfxclkFreq1);
2535                 if (ret)
2536                         return ret;
2537         }
2538
2539         if (!boot_od_table->GfxclkVolt2) {
2540                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2541                                                                 &boot_od_table->GfxclkVolt2,
2542                                                                 boot_od_table->GfxclkFreq2);
2543                 if (ret)
2544                         return ret;
2545         }
2546
2547         if (!boot_od_table->GfxclkVolt3) {
2548                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2549                                                                 &boot_od_table->GfxclkVolt3,
2550                                                                 boot_od_table->GfxclkFreq3);
2551                 if (ret)
2552                         return ret;
2553         }
2554
2555         navi10_dump_od_table(smu, boot_od_table);
2556
2557         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2558         memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2559
2560         return 0;
2561 }
2562
2563 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size)
2564 {
2565         int i;
2566         int ret = 0;
2567         struct smu_table_context *table_context = &smu->smu_table;
2568         OverDriveTable_t *od_table;
2569         struct smu_11_0_overdrive_table *od_settings;
2570         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2571         uint16_t *freq_ptr, *voltage_ptr;
2572         od_table = (OverDriveTable_t *)table_context->overdrive_table;
2573
2574         if (!smu->od_enabled) {
2575                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2576                 return -EINVAL;
2577         }
2578
2579         if (!smu->od_settings) {
2580                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2581                 return -ENOENT;
2582         }
2583
2584         od_settings = smu->od_settings;
2585
2586         switch (type) {
2587         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2588                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2589                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2590                         return -ENOTSUPP;
2591                 }
2592                 if (!table_context->overdrive_table) {
2593                         dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2594                         return -EINVAL;
2595                 }
2596                 for (i = 0; i < size; i += 2) {
2597                         if (i + 2 > size) {
2598                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2599                                 return -EINVAL;
2600                         }
2601                         switch (input[i]) {
2602                         case 0:
2603                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2604                                 freq_ptr = &od_table->GfxclkFmin;
2605                                 if (input[i + 1] > od_table->GfxclkFmax) {
2606                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2607                                                 input[i + 1],
2608                                                 od_table->GfxclkFmin);
2609                                         return -EINVAL;
2610                                 }
2611                                 break;
2612                         case 1:
2613                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2614                                 freq_ptr = &od_table->GfxclkFmax;
2615                                 if (input[i + 1] < od_table->GfxclkFmin) {
2616                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2617                                                 input[i + 1],
2618                                                 od_table->GfxclkFmax);
2619                                         return -EINVAL;
2620                                 }
2621                                 break;
2622                         default:
2623                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2624                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2625                                 return -EINVAL;
2626                         }
2627                         ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2628                         if (ret)
2629                                 return ret;
2630                         *freq_ptr = input[i + 1];
2631                 }
2632                 break;
2633         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2634                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2635                         dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2636                         return -ENOTSUPP;
2637                 }
2638                 if (size < 2) {
2639                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2640                         return -EINVAL;
2641                 }
2642                 if (input[0] != 1) {
2643                         dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2644                         dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2645                         return -EINVAL;
2646                 }
2647                 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2648                 if (ret)
2649                         return ret;
2650                 od_table->UclkFmax = input[1];
2651                 break;
2652         case PP_OD_RESTORE_DEFAULT_TABLE:
2653                 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2654                         dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2655                         return -EINVAL;
2656                 }
2657                 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2658                 break;
2659         case PP_OD_COMMIT_DPM_TABLE:
2660                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2661                         navi10_dump_od_table(smu, od_table);
2662                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2663                         if (ret) {
2664                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2665                                 return ret;
2666                         }
2667                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2668                         smu->user_dpm_profile.user_od = true;
2669
2670                         if (!memcmp(table_context->user_overdrive_table,
2671                                     table_context->boot_overdrive_table,
2672                                     sizeof(OverDriveTable_t)))
2673                                 smu->user_dpm_profile.user_od = false;
2674                 }
2675                 break;
2676         case PP_OD_EDIT_VDDC_CURVE:
2677                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2678                         dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2679                         return -ENOTSUPP;
2680                 }
2681                 if (size < 3) {
2682                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2683                         return -EINVAL;
2684                 }
2685                 if (!od_table) {
2686                         dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2687                         return -EINVAL;
2688                 }
2689
2690                 switch (input[0]) {
2691                 case 0:
2692                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2693                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2694                         freq_ptr = &od_table->GfxclkFreq1;
2695                         voltage_ptr = &od_table->GfxclkVolt1;
2696                         break;
2697                 case 1:
2698                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2699                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2700                         freq_ptr = &od_table->GfxclkFreq2;
2701                         voltage_ptr = &od_table->GfxclkVolt2;
2702                         break;
2703                 case 2:
2704                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2705                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2706                         freq_ptr = &od_table->GfxclkFreq3;
2707                         voltage_ptr = &od_table->GfxclkVolt3;
2708                         break;
2709                 default:
2710                         dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2711                         dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2712                         return -EINVAL;
2713                 }
2714                 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2715                 if (ret)
2716                         return ret;
2717                 // Allow setting zero to disable the OverDrive VDDC curve
2718                 if (input[2] != 0) {
2719                         ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2720                         if (ret)
2721                                 return ret;
2722                         *freq_ptr = input[1];
2723                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2724                         dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2725                 } else {
2726                         // If setting 0, disable all voltage curve settings
2727                         od_table->GfxclkVolt1 = 0;
2728                         od_table->GfxclkVolt2 = 0;
2729                         od_table->GfxclkVolt3 = 0;
2730                 }
2731                 navi10_dump_od_table(smu, od_table);
2732                 break;
2733         default:
2734                 return -ENOSYS;
2735         }
2736         return ret;
2737 }
2738
2739 static int navi10_run_btc(struct smu_context *smu)
2740 {
2741         int ret = 0;
2742
2743         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2744         if (ret)
2745                 dev_err(smu->adev->dev, "RunBtc failed!\n");
2746
2747         return ret;
2748 }
2749
2750 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2751 {
2752         struct amdgpu_device *adev = smu->adev;
2753
2754         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2755                 return false;
2756
2757         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) ||
2758             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5))
2759                 return true;
2760
2761         return false;
2762 }
2763
2764 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2765 {
2766         uint32_t uclk_count, uclk_min, uclk_max;
2767         int ret = 0;
2768
2769         /* This workaround can be applied only with uclk dpm enabled */
2770         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2771                 return 0;
2772
2773         ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2774         if (ret)
2775                 return ret;
2776
2777         ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2778         if (ret)
2779                 return ret;
2780
2781         /*
2782          * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2783          * This workaround is needed only when the max uclk frequency
2784          * not greater than that.
2785          */
2786         if (uclk_max > 0x2EE)
2787                 return 0;
2788
2789         ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2790         if (ret)
2791                 return ret;
2792
2793         /* Force UCLK out of the highest DPM */
2794         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2795         if (ret)
2796                 return ret;
2797
2798         /* Revert the UCLK Hardmax */
2799         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2800         if (ret)
2801                 return ret;
2802
2803         /*
2804          * In this case, SMU already disabled dummy pstate during enablement
2805          * of UCLK DPM, we have to re-enabled it.
2806          */
2807         return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2808 }
2809
2810 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2811 {
2812         struct smu_table_context *smu_table = &smu->smu_table;
2813         struct smu_table *dummy_read_table =
2814                                 &smu_table->dummy_read_1_table;
2815         char *dummy_table = dummy_read_table->cpu_addr;
2816         int ret = 0;
2817         uint32_t i;
2818
2819         for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2820                 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2821                 dummy_table += 0x1000;
2822                 memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2823                 dummy_table += 0x1000;
2824         }
2825
2826         amdgpu_asic_flush_hdp(smu->adev, NULL);
2827
2828         ret = smu_cmn_send_smc_msg_with_param(smu,
2829                                               SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2830                                               upper_32_bits(dummy_read_table->mc_address),
2831                                               NULL);
2832         if (ret)
2833                 return ret;
2834
2835         return smu_cmn_send_smc_msg_with_param(smu,
2836                                                SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2837                                                lower_32_bits(dummy_read_table->mc_address),
2838                                                NULL);
2839 }
2840
2841 static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2842 {
2843         struct amdgpu_device *adev = smu->adev;
2844         uint8_t umc_fw_greater_than_v136 = false;
2845         uint8_t umc_fw_disable_cdr = false;
2846         uint32_t pmfw_version;
2847         uint32_t param;
2848         int ret = 0;
2849
2850         if (!navi10_need_umc_cdr_workaround(smu))
2851                 return 0;
2852
2853         ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
2854         if (ret) {
2855                 dev_err(adev->dev, "Failed to get smu version!\n");
2856                 return ret;
2857         }
2858
2859         /*
2860          * The messages below are only supported by Navi10 42.53.0 and later
2861          * PMFWs and Navi14 53.29.0 and later PMFWs.
2862          * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2863          * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2864          * - PPSMC_MSG_GetUMCFWWA
2865          */
2866         if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
2867             ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
2868                 ret = smu_cmn_send_smc_msg_with_param(smu,
2869                                                       SMU_MSG_GET_UMC_FW_WA,
2870                                                       0,
2871                                                       &param);
2872                 if (ret)
2873                         return ret;
2874
2875                 /* First bit indicates if the UMC f/w is above v137 */
2876                 umc_fw_greater_than_v136 = param & 0x1;
2877
2878                 /* Second bit indicates if hybrid-cdr is disabled */
2879                 umc_fw_disable_cdr = param & 0x2;
2880
2881                 /* w/a only allowed if UMC f/w is <= 136 */
2882                 if (umc_fw_greater_than_v136)
2883                         return 0;
2884
2885                 if (umc_fw_disable_cdr) {
2886                         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
2887                                 return navi10_umc_hybrid_cdr_workaround(smu);
2888                 } else {
2889                         return navi10_set_dummy_pstates_table_location(smu);
2890                 }
2891         } else {
2892                 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
2893                         return navi10_umc_hybrid_cdr_workaround(smu);
2894         }
2895
2896         return 0;
2897 }
2898
2899 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2900                                              void **table)
2901 {
2902         struct smu_table_context *smu_table = &smu->smu_table;
2903         struct gpu_metrics_v1_3 *gpu_metrics =
2904                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2905         SmuMetrics_legacy_t metrics;
2906         int ret = 0;
2907
2908         ret = smu_cmn_get_metrics_table(smu,
2909                                         NULL,
2910                                         true);
2911         if (ret)
2912                 return ret;
2913
2914         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2915
2916         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2917
2918         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2919         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2920         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2921         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2922         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2923         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2924
2925         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2926         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2927
2928         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2929
2930         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2931         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2932         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2933
2934         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2935         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2936         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2937         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2938         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2939
2940         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2941         gpu_metrics->indep_throttle_status =
2942                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2943                                                            navi1x_throttler_map);
2944
2945         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2946
2947         gpu_metrics->pcie_link_width =
2948                         smu_v11_0_get_current_pcie_link_width(smu);
2949         gpu_metrics->pcie_link_speed =
2950                         smu_v11_0_get_current_pcie_link_speed(smu);
2951
2952         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2953
2954         if (metrics.CurrGfxVoltageOffset)
2955                 gpu_metrics->voltage_gfx =
2956                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2957         if (metrics.CurrMemVidOffset)
2958                 gpu_metrics->voltage_mem =
2959                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2960         if (metrics.CurrSocVoltageOffset)
2961                 gpu_metrics->voltage_soc =
2962                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2963
2964         *table = (void *)gpu_metrics;
2965
2966         return sizeof(struct gpu_metrics_v1_3);
2967 }
2968
2969 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2970                            struct i2c_msg *msg, int num_msgs)
2971 {
2972         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2973         struct amdgpu_device *adev = smu_i2c->adev;
2974         struct smu_context *smu = adev->powerplay.pp_handle;
2975         struct smu_table_context *smu_table = &smu->smu_table;
2976         struct smu_table *table = &smu_table->driver_table;
2977         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2978         int i, j, r, c;
2979         u16 dir;
2980
2981         if (!adev->pm.dpm_enabled)
2982                 return -EBUSY;
2983
2984         req = kzalloc(sizeof(*req), GFP_KERNEL);
2985         if (!req)
2986                 return -ENOMEM;
2987
2988         req->I2CcontrollerPort = smu_i2c->port;
2989         req->I2CSpeed = I2C_SPEED_FAST_400K;
2990         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2991         dir = msg[0].flags & I2C_M_RD;
2992
2993         for (c = i = 0; i < num_msgs; i++) {
2994                 for (j = 0; j < msg[i].len; j++, c++) {
2995                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2996
2997                         if (!(msg[i].flags & I2C_M_RD)) {
2998                                 /* write */
2999                                 cmd->Cmd = I2C_CMD_WRITE;
3000                                 cmd->RegisterAddr = msg[i].buf[j];
3001                         }
3002
3003                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
3004                                 /* The direction changes.
3005                                  */
3006                                 dir = msg[i].flags & I2C_M_RD;
3007                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3008                         }
3009
3010                         req->NumCmds++;
3011
3012                         /*
3013                          * Insert STOP if we are at the last byte of either last
3014                          * message for the transaction or the client explicitly
3015                          * requires a STOP at this particular message.
3016                          */
3017                         if ((j == msg[i].len - 1) &&
3018                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3019                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3020                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3021                         }
3022                 }
3023         }
3024         mutex_lock(&adev->pm.mutex);
3025         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3026         if (r)
3027                 goto fail;
3028
3029         for (c = i = 0; i < num_msgs; i++) {
3030                 if (!(msg[i].flags & I2C_M_RD)) {
3031                         c += msg[i].len;
3032                         continue;
3033                 }
3034                 for (j = 0; j < msg[i].len; j++, c++) {
3035                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3036
3037                         msg[i].buf[j] = cmd->Data;
3038                 }
3039         }
3040         r = num_msgs;
3041 fail:
3042         mutex_unlock(&adev->pm.mutex);
3043         kfree(req);
3044         return r;
3045 }
3046
3047 static u32 navi10_i2c_func(struct i2c_adapter *adap)
3048 {
3049         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3050 }
3051
3052
3053 static const struct i2c_algorithm navi10_i2c_algo = {
3054         .master_xfer = navi10_i2c_xfer,
3055         .functionality = navi10_i2c_func,
3056 };
3057
3058 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
3059         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3060         .max_read_len  = MAX_SW_I2C_COMMANDS,
3061         .max_write_len = MAX_SW_I2C_COMMANDS,
3062         .max_comb_1st_msg_len = 2,
3063         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3064 };
3065
3066 static int navi10_i2c_control_init(struct smu_context *smu)
3067 {
3068         struct amdgpu_device *adev = smu->adev;
3069         int res, i;
3070
3071         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3072                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3073                 struct i2c_adapter *control = &smu_i2c->adapter;
3074
3075                 smu_i2c->adev = adev;
3076                 smu_i2c->port = i;
3077                 mutex_init(&smu_i2c->mutex);
3078                 control->owner = THIS_MODULE;
3079                 control->class = I2C_CLASS_HWMON;
3080                 control->dev.parent = &adev->pdev->dev;
3081                 control->algo = &navi10_i2c_algo;
3082                 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3083                 control->quirks = &navi10_i2c_control_quirks;
3084                 i2c_set_adapdata(control, smu_i2c);
3085
3086                 res = i2c_add_adapter(control);
3087                 if (res) {
3088                         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3089                         goto Out_err;
3090                 }
3091         }
3092
3093         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3094         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3095
3096         return 0;
3097 Out_err:
3098         for ( ; i >= 0; i--) {
3099                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3100                 struct i2c_adapter *control = &smu_i2c->adapter;
3101
3102                 i2c_del_adapter(control);
3103         }
3104         return res;
3105 }
3106
3107 static void navi10_i2c_control_fini(struct smu_context *smu)
3108 {
3109         struct amdgpu_device *adev = smu->adev;
3110         int i;
3111
3112         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3113                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3114                 struct i2c_adapter *control = &smu_i2c->adapter;
3115
3116                 i2c_del_adapter(control);
3117         }
3118         adev->pm.ras_eeprom_i2c_bus = NULL;
3119         adev->pm.fru_eeprom_i2c_bus = NULL;
3120 }
3121
3122 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
3123                                       void **table)
3124 {
3125         struct smu_table_context *smu_table = &smu->smu_table;
3126         struct gpu_metrics_v1_3 *gpu_metrics =
3127                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3128         SmuMetrics_t metrics;
3129         int ret = 0;
3130
3131         ret = smu_cmn_get_metrics_table(smu,
3132                                         NULL,
3133                                         true);
3134         if (ret)
3135                 return ret;
3136
3137         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
3138
3139         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3140
3141         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3142         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3143         gpu_metrics->temperature_mem = metrics.TemperatureMem;
3144         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3145         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3146         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3147
3148         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3149         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3150
3151         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3152
3153         if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3154                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3155         else
3156                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3157
3158         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3159         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3160
3161         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3162         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3163         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3164         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3165         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3166
3167         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3168         gpu_metrics->indep_throttle_status =
3169                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3170                                                            navi1x_throttler_map);
3171
3172         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3173
3174         gpu_metrics->pcie_link_width = metrics.PcieWidth;
3175         gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3176
3177         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3178
3179         if (metrics.CurrGfxVoltageOffset)
3180                 gpu_metrics->voltage_gfx =
3181                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3182         if (metrics.CurrMemVidOffset)
3183                 gpu_metrics->voltage_mem =
3184                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3185         if (metrics.CurrSocVoltageOffset)
3186                 gpu_metrics->voltage_soc =
3187                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3188
3189         *table = (void *)gpu_metrics;
3190
3191         return sizeof(struct gpu_metrics_v1_3);
3192 }
3193
3194 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
3195                                              void **table)
3196 {
3197         struct smu_table_context *smu_table = &smu->smu_table;
3198         struct gpu_metrics_v1_3 *gpu_metrics =
3199                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3200         SmuMetrics_NV12_legacy_t metrics;
3201         int ret = 0;
3202
3203         ret = smu_cmn_get_metrics_table(smu,
3204                                         NULL,
3205                                         true);
3206         if (ret)
3207                 return ret;
3208
3209         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
3210
3211         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3212
3213         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3214         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3215         gpu_metrics->temperature_mem = metrics.TemperatureMem;
3216         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3217         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3218         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3219
3220         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3221         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3222
3223         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3224
3225         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
3226         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3227         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
3228
3229         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3230         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3231         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3232         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3233
3234         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3235         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3236         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3237         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3238         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3239
3240         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3241         gpu_metrics->indep_throttle_status =
3242                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3243                                                            navi1x_throttler_map);
3244
3245         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3246
3247         gpu_metrics->pcie_link_width =
3248                         smu_v11_0_get_current_pcie_link_width(smu);
3249         gpu_metrics->pcie_link_speed =
3250                         smu_v11_0_get_current_pcie_link_speed(smu);
3251
3252         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3253
3254         if (metrics.CurrGfxVoltageOffset)
3255                 gpu_metrics->voltage_gfx =
3256                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3257         if (metrics.CurrMemVidOffset)
3258                 gpu_metrics->voltage_mem =
3259                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3260         if (metrics.CurrSocVoltageOffset)
3261                 gpu_metrics->voltage_soc =
3262                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3263
3264         *table = (void *)gpu_metrics;
3265
3266         return sizeof(struct gpu_metrics_v1_3);
3267 }
3268
3269 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
3270                                       void **table)
3271 {
3272         struct smu_table_context *smu_table = &smu->smu_table;
3273         struct gpu_metrics_v1_3 *gpu_metrics =
3274                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3275         SmuMetrics_NV12_t metrics;
3276         int ret = 0;
3277
3278         ret = smu_cmn_get_metrics_table(smu,
3279                                         NULL,
3280                                         true);
3281         if (ret)
3282                 return ret;
3283
3284         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
3285
3286         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3287
3288         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3289         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3290         gpu_metrics->temperature_mem = metrics.TemperatureMem;
3291         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3292         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3293         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3294
3295         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3296         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3297
3298         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3299
3300         if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3301                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3302         else
3303                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3304
3305         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3306         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3307
3308         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3309         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3310         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3311         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3312
3313         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3314         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3315         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3316         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3317         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3318
3319         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3320         gpu_metrics->indep_throttle_status =
3321                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3322                                                            navi1x_throttler_map);
3323
3324         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3325
3326         gpu_metrics->pcie_link_width = metrics.PcieWidth;
3327         gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3328
3329         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3330
3331         if (metrics.CurrGfxVoltageOffset)
3332                 gpu_metrics->voltage_gfx =
3333                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3334         if (metrics.CurrMemVidOffset)
3335                 gpu_metrics->voltage_mem =
3336                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3337         if (metrics.CurrSocVoltageOffset)
3338                 gpu_metrics->voltage_soc =
3339                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3340
3341         *table = (void *)gpu_metrics;
3342
3343         return sizeof(struct gpu_metrics_v1_3);
3344 }
3345
3346 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
3347                                       void **table)
3348 {
3349         struct amdgpu_device *adev = smu->adev;
3350         uint32_t smu_version;
3351         int ret = 0;
3352
3353         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3354         if (ret) {
3355                 dev_err(adev->dev, "Failed to get smu version!\n");
3356                 return ret;
3357         }
3358
3359         switch (adev->ip_versions[MP1_HWIP][0]) {
3360         case IP_VERSION(11, 0, 9):
3361                 if (smu_version > 0x00341C00)
3362                         ret = navi12_get_gpu_metrics(smu, table);
3363                 else
3364                         ret = navi12_get_legacy_gpu_metrics(smu, table);
3365                 break;
3366         case IP_VERSION(11, 0, 0):
3367         case IP_VERSION(11, 0, 5):
3368         default:
3369                 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
3370                       ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
3371                         ret = navi10_get_gpu_metrics(smu, table);
3372                 else
3373                         ret = navi10_get_legacy_gpu_metrics(smu, table);
3374                 break;
3375         }
3376
3377         return ret;
3378 }
3379
3380 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
3381 {
3382         struct smu_table_context *table_context = &smu->smu_table;
3383         PPTable_t *smc_pptable = table_context->driver_pptable;
3384         struct amdgpu_device *adev = smu->adev;
3385         uint32_t param = 0;
3386
3387         /* Navi12 does not support this */
3388         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))
3389                 return 0;
3390
3391         /*
3392          * Skip the MGpuFanBoost setting for those ASICs
3393          * which do not support it
3394          */
3395         if (!smc_pptable->MGpuFanBoostLimitRpm)
3396                 return 0;
3397
3398         /* Workaround for WS SKU */
3399         if (adev->pdev->device == 0x7312 &&
3400             adev->pdev->revision == 0)
3401                 param = 0xD188;
3402
3403         return smu_cmn_send_smc_msg_with_param(smu,
3404                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
3405                                                param,
3406                                                NULL);
3407 }
3408
3409 static int navi10_post_smu_init(struct smu_context *smu)
3410 {
3411         struct amdgpu_device *adev = smu->adev;
3412         int ret = 0;
3413
3414         if (amdgpu_sriov_vf(adev))
3415                 return 0;
3416
3417         ret = navi10_run_umc_cdr_workaround(smu);
3418         if (ret)
3419                 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
3420
3421         return ret;
3422 }
3423
3424 static int navi10_get_default_config_table_settings(struct smu_context *smu,
3425                                                     struct config_table_setting *table)
3426 {
3427         if (!table)
3428                 return -EINVAL;
3429
3430         table->gfxclk_average_tau = 10;
3431         table->socclk_average_tau = 10;
3432         table->uclk_average_tau = 10;
3433         table->gfx_activity_average_tau = 10;
3434         table->mem_activity_average_tau = 10;
3435         table->socket_power_average_tau = 10;
3436
3437         return 0;
3438 }
3439
3440 static int navi10_set_config_table(struct smu_context *smu,
3441                                    struct config_table_setting *table)
3442 {
3443         DriverSmuConfig_t driver_smu_config_table;
3444
3445         if (!table)
3446                 return -EINVAL;
3447
3448         memset(&driver_smu_config_table,
3449                0,
3450                sizeof(driver_smu_config_table));
3451
3452         driver_smu_config_table.GfxclkAverageLpfTau =
3453                                 table->gfxclk_average_tau;
3454         driver_smu_config_table.SocclkAverageLpfTau =
3455                                 table->socclk_average_tau;
3456         driver_smu_config_table.UclkAverageLpfTau =
3457                                 table->uclk_average_tau;
3458         driver_smu_config_table.GfxActivityLpfTau =
3459                                 table->gfx_activity_average_tau;
3460         driver_smu_config_table.UclkActivityLpfTau =
3461                                 table->mem_activity_average_tau;
3462         driver_smu_config_table.SocketPowerLpfTau =
3463                                 table->socket_power_average_tau;
3464
3465         return smu_cmn_update_table(smu,
3466                                     SMU_TABLE_DRIVER_SMU_CONFIG,
3467                                     0,
3468                                     (void *)&driver_smu_config_table,
3469                                     true);
3470 }
3471
3472 static const struct pptable_funcs navi10_ppt_funcs = {
3473         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3474         .set_default_dpm_table = navi10_set_default_dpm_table,
3475         .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
3476         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
3477         .i2c_init = navi10_i2c_control_init,
3478         .i2c_fini = navi10_i2c_control_fini,
3479         .print_clk_levels = navi10_print_clk_levels,
3480         .emit_clk_levels = navi10_emit_clk_levels,
3481         .force_clk_levels = navi10_force_clk_levels,
3482         .populate_umd_state_clk = navi10_populate_umd_state_clk,
3483         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
3484         .pre_display_config_changed = navi10_pre_display_config_changed,
3485         .display_config_changed = navi10_display_config_changed,
3486         .notify_smc_display_config = navi10_notify_smc_display_config,
3487         .is_dpm_running = navi10_is_dpm_running,
3488         .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3489         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
3490         .get_power_profile_mode = navi10_get_power_profile_mode,
3491         .set_power_profile_mode = navi10_set_power_profile_mode,
3492         .set_watermarks_table = navi10_set_watermarks_table,
3493         .read_sensor = navi10_read_sensor,
3494         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
3495         .set_performance_level = smu_v11_0_set_performance_level,
3496         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
3497         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
3498         .get_power_limit = navi10_get_power_limit,
3499         .update_pcie_parameters = navi10_update_pcie_parameters,
3500         .init_microcode = smu_v11_0_init_microcode,
3501         .load_microcode = smu_v11_0_load_microcode,
3502         .fini_microcode = smu_v11_0_fini_microcode,
3503         .init_smc_tables = navi10_init_smc_tables,
3504         .fini_smc_tables = smu_v11_0_fini_smc_tables,
3505         .init_power = smu_v11_0_init_power,
3506         .fini_power = smu_v11_0_fini_power,
3507         .check_fw_status = smu_v11_0_check_fw_status,
3508         .setup_pptable = navi10_setup_pptable,
3509         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3510         .check_fw_version = smu_v11_0_check_fw_version,
3511         .write_pptable = smu_cmn_write_pptable,
3512         .set_driver_table_location = smu_v11_0_set_driver_table_location,
3513         .set_tool_table_location = smu_v11_0_set_tool_table_location,
3514         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3515         .system_features_control = smu_v11_0_system_features_control,
3516         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3517         .send_smc_msg = smu_cmn_send_smc_msg,
3518         .init_display_count = smu_v11_0_init_display_count,
3519         .set_allowed_mask = smu_v11_0_set_allowed_mask,
3520         .get_enabled_mask = smu_cmn_get_enabled_mask,
3521         .feature_is_enabled = smu_cmn_feature_is_enabled,
3522         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3523         .notify_display_change = smu_v11_0_notify_display_change,
3524         .set_power_limit = smu_v11_0_set_power_limit,
3525         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3526         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3527         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3528         .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3529         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3530         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3531         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3532         .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3533         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3534         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3535         .gfx_off_control = smu_v11_0_gfx_off_control,
3536         .register_irq_handler = smu_v11_0_register_irq_handler,
3537         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3538         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3539         .baco_is_support = smu_v11_0_baco_is_support,
3540         .baco_get_state = smu_v11_0_baco_get_state,
3541         .baco_set_state = smu_v11_0_baco_set_state,
3542         .baco_enter = navi10_baco_enter,
3543         .baco_exit = navi10_baco_exit,
3544         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3545         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3546         .set_default_od_settings = navi10_set_default_od_settings,
3547         .od_edit_dpm_table = navi10_od_edit_dpm_table,
3548         .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3549         .run_btc = navi10_run_btc,
3550         .set_power_source = smu_v11_0_set_power_source,
3551         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3552         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3553         .get_gpu_metrics = navi1x_get_gpu_metrics,
3554         .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3555         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3556         .deep_sleep_control = smu_v11_0_deep_sleep_control,
3557         .get_fan_parameters = navi10_get_fan_parameters,
3558         .post_init = navi10_post_smu_init,
3559         .interrupt_work = smu_v11_0_interrupt_work,
3560         .set_mp1_state = smu_cmn_set_mp1_state,
3561         .get_default_config_table_settings = navi10_get_default_config_table_settings,
3562         .set_config_table = navi10_set_config_table,
3563 };
3564
3565 void navi10_set_ppt_funcs(struct smu_context *smu)
3566 {
3567         smu->ppt_funcs = &navi10_ppt_funcs;
3568         smu->message_map = navi10_message_map;
3569         smu->clock_map = navi10_clk_map;
3570         smu->feature_map = navi10_feature_mask_map;
3571         smu->table_map = navi10_table_map;
3572         smu->pwr_src_map = navi10_pwr_src_map;
3573         smu->workload_map = navi10_workload_map;
3574         smu_v11_0_set_smu_mailbox_registers(smu);
3575 }