drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_arcturus.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "arcturus_ppt.h"
  38 #include "smu_v11_0_pptable.h"
  39 #include "arcturus_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/i2c.h>
  46 #include <linux/pci.h>
  47 #include "amdgpu_ras.h"
  48 #include "smu_cmn.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  63         [smu_feature] = {1, (arcturus_feature)}
  64
  65 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  66 #define SMU_FEATURES_LOW_SHIFT       0
  67 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  68 #define SMU_FEATURES_HIGH_SHIFT      32
  69
  70 #define SMC_DPM_FEATURE ( \
  71         FEATURE_DPM_PREFETCHER_MASK | \
  72         FEATURE_DPM_GFXCLK_MASK | \
  73         FEATURE_DPM_UCLK_MASK | \
  74         FEATURE_DPM_SOCCLK_MASK | \
  75         FEATURE_DPM_MP0CLK_MASK | \
  76         FEATURE_DPM_FCLK_MASK | \
  77         FEATURE_DPM_XGMI_MASK)
  78
  79 /* possible frequency drift (1Mhz) */
  80 #define EPSILON                         1
  81
  82 #define smnPCIE_ESM_CTRL                        0x111003D0
  83
  84 #define mmCG_FDO_CTRL0_ARCT                     0x8B
  85 #define mmCG_FDO_CTRL0_ARCT_BASE_IDX            0
  86
  87 #define mmCG_FDO_CTRL1_ARCT                     0x8C
  88 #define mmCG_FDO_CTRL1_ARCT_BASE_IDX            0
  89
  90 #define mmCG_FDO_CTRL2_ARCT                     0x8D
  91 #define mmCG_FDO_CTRL2_ARCT_BASE_IDX            0
  92
  93 #define mmCG_TACH_CTRL_ARCT                     0x8E
  94 #define mmCG_TACH_CTRL_ARCT_BASE_IDX            0
  95
  96 #define mmCG_TACH_STATUS_ARCT                   0x8F
  97 #define mmCG_TACH_STATUS_ARCT_BASE_IDX          0
  98
  99 #define mmCG_THERMAL_STATUS_ARCT                0x90
 100 #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX       0
 101
 102 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
 103         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
 104         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
 105         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
 106         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
 107         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
 108         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
 109         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
 110         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
 111         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
 112         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
 113         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
 114         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
 115         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
 116         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
 117         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 118         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 119         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 120         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 121         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 122         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 123         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 124         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 125         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 126         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 127         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 128         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 129         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 130         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 131         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 132         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 133         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 134         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 135         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 136         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 137         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 138         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 139         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 140         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 141         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 142         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 143         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 144         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 145         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 146         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 147         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 148         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 149         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 150         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 151         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 152         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 153         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 154         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 155         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 156         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 157         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 158         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 159         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 160         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 161         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 162         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 163         MSG_MAP(LightSBR,                            PPSMC_MSG_LightSBR,                        0),
 164 };
 165
 166 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 167         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 168         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 169         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 170         CLK_MAP(FCLK, PPCLK_FCLK),
 171         CLK_MAP(UCLK, PPCLK_UCLK),
 172         CLK_MAP(MCLK, PPCLK_UCLK),
 173         CLK_MAP(DCLK, PPCLK_DCLK),
 174         CLK_MAP(VCLK, PPCLK_VCLK),
 175 };
 176
 177 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 178         FEA_MAP(DPM_PREFETCHER),
 179         FEA_MAP(DPM_GFXCLK),
 180         FEA_MAP(DPM_UCLK),
 181         FEA_MAP(DPM_SOCCLK),
 182         FEA_MAP(DPM_FCLK),
 183         FEA_MAP(DPM_MP0CLK),
 184         FEA_MAP(DPM_XGMI),
 185         FEA_MAP(DS_GFXCLK),
 186         FEA_MAP(DS_SOCCLK),
 187         FEA_MAP(DS_LCLK),
 188         FEA_MAP(DS_FCLK),
 189         FEA_MAP(DS_UCLK),
 190         FEA_MAP(GFX_ULV),
 191         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
 192         FEA_MAP(RSMU_SMN_CG),
 193         FEA_MAP(WAFL_CG),
 194         FEA_MAP(PPT),
 195         FEA_MAP(TDC),
 196         FEA_MAP(APCC_PLUS),
 197         FEA_MAP(VR0HOT),
 198         FEA_MAP(VR1HOT),
 199         FEA_MAP(FW_CTF),
 200         FEA_MAP(FAN_CONTROL),
 201         FEA_MAP(THERMAL),
 202         FEA_MAP(OUT_OF_BAND_MONITOR),
 203         FEA_MAP(TEMP_DEPENDENT_VMIN),
 204 };
 205
 206 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 207         TAB_MAP(PPTABLE),
 208         TAB_MAP(AVFS),
 209         TAB_MAP(AVFS_PSM_DEBUG),
 210         TAB_MAP(AVFS_FUSE_OVERRIDE),
 211         TAB_MAP(PMSTATUSLOG),
 212         TAB_MAP(SMU_METRICS),
 213         TAB_MAP(DRIVER_SMU_CONFIG),
 214         TAB_MAP(OVERDRIVE),
 215         TAB_MAP(I2C_COMMANDS),
 216         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 217 };
 218
 219 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 220         PWR_MAP(AC),
 221         PWR_MAP(DC),
 222 };
 223
 224 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 225         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 226         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 227         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 228         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 229         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 230 };
 231
 232 static const uint8_t arcturus_throttler_map[] = {
 233         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 234         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 235         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 236         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 237         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 238         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 239         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 240         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 241         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 242         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 243         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 244         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 245         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 246         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 247         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 248         [THROTTLER_VRHOT0_BIT]          = (SMU_THROTTLER_VRHOT0_BIT),
 249         [THROTTLER_VRHOT1_BIT]          = (SMU_THROTTLER_VRHOT1_BIT),
 250 };
 251
 252 static int arcturus_tables_init(struct smu_context *smu)
 253 {
 254         struct smu_table_context *smu_table = &smu->smu_table;
 255         struct smu_table *tables = smu_table->tables;
 256
 257         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 258                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 259
 260         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 261                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 262
 263         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 264                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 265
 266         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 267                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 268
 269         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 270                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 271                        AMDGPU_GEM_DOMAIN_VRAM);
 272
 273         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 274         if (!smu_table->metrics_table)
 275                 return -ENOMEM;
 276         smu_table->metrics_time = 0;
 277
 278         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 279         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 280         if (!smu_table->gpu_metrics_table) {
 281                 kfree(smu_table->metrics_table);
 282                 return -ENOMEM;
 283         }
 284
 285         return 0;
 286 }
 287
 288 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 289 {
 290         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 291
 292         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 293                                        GFP_KERNEL);
 294         if (!smu_dpm->dpm_context)
 295                 return -ENOMEM;
 296         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 297
 298         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 299                                        GFP_KERNEL);
 300         if (!smu_dpm->dpm_current_power_state)
 301                 return -ENOMEM;
 302
 303         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 304                                        GFP_KERNEL);
 305         if (!smu_dpm->dpm_request_power_state)
 306                 return -ENOMEM;
 307
 308         return 0;
 309 }
 310
 311 static int arcturus_init_smc_tables(struct smu_context *smu)
 312 {
 313         int ret = 0;
 314
 315         ret = arcturus_tables_init(smu);
 316         if (ret)
 317                 return ret;
 318
 319         ret = arcturus_allocate_dpm_context(smu);
 320         if (ret)
 321                 return ret;
 322
 323         return smu_v11_0_init_smc_tables(smu);
 324 }
 325
 326 static int
 327 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 328                                   uint32_t *feature_mask, uint32_t num)
 329 {
 330         if (num > 2)
 331                 return -EINVAL;
 332
 333         /* pptable will handle the features to enable */
 334         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 335
 336         return 0;
 337 }
 338
 339 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 340 {
 341         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 342         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 343         struct smu_11_0_dpm_table *dpm_table = NULL;
 344         int ret = 0;
 345
 346         /* socclk dpm table setup */
 347         dpm_table = &dpm_context->dpm_tables.soc_table;
 348         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 349                 ret = smu_v11_0_set_single_dpm_table(smu,
 350                                                      SMU_SOCCLK,
 351                                                      dpm_table);
 352                 if (ret)
 353                         return ret;
 354                 dpm_table->is_fine_grained =
 355                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 356         } else {
 357                 dpm_table->count = 1;
 358                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 359                 dpm_table->dpm_levels[0].enabled = true;
 360                 dpm_table->min = dpm_table->dpm_levels[0].value;
 361                 dpm_table->max = dpm_table->dpm_levels[0].value;
 362         }
 363
 364         /* gfxclk dpm table setup */
 365         dpm_table = &dpm_context->dpm_tables.gfx_table;
 366         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 367                 ret = smu_v11_0_set_single_dpm_table(smu,
 368                                                      SMU_GFXCLK,
 369                                                      dpm_table);
 370                 if (ret)
 371                         return ret;
 372                 dpm_table->is_fine_grained =
 373                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 374         } else {
 375                 dpm_table->count = 1;
 376                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 377                 dpm_table->dpm_levels[0].enabled = true;
 378                 dpm_table->min = dpm_table->dpm_levels[0].value;
 379                 dpm_table->max = dpm_table->dpm_levels[0].value;
 380         }
 381
 382         /* memclk dpm table setup */
 383         dpm_table = &dpm_context->dpm_tables.uclk_table;
 384         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 385                 ret = smu_v11_0_set_single_dpm_table(smu,
 386                                                      SMU_UCLK,
 387                                                      dpm_table);
 388                 if (ret)
 389                         return ret;
 390                 dpm_table->is_fine_grained =
 391                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 392         } else {
 393                 dpm_table->count = 1;
 394                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 395                 dpm_table->dpm_levels[0].enabled = true;
 396                 dpm_table->min = dpm_table->dpm_levels[0].value;
 397                 dpm_table->max = dpm_table->dpm_levels[0].value;
 398         }
 399
 400         /* fclk dpm table setup */
 401         dpm_table = &dpm_context->dpm_tables.fclk_table;
 402         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 403                 ret = smu_v11_0_set_single_dpm_table(smu,
 404                                                      SMU_FCLK,
 405                                                      dpm_table);
 406                 if (ret)
 407                         return ret;
 408                 dpm_table->is_fine_grained =
 409                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 410         } else {
 411                 dpm_table->count = 1;
 412                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 413                 dpm_table->dpm_levels[0].enabled = true;
 414                 dpm_table->min = dpm_table->dpm_levels[0].value;
 415                 dpm_table->max = dpm_table->dpm_levels[0].value;
 416         }
 417
 418         return 0;
 419 }
 420
 421 static void arcturus_check_bxco_support(struct smu_context *smu)
 422 {
 423         struct smu_table_context *table_context = &smu->smu_table;
 424         struct smu_11_0_powerplay_table *powerplay_table =
 425                 table_context->power_play_table;
 426         struct smu_baco_context *smu_baco = &smu->smu_baco;
 427         struct amdgpu_device *adev = smu->adev;
 428         uint32_t val;
 429
 430         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 431             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 432                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 433                 smu_baco->platform_support =
 434                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 435                                                                         false;
 436         }
 437 }
 438
 439 static int arcturus_check_powerplay_table(struct smu_context *smu)
 440 {
 441         struct smu_table_context *table_context = &smu->smu_table;
 442         struct smu_11_0_powerplay_table *powerplay_table =
 443                 table_context->power_play_table;
 444
 445         arcturus_check_bxco_support(smu);
 446
 447         table_context->thermal_controller_type =
 448                 powerplay_table->thermal_controller_type;
 449
 450         return 0;
 451 }
 452
 453 static int arcturus_store_powerplay_table(struct smu_context *smu)
 454 {
 455         struct smu_table_context *table_context = &smu->smu_table;
 456         struct smu_11_0_powerplay_table *powerplay_table =
 457                 table_context->power_play_table;
 458
 459         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 460                sizeof(PPTable_t));
 461
 462         return 0;
 463 }
 464
 465 static int arcturus_append_powerplay_table(struct smu_context *smu)
 466 {
 467         struct smu_table_context *table_context = &smu->smu_table;
 468         PPTable_t *smc_pptable = table_context->driver_pptable;
 469         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 470         int index, ret;
 471
 472         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 473                                            smc_dpm_info);
 474
 475         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 476                                       (uint8_t **)&smc_dpm_table);
 477         if (ret)
 478                 return ret;
 479
 480         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 481                         smc_dpm_table->table_header.format_revision,
 482                         smc_dpm_table->table_header.content_revision);
 483
 484         if ((smc_dpm_table->table_header.format_revision == 4) &&
 485             (smc_dpm_table->table_header.content_revision == 6))
 486                 smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved,
 487                                     smc_dpm_table, maxvoltagestepgfx);
 488         return 0;
 489 }
 490
 491 static int arcturus_setup_pptable(struct smu_context *smu)
 492 {
 493         int ret = 0;
 494
 495         ret = smu_v11_0_setup_pptable(smu);
 496         if (ret)
 497                 return ret;
 498
 499         ret = arcturus_store_powerplay_table(smu);
 500         if (ret)
 501                 return ret;
 502
 503         ret = arcturus_append_powerplay_table(smu);
 504         if (ret)
 505                 return ret;
 506
 507         ret = arcturus_check_powerplay_table(smu);
 508         if (ret)
 509                 return ret;
 510
 511         return ret;
 512 }
 513
 514 static int arcturus_run_btc(struct smu_context *smu)
 515 {
 516         int ret = 0;
 517
 518         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 519         if (ret) {
 520                 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 521                 return ret;
 522         }
 523
 524         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 525 }
 526
 527 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 528 {
 529         struct smu_11_0_dpm_context *dpm_context =
 530                                 smu->smu_dpm.dpm_context;
 531         struct smu_11_0_dpm_table *gfx_table =
 532                                 &dpm_context->dpm_tables.gfx_table;
 533         struct smu_11_0_dpm_table *mem_table =
 534                                 &dpm_context->dpm_tables.uclk_table;
 535         struct smu_11_0_dpm_table *soc_table =
 536                                 &dpm_context->dpm_tables.soc_table;
 537         struct smu_umd_pstate_table *pstate_table =
 538                                 &smu->pstate_table;
 539
 540         pstate_table->gfxclk_pstate.min = gfx_table->min;
 541         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 542
 543         pstate_table->uclk_pstate.min = mem_table->min;
 544         pstate_table->uclk_pstate.peak = mem_table->max;
 545
 546         pstate_table->socclk_pstate.min = soc_table->min;
 547         pstate_table->socclk_pstate.peak = soc_table->max;
 548
 549         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 550             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 551             soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 552                 pstate_table->gfxclk_pstate.standard =
 553                         gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 554                 pstate_table->uclk_pstate.standard =
 555                         mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 556                 pstate_table->socclk_pstate.standard =
 557                         soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 558         } else {
 559                 pstate_table->gfxclk_pstate.standard =
 560                         pstate_table->gfxclk_pstate.min;
 561                 pstate_table->uclk_pstate.standard =
 562                         pstate_table->uclk_pstate.min;
 563                 pstate_table->socclk_pstate.standard =
 564                         pstate_table->socclk_pstate.min;
 565         }
 566
 567         return 0;
 568 }
 569
 570 static int arcturus_get_clk_table(struct smu_context *smu,
 571                         struct pp_clock_levels_with_latency *clocks,
 572                         struct smu_11_0_dpm_table *dpm_table)
 573 {
 574         int i, count;
 575
 576         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 577         clocks->num_levels = count;
 578
 579         for (i = 0; i < count; i++) {
 580                 clocks->data[i].clocks_in_khz =
 581                         dpm_table->dpm_levels[i].value * 1000;
 582                 clocks->data[i].latency_in_us = 0;
 583         }
 584
 585         return 0;
 586 }
 587
 588 static int arcturus_freqs_in_same_level(int32_t frequency1,
 589                                         int32_t frequency2)
 590 {
 591         return (abs(frequency1 - frequency2) <= EPSILON);
 592 }
 593
 594 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 595                                          MetricsMember_t member,
 596                                          uint32_t *value)
 597 {
 598         struct smu_table_context *smu_table= &smu->smu_table;
 599         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 600         int ret = 0;
 601
 602         mutex_lock(&smu->metrics_lock);
 603
 604         ret = smu_cmn_get_metrics_table_locked(smu,
 605                                                NULL,
 606                                                false);
 607         if (ret) {
 608                 mutex_unlock(&smu->metrics_lock);
 609                 return ret;
 610         }
 611
 612         switch (member) {
 613         case METRICS_CURR_GFXCLK:
 614                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 615                 break;
 616         case METRICS_CURR_SOCCLK:
 617                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 618                 break;
 619         case METRICS_CURR_UCLK:
 620                 *value = metrics->CurrClock[PPCLK_UCLK];
 621                 break;
 622         case METRICS_CURR_VCLK:
 623                 *value = metrics->CurrClock[PPCLK_VCLK];
 624                 break;
 625         case METRICS_CURR_DCLK:
 626                 *value = metrics->CurrClock[PPCLK_DCLK];
 627                 break;
 628         case METRICS_CURR_FCLK:
 629                 *value = metrics->CurrClock[PPCLK_FCLK];
 630                 break;
 631         case METRICS_AVERAGE_GFXCLK:
 632                 *value = metrics->AverageGfxclkFrequency;
 633                 break;
 634         case METRICS_AVERAGE_SOCCLK:
 635                 *value = metrics->AverageSocclkFrequency;
 636                 break;
 637         case METRICS_AVERAGE_UCLK:
 638                 *value = metrics->AverageUclkFrequency;
 639                 break;
 640         case METRICS_AVERAGE_VCLK:
 641                 *value = metrics->AverageVclkFrequency;
 642                 break;
 643         case METRICS_AVERAGE_DCLK:
 644                 *value = metrics->AverageDclkFrequency;
 645                 break;
 646         case METRICS_AVERAGE_GFXACTIVITY:
 647                 *value = metrics->AverageGfxActivity;
 648                 break;
 649         case METRICS_AVERAGE_MEMACTIVITY:
 650                 *value = metrics->AverageUclkActivity;
 651                 break;
 652         case METRICS_AVERAGE_VCNACTIVITY:
 653                 *value = metrics->VcnActivityPercentage;
 654                 break;
 655         case METRICS_AVERAGE_SOCKETPOWER:
 656                 *value = metrics->AverageSocketPower << 8;
 657                 break;
 658         case METRICS_TEMPERATURE_EDGE:
 659                 *value = metrics->TemperatureEdge *
 660                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 661                 break;
 662         case METRICS_TEMPERATURE_HOTSPOT:
 663                 *value = metrics->TemperatureHotspot *
 664                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 665                 break;
 666         case METRICS_TEMPERATURE_MEM:
 667                 *value = metrics->TemperatureHBM *
 668                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 669                 break;
 670         case METRICS_TEMPERATURE_VRGFX:
 671                 *value = metrics->TemperatureVrGfx *
 672                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 673                 break;
 674         case METRICS_TEMPERATURE_VRSOC:
 675                 *value = metrics->TemperatureVrSoc *
 676                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 677                 break;
 678         case METRICS_TEMPERATURE_VRMEM:
 679                 *value = metrics->TemperatureVrMem *
 680                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 681                 break;
 682         case METRICS_THROTTLER_STATUS:
 683                 *value = metrics->ThrottlerStatus;
 684                 break;
 685         case METRICS_CURR_FANSPEED:
 686                 *value = metrics->CurrFanSpeed;
 687                 break;
 688         default:
 689                 *value = UINT_MAX;
 690                 break;
 691         }
 692
 693         mutex_unlock(&smu->metrics_lock);
 694
 695         return ret;
 696 }
 697
 698 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 699                                        enum smu_clk_type clk_type,
 700                                        uint32_t *value)
 701 {
 702         MetricsMember_t member_type;
 703         int clk_id = 0;
 704
 705         if (!value)
 706                 return -EINVAL;
 707
 708         clk_id = smu_cmn_to_asic_specific_index(smu,
 709                                                 CMN2ASIC_MAPPING_CLK,
 710                                                 clk_type);
 711         if (clk_id < 0)
 712                 return -EINVAL;
 713
 714         switch (clk_id) {
 715         case PPCLK_GFXCLK:
 716                 /*
 717                  * CurrClock[clk_id] can provide accurate
 718                  *   output only when the dpm feature is enabled.
 719                  * We can use Average_* for dpm disabled case.
 720                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 721                  */
 722                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 723                         member_type = METRICS_CURR_GFXCLK;
 724                 else
 725                         member_type = METRICS_AVERAGE_GFXCLK;
 726                 break;
 727         case PPCLK_UCLK:
 728                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 729                         member_type = METRICS_CURR_UCLK;
 730                 else
 731                         member_type = METRICS_AVERAGE_UCLK;
 732                 break;
 733         case PPCLK_SOCCLK:
 734                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 735                         member_type = METRICS_CURR_SOCCLK;
 736                 else
 737                         member_type = METRICS_AVERAGE_SOCCLK;
 738                 break;
 739         case PPCLK_VCLK:
 740                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 741                         member_type = METRICS_CURR_VCLK;
 742                 else
 743                         member_type = METRICS_AVERAGE_VCLK;
 744                 break;
 745         case PPCLK_DCLK:
 746                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 747                         member_type = METRICS_CURR_DCLK;
 748                 else
 749                         member_type = METRICS_AVERAGE_DCLK;
 750                 break;
 751         case PPCLK_FCLK:
 752                 member_type = METRICS_CURR_FCLK;
 753                 break;
 754         default:
 755                 return -EINVAL;
 756         }
 757
 758         return arcturus_get_smu_metrics_data(smu,
 759                                              member_type,
 760                                              value);
 761 }
 762
 763 static int arcturus_print_clk_levels(struct smu_context *smu,
 764                         enum smu_clk_type type, char *buf)
 765 {
 766         int i, now, size = 0;
 767         int ret = 0;
 768         struct pp_clock_levels_with_latency clocks;
 769         struct smu_11_0_dpm_table *single_dpm_table;
 770         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 771         struct smu_11_0_dpm_context *dpm_context = NULL;
 772         uint32_t gen_speed, lane_width;
 773
 774         if (amdgpu_ras_intr_triggered())
 775                 return sysfs_emit(buf, "unavailable\n");
 776
 777         dpm_context = smu_dpm->dpm_context;
 778
 779         switch (type) {
 780         case SMU_SCLK:
 781                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 782                 if (ret) {
 783                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 784                         return ret;
 785                 }
 786
 787                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 788                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 789                 if (ret) {
 790                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 791                         return ret;
 792                 }
 793
 794                 /*
 795                  * For DPM disabled case, there will be only one clock level.
 796                  * And it's safe to assume that is always the current clock.
 797                  */
 798                 for (i = 0; i < clocks.num_levels; i++)
 799                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 800                                         clocks.data[i].clocks_in_khz / 1000,
 801                                         (clocks.num_levels == 1) ? "*" :
 802                                         (arcturus_freqs_in_same_level(
 803                                         clocks.data[i].clocks_in_khz / 1000,
 804                                         now) ? "*" : ""));
 805                 break;
 806
 807         case SMU_MCLK:
 808                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 809                 if (ret) {
 810                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 811                         return ret;
 812                 }
 813
 814                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 815                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 816                 if (ret) {
 817                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 818                         return ret;
 819                 }
 820
 821                 for (i = 0; i < clocks.num_levels; i++)
 822                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 823                                 i, clocks.data[i].clocks_in_khz / 1000,
 824                                 (clocks.num_levels == 1) ? "*" :
 825                                 (arcturus_freqs_in_same_level(
 826                                 clocks.data[i].clocks_in_khz / 1000,
 827                                 now) ? "*" : ""));
 828                 break;
 829
 830         case SMU_SOCCLK:
 831                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 832                 if (ret) {
 833                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 834                         return ret;
 835                 }
 836
 837                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 838                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 839                 if (ret) {
 840                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 841                         return ret;
 842                 }
 843
 844                 for (i = 0; i < clocks.num_levels; i++)
 845                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 846                                 i, clocks.data[i].clocks_in_khz / 1000,
 847                                 (clocks.num_levels == 1) ? "*" :
 848                                 (arcturus_freqs_in_same_level(
 849                                 clocks.data[i].clocks_in_khz / 1000,
 850                                 now) ? "*" : ""));
 851                 break;
 852
 853         case SMU_FCLK:
 854                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 855                 if (ret) {
 856                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 857                         return ret;
 858                 }
 859
 860                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 861                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 862                 if (ret) {
 863                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 864                         return ret;
 865                 }
 866
 867                 for (i = 0; i < single_dpm_table->count; i++)
 868                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 869                                 i, single_dpm_table->dpm_levels[i].value,
 870                                 (clocks.num_levels == 1) ? "*" :
 871                                 (arcturus_freqs_in_same_level(
 872                                 clocks.data[i].clocks_in_khz / 1000,
 873                                 now) ? "*" : ""));
 874                 break;
 875
 876         case SMU_VCLK:
 877                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 878                 if (ret) {
 879                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 880                         return ret;
 881                 }
 882
 883                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 884                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 885                 if (ret) {
 886                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 887                         return ret;
 888                 }
 889
 890                 for (i = 0; i < single_dpm_table->count; i++)
 891                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 892                                 i, single_dpm_table->dpm_levels[i].value,
 893                                 (clocks.num_levels == 1) ? "*" :
 894                                 (arcturus_freqs_in_same_level(
 895                                 clocks.data[i].clocks_in_khz / 1000,
 896                                 now) ? "*" : ""));
 897                 break;
 898
 899         case SMU_DCLK:
 900                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 901                 if (ret) {
 902                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 903                         return ret;
 904                 }
 905
 906                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 907                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 908                 if (ret) {
 909                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 910                         return ret;
 911                 }
 912
 913                 for (i = 0; i < single_dpm_table->count; i++)
 914                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 915                                 i, single_dpm_table->dpm_levels[i].value,
 916                                 (clocks.num_levels == 1) ? "*" :
 917                                 (arcturus_freqs_in_same_level(
 918                                 clocks.data[i].clocks_in_khz / 1000,
 919                                 now) ? "*" : ""));
 920                 break;
 921
 922         case SMU_PCIE:
 923                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 924                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 925                 size += sysfs_emit_at(buf, size, "0: %s %s %dMhz *\n",
 926                                 (gen_speed == 0) ? "2.5GT/s," :
 927                                 (gen_speed == 1) ? "5.0GT/s," :
 928                                 (gen_speed == 2) ? "8.0GT/s," :
 929                                 (gen_speed == 3) ? "16.0GT/s," : "",
 930                                 (lane_width == 1) ? "x1" :
 931                                 (lane_width == 2) ? "x2" :
 932                                 (lane_width == 3) ? "x4" :
 933                                 (lane_width == 4) ? "x8" :
 934                                 (lane_width == 5) ? "x12" :
 935                                 (lane_width == 6) ? "x16" : "",
 936                                 smu->smu_table.boot_values.lclk / 100);
 937                 break;
 938
 939         default:
 940                 break;
 941         }
 942
 943         return size;
 944 }
 945
 946 static int arcturus_upload_dpm_level(struct smu_context *smu,
 947                                      bool max,
 948                                      uint32_t feature_mask,
 949                                      uint32_t level)
 950 {
 951         struct smu_11_0_dpm_context *dpm_context =
 952                         smu->smu_dpm.dpm_context;
 953         uint32_t freq;
 954         int ret = 0;
 955
 956         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 957             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 958                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 959                 ret = smu_cmn_send_smc_msg_with_param(smu,
 960                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 961                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 962                         NULL);
 963                 if (ret) {
 964                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 965                                                 max ? "max" : "min");
 966                         return ret;
 967                 }
 968         }
 969
 970         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 971             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 972                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 973                 ret = smu_cmn_send_smc_msg_with_param(smu,
 974                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 975                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 976                         NULL);
 977                 if (ret) {
 978                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 979                                                 max ? "max" : "min");
 980                         return ret;
 981                 }
 982         }
 983
 984         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 985             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 986                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 987                 ret = smu_cmn_send_smc_msg_with_param(smu,
 988                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 989                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 990                         NULL);
 991                 if (ret) {
 992                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 993                                                 max ? "max" : "min");
 994                         return ret;
 995                 }
 996         }
 997
 998         return ret;
 999 }
1000
1001 static int arcturus_force_clk_levels(struct smu_context *smu,
1002                         enum smu_clk_type type, uint32_t mask)
1003 {
1004         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1005         struct smu_11_0_dpm_table *single_dpm_table = NULL;
1006         uint32_t soft_min_level, soft_max_level;
1007         uint32_t smu_version;
1008         int ret = 0;
1009
1010         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1011         if (ret) {
1012                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1013                 return ret;
1014         }
1015
1016         if ((smu_version >= 0x361200) &&
1017             (smu_version <= 0x361a00)) {
1018                 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1019                        "54.18 - 54.26(included) SMU firmwares\n");
1020                 return -EOPNOTSUPP;
1021         }
1022
1023         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1024         soft_max_level = mask ? (fls(mask) - 1) : 0;
1025
1026         switch (type) {
1027         case SMU_SCLK:
1028                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1029                 if (soft_max_level >= single_dpm_table->count) {
1030                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1031                                         soft_max_level, single_dpm_table->count - 1);
1032                         ret = -EINVAL;
1033                         break;
1034                 }
1035
1036                 ret = arcturus_upload_dpm_level(smu,
1037                                                 false,
1038                                                 FEATURE_DPM_GFXCLK_MASK,
1039                                                 soft_min_level);
1040                 if (ret) {
1041                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1042                         break;
1043                 }
1044
1045                 ret = arcturus_upload_dpm_level(smu,
1046                                                 true,
1047                                                 FEATURE_DPM_GFXCLK_MASK,
1048                                                 soft_max_level);
1049                 if (ret)
1050                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1051
1052                 break;
1053
1054         case SMU_MCLK:
1055         case SMU_SOCCLK:
1056         case SMU_FCLK:
1057                 /*
1058                  * Should not arrive here since Arcturus does not
1059                  * support mclk/socclk/fclk softmin/softmax settings
1060                  */
1061                 ret = -EINVAL;
1062                 break;
1063
1064         default:
1065                 break;
1066         }
1067
1068         return ret;
1069 }
1070
1071 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1072                                                 struct smu_temperature_range *range)
1073 {
1074         struct smu_table_context *table_context = &smu->smu_table;
1075         struct smu_11_0_powerplay_table *powerplay_table =
1076                                 table_context->power_play_table;
1077         PPTable_t *pptable = smu->smu_table.driver_pptable;
1078
1079         if (!range)
1080                 return -EINVAL;
1081
1082         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1083
1084         range->max = pptable->TedgeLimit *
1085                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1086         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1087                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1088         range->hotspot_crit_max = pptable->ThotspotLimit *
1089                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1090         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1091                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1092         range->mem_crit_max = pptable->TmemLimit *
1093                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1094         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1095                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1096         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1097
1098         return 0;
1099 }
1100
1101 static int arcturus_read_sensor(struct smu_context *smu,
1102                                 enum amd_pp_sensors sensor,
1103                                 void *data, uint32_t *size)
1104 {
1105         struct smu_table_context *table_context = &smu->smu_table;
1106         PPTable_t *pptable = table_context->driver_pptable;
1107         int ret = 0;
1108
1109         if (amdgpu_ras_intr_triggered())
1110                 return 0;
1111
1112         if (!data || !size)
1113                 return -EINVAL;
1114
1115         mutex_lock(&smu->sensor_lock);
1116         switch (sensor) {
1117         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1118                 *(uint32_t *)data = pptable->FanMaximumRpm;
1119                 *size = 4;
1120                 break;
1121         case AMDGPU_PP_SENSOR_MEM_LOAD:
1122                 ret = arcturus_get_smu_metrics_data(smu,
1123                                                     METRICS_AVERAGE_MEMACTIVITY,
1124                                                     (uint32_t *)data);
1125                 *size = 4;
1126                 break;
1127         case AMDGPU_PP_SENSOR_GPU_LOAD:
1128                 ret = arcturus_get_smu_metrics_data(smu,
1129                                                     METRICS_AVERAGE_GFXACTIVITY,
1130                                                     (uint32_t *)data);
1131                 *size = 4;
1132                 break;
1133         case AMDGPU_PP_SENSOR_GPU_POWER:
1134                 ret = arcturus_get_smu_metrics_data(smu,
1135                                                     METRICS_AVERAGE_SOCKETPOWER,
1136                                                     (uint32_t *)data);
1137                 *size = 4;
1138                 break;
1139         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1140                 ret = arcturus_get_smu_metrics_data(smu,
1141                                                     METRICS_TEMPERATURE_HOTSPOT,
1142                                                     (uint32_t *)data);
1143                 *size = 4;
1144                 break;
1145         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1146                 ret = arcturus_get_smu_metrics_data(smu,
1147                                                     METRICS_TEMPERATURE_EDGE,
1148                                                     (uint32_t *)data);
1149                 *size = 4;
1150                 break;
1151         case AMDGPU_PP_SENSOR_MEM_TEMP:
1152                 ret = arcturus_get_smu_metrics_data(smu,
1153                                                     METRICS_TEMPERATURE_MEM,
1154                                                     (uint32_t *)data);
1155                 *size = 4;
1156                 break;
1157         case AMDGPU_PP_SENSOR_GFX_MCLK:
1158                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1159                 /* the output clock frequency in 10K unit */
1160                 *(uint32_t *)data *= 100;
1161                 *size = 4;
1162                 break;
1163         case AMDGPU_PP_SENSOR_GFX_SCLK:
1164                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1165                 *(uint32_t *)data *= 100;
1166                 *size = 4;
1167                 break;
1168         case AMDGPU_PP_SENSOR_VDDGFX:
1169                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1170                 *size = 4;
1171                 break;
1172         default:
1173                 ret = -EOPNOTSUPP;
1174                 break;
1175         }
1176         mutex_unlock(&smu->sensor_lock);
1177
1178         return ret;
1179 }
1180
1181 static int arcturus_set_fan_static_mode(struct smu_context *smu,
1182                                         uint32_t mode)
1183 {
1184         struct amdgpu_device *adev = smu->adev;
1185
1186         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1187                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1188                                    CG_FDO_CTRL2, TMIN, 0));
1189         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1190                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1191                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1192
1193         return 0;
1194 }
1195
1196 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1197                                       uint32_t *speed)
1198 {
1199         struct amdgpu_device *adev = smu->adev;
1200         uint32_t crystal_clock_freq = 2500;
1201         uint32_t tach_status;
1202         uint64_t tmp64;
1203         int ret = 0;
1204
1205         if (!speed)
1206                 return -EINVAL;
1207
1208         switch (smu_v11_0_get_fan_control_mode(smu)) {
1209         case AMD_FAN_CTRL_AUTO:
1210                 ret = arcturus_get_smu_metrics_data(smu,
1211                                                     METRICS_CURR_FANSPEED,
1212                                                     speed);
1213                 break;
1214         default:
1215                 /*
1216                  * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1217                  * detected via register retrieving. To workaround this, we will
1218                  * report the fan speed as 0 RPM if user just requested such.
1219                  */
1220                 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1221                      && !smu->user_dpm_profile.fan_speed_rpm) {
1222                         *speed = 0;
1223                         return 0;
1224                 }
1225
1226                 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1227                 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
1228                 if (tach_status) {
1229                         do_div(tmp64, tach_status);
1230                         *speed = (uint32_t)tmp64;
1231                 } else {
1232                         *speed = 0;
1233                 }
1234
1235                 break;
1236         }
1237
1238         return ret;
1239 }
1240
1241 static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1242                                       uint32_t speed)
1243 {
1244         struct amdgpu_device *adev = smu->adev;
1245         uint32_t duty100, duty;
1246         uint64_t tmp64;
1247
1248         speed = MIN(speed, 255);
1249
1250         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1251                                 CG_FDO_CTRL1, FMAX_DUTY100);
1252         if (!duty100)
1253                 return -EINVAL;
1254
1255         tmp64 = (uint64_t)speed * duty100;
1256         do_div(tmp64, 255);
1257         duty = (uint32_t)tmp64;
1258
1259         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
1260                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
1261                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1262
1263         return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1264 }
1265
1266 static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1267                                       uint32_t speed)
1268 {
1269         struct amdgpu_device *adev = smu->adev;
1270         /*
1271          * crystal_clock_freq used for fan speed rpm calculation is
1272          * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1273          */
1274         uint32_t crystal_clock_freq = 2500;
1275         uint32_t tach_period;
1276
1277         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1278         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1279                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
1280                                    CG_TACH_CTRL, TARGET_PERIOD,
1281                                    tach_period));
1282
1283         return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1284 }
1285
1286 static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1287                                       uint32_t *speed)
1288 {
1289         struct amdgpu_device *adev = smu->adev;
1290         uint32_t duty100, duty;
1291         uint64_t tmp64;
1292
1293         /*
1294          * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1295          * detected via register retrieving. To workaround this, we will
1296          * report the fan speed as 0 PWM if user just requested such.
1297          */
1298         if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1299              && !smu->user_dpm_profile.fan_speed_pwm) {
1300                 *speed = 0;
1301                 return 0;
1302         }
1303
1304         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1305                                 CG_FDO_CTRL1, FMAX_DUTY100);
1306         duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
1307                                 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1308
1309         if (duty100) {
1310                 tmp64 = (uint64_t)duty * 255;
1311                 do_div(tmp64, duty100);
1312                 *speed = MIN((uint32_t)tmp64, 255);
1313         } else {
1314                 *speed = 0;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int arcturus_get_fan_parameters(struct smu_context *smu)
1321 {
1322         PPTable_t *pptable = smu->smu_table.driver_pptable;
1323
1324         smu->fan_max_rpm = pptable->FanMaximumRpm;
1325
1326         return 0;
1327 }
1328
1329 static int arcturus_get_power_limit(struct smu_context *smu,
1330                                     uint32_t *current_power_limit,
1331                                     uint32_t *default_power_limit,
1332                                     uint32_t *max_power_limit)
1333 {
1334         struct smu_11_0_powerplay_table *powerplay_table =
1335                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1336         PPTable_t *pptable = smu->smu_table.driver_pptable;
1337         uint32_t power_limit, od_percent;
1338
1339         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1340                 /* the last hope to figure out the ppt limit */
1341                 if (!pptable) {
1342                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1343                         return -EINVAL;
1344                 }
1345                 power_limit =
1346                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1347         }
1348
1349         if (current_power_limit)
1350                 *current_power_limit = power_limit;
1351         if (default_power_limit)
1352                 *default_power_limit = power_limit;
1353
1354         if (max_power_limit) {
1355                 if (smu->od_enabled) {
1356                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1357
1358                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1359
1360                         power_limit *= (100 + od_percent);
1361                         power_limit /= 100;
1362                 }
1363
1364                 *max_power_limit = power_limit;
1365         }
1366
1367         return 0;
1368 }
1369
1370 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1371                                            char *buf)
1372 {
1373         DpmActivityMonitorCoeffInt_t activity_monitor;
1374         static const char *profile_name[] = {
1375                                         "BOOTUP_DEFAULT",
1376                                         "3D_FULL_SCREEN",
1377                                         "POWER_SAVING",
1378                                         "VIDEO",
1379                                         "VR",
1380                                         "COMPUTE",
1381                                         "CUSTOM"};
1382         static const char *title[] = {
1383                         "PROFILE_INDEX(NAME)",
1384                         "CLOCK_TYPE(NAME)",
1385                         "FPS",
1386                         "UseRlcBusy",
1387                         "MinActiveFreqType",
1388                         "MinActiveFreq",
1389                         "BoosterFreqType",
1390                         "BoosterFreq",
1391                         "PD_Data_limit_c",
1392                         "PD_Data_error_coeff",
1393                         "PD_Data_error_rate_coeff"};
1394         uint32_t i, size = 0;
1395         int16_t workload_type = 0;
1396         int result = 0;
1397         uint32_t smu_version;
1398
1399         if (!buf)
1400                 return -EINVAL;
1401
1402         result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1403         if (result)
1404                 return result;
1405
1406         if (smu_version >= 0x360d00)
1407                 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1408                         title[0], title[1], title[2], title[3], title[4], title[5],
1409                         title[6], title[7], title[8], title[9], title[10]);
1410         else
1411                 size += sysfs_emit_at(buf, size, "%16s\n",
1412                         title[0]);
1413
1414         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1415                 /*
1416                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1417                  * Not all profile modes are supported on arcturus.
1418                  */
1419                 workload_type = smu_cmn_to_asic_specific_index(smu,
1420                                                                CMN2ASIC_MAPPING_WORKLOAD,
1421                                                                i);
1422                 if (workload_type < 0)
1423                         continue;
1424
1425                 if (smu_version >= 0x360d00) {
1426                         result = smu_cmn_update_table(smu,
1427                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1428                                                   workload_type,
1429                                                   (void *)(&activity_monitor),
1430                                                   false);
1431                         if (result) {
1432                                 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1433                                 return result;
1434                         }
1435                 }
1436
1437                 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1438                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1439
1440                 if (smu_version >= 0x360d00) {
1441                         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1442                                 " ",
1443                                 0,
1444                                 "GFXCLK",
1445                                 activity_monitor.Gfx_FPS,
1446                                 activity_monitor.Gfx_UseRlcBusy,
1447                                 activity_monitor.Gfx_MinActiveFreqType,
1448                                 activity_monitor.Gfx_MinActiveFreq,
1449                                 activity_monitor.Gfx_BoosterFreqType,
1450                                 activity_monitor.Gfx_BoosterFreq,
1451                                 activity_monitor.Gfx_PD_Data_limit_c,
1452                                 activity_monitor.Gfx_PD_Data_error_coeff,
1453                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1454
1455                         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1456                                 " ",
1457                                 1,
1458                                 "UCLK",
1459                                 activity_monitor.Mem_FPS,
1460                                 activity_monitor.Mem_UseRlcBusy,
1461                                 activity_monitor.Mem_MinActiveFreqType,
1462                                 activity_monitor.Mem_MinActiveFreq,
1463                                 activity_monitor.Mem_BoosterFreqType,
1464                                 activity_monitor.Mem_BoosterFreq,
1465                                 activity_monitor.Mem_PD_Data_limit_c,
1466                                 activity_monitor.Mem_PD_Data_error_coeff,
1467                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1468                 }
1469         }
1470
1471         return size;
1472 }
1473
1474 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1475                                            long *input,
1476                                            uint32_t size)
1477 {
1478         DpmActivityMonitorCoeffInt_t activity_monitor;
1479         int workload_type = 0;
1480         uint32_t profile_mode = input[size];
1481         int ret = 0;
1482         uint32_t smu_version;
1483
1484         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1485                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1486                 return -EINVAL;
1487         }
1488
1489         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1490         if (ret)
1491                 return ret;
1492
1493         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1494              (smu_version >=0x360d00)) {
1495                 ret = smu_cmn_update_table(smu,
1496                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1497                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1498                                        (void *)(&activity_monitor),
1499                                        false);
1500                 if (ret) {
1501                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1502                         return ret;
1503                 }
1504
1505                 switch (input[0]) {
1506                 case 0: /* Gfxclk */
1507                         activity_monitor.Gfx_FPS = input[1];
1508                         activity_monitor.Gfx_UseRlcBusy = input[2];
1509                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1510                         activity_monitor.Gfx_MinActiveFreq = input[4];
1511                         activity_monitor.Gfx_BoosterFreqType = input[5];
1512                         activity_monitor.Gfx_BoosterFreq = input[6];
1513                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1514                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1515                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1516                         break;
1517                 case 1: /* Uclk */
1518                         activity_monitor.Mem_FPS = input[1];
1519                         activity_monitor.Mem_UseRlcBusy = input[2];
1520                         activity_monitor.Mem_MinActiveFreqType = input[3];
1521                         activity_monitor.Mem_MinActiveFreq = input[4];
1522                         activity_monitor.Mem_BoosterFreqType = input[5];
1523                         activity_monitor.Mem_BoosterFreq = input[6];
1524                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1525                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1526                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1527                         break;
1528                 }
1529
1530                 ret = smu_cmn_update_table(smu,
1531                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1532                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1533                                        (void *)(&activity_monitor),
1534                                        true);
1535                 if (ret) {
1536                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1537                         return ret;
1538                 }
1539         }
1540
1541         /*
1542          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1543          * Not all profile modes are supported on arcturus.
1544          */
1545         workload_type = smu_cmn_to_asic_specific_index(smu,
1546                                                        CMN2ASIC_MAPPING_WORKLOAD,
1547                                                        profile_mode);
1548         if (workload_type < 0) {
1549                 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1550                 return -EINVAL;
1551         }
1552
1553         ret = smu_cmn_send_smc_msg_with_param(smu,
1554                                           SMU_MSG_SetWorkloadMask,
1555                                           1 << workload_type,
1556                                           NULL);
1557         if (ret) {
1558                 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1559                 return ret;
1560         }
1561
1562         smu->power_profile_mode = profile_mode;
1563
1564         return 0;
1565 }
1566
1567 static int arcturus_set_performance_level(struct smu_context *smu,
1568                                           enum amd_dpm_forced_level level)
1569 {
1570         uint32_t smu_version;
1571         int ret;
1572
1573         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1574         if (ret) {
1575                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1576                 return ret;
1577         }
1578
1579         switch (level) {
1580         case AMD_DPM_FORCED_LEVEL_HIGH:
1581         case AMD_DPM_FORCED_LEVEL_LOW:
1582         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1583         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1584         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1585         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1586                 if ((smu_version >= 0x361200) &&
1587                     (smu_version <= 0x361a00)) {
1588                         dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1589                                "54.18 - 54.26(included) SMU firmwares\n");
1590                         return -EOPNOTSUPP;
1591                 }
1592                 break;
1593         default:
1594                 break;
1595         }
1596
1597         return smu_v11_0_set_performance_level(smu, level);
1598 }
1599
1600 static void arcturus_dump_pptable(struct smu_context *smu)
1601 {
1602         struct smu_table_context *table_context = &smu->smu_table;
1603         PPTable_t *pptable = table_context->driver_pptable;
1604         int i;
1605
1606         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1607
1608         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1609
1610         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1611         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1612
1613         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1614                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1615                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1616         }
1617
1618         dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1619         dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1620         dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1621         dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1622
1623         dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1624         dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1625         dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1626         dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1627         dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1628         dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1629         dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1630
1631         dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1632         dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1633
1634         dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1635
1636         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1637         dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1638
1639         dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1640         dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1641         dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1642         dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1643
1644         dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1645         dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1646         dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1647         dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1648
1649         dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1650         dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1651
1652         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1653                         "  .VoltageMode          = 0x%02x\n"
1654                         "  .SnapToDiscrete       = 0x%02x\n"
1655                         "  .NumDiscreteLevels    = 0x%02x\n"
1656                         "  .padding              = 0x%02x\n"
1657                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1658                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1659                         "  .SsFmin               = 0x%04x\n"
1660                         "  .Padding_16           = 0x%04x\n",
1661                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1662                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1663                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1664                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1665                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1666                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1667                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1668                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1669                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1670                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1671                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1672
1673         dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1674                         "  .VoltageMode          = 0x%02x\n"
1675                         "  .SnapToDiscrete       = 0x%02x\n"
1676                         "  .NumDiscreteLevels    = 0x%02x\n"
1677                         "  .padding              = 0x%02x\n"
1678                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1679                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1680                         "  .SsFmin               = 0x%04x\n"
1681                         "  .Padding_16           = 0x%04x\n",
1682                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1683                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1684                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1685                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1686                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1687                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1688                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1689                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1690                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1691                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1692                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1693
1694         dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1695                         "  .VoltageMode          = 0x%02x\n"
1696                         "  .SnapToDiscrete       = 0x%02x\n"
1697                         "  .NumDiscreteLevels    = 0x%02x\n"
1698                         "  .padding              = 0x%02x\n"
1699                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1700                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1701                         "  .SsFmin               = 0x%04x\n"
1702                         "  .Padding_16           = 0x%04x\n",
1703                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1704                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1705                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1706                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1707                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1708                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1709                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1710                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1711                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1712                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1713                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1714
1715         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1716                         "  .VoltageMode          = 0x%02x\n"
1717                         "  .SnapToDiscrete       = 0x%02x\n"
1718                         "  .NumDiscreteLevels    = 0x%02x\n"
1719                         "  .padding              = 0x%02x\n"
1720                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1721                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1722                         "  .SsFmin               = 0x%04x\n"
1723                         "  .Padding_16           = 0x%04x\n",
1724                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1725                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1726                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1727                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1728                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1729                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1730                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1731                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1732                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1733                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1734                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1735
1736         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1737                         "  .VoltageMode          = 0x%02x\n"
1738                         "  .SnapToDiscrete       = 0x%02x\n"
1739                         "  .NumDiscreteLevels    = 0x%02x\n"
1740                         "  .padding              = 0x%02x\n"
1741                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1742                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1743                         "  .SsFmin               = 0x%04x\n"
1744                         "  .Padding_16           = 0x%04x\n",
1745                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1746                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1747                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1748                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1749                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1750                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1751                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1752                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1753                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1754                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1755                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1756
1757         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1758                         "  .VoltageMode          = 0x%02x\n"
1759                         "  .SnapToDiscrete       = 0x%02x\n"
1760                         "  .NumDiscreteLevels    = 0x%02x\n"
1761                         "  .padding              = 0x%02x\n"
1762                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1763                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1764                         "  .SsFmin               = 0x%04x\n"
1765                         "  .Padding_16           = 0x%04x\n",
1766                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1767                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1768                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1769                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1770                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1771                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1772                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1773                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1774                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1775                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1776                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1777
1778
1779         dev_info(smu->adev->dev, "FreqTableGfx\n");
1780         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1781                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1782
1783         dev_info(smu->adev->dev, "FreqTableVclk\n");
1784         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1785                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1786
1787         dev_info(smu->adev->dev, "FreqTableDclk\n");
1788         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1789                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1790
1791         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1792         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1793                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1794
1795         dev_info(smu->adev->dev, "FreqTableUclk\n");
1796         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1797                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1798
1799         dev_info(smu->adev->dev, "FreqTableFclk\n");
1800         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1801                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1802
1803         dev_info(smu->adev->dev, "Mp0clkFreq\n");
1804         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1805                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1806
1807         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1808         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1809                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1810
1811         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1812         dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1813         dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1814         dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1815         dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1816         dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1817         dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1818         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1819         dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1820
1821         dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1822         dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1823         dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1824         dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1825
1826         dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1827         dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1828
1829         dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1830         dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1831         dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1832         dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1833         dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1834         dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1835
1836         dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1837         dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1838         dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1839         dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1840         dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1841         dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1842         dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1843         dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1844         dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1845
1846         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1847         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1848         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1849         dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1850
1851         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1852         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1853         dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1854         dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1855
1856         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1857                         pptable->dBtcGbGfxPll.a,
1858                         pptable->dBtcGbGfxPll.b,
1859                         pptable->dBtcGbGfxPll.c);
1860         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1861                         pptable->dBtcGbGfxAfll.a,
1862                         pptable->dBtcGbGfxAfll.b,
1863                         pptable->dBtcGbGfxAfll.c);
1864         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1865                         pptable->dBtcGbSoc.a,
1866                         pptable->dBtcGbSoc.b,
1867                         pptable->dBtcGbSoc.c);
1868
1869         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1870                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1871                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1872         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1873                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1874                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1875
1876         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1877                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1878                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1879                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1880         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1881                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1882                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1883                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1884
1885         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1886         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1887
1888         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1889         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1890         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1891         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1892
1893         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1894         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1895         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1896         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1897
1898         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1899         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1900
1901         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1902         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1903                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1904         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1905         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1906
1907         dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1908         dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1909         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1910         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1911         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1912         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1913         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1914         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1915
1916         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1917         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1918                         pptable->ReservedEquation0.a,
1919                         pptable->ReservedEquation0.b,
1920                         pptable->ReservedEquation0.c);
1921         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1922                         pptable->ReservedEquation1.a,
1923                         pptable->ReservedEquation1.b,
1924                         pptable->ReservedEquation1.c);
1925         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1926                         pptable->ReservedEquation2.a,
1927                         pptable->ReservedEquation2.b,
1928                         pptable->ReservedEquation2.c);
1929         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1930                         pptable->ReservedEquation3.a,
1931                         pptable->ReservedEquation3.b,
1932                         pptable->ReservedEquation3.c);
1933
1934         dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1935         dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1936
1937         dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1938         dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1939         dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1940
1941         dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1942         dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1943
1944         dev_info(smu->adev->dev, "Board Parameters:\n");
1945         dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1946         dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1947
1948         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1949         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1950         dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1951         dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1952
1953         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1954         dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1955
1956         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1957         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1958         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1959
1960         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1961         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1962         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1963
1964         dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1965         dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1966         dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1967
1968         dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1969         dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1970         dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1971
1972         dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1973         dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1974         dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1975         dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1976
1977         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1978         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1979         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1980
1981         dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1982         dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1983         dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1984
1985         dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1986         dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1987         dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1988
1989         dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1990         dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1991         dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1992
1993         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1994                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1995                 dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1996                                 pptable->I2cControllers[i].Enabled);
1997                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
1998                                 pptable->I2cControllers[i].SlaveAddress);
1999                 dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
2000                                 pptable->I2cControllers[i].ControllerPort);
2001                 dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
2002                                 pptable->I2cControllers[i].ControllerName);
2003                 dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
2004                                 pptable->I2cControllers[i].ThermalThrotter);
2005                 dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
2006                                 pptable->I2cControllers[i].I2cProtocol);
2007                 dev_info(smu->adev->dev, "                   .Speed = %d\n",
2008                                 pptable->I2cControllers[i].Speed);
2009         }
2010
2011         dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
2012         dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
2013
2014         dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
2015
2016         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2017         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2018                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
2019         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2020         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2021                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
2022         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2023         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2024                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
2025         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2026         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2027                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
2028
2029 }
2030
2031 static bool arcturus_is_dpm_running(struct smu_context *smu)
2032 {
2033         int ret = 0;
2034         uint32_t feature_mask[2];
2035         uint64_t feature_enabled;
2036
2037         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
2038         if (ret)
2039                 return false;
2040
2041         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
2042
2043         return !!(feature_enabled & SMC_DPM_FEATURE);
2044 }
2045
2046 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
2047 {
2048         int ret = 0;
2049
2050         if (enable) {
2051                 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2052                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
2053                         if (ret) {
2054                                 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
2055                                 return ret;
2056                         }
2057                 }
2058         } else {
2059                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2060                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
2061                         if (ret) {
2062                                 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
2063                                 return ret;
2064                         }
2065                 }
2066         }
2067
2068         return ret;
2069 }
2070
2071 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
2072                              struct i2c_msg *msg, int num_msgs)
2073 {
2074         struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
2075         struct smu_table_context *smu_table = &adev->smu.smu_table;
2076         struct smu_table *table = &smu_table->driver_table;
2077         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2078         int i, j, r, c;
2079         u16 dir;
2080
2081         req = kzalloc(sizeof(*req), GFP_KERNEL);
2082         if (!req)
2083                 return -ENOMEM;
2084
2085         req->I2CcontrollerPort = 0;
2086         req->I2CSpeed = I2C_SPEED_FAST_400K;
2087         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2088         dir = msg[0].flags & I2C_M_RD;
2089
2090         for (c = i = 0; i < num_msgs; i++) {
2091                 for (j = 0; j < msg[i].len; j++, c++) {
2092                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2093
2094                         if (!(msg[i].flags & I2C_M_RD)) {
2095                                 /* write */
2096                                 cmd->Cmd = I2C_CMD_WRITE;
2097                                 cmd->RegisterAddr = msg[i].buf[j];
2098                         }
2099
2100                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
2101                                 /* The direction changes.
2102                                  */
2103                                 dir = msg[i].flags & I2C_M_RD;
2104                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2105                         }
2106
2107                         req->NumCmds++;
2108
2109                         /*
2110                          * Insert STOP if we are at the last byte of either last
2111                          * message for the transaction or the client explicitly
2112                          * requires a STOP at this particular message.
2113                          */
2114                         if ((j == msg[i].len - 1) &&
2115                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2116                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2117                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2118                         }
2119                 }
2120         }
2121         mutex_lock(&adev->smu.mutex);
2122         r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2123         mutex_unlock(&adev->smu.mutex);
2124         if (r)
2125                 goto fail;
2126
2127         for (c = i = 0; i < num_msgs; i++) {
2128                 if (!(msg[i].flags & I2C_M_RD)) {
2129                         c += msg[i].len;
2130                         continue;
2131                 }
2132                 for (j = 0; j < msg[i].len; j++, c++) {
2133                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2134
2135                         msg[i].buf[j] = cmd->Data;
2136                 }
2137         }
2138         r = num_msgs;
2139 fail:
2140         kfree(req);
2141         return r;
2142 }
2143
2144 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2145 {
2146         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2147 }
2148
2149
2150 static const struct i2c_algorithm arcturus_i2c_algo = {
2151         .master_xfer = arcturus_i2c_xfer,
2152         .functionality = arcturus_i2c_func,
2153 };
2154
2155
2156 static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
2157         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2158         .max_read_len  = MAX_SW_I2C_COMMANDS,
2159         .max_write_len = MAX_SW_I2C_COMMANDS,
2160         .max_comb_1st_msg_len = 2,
2161         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2162 };
2163
2164 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2165 {
2166         struct amdgpu_device *adev = to_amdgpu_device(control);
2167         int res;
2168
2169         control->owner = THIS_MODULE;
2170         control->class = I2C_CLASS_HWMON;
2171         control->dev.parent = &adev->pdev->dev;
2172         control->algo = &arcturus_i2c_algo;
2173         control->quirks = &arcturus_i2c_control_quirks;
2174         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2175
2176         res = i2c_add_adapter(control);
2177         if (res)
2178                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2179
2180         return res;
2181 }
2182
2183 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2184 {
2185         i2c_del_adapter(control);
2186 }
2187
2188 static void arcturus_get_unique_id(struct smu_context *smu)
2189 {
2190         struct amdgpu_device *adev = smu->adev;
2191         uint32_t top32 = 0, bottom32 = 0, smu_version;
2192         uint64_t id;
2193
2194         if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2195                 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2196                 return;
2197         }
2198
2199         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2200         if (smu_version < 0x361700) {
2201                 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2202                 return;
2203         }
2204
2205         /* Get the SN to turn into a Unique ID */
2206         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2207         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2208
2209         id = ((uint64_t)bottom32 << 32) | top32;
2210         adev->unique_id = id;
2211         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2212          * 16-digit HEX string for convenience and backwards-compatibility
2213          */
2214         sprintf(adev->serial, "%llx", id);
2215 }
2216
2217 static int arcturus_set_df_cstate(struct smu_context *smu,
2218                                   enum pp_df_cstate state)
2219 {
2220         uint32_t smu_version;
2221         int ret;
2222
2223         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2224         if (ret) {
2225                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2226                 return ret;
2227         }
2228
2229         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2230         if (smu_version < 0x360F00) {
2231                 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2232                 return -EINVAL;
2233         }
2234
2235         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2236 }
2237
2238 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2239 {
2240         uint32_t smu_version;
2241         int ret;
2242
2243         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2244         if (ret) {
2245                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2246                 return ret;
2247         }
2248
2249         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2250         if (smu_version < 0x00361700) {
2251                 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2252                 return -EINVAL;
2253         }
2254
2255         if (en)
2256                 return smu_cmn_send_smc_msg_with_param(smu,
2257                                                    SMU_MSG_GmiPwrDnControl,
2258                                                    1,
2259                                                    NULL);
2260
2261         return smu_cmn_send_smc_msg_with_param(smu,
2262                                            SMU_MSG_GmiPwrDnControl,
2263                                            0,
2264                                            NULL);
2265 }
2266
2267 static const struct throttling_logging_label {
2268         uint32_t feature_mask;
2269         const char *label;
2270 } logging_label[] = {
2271         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2272         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2273         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2274         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2275         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2276         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2277         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2278 };
2279 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2280 {
2281         int ret;
2282         int throttler_idx, throtting_events = 0, buf_idx = 0;
2283         struct amdgpu_device *adev = smu->adev;
2284         uint32_t throttler_status;
2285         char log_buf[256];
2286
2287         ret = arcturus_get_smu_metrics_data(smu,
2288                                             METRICS_THROTTLER_STATUS,
2289                                             &throttler_status);
2290         if (ret)
2291                 return;
2292
2293         memset(log_buf, 0, sizeof(log_buf));
2294         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2295              throttler_idx++) {
2296                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2297                         throtting_events++;
2298                         buf_idx += snprintf(log_buf + buf_idx,
2299                                             sizeof(log_buf) - buf_idx,
2300                                             "%s%s",
2301                                             throtting_events > 1 ? " and " : "",
2302                                             logging_label[throttler_idx].label);
2303                         if (buf_idx >= sizeof(log_buf)) {
2304                                 dev_err(adev->dev, "buffer overflow!\n");
2305                                 log_buf[sizeof(log_buf) - 1] = '\0';
2306                                 break;
2307                         }
2308                 }
2309         }
2310
2311         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2312                         log_buf);
2313         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
2314                 smu_cmn_get_indep_throttler_status(throttler_status,
2315                                                    arcturus_throttler_map));
2316 }
2317
2318 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2319 {
2320         struct amdgpu_device *adev = smu->adev;
2321         uint32_t esm_ctrl;
2322
2323         /* TODO: confirm this on real target */
2324         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2325         if ((esm_ctrl >> 15) & 0x1FFFF)
2326                 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
2327
2328         return smu_v11_0_get_current_pcie_link_speed(smu);
2329 }
2330
2331 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2332                                         void **table)
2333 {
2334         struct smu_table_context *smu_table = &smu->smu_table;
2335         struct gpu_metrics_v1_3 *gpu_metrics =
2336                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2337         SmuMetrics_t metrics;
2338         int ret = 0;
2339
2340         ret = smu_cmn_get_metrics_table(smu,
2341                                         &metrics,
2342                                         true);
2343         if (ret)
2344                 return ret;
2345
2346         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2347
2348         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2349         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2350         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2351         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2352         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2353         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2354
2355         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2356         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2357         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2358
2359         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2360         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2361
2362         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2363         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2364         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2365         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2366         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2367
2368         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2369         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2370         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2371         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2372         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2373
2374         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2375         gpu_metrics->indep_throttle_status =
2376                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2377                                                            arcturus_throttler_map);
2378
2379         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2380
2381         gpu_metrics->pcie_link_width =
2382                         smu_v11_0_get_current_pcie_link_width(smu);
2383         gpu_metrics->pcie_link_speed =
2384                         arcturus_get_current_pcie_link_speed(smu);
2385
2386         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2387
2388         *table = (void *)gpu_metrics;
2389
2390         return sizeof(struct gpu_metrics_v1_3);
2391 }
2392
2393 static const struct pptable_funcs arcturus_ppt_funcs = {
2394         /* init dpm */
2395         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2396         /* btc */
2397         .run_btc = arcturus_run_btc,
2398         /* dpm/clk tables */
2399         .set_default_dpm_table = arcturus_set_default_dpm_table,
2400         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2401         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2402         .print_clk_levels = arcturus_print_clk_levels,
2403         .force_clk_levels = arcturus_force_clk_levels,
2404         .read_sensor = arcturus_read_sensor,
2405         .get_fan_speed_pwm = arcturus_get_fan_speed_pwm,
2406         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2407         .get_power_profile_mode = arcturus_get_power_profile_mode,
2408         .set_power_profile_mode = arcturus_set_power_profile_mode,
2409         .set_performance_level = arcturus_set_performance_level,
2410         /* debug (internal used) */
2411         .dump_pptable = arcturus_dump_pptable,
2412         .get_power_limit = arcturus_get_power_limit,
2413         .is_dpm_running = arcturus_is_dpm_running,
2414         .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2415         .i2c_init = arcturus_i2c_control_init,
2416         .i2c_fini = arcturus_i2c_control_fini,
2417         .get_unique_id = arcturus_get_unique_id,
2418         .init_microcode = smu_v11_0_init_microcode,
2419         .load_microcode = smu_v11_0_load_microcode,
2420         .fini_microcode = smu_v11_0_fini_microcode,
2421         .init_smc_tables = arcturus_init_smc_tables,
2422         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2423         .init_power = smu_v11_0_init_power,
2424         .fini_power = smu_v11_0_fini_power,
2425         .check_fw_status = smu_v11_0_check_fw_status,
2426         /* pptable related */
2427         .setup_pptable = arcturus_setup_pptable,
2428         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2429         .check_fw_version = smu_v11_0_check_fw_version,
2430         .write_pptable = smu_cmn_write_pptable,
2431         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2432         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2433         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2434         .system_features_control = smu_v11_0_system_features_control,
2435         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2436         .send_smc_msg = smu_cmn_send_smc_msg,
2437         .init_display_count = NULL,
2438         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2439         .get_enabled_mask = smu_cmn_get_enabled_mask,
2440         .feature_is_enabled = smu_cmn_feature_is_enabled,
2441         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2442         .notify_display_change = NULL,
2443         .set_power_limit = smu_v11_0_set_power_limit,
2444         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2445         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2446         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2447         .set_min_dcef_deep_sleep = NULL,
2448         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2449         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2450         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2451         .set_fan_speed_pwm = arcturus_set_fan_speed_pwm,
2452         .set_fan_speed_rpm = arcturus_set_fan_speed_rpm,
2453         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2454         .gfx_off_control = smu_v11_0_gfx_off_control,
2455         .register_irq_handler = smu_v11_0_register_irq_handler,
2456         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2457         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2458         .baco_is_support = smu_v11_0_baco_is_support,
2459         .baco_get_state = smu_v11_0_baco_get_state,
2460         .baco_set_state = smu_v11_0_baco_set_state,
2461         .baco_enter = smu_v11_0_baco_enter,
2462         .baco_exit = smu_v11_0_baco_exit,
2463         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2464         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2465         .set_df_cstate = arcturus_set_df_cstate,
2466         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2467         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2468         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2469         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2470         .get_gpu_metrics = arcturus_get_gpu_metrics,
2471         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2472         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2473         .get_fan_parameters = arcturus_get_fan_parameters,
2474         .interrupt_work = smu_v11_0_interrupt_work,
2475         .set_light_sbr = smu_v11_0_set_light_sbr,
2476         .set_mp1_state = smu_cmn_set_mp1_state,
2477 };
2478
2479 void arcturus_set_ppt_funcs(struct smu_context *smu)
2480 {
2481         smu->ppt_funcs = &arcturus_ppt_funcs;
2482         smu->message_map = arcturus_message_map;
2483         smu->clock_map = arcturus_clk_map;
2484         smu->feature_map = arcturus_feature_mask_map;
2485         smu->table_map = arcturus_table_map;
2486         smu->pwr_src_map = arcturus_pwr_src_map;
2487         smu->workload_map = arcturus_workload_map;
2488 }