drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __SMU_V13_0_H__
  24 #define __SMU_V13_0_H__
  25
  26 #include "amdgpu_smu.h"
  27
  28 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
  29 #define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04
  30 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08
  31 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x05
  32 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
  33 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x30
  34 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
  35
  36 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  37
  38 /* MP Apertures */
  39 #define MP0_Public                      0x03800000
  40 #define MP0_SRAM                        0x03900000
  41 #define MP1_Public                      0x03b00000
  42 #define MP1_SRAM                        0x03c00004
  43
  44 /* address block */
  45 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  46 #define smnMP1_V13_0_4_FIRMWARE_FLAGS   0x3010028
  47 #define smnMP0_FW_INTF                  0x30101c0
  48 #define smnMP1_PUB_CTRL                 0x3010b14
  49
  50 #define TEMP_RANGE_MIN                  (0)
  51 #define TEMP_RANGE_MAX                  (80 * 1000)
  52
  53 #define SMU13_TOOL_SIZE                 0x19000
  54
  55 #define MAX_DPM_LEVELS 16
  56 #define MAX_PCIE_CONF 3
  57
  58 #define CTF_OFFSET_EDGE                 5
  59 #define CTF_OFFSET_HOTSPOT              5
  60 #define CTF_OFFSET_MEM                  5
  61
  62 struct smu_13_0_max_sustainable_clocks {
  63         uint32_t display_clock;
  64         uint32_t phy_clock;
  65         uint32_t pixel_clock;
  66         uint32_t uclock;
  67         uint32_t dcef_clock;
  68         uint32_t soc_clock;
  69 };
  70
  71 struct smu_13_0_dpm_clk_level {
  72         bool                            enabled;
  73         uint32_t                        value;
  74 };
  75
  76 struct smu_13_0_dpm_table {
  77         uint32_t                        min;        /* MHz */
  78         uint32_t                        max;        /* MHz */
  79         uint32_t                        count;
  80         bool                            is_fine_grained;
  81         struct smu_13_0_dpm_clk_level   dpm_levels[MAX_DPM_LEVELS];
  82 };
  83
  84 struct smu_13_0_pcie_table {
  85         uint8_t  pcie_gen[MAX_PCIE_CONF];
  86         uint8_t  pcie_lane[MAX_PCIE_CONF];
  87         uint16_t clk_freq[MAX_PCIE_CONF];
  88         uint32_t num_of_link_levels;
  89 };
  90
  91 struct smu_13_0_dpm_tables {
  92         struct smu_13_0_dpm_table        soc_table;
  93         struct smu_13_0_dpm_table        gfx_table;
  94         struct smu_13_0_dpm_table        uclk_table;
  95         struct smu_13_0_dpm_table        eclk_table;
  96         struct smu_13_0_dpm_table        vclk_table;
  97         struct smu_13_0_dpm_table        dclk_table;
  98         struct smu_13_0_dpm_table        dcef_table;
  99         struct smu_13_0_dpm_table        pixel_table;
 100         struct smu_13_0_dpm_table        display_table;
 101         struct smu_13_0_dpm_table        phy_table;
 102         struct smu_13_0_dpm_table        fclk_table;
 103         struct smu_13_0_pcie_table       pcie_table;
 104 };
 105
 106 struct smu_13_0_dpm_context {
 107         struct smu_13_0_dpm_tables  dpm_tables;
 108         uint32_t                    workload_policy_mask;
 109         uint32_t                    dcef_min_ds_clk;
 110 };
 111
 112 enum smu_13_0_power_state {
 113         SMU_13_0_POWER_STATE__D0 = 0,
 114         SMU_13_0_POWER_STATE__D1,
 115         SMU_13_0_POWER_STATE__D3, /* Sleep*/
 116         SMU_13_0_POWER_STATE__D4, /* Hibernate*/
 117         SMU_13_0_POWER_STATE__D5, /* Power off*/
 118 };
 119
 120 struct smu_13_0_power_context {
 121         uint32_t        power_source;
 122         uint8_t         in_power_limit_boost_mode;
 123         enum smu_13_0_power_state power_state;
 124 };
 125
 126 enum smu_v13_0_baco_seq {
 127         BACO_SEQ_BACO = 0,
 128         BACO_SEQ_MSR,
 129         BACO_SEQ_BAMACO,
 130         BACO_SEQ_ULPS,
 131         BACO_SEQ_COUNT,
 132 };
 133
 134 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
 135
 136 int smu_v13_0_init_microcode(struct smu_context *smu);
 137
 138 void smu_v13_0_fini_microcode(struct smu_context *smu);
 139
 140 int smu_v13_0_load_microcode(struct smu_context *smu);
 141
 142 int smu_v13_0_init_smc_tables(struct smu_context *smu);
 143
 144 int smu_v13_0_fini_smc_tables(struct smu_context *smu);
 145
 146 int smu_v13_0_init_power(struct smu_context *smu);
 147
 148 int smu_v13_0_fini_power(struct smu_context *smu);
 149
 150 int smu_v13_0_check_fw_status(struct smu_context *smu);
 151
 152 int smu_v13_0_setup_pptable(struct smu_context *smu);
 153
 154 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
 155
 156 int smu_v13_0_check_fw_version(struct smu_context *smu);
 157
 158 int smu_v13_0_set_driver_table_location(struct smu_context *smu);
 159
 160 int smu_v13_0_set_tool_table_location(struct smu_context *smu);
 161
 162 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
 163
 164 int smu_v13_0_system_features_control(struct smu_context *smu,
 165                                       bool en);
 166
 167 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);
 168
 169 int smu_v13_0_set_allowed_mask(struct smu_context *smu);
 170
 171 int smu_v13_0_notify_display_change(struct smu_context *smu);
 172
 173 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
 174                                       uint32_t *power_limit);
 175
 176 int smu_v13_0_set_power_limit(struct smu_context *smu,
 177                               enum smu_ppt_limit_type limit_type,
 178                               uint32_t limit);
 179
 180 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
 181
 182 int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
 183
 184 int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
 185
 186 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
 187
 188 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
 189
 190 int
 191 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
 192                                         struct pp_display_clock_request
 193                                         *clock_req);
 194
 195 uint32_t
 196 smu_v13_0_get_fan_control_mode(struct smu_context *smu);
 197
 198 int
 199 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
 200                                uint32_t mode);
 201
 202 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
 203                                 uint32_t speed);
 204
 205 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
 206                                 uint32_t speed);
 207
 208 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
 209                               uint32_t pstate);
 210
 211 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
 212
 213 int smu_v13_0_register_irq_handler(struct smu_context *smu);
 214
 215 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
 216
 217 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
 218                                                struct pp_smu_nv_clock_table *max_clocks);
 219
 220 bool smu_v13_0_baco_is_support(struct smu_context *smu);
 221
 222 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
 223
 224 int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
 225
 226 int smu_v13_0_baco_enter(struct smu_context *smu);
 227 int smu_v13_0_baco_exit(struct smu_context *smu);
 228
 229 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
 230                                     uint32_t *min, uint32_t *max);
 231
 232 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
 233                                           uint32_t min, uint32_t max);
 234
 235 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
 236                                           enum smu_clk_type clk_type,
 237                                           uint32_t min,
 238                                           uint32_t max);
 239
 240 int smu_v13_0_set_performance_level(struct smu_context *smu,
 241                                     enum amd_dpm_forced_level level);
 242
 243 int smu_v13_0_set_power_source(struct smu_context *smu,
 244                                enum smu_power_src_type power_src);
 245
 246 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
 247                                    enum smu_clk_type clk_type,
 248                                    struct smu_13_0_dpm_table *single_dpm_table);
 249
 250 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
 251                                   enum smu_clk_type clk_type,
 252                                   uint32_t *min_value,
 253                                   uint32_t *max_value);
 254
 255 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
 256
 257 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
 258
 259 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
 260
 261 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
 262
 263 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
 264                               bool enablement);
 265
 266 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
 267                              uint64_t event_arg);
 268
 269 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
 270                              bool enable);
 271
 272 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
 273                               bool enable);
 274
 275 int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
 276
 277 int smu_v13_0_run_btc(struct smu_context *smu);
 278
 279 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
 280                                  bool enablement);
 281
 282 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
 283
 284 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
 285                                 enum PP_OD_DPM_TABLE_COMMAND type,
 286                                 long input[],
 287                                 uint32_t size);
 288
 289 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
 290
 291 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
 292
 293 int smu_v13_0_mode1_reset(struct smu_context *smu);
 294
 295 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
 296                                         void **table,
 297                                         uint32_t *size,
 298                                         uint32_t pptable_id);
 299
 300 #endif
 301 #endif