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24 #ifndef __SMU13_DRIVER_IF_V13_0_4_H__
25 #define __SMU13_DRIVER_IF_V13_0_4_H__
28 // SMU TEAM: Always increment the interface version if
29 // any structure is changed in this file
30 #define PMFW_DRIVER_IF_VERSION 5
34 uint32_t numFractionalBits;
46 uint16_t Freq; // in MHz
47 uint16_t Vid; // min voltage in SVI3 VID
48 } DisplayClockTable_t;
51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
57 uint8_t WmType; // Used for normal pstate change or memory retraining
59 } WatermarkRowGeneric_t;
61 #define NUM_WM_RANGES 4
62 #define WM_PSTATE_CHG 0
63 #define WM_RETRAINING 1
73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
75 uint32_t MmHubPadding[7]; // SMU internal use
79 CUSTOM_DPM_SETTING_GFXCLK,
80 CUSTOM_DPM_SETTING_CCLK,
81 CUSTOM_DPM_SETTING_FCLK_CCX,
82 CUSTOM_DPM_SETTING_FCLK_GFX,
83 CUSTOM_DPM_SETTING_FCLK_STALLS,
84 CUSTOM_DPM_SETTING_LCLK,
85 CUSTOM_DPM_SETTING_COUNT,
86 } CUSTOM_DPM_SETTING_e;
89 uint8_t ActiveHystLimit;
90 uint8_t IdleHystLimit;
92 uint8_t MinActiveFreqType;
93 FloatInIntFormat_t MinActiveFreq;
94 FloatInIntFormat_t PD_Data_limit;
95 FloatInIntFormat_t PD_Data_time_constant;
96 FloatInIntFormat_t PD_Data_error_coeff;
97 FloatInIntFormat_t PD_Data_error_rate_coeff;
98 } DpmActivityMonitorCoeffExt_t;
101 DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
102 } CustomDpmSettings_t;
104 #define NUM_DCFCLK_DPM_LEVELS 8
105 #define NUM_DISPCLK_DPM_LEVELS 8
106 #define NUM_DPPCLK_DPM_LEVELS 8
107 #define NUM_SOCCLK_DPM_LEVELS 8
108 #define NUM_VCN_DPM_LEVELS 8
109 #define NUM_SOC_VOLTAGE_LEVELS 8
110 #define NUM_DF_PSTATE_LEVELS 4
121 //Voltage in milli volts with 2 fractional bits
123 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
124 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
125 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
126 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
127 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
128 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
129 uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
130 DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
132 uint8_t NumDcfClkLevelsEnabled;
133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
134 uint8_t NumSocClkLevelsEnabled;
135 uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
136 uint8_t NumDfPstatesEnabled;
144 // Throttler Status Bitmask
145 #define THROTTLER_STATUS_BIT_SPL 0
146 #define THROTTLER_STATUS_BIT_FPPT 1
147 #define THROTTLER_STATUS_BIT_SPPT 2
148 #define THROTTLER_STATUS_BIT_SPPT_APU 3
149 #define THROTTLER_STATUS_BIT_THM_CORE 4
150 #define THROTTLER_STATUS_BIT_THM_GFX 5
151 #define THROTTLER_STATUS_BIT_THM_SOC 6
152 #define THROTTLER_STATUS_BIT_TDC_VDD 7
153 #define THROTTLER_STATUS_BIT_TDC_SOC 8
154 #define THROTTLER_STATUS_BIT_PROCHOT_CPU 9
155 #define THROTTLER_STATUS_BIT_PROCHOT_GFX 10
156 #define THROTTLER_STATUS_BIT_EDC_CPU 11
157 #define THROTTLER_STATUS_BIT_EDC_GFX 12
160 uint16_t GfxclkFrequency; //[MHz]
161 uint16_t SocclkFrequency; //[MHz]
162 uint16_t VclkFrequency; //[MHz]
163 uint16_t DclkFrequency; //[MHz]
164 uint16_t MemclkFrequency; //[MHz]
165 uint16_t spare; //[centi]
166 uint16_t UvdActivity; //[centi]
167 uint16_t GfxActivity; //[centi]
169 uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
170 uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC
171 uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
173 //3rd party tools in Windows need this info in the case of APUs
174 uint16_t CoreFrequency[8]; //[MHz]
175 uint16_t CorePower[8]; //[mW]
176 uint16_t CoreTemperature[8]; //[centi-Celsius]
177 uint16_t L3Frequency; //[MHz]
178 uint16_t L3Temperature; //[centi-Celsius]
180 uint16_t GfxTemperature; //[centi-Celsius]
181 uint16_t SocTemperature; //[centi-Celsius]
182 uint16_t ThrottlerStatus;
184 uint16_t CurrentSocketPower; //[mW]
185 uint16_t StapmOpnLimit; //[W]
186 uint16_t StapmCurrentLimit; //[W]
187 uint32_t ApuPower; //[mW]
188 uint32_t dGpuPower; //[mW]
190 uint16_t VddTdcValue; //[mA]
191 uint16_t SocTdcValue; //[mA]
192 uint16_t VddEdcValue; //[mA]
193 uint16_t SocEdcValue; //[mA]
195 uint16_t InfrastructureCpuMaxFreq; //[MHz]
196 uint16_t InfrastructureGfxMaxFreq; //[MHz]
199 uint16_t DeviceState;
200 uint16_t CurTemp; //[centi-Celsius]
205 uint16_t StapmMaxPlatformLimit; //[W]
206 uint16_t StapmMinPlatformLimit; //[W]
207 uint16_t FastPptMaxPlatformLimit; //[W]
208 uint16_t FastPptMinPlatformLimit; //[W]
209 uint16_t SlowPptMaxPlatformLimit; //[W]
210 uint16_t SlowPptMinPlatformLimit; //[W]
211 uint16_t SlowPptApuMaxPlatformLimit; //[W]
212 uint16_t SlowPptApuMinPlatformLimit; //[W]
215 //ISP tile definitions
217 TILE_ISPX = 0, // ISPX
219 TILE_ISPC, // ISPCORE
220 TILE_ISPPRE, // ISPPRE
221 TILE_ISPPOST0, // ISPPOST0,
222 TILE_ISPPOST1, // ISPPOST1
226 // Tile Selection (Based on arguments)
227 #define TILE_SEL_ISPX (1<<(TILE_ISPX))
228 #define TILE_SEL_ISPM (1<<(TILE_ISPM))
229 #define TILE_SEL_ISPC (1<<(TILE_ISPC))
230 #define TILE_SEL_ISPPRE (1<<(TILE_ISPPRE))
231 #define TILE_SEL_ISPPOST0 (1<<(TILE_ISPPOST0))
232 #define TILE_SEL_ISPPOST1 (1<<(TILE_ISPPOST1))
235 // Mask for ISP tiles in PGFSM PWR Status Registers
236 //Bit[1:0] maps to ISPX, (ISPX)
237 //Bit[3:2] maps to ISPM, (ISPM)
238 //Bit[5:4] maps to ISPCORE, (ISPCORE)
239 //Bit[7:6] maps to ISPPRE, (ISPPRE)
240 //Bit[9:8] maps to POST, (ISPPOST
241 #define TILE_ISPX_MASK ((1<<0) | (1<<1))
242 #define TILE_ISPM_MASK ((1<<2) | (1<<3))
243 #define TILE_ISPC_MASK ((1<<4) | (1<<5))
244 #define TILE_ISPPRE_MASK ((1<<6) | (1<<7))
245 #define TILE_ISPPOST0_MASK ((1<<8) | (1<<9))
246 #define TILE_ISPPOST1_MASK ((1<<10) | (1<<11))
250 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
251 #define WORKLOAD_PPLIB_VIDEO_BIT 2
252 #define WORKLOAD_PPLIB_VR_BIT 3
253 #define WORKLOAD_PPLIB_COMPUTE_BIT 4
254 #define WORKLOAD_PPLIB_CUSTOM_BIT 5
255 #define WORKLOAD_PPLIB_COUNT 6
257 #define TABLE_BIOS_IF 0 // Called by BIOS
258 #define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
259 #define TABLE_CUSTOM_DPM 2 // Called by Driver
260 #define TABLE_SPARE1 3
261 #define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
262 #define TABLE_MOMENTARY_PM 5 // Called by Tools
263 #define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
264 #define TABLE_SMU_METRICS 7 // Called by Driver and PMF
265 #define TABLE_INFRASTRUCTURE_LIMITS 8 // Called by PMF
266 #define TABLE_COUNT 9