2 * Copyright 2021 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef SMU13_DRIVER_IF_V13_0_0_H
25 #define SMU13_DRIVER_IF_V13_0_0_H
27 //Increment this version if SkuTable_t or BoardTable_t change
28 #define PPTABLE_VERSION 0x26
30 #define NUM_GFXCLK_DPM_LEVELS 16
31 #define NUM_SOCCLK_DPM_LEVELS 8
32 #define NUM_MP0CLK_DPM_LEVELS 2
33 #define NUM_DCLK_DPM_LEVELS 8
34 #define NUM_VCLK_DPM_LEVELS 8
35 #define NUM_DISPCLK_DPM_LEVELS 8
36 #define NUM_DPPCLK_DPM_LEVELS 8
37 #define NUM_DPREFCLK_DPM_LEVELS 8
38 #define NUM_DCFCLK_DPM_LEVELS 8
39 #define NUM_DTBCLK_DPM_LEVELS 8
40 #define NUM_UCLK_DPM_LEVELS 4
41 #define NUM_LINK_LEVELS 3
42 #define NUM_FCLK_DPM_LEVELS 8
43 #define NUM_OD_FAN_MAX_POINTS 6
45 // Feature Control Defines
46 #define FEATURE_FW_DATA_READ_BIT 0
47 #define FEATURE_DPM_GFXCLK_BIT 1
48 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2
49 #define FEATURE_DPM_UCLK_BIT 3
50 #define FEATURE_DPM_FCLK_BIT 4
51 #define FEATURE_DPM_SOCCLK_BIT 5
52 #define FEATURE_DPM_MP0CLK_BIT 6
53 #define FEATURE_DPM_LINK_BIT 7
54 #define FEATURE_DPM_DCN_BIT 8
55 #define FEATURE_VMEMP_SCALING_BIT 9
56 #define FEATURE_VDDIO_MEM_SCALING_BIT 10
57 #define FEATURE_DS_GFXCLK_BIT 11
58 #define FEATURE_DS_SOCCLK_BIT 12
59 #define FEATURE_DS_FCLK_BIT 13
60 #define FEATURE_DS_LCLK_BIT 14
61 #define FEATURE_DS_DCFCLK_BIT 15
62 #define FEATURE_DS_UCLK_BIT 16
63 #define FEATURE_GFX_ULV_BIT 17
64 #define FEATURE_FW_DSTATE_BIT 18
65 #define FEATURE_GFXOFF_BIT 19
66 #define FEATURE_BACO_BIT 20
67 #define FEATURE_MM_DPM_BIT 21
68 #define FEATURE_SOC_MPCLK_DS_BIT 22
69 #define FEATURE_BACO_MPCLK_DS_BIT 23
70 #define FEATURE_THROTTLERS_BIT 24
71 #define FEATURE_SMARTSHIFT_BIT 25
72 #define FEATURE_GTHR_BIT 26
73 #define FEATURE_ACDC_BIT 27
74 #define FEATURE_VR0HOT_BIT 28
75 #define FEATURE_FW_CTF_BIT 29
76 #define FEATURE_FAN_CONTROL_BIT 30
77 #define FEATURE_GFX_DCS_BIT 31
78 #define FEATURE_GFX_READ_MARGIN_BIT 32
79 #define FEATURE_LED_DISPLAY_BIT 33
80 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34
81 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35
82 #define FEATURE_OPTIMIZED_VMIN_BIT 36
83 #define FEATURE_GFX_IMU_BIT 37
84 #define FEATURE_BOOT_TIME_CAL_BIT 38
85 #define FEATURE_GFX_PCC_DFLL_BIT 39
86 #define FEATURE_SOC_CG_BIT 40
87 #define FEATURE_DF_CSTATE_BIT 41
88 #define FEATURE_GFX_EDC_BIT 42
89 #define FEATURE_BOOT_POWER_OPT_BIT 43
90 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44
91 #define FEATURE_DS_VCN_BIT 45
92 #define FEATURE_BACO_CG_BIT 46
93 #define FEATURE_MEM_TEMP_READ_BIT 47
94 #define FEATURE_ATHUB_MMHUB_PG_BIT 48
95 #define FEATURE_SOC_PCC_BIT 49
96 #define FEATURE_EDC_PWRBRK_BIT 50
97 #define FEATURE_SPARE_51_BIT 51
98 #define FEATURE_SPARE_52_BIT 52
99 #define FEATURE_SPARE_53_BIT 53
100 #define FEATURE_SPARE_54_BIT 54
101 #define FEATURE_SPARE_55_BIT 55
102 #define FEATURE_SPARE_56_BIT 56
103 #define FEATURE_SPARE_57_BIT 57
104 #define FEATURE_SPARE_58_BIT 58
105 #define FEATURE_SPARE_59_BIT 59
106 #define FEATURE_SPARE_60_BIT 60
107 #define FEATURE_SPARE_61_BIT 61
108 #define FEATURE_SPARE_62_BIT 62
109 #define FEATURE_SPARE_63_BIT 63
110 #define NUM_FEATURES 64
112 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL
113 #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \
114 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
115 (1 << FEATURE_DPM_UCLK_BIT) | \
116 (1 << FEATURE_DPM_FCLK_BIT) | \
117 (1 << FEATURE_DPM_SOCCLK_BIT) | \
118 (1 << FEATURE_DPM_MP0CLK_BIT) | \
119 (1 << FEATURE_DPM_LINK_BIT) | \
120 (1 << FEATURE_DPM_DCN_BIT) | \
121 (1 << FEATURE_DS_GFXCLK_BIT) | \
122 (1 << FEATURE_DS_SOCCLK_BIT) | \
123 (1 << FEATURE_DS_FCLK_BIT) | \
124 (1 << FEATURE_DS_LCLK_BIT) | \
125 (1 << FEATURE_DS_DCFCLK_BIT) | \
126 (1 << FEATURE_DS_UCLK_BIT))
128 //For use with feature control messages
135 FEATURE_PWR_DOMAIN_COUNT,
136 } FEATURE_PWR_DOMAIN_e;
139 // Debug Overrides Bitmask
140 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001
141 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002
142 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004
143 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008
144 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010
145 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020
146 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040
147 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080
148 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100
149 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200
150 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400
151 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800
152 #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000
154 // VR Mapping Bit Defines
155 #define VR_MAPPING_VR_SELECT_MASK 0x01
156 #define VR_MAPPING_VR_SELECT_SHIFT 0x00
158 #define VR_MAPPING_PLANE_SELECT_MASK 0x02
159 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
162 #define PSI_SEL_VR0_PLANE0_PSI0 0x01
163 #define PSI_SEL_VR0_PLANE0_PSI1 0x02
164 #define PSI_SEL_VR0_PLANE1_PSI0 0x04
165 #define PSI_SEL_VR0_PLANE1_PSI1 0x08
166 #define PSI_SEL_VR1_PLANE0_PSI0 0x10
167 #define PSI_SEL_VR1_PLANE0_PSI1 0x20
168 #define PSI_SEL_VR1_PLANE1_PSI0 0x40
169 #define PSI_SEL_VR1_PLANE1_PSI1 0x80
172 SVI_PSI_0, // Full phase count (default)
173 SVI_PSI_1, // Phase count 1st level
174 SVI_PSI_2, // Phase count 2nd level
175 SVI_PSI_3, // Single phase operation + active diode emulation
176 SVI_PSI_4, // Single phase operation + passive diode emulation *optional*
177 SVI_PSI_5, // Reserved
178 SVI_PSI_6, // Power down to 0V (voltage regulation disabled)
179 SVI_PSI_7, // Automated phase shedding and diode emulation
182 // Throttler Control/Status Bits
183 #define THROTTLER_TEMP_EDGE_BIT 0
184 #define THROTTLER_TEMP_HOTSPOT_BIT 1
185 #define THROTTLER_TEMP_HOTSPOT_G_BIT 2
186 #define THROTTLER_TEMP_HOTSPOT_M_BIT 3
187 #define THROTTLER_TEMP_MEM_BIT 4
188 #define THROTTLER_TEMP_VR_GFX_BIT 5
189 #define THROTTLER_TEMP_VR_MEM0_BIT 6
190 #define THROTTLER_TEMP_VR_MEM1_BIT 7
191 #define THROTTLER_TEMP_VR_SOC_BIT 8
192 #define THROTTLER_TEMP_VR_U_BIT 9
193 #define THROTTLER_TEMP_LIQUID0_BIT 10
194 #define THROTTLER_TEMP_LIQUID1_BIT 11
195 #define THROTTLER_TEMP_PLX_BIT 12
196 #define THROTTLER_TDC_GFX_BIT 13
197 #define THROTTLER_TDC_SOC_BIT 14
198 #define THROTTLER_TDC_U_BIT 15
199 #define THROTTLER_PPT0_BIT 16
200 #define THROTTLER_PPT1_BIT 17
201 #define THROTTLER_PPT2_BIT 18
202 #define THROTTLER_PPT3_BIT 19
203 #define THROTTLER_FIT_BIT 20
204 #define THROTTLER_GFX_APCC_PLUS_BIT 21
205 #define THROTTLER_COUNT 22
207 // FW DState Features Control Bits
208 #define FW_DSTATE_SOC_ULV_BIT 0
209 #define FW_DSTATE_G6_HSR_BIT 1
210 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2
211 #define FW_DSTATE_SMN_DS_BIT 3
212 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4
213 #define FW_DSTATE_SOC_LIV_MIN_BIT 5
214 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6
215 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7
216 #define FW_DSTATE_MALL_ALLOC_BIT 8
217 #define FW_DSTATE_MEM_PSI_BIT 9
218 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
219 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11
220 #define FW_DSTATE_U_ULV_BIT 12
221 #define FW_DSTATE_MALL_FLUSH_BIT 13
222 #define FW_DSTATE_SOC_PSI_BIT 14
223 #define FW_DSTATE_U_PSI_BIT 15
224 #define FW_DSTATE_UCP_DS_BIT 16
225 #define FW_DSTATE_CSRCLK_DS_BIT 17
226 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18
227 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19
228 #define FW_DSTATE_CLDO_PRG_BIT 20
229 #define FW_DSTATE_DF_PLL_PWRDN_BIT 21
230 #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22
231 #define FW_DSTATE_GFX_PSI6_BIT 23
232 #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24
234 //LED Display Mask & Control Bits
235 #define LED_DISPLAY_GFX_DPM_BIT 0
236 #define LED_DISPLAY_PCIE_BIT 1
237 #define LED_DISPLAY_ERROR_BIT 2
240 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0
241 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1
242 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2
245 SMARTSHIFT_VERSION_1,
246 SMARTSHIFT_VERSION_2,
247 SMARTSHIFT_VERSION_3,
248 } SMARTSHIFT_VERSION_e;
251 FOPT_CALC_AC_CALC_DC,
252 FOPT_PPTABLE_AC_CALC_DC,
253 FOPT_CALC_AC_PPTABLE_DC,
254 FOPT_PPTABLE_AC_PPTABLE_DC,
258 DRAM_BIT_WIDTH_DISABLED = 0,
259 DRAM_BIT_WIDTH_X_8 = 8,
260 DRAM_BIT_WIDTH_X_16 = 16,
261 DRAM_BIT_WIDTH_X_32 = 32,
262 DRAM_BIT_WIDTH_X_64 = 64,
263 DRAM_BIT_WIDTH_X_128 = 128,
264 DRAM_BIT_WIDTH_COUNT,
265 } DRAM_BIT_WIDTH_TYPE_e;
268 #define NUM_I2C_CONTROLLERS 8
270 #define I2C_CONTROLLER_ENABLED 1
271 #define I2C_CONTROLLER_DISABLED 0
273 #define MAX_SW_I2C_COMMANDS 24
276 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0
277 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1
278 I2C_CONTROLLER_PORT_COUNT,
279 } I2cControllerPort_e;
282 I2C_CONTROLLER_NAME_VR_GFX = 0,
283 I2C_CONTROLLER_NAME_VR_SOC,
284 I2C_CONTROLLER_NAME_VR_VMEMP,
285 I2C_CONTROLLER_NAME_VR_VDDIO,
286 I2C_CONTROLLER_NAME_LIQUID0,
287 I2C_CONTROLLER_NAME_LIQUID1,
288 I2C_CONTROLLER_NAME_PLX,
289 I2C_CONTROLLER_NAME_FAN_INTAKE,
290 I2C_CONTROLLER_NAME_COUNT,
291 } I2cControllerName_e;
294 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
295 I2C_CONTROLLER_THROTTLER_VR_GFX,
296 I2C_CONTROLLER_THROTTLER_VR_SOC,
297 I2C_CONTROLLER_THROTTLER_VR_VMEMP,
298 I2C_CONTROLLER_THROTTLER_VR_VDDIO,
299 I2C_CONTROLLER_THROTTLER_LIQUID0,
300 I2C_CONTROLLER_THROTTLER_LIQUID1,
301 I2C_CONTROLLER_THROTTLER_PLX,
302 I2C_CONTROLLER_THROTTLER_FAN_INTAKE,
303 I2C_CONTROLLER_THROTTLER_INA3221,
304 I2C_CONTROLLER_THROTTLER_COUNT,
305 } I2cControllerThrottler_e;
308 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
309 I2C_CONTROLLER_PROTOCOL_VR_IR35217,
310 I2C_CONTROLLER_PROTOCOL_TMP_MAX31875,
311 I2C_CONTROLLER_PROTOCOL_INA3221,
312 I2C_CONTROLLER_PROTOCOL_COUNT,
313 } I2cControllerProtocol_e;
318 uint8_t SlaveAddress;
319 uint8_t ControllerPort;
320 uint8_t ControllerName;
321 uint8_t ThermalThrotter;
323 uint8_t PaddingConfig;
324 } I2cControllerConfig_t;
327 I2C_PORT_SVD_SCL = 0,
332 I2C_SPEED_FAST_50K = 0, //50 Kbits/s
333 I2C_SPEED_FAST_100K, //100 Kbits/s
334 I2C_SPEED_FAST_400K, //400 Kbits/s
335 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
336 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode)
337 I2C_SPEED_HIGH_2M, //2.3 Mbits/s
347 #define CMDCONFIG_STOP_BIT 0
348 #define CMDCONFIG_RESTART_BIT 1
349 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write
351 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
352 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
353 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT)
356 uint8_t ReadWriteData; //Return data for read. Data to send for write
357 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write
358 } SwI2cCmd_t; //SW I2C Command Table
361 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
362 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select
363 uint8_t SlaveAddress; //Slave address of device
364 uint8_t NumCmds; //Number of commands
366 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
367 } SwI2cRequest_t; // SW I2C Request Table
370 SwI2cRequest_t SwI2cRequest;
373 uint32_t MmHubPadding[8]; // SMU internal use
374 } SwI2cRequestExternal_t;
377 uint64_t mca_umc_status;
378 uint64_t mca_umc_addr;
380 uint16_t ce_count_lo_chip;
381 uint16_t ce_count_hi_chip;
387 EccInfo_t EccInfo[24];
396 D3HOT_SEQUENCE_COUNT,
399 //This is aligned with RSMU PGFSM Register Mapping
405 //This is aligned with RSMU PGFSM Register Mapping
409 } PowerGatingSettings_e;
412 uint32_t a; // store in IEEE float format in this variable
413 uint32_t b; // store in IEEE float format in this variable
414 uint32_t c; // store in IEEE float format in this variable
418 uint32_t m; // store in IEEE float format in this variable
419 uint32_t b; // store in IEEE float format in this variable
423 uint32_t a; // store in IEEE float format in this variable
424 uint32_t b; // store in IEEE float format in this variable
425 uint32_t c; // store in IEEE float format in this variable
434 //Only Clks that have DPM descriptors are listed here
453 VOLTAGE_MODE_PPTABLE = 0,
460 AVFS_VOLTAGE_GFX = 0,
463 } AVFS_VOLTAGE_TYPE_e;
486 GPIO_INT_POLARITY_ACTIVE_LOW = 0,
487 GPIO_INT_POLARITY_ACTIVE_HIGH,
493 PWR_CONFIG_TCP_ESTIMATED,
494 PWR_CONFIG_TCP_MEASURED,
499 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
500 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
501 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e
502 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
503 uint32_t Padding3[3];
505 uint16_t FoptimalDc; //Foptimal frequency in DC power mode.
506 uint16_t FoptimalAc; //Foptimal frequency in AC power mode.
554 PMFW_VOLT_PLANE_COUNT
558 CUSTOMER_VARIANT_ROW,
559 CUSTOMER_VARIANT_FALCON,
560 CUSTOMER_VARIANT_COUNT,
561 } CUSTOMER_VARIANT_e;
579 MEM_VENDOR_PLACEHOLDER0,
580 MEM_VENDOR_PLACEHOLDER1,
581 MEM_VENDOR_PLACEHOLDER2,
582 MEM_VENDOR_PLACEHOLDER3,
583 MEM_VENDOR_PLACEHOLDER4,
584 MEM_VENDOR_PLACEHOLDER5,
590 PP_GRTAVFS_HW_CPO_CTL_ZONE0,
591 PP_GRTAVFS_HW_CPO_CTL_ZONE1,
592 PP_GRTAVFS_HW_CPO_CTL_ZONE2,
593 PP_GRTAVFS_HW_CPO_CTL_ZONE3,
594 PP_GRTAVFS_HW_CPO_CTL_ZONE4,
595 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0,
596 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0,
597 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1,
598 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1,
599 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2,
600 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2,
601 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3,
602 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3,
603 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4,
604 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4,
605 PP_GRTAVFS_HW_ZONE0_VF,
606 PP_GRTAVFS_HW_ZONE1_VF1,
607 PP_GRTAVFS_HW_ZONE2_VF2,
608 PP_GRTAVFS_HW_ZONE3_VF3,
609 PP_GRTAVFS_HW_VOLTAGE_GB,
610 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0,
611 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1,
612 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2,
613 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3,
614 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4,
615 PP_GRTAVFS_HW_RESERVED_0,
616 PP_GRTAVFS_HW_RESERVED_1,
617 PP_GRTAVFS_HW_RESERVED_2,
618 PP_GRTAVFS_HW_RESERVED_3,
619 PP_GRTAVFS_HW_RESERVED_4,
620 PP_GRTAVFS_HW_RESERVED_5,
621 PP_GRTAVFS_HW_RESERVED_6,
622 PP_GRTAVFS_HW_FUSE_COUNT,
623 } PP_GRTAVFS_HW_FUSE_e;
626 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0,
627 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0,
628 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0,
629 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0,
630 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0,
631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0,
632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0,
633 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0,
634 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0,
635 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1,
636 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2,
637 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3,
638 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4,
639 PP_GRTAVFS_FW_COMMON_FUSE_COUNT,
640 } PP_GRTAVFS_FW_COMMON_FUSE_e;
643 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1,
644 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0,
645 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1,
646 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2,
647 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3,
648 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4,
649 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1,
650 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0,
651 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1,
652 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2,
653 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3,
654 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4,
655 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY,
656 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY,
657 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0,
658 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1,
659 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2,
660 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3,
661 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4,
662 PP_GRTAVFS_FW_SEP_FUSE_COUNT,
663 } PP_GRTAVFS_FW_SEP_FUSE_e;
665 #define PP_NUM_RTAVFS_PWL_ZONES 5
669 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3
670 // Slope Q1.7, Offset Q1.2
672 int8_t Offset; // in Amps
674 uint16_t MaxCurrent; // in Amps
675 } SviTelemetryScale_t;
677 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1
681 FAN_MODE_MANUAL_LINEAR,
685 uint32_t FeatureCtrlMask;
688 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS];
689 uint16_t VddGfxVmax; // in mV
691 uint8_t IdlePwrSavingFeaturesCtrl;
692 uint8_t RuntimePwrSavingFeaturesCtrl;
695 int16_t GfxclkFmin; // MHz
696 int16_t GfxclkFmax; // MHz
697 uint16_t UclkFmin; // MHz
698 uint16_t UclkFmax; // MHz
705 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
706 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
707 uint16_t FanMinimumPwm;
708 uint16_t AcousticTargetRpmThreshold;
709 uint16_t AcousticLimitRpmThreshold;
710 uint16_t FanTargetTemperature; // Degree Celcius
711 uint8_t FanZeroRpmEnable;
712 uint8_t FanZeroRpmStopTemp;
717 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround
721 OverDriveTable_t OverDriveTable;
723 } OverDriveTableExternal_t;
726 uint32_t FeatureCtrlMask;
728 int16_t VoltageOffsetPerZoneBoundary;
729 uint16_t VddGfxVmax; // in mV
731 uint8_t IdlePwrSavingFeaturesCtrl;
732 uint8_t RuntimePwrSavingFeaturesCtrl;
734 int16_t GfxclkFmin; // MHz
735 int16_t GfxclkFmax; // MHz
736 uint16_t UclkFmin; // MHz
737 uint16_t UclkFmax; // MHz
743 uint8_t FanLinearPwmPoints;
744 uint8_t FanLinearTempPoints;
745 uint16_t FanMinimumPwm;
746 uint16_t AcousticTargetRpmThreshold;
747 uint16_t AcousticLimitRpmThreshold;
748 uint16_t FanTargetTemperature; // Degree Celcius
749 uint8_t FanZeroRpmEnable;
750 uint8_t FanZeroRpmStopTemp;
792 MAX_BOARD_GPIO_SMUIO_NUM,
800 BOARD_GPIO_DC_GENLK_CLK,
801 BOARD_GPIO_DC_GENLK_VSYNC,
802 BOARD_GPIO_DC_SWAPLOCK_A,
803 BOARD_GPIO_DC_SWAPLOCK_B,
806 #define INVALID_BOARD_GPIO 0xFF
811 uint16_t InitGfxclk_bypass;
814 uint16_t InitMpioclk;
820 uint16_t InitDprefclk;
824 uint16_t InitDclk; //assume same DCLK/VCLK for both instances
827 uint16_t InitUsbdfsclk;
830 uint16_t InitBaco400clk_bypass;
831 uint16_t InitBaco1200clk_bypass;
832 uint16_t InitBaco700clk_bypass;
836 uint16_t InitGfxclk_clkb;
839 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk
843 uint32_t InitVcoFreqPll0;
844 uint32_t InitVcoFreqPll1;
845 uint32_t InitVcoFreqPll2;
846 uint32_t InitVcoFreqPll3;
847 uint32_t InitVcoFreqPll4;
848 uint32_t InitVcoFreqPll5;
849 uint32_t InitVcoFreqPll6;
851 //encoding will change depending on SVI2/SVI3
852 uint16_t InitGfx; // In mV(Q2) , should be 0?
853 uint16_t InitSoc; // In mV(Q2)
854 uint16_t InitU; // In Mv(Q2)
864 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts
865 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps
867 uint16_t Temperature[TEMP_COUNT]; // Celsius
871 uint8_t FanTargetTemperature;
874 uint16_t AcousticTargetRpmThresholdMin;
875 uint16_t AcousticTargetRpmThresholdMax;
877 uint16_t AcousticLimitRpmThresholdMin;
878 uint16_t AcousticLimitRpmThresholdMax;
880 uint16_t PccLimitMin;
881 uint16_t PccLimitMax;
883 uint16_t FanStopTempMin;
884 uint16_t FanStopTempMax;
885 uint16_t FanStartTempMin;
886 uint16_t FanStartTempMax;
888 uint16_t PowerMinPpt0[POWER_SOURCE_COUNT];
894 uint16_t BaseClockAc;
895 uint16_t GameClockAc;
896 uint16_t BoostClockAc;
897 uint16_t BaseClockDc;
898 uint16_t GameClockDc;
899 uint16_t BoostClockDc;
901 uint32_t Reserved[4];
902 } DriverReportedClocks_t;
905 uint8_t DcBtcEnabled;
908 uint16_t DcTol; // mV Q2
909 uint16_t DcBtcGb; // mV Q2
911 uint16_t DcBtcMin; // mV Q2
912 uint16_t DcBtcMax; // mV Q2
914 LinearInt_t DcBtcGbScalar;
919 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C
920 uint16_t VftFMin; // in MHz
921 uint16_t VInversion; // in mV Q2
922 QuadraticInt_t qVft[AVFS_TEMP_COUNT];
923 QuadraticInt_t qAvfsGb;
924 QuadraticInt_t qAvfsGb2;
925 } AvfsFuseOverride_t;
930 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different)
932 // SECTION: Feature Control
933 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping
935 // SECTION: Miscellaneous Configuration
936 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e
937 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e
938 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT
939 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e
941 // SECTION: Infrastructure Limits
942 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported
943 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported
945 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift
947 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars
949 uint8_t EnableLegacyPptLimit;
950 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support
951 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting
953 uint8_t PaddingPpt[1];
955 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature
957 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail
959 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input
961 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only
963 uint16_t PaddingInfra;
965 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years)
966 uint32_t FitControllerFailureRateLimit; //in IEEE float
967 //Expected GFX Duty Cycle at Vmax.
968 uint32_t FitControllerGfxDutyCycle; // in IEEE float
969 //Expected SOC Duty Cycle at Vmax.
970 uint32_t FitControllerSocDutyCycle; // in IEEE float
972 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block.
973 uint32_t FitControllerSocOffset; //in IEEE float
975 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value
977 // SECTION: Throttler settings
978 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping
980 // SECTION: FW DSTATE Settings
981 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping
983 // SECTION: Voltage Control Parameters
984 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE)
986 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE)
987 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE
990 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled
991 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled
994 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin
995 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin
996 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot.
997 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold.
998 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot.
999 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold.
1000 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin
1001 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot
1002 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold
1004 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for.
1005 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT];
1006 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts.
1007 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT];
1008 //Scalar coefficient of the PSM aging degradation function
1009 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM
1010 //Exponential coefficient of the PSM aging degradation function
1011 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM
1012 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold.
1013 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN
1014 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold.
1015 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN
1017 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT];
1018 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT];
1020 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
1021 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
1023 QuadraticInt_t Vmin_droop;
1024 uint32_t SpareVmin[9];
1027 //SECTION: DPM Configuration 1
1028 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
1030 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
1031 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz
1032 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz
1033 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz
1034 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1035 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
1036 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz
1037 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz
1038 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz
1039 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz
1040 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1042 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
1044 // SECTION: DPM Configuration 2
1045 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
1046 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
1048 uint8_t GfxclkSpare[2];
1049 uint16_t GfxclkFreqCap;
1051 //GFX Idle Power Settings
1052 uint16_t GfxclkFgfxoffEntry; // in Mhz
1053 uint16_t GfxclkFgfxoffExitImu; // in Mhz
1054 uint16_t GfxclkFgfxoffExitRlc; // in Mhz
1055 uint16_t GfxclkThrottleClock; //Used primarily in DCS
1056 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
1057 uint8_t GfxIdlePadding;
1059 uint8_t SmsRepairWRCKClkDivEn;
1060 uint8_t SmsRepairWRCKClkDivVal;
1061 uint8_t GfxOffEntryEarlyMGCGEn;
1062 uint8_t GfxOffEntryForceCGCGEn;
1063 uint8_t GfxOffEntryForceCGCGDelayEn;
1064 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds
1066 uint16_t GfxclkFreqGfxUlv; // in MHz
1067 uint8_t GfxIdlePadding2[2];
1069 uint32_t GfxOffEntryHysteresis;
1070 uint32_t GfxoffSpare[15];
1073 uint32_t DfllBtcMasterScalerM;
1074 int32_t DfllBtcMasterScalerB;
1075 uint32_t DfllBtcSlaveScalerM;
1076 int32_t DfllBtcSlaveScalerB;
1078 uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg
1079 uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg
1081 uint32_t DfllL2FrequencyBoostM; //Unitless (float)
1082 uint32_t DfllL2FrequencyBoostB; //In MHz (integer)
1083 uint32_t GfxGpoSpare[8];
1087 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase
1088 uint16_t PaddingDcs;
1090 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
1091 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
1093 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1095 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
1096 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
1099 uint32_t DcsSpare[16];
1102 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations
1103 uint8_t PaddingMem[3];
1105 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
1106 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
1108 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1109 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1113 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state.
1114 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state.
1115 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1116 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value
1117 uint16_t PaddingFclk;
1119 // Link DPM Settings
1120 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
1121 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1122 uint16_t LclkFreq[NUM_LINK_LEVELS];
1124 // SECTION: Fan Control
1125 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius
1126 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius
1128 uint16_t FanGain[TEMP_COUNT];
1129 uint16_t FanGainPadding;
1132 uint16_t AcousticTargetRpmThreshold;
1133 uint16_t AcousticLimitRpmThreshold;
1134 uint16_t FanMaximumRpm;
1135 uint16_t MGpuAcousticLimitRpmThreshold;
1136 uint16_t FanTargetGfxclk;
1137 uint32_t TempInputSelectMask;
1138 uint8_t FanZeroRpmEnable;
1139 uint8_t FanTachEdgePerRev;
1140 uint16_t FanTargetTemperature[TEMP_COUNT];
1142 // The following are AFC override parameters. Leave at 0 to use FW defaults.
1143 int16_t FuzzyFan_ErrorSetDelta;
1144 int16_t FuzzyFan_ErrorRateSetDelta;
1145 int16_t FuzzyFan_PwmSetDelta;
1146 uint16_t FuzzyFan_Reserved;
1148 uint16_t FwCtfLimit[TEMP_COUNT];
1150 uint16_t IntakeTempEnableRPM;
1151 int16_t IntakeTempOffsetTemp;
1152 uint16_t IntakeTempReleaseTemp;
1153 uint16_t IntakeTempHighIntakeAcousticLimit;
1154 uint16_t IntakeTempAcouticLimitReleaseRate;
1156 int16_t FanAbnormalTempLimitOffset;
1157 uint16_t FanStalledTriggerRpm;
1158 uint16_t FanAbnormalTriggerRpmCoeff;
1159 uint16_t FanAbnormalDetectionEnable;
1161 uint8_t FanIntakeSensorSupport;
1162 uint8_t FanIntakePadding[3];
1163 uint32_t FanSpare[13];
1165 // SECTION: VDD_GFX AVFS
1167 uint8_t OverrideGfxAvfsFuses;
1168 uint8_t GfxAvfsPadding[3];
1170 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding
1171 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT];
1173 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT];
1175 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];
1176 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];
1178 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES];
1179 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES];
1180 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES];
1181 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES];
1183 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES];
1185 uint32_t dGbV_dT_vmin;
1186 uint32_t dGbV_dT_vmax;
1189 uint32_t V2F_vmin_range_low;
1190 uint32_t V2F_vmin_range_high;
1191 uint32_t V2F_vmax_range_low;
1192 uint32_t V2F_vmax_range_high;
1194 AvfsDcBtcParams_t DcBtcGfxParams;
1196 uint32_t GfxAvfsSpare[32];
1198 //SECTION: VDD_SOC AVFS
1200 uint8_t OverrideSocAvfsFuses;
1201 uint8_t MinSocAvfsRevision;
1202 uint8_t SocAvfsPadding[2];
1204 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT];
1206 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb
1208 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V
1210 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V
1212 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT];
1214 uint32_t SocAvfsSpare[32];
1216 //SECTION: Boot clock and voltage values
1217 BootValues_t BootValues;
1219 //SECTION: Driver Reported Clocks
1220 DriverReportedClocks_t DriverReportedClocks;
1222 //SECTION: Message Limits
1223 MsgLimits_t MsgLimits;
1225 //SECTION: OverDrive Limits
1226 OverDriveLimits_t OverDriveLimitsMin;
1227 OverDriveLimits_t OverDriveLimitsBasicMax;
1228 uint32_t reserved[22];
1230 // SECTION: Advanced Options
1231 uint32_t DebugOverrides;
1233 // Section: Total Board Power idle vs active coefficients
1234 uint8_t TotalBoardPowerSupport;
1235 uint8_t TotalBoardPowerPadding[3];
1237 int16_t TotalIdleBoardPowerM;
1238 int16_t TotalIdleBoardPowerB;
1239 int16_t TotalBoardPowerM;
1240 int16_t TotalBoardPowerB;
1243 QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT];
1244 QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT];
1245 QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT];
1247 // SECTION: Sku Reserved
1250 // Padding for MMHUB - do not modify this
1251 uint32_t MmHubPadding[8];
1257 uint32_t Version; //should be unique to each board type
1260 // SECTION: I2C Control
1261 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
1263 // SECTION: SVI2 Board Parameters
1264 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
1265 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
1266 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
1267 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
1269 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1270 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1271 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1272 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1274 //SECTION SVI3 Board Parameters
1275 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT];
1276 uint8_t VrPsiSupport[SVI_PLANE_COUNT];
1278 uint8_t PaddingPsi[SVI_PLANE_COUNT];
1279 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3
1281 // SECTION: Voltage Regulator Settings
1282 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT];
1283 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
1285 uint8_t DownSlewRateVr[SVI_PLANE_COUNT];
1287 // SECTION: GPIO Settings
1291 uint8_t GfxVrPowerStageOffGpio;
1293 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
1294 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
1295 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
1296 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
1298 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
1299 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
1301 // LED Display Settings
1302 uint8_t LedPin0; // GPIO number for LedPin[0]
1303 uint8_t LedPin1; // GPIO number for LedPin[1]
1304 uint8_t LedPin2; // GPIO number for LedPin[2]
1305 uint8_t LedEnableMask;
1307 uint8_t LedPcie; // GPIO number for PCIE results
1308 uint8_t LedError; // GPIO number for Error Cases
1310 // SECTION: Clock Spread Spectrum
1312 // UCLK Spread Spectrum
1313 uint8_t UclkTrainingModeSpreadPercent;
1314 uint8_t UclkSpreadPadding;
1315 uint16_t UclkSpreadFreq; // kHz
1317 // UCLK Spread Spectrum
1318 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT];
1320 // FCLK Spread Spectrum
1321 uint8_t FclkSpreadPadding;
1322 uint8_t FclkSpreadPercent; // Q4.4
1323 uint16_t FclkSpreadFreq; // kHz
1325 // Section: Memory Config
1326 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e
1327 uint8_t PaddingMem1[7];
1329 // SECTION: UMC feature flags
1331 uint8_t VddqOffEnabled;
1332 uint8_t PaddingUmcFlags[2];
1334 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued
1335 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS
1337 uint8_t FuseWritePowerMuxPresent;
1338 uint8_t FuseWritePadding[3];
1340 // SECTION: Board Reserved
1341 uint32_t BoardSpare[63];
1343 // SECTION: Structure Padding
1345 // Padding for MMHUB - do not modify this
1346 uint32_t MmHubPadding[8];
1350 SkuTable_t SkuTable;
1351 BoardTable_t BoardTable;
1355 // Time constant parameters for clock averages in ms
1356 uint16_t GfxclkAverageLpfTau;
1357 uint16_t FclkAverageLpfTau;
1358 uint16_t UclkAverageLpfTau;
1359 uint16_t GfxActivityLpfTau;
1360 uint16_t UclkActivityLpfTau;
1361 uint16_t SocketPowerLpfTau;
1362 uint16_t VcnClkAverageLpfTau;
1363 uint16_t VcnUsageAverageLpfTau;
1364 } DriverSmuConfig_t;
1367 DriverSmuConfig_t DriverSmuConfig;
1371 uint32_t MmHubPadding[8]; // SMU internal use
1372 } DriverSmuConfigExternal_t;
1377 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
1378 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz
1379 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz
1380 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz
1381 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1382 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
1383 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz
1384 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz
1385 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz
1386 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz
1387 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1389 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
1396 uint32_t MmHubPadding[8]; // SMU internal use
1398 } DriverInfoTable_t;
1401 uint32_t CurrClock[PPCLK_COUNT];
1403 uint16_t AverageGfxclkFrequencyTarget;
1404 uint16_t AverageGfxclkFrequencyPreDs;
1405 uint16_t AverageGfxclkFrequencyPostDs;
1406 uint16_t AverageFclkFrequencyPreDs;
1407 uint16_t AverageFclkFrequencyPostDs;
1408 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock
1409 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock
1410 uint16_t AverageVclk0Frequency ;
1411 uint16_t AverageDclk0Frequency ;
1412 uint16_t AverageVclk1Frequency ;
1413 uint16_t AverageDclk1Frequency ;
1415 uint16_t dGPU_W_MAX;
1418 uint32_t MetricsCounter;
1420 uint16_t AvgVoltage[SVI_PLANE_COUNT];
1421 uint16_t AvgCurrent[SVI_PLANE_COUNT];
1423 uint16_t AverageGfxActivity ;
1424 uint16_t AverageUclkActivity ;
1425 uint16_t Vcn0ActivityPercentage ;
1426 uint16_t Vcn1ActivityPercentage ;
1428 uint32_t EnergyAccumulator;
1429 uint16_t AverageSocketPower;
1430 uint16_t AverageTotalBoardPower;
1432 uint16_t AvgTemperature[TEMP_COUNT];
1433 uint16_t AvgTemperatureFanIntake;
1443 uint8_t ThrottlingPercentage[THROTTLER_COUNT];
1445 //metrics for D3hot entry/exit and driver ARM msgs
1446 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
1447 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
1448 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
1450 uint16_t ApuSTAPMSmartShiftLimit;
1451 uint16_t ApuSTAPMLimit;
1452 uint16_t AvgApuSocketPower;
1454 uint16_t AverageUclkActivity_MAX;
1456 uint32_t PublicSerialNumberLower;
1457 uint32_t PublicSerialNumberUpper;
1462 SmuMetrics_t SmuMetrics;
1466 uint32_t MmHubPadding[8]; // SMU internal use
1467 } SmuMetricsExternal_t;
1474 } WatermarkRowGeneric_t;
1476 #define NUM_WM_RANGES 4
1479 WATERMARKS_CLOCK_RANGE = 0,
1480 WATERMARKS_DUMMY_PSTATE,
1483 } WATERMARKS_FLAGS_e;
1487 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
1491 Watermarks_t Watermarks;
1494 uint32_t MmHubPadding[8]; // SMU internal use
1495 } WatermarksExternal_t;
1498 uint16_t avgPsmCount[214];
1499 uint16_t minPsmCount[214];
1500 float avgPsmVoltage[214];
1501 float minPsmVoltage[214];
1505 AvfsDebugTable_t AvfsDebugTable;
1507 uint32_t MmHubPadding[8]; // SMU internal use
1508 } AvfsDebugTableExternal_t;
1512 uint8_t Gfx_ActiveHystLimit;
1513 uint8_t Gfx_IdleHystLimit;
1515 uint8_t Gfx_MinActiveFreqType;
1516 uint8_t Gfx_BoosterFreqType;
1518 uint16_t Gfx_MinActiveFreq; // MHz
1519 uint16_t Gfx_BoosterFreq; // MHz
1520 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms
1521 uint32_t Gfx_PD_Data_limit_a; // Q16
1522 uint32_t Gfx_PD_Data_limit_b; // Q16
1523 uint32_t Gfx_PD_Data_limit_c; // Q16
1524 uint32_t Gfx_PD_Data_error_coeff; // Q16
1525 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16
1527 uint8_t Fclk_ActiveHystLimit;
1528 uint8_t Fclk_IdleHystLimit;
1530 uint8_t Fclk_MinActiveFreqType;
1531 uint8_t Fclk_BoosterFreqType;
1532 uint8_t PaddingFclk;
1533 uint16_t Fclk_MinActiveFreq; // MHz
1534 uint16_t Fclk_BoosterFreq; // MHz
1535 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms
1536 uint32_t Fclk_PD_Data_limit_a; // Q16
1537 uint32_t Fclk_PD_Data_limit_b; // Q16
1538 uint32_t Fclk_PD_Data_limit_c; // Q16
1539 uint32_t Fclk_PD_Data_error_coeff; // Q16
1540 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16
1542 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16
1543 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];
1544 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS];
1548 } DpmActivityMonitorCoeffInt_t;
1552 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt;
1553 uint32_t MmHubPadding[8]; // SMU internal use
1554 } DpmActivityMonitorCoeffIntExternal_t;
1559 #define WORKLOAD_PPLIB_DEFAULT_BIT 0
1560 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
1561 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
1562 #define WORKLOAD_PPLIB_VIDEO_BIT 3
1563 #define WORKLOAD_PPLIB_VR_BIT 4
1564 #define WORKLOAD_PPLIB_COMPUTE_BIT 5
1565 #define WORKLOAD_PPLIB_CUSTOM_BIT 6
1566 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7
1567 #define WORKLOAD_PPLIB_COUNT 8
1570 // These defines are used with the following messages:
1571 // SMC_MSG_TransferTableDram2Smu
1572 // SMC_MSG_TransferTableSmu2Dram
1574 // Table transfer status
1575 #define TABLE_TRANSFER_OK 0x0
1576 #define TABLE_TRANSFER_FAILED 0xFF
1577 #define TABLE_TRANSFER_PENDING 0xAB
1580 #define TABLE_PPTABLE 0
1581 #define TABLE_COMBO_PPTABLE 1
1582 #define TABLE_WATERMARKS 2
1583 #define TABLE_AVFS_PSM_DEBUG 3
1584 #define TABLE_PMSTATUSLOG 4
1585 #define TABLE_SMU_METRICS 5
1586 #define TABLE_DRIVER_SMU_CONFIG 6
1587 #define TABLE_ACTIVITY_MONITOR_COEFF 7
1588 #define TABLE_OVERDRIVE 8
1589 #define TABLE_I2C_COMMANDS 9
1590 #define TABLE_DRIVER_INFO 10
1591 #define TABLE_ECCINFO 11
1592 #define TABLE_COUNT 12
1595 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE
1596 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2
1597 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3
1598 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4
1599 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5
1600 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6
1601 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7
1602 #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8
1603 #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9