drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomfwctrl.h"
  33 #include "atomfirmware.h"
  34 #include "cgs_common.h"
  35 #include "vega10_powertune.h"
  36 #include "smu9.h"
  37 #include "smu9_driver_if.h"
  38 #include "vega10_inc.h"
  39 #include "soc15_common.h"
  40 #include "pppcielanes.h"
  41 #include "vega10_hwmgr.h"
  42 #include "vega10_smumgr.h"
  43 #include "vega10_processpptables.h"
  44 #include "vega10_pptable.h"
  45 #include "vega10_thermal.h"
  46 #include "pp_debug.h"
  47 #include "amd_pcie_helpers.h"
  48 #include "ppinterrupt.h"
  49 #include "pp_overdriver.h"
  50 #include "pp_thermal.h"
  51 #include "vega10_baco.h"
  52
  53 #include "smuio/smuio_9_0_offset.h"
  54 #include "smuio/smuio_9_0_sh_mask.h"
  55
  56 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  57 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  58
  59 #define HBM_MEMORY_CHANNEL_WIDTH    128
  60
  61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  62
  63 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  64 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  65
  66 //DF_CS_AON0_DramBaseAddress0
  67 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  68 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  69 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  70 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  71 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  72 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  73 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  74 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  75 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  76 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  77
  78 typedef enum {
  79         CLK_SMNCLK = 0,
  80         CLK_SOCCLK,
  81         CLK_MP0CLK,
  82         CLK_MP1CLK,
  83         CLK_LCLK,
  84         CLK_DCEFCLK,
  85         CLK_VCLK,
  86         CLK_DCLK,
  87         CLK_ECLK,
  88         CLK_UCLK,
  89         CLK_GFXCLK,
  90         CLK_COUNT,
  91 } CLOCK_ID_e;
  92
  93 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
  94
  95 static struct vega10_power_state *cast_phw_vega10_power_state(
  96                                   struct pp_hw_power_state *hw_ps)
  97 {
  98         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  99                                 "Invalid Powerstate Type!",
 100                                  return NULL;);
 101
 102         return (struct vega10_power_state *)hw_ps;
 103 }
 104
 105 static const struct vega10_power_state *cast_const_phw_vega10_power_state(
 106                                  const struct pp_hw_power_state *hw_ps)
 107 {
 108         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
 109                                 "Invalid Powerstate Type!",
 110                                  return NULL;);
 111
 112         return (const struct vega10_power_state *)hw_ps;
 113 }
 114
 115 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
 116 {
 117         struct vega10_hwmgr *data = hwmgr->backend;
 118
 119         data->registry_data.sclk_dpm_key_disabled =
 120                         hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
 121         data->registry_data.socclk_dpm_key_disabled =
 122                         hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
 123         data->registry_data.mclk_dpm_key_disabled =
 124                         hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
 125         data->registry_data.pcie_dpm_key_disabled =
 126                         hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
 127
 128         data->registry_data.dcefclk_dpm_key_disabled =
 129                         hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
 130
 131         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 132                 data->registry_data.power_containment_support = 1;
 133                 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
 134                 data->registry_data.enable_tdc_limit_feature = 1;
 135         }
 136
 137         data->registry_data.clock_stretcher_support =
 138                         hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
 139
 140         data->registry_data.ulv_support =
 141                         hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 142
 143         data->registry_data.sclk_deep_sleep_support =
 144                         hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
 145
 146         data->registry_data.disable_water_mark = 0;
 147
 148         data->registry_data.fan_control_support = 1;
 149         data->registry_data.thermal_support = 1;
 150         data->registry_data.fw_ctf_enabled = 1;
 151
 152         data->registry_data.avfs_support =
 153                 hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
 154         data->registry_data.led_dpm_enabled = 1;
 155
 156         data->registry_data.vr0hot_enabled = 1;
 157         data->registry_data.vr1hot_enabled = 1;
 158         data->registry_data.regulator_hot_gpio_support = 1;
 159
 160         data->registry_data.didt_support = 1;
 161         if (data->registry_data.didt_support) {
 162                 data->registry_data.didt_mode = 6;
 163                 data->registry_data.sq_ramping_support = 1;
 164                 data->registry_data.db_ramping_support = 0;
 165                 data->registry_data.td_ramping_support = 0;
 166                 data->registry_data.tcp_ramping_support = 0;
 167                 data->registry_data.dbr_ramping_support = 0;
 168                 data->registry_data.edc_didt_support = 1;
 169                 data->registry_data.gc_didt_support = 0;
 170                 data->registry_data.psm_didt_support = 0;
 171         }
 172
 173         data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
 174         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 175         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 176         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 177         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 178         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 179         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 180         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 181         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 182         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 183         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 184         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 185         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 186
 187         data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
 188         data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
 189         data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
 190         data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
 191 }
 192
 193 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 194 {
 195         struct vega10_hwmgr *data = hwmgr->backend;
 196         struct phm_ppt_v2_information *table_info =
 197                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 198         struct amdgpu_device *adev = hwmgr->adev;
 199
 200         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 201                         PHM_PlatformCaps_SclkDeepSleep);
 202
 203         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 204                         PHM_PlatformCaps_DynamicPatchPowerState);
 205
 206         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
 207                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 208                                 PHM_PlatformCaps_ControlVDDCI);
 209
 210         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 211                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 212
 213         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 214                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 215                                 PHM_PlatformCaps_UVDPowerGating);
 216
 217         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 218                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 219                                 PHM_PlatformCaps_VCEPowerGating);
 220
 221         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 222                         PHM_PlatformCaps_UnTabledHardwareInterface);
 223
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 226
 227         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 228                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 229
 230         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 231                                 PHM_PlatformCaps_DynamicPowerManagement);
 232
 233         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 234                         PHM_PlatformCaps_SMC);
 235
 236         /* power tune caps */
 237         /* assume disabled */
 238         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 239                         PHM_PlatformCaps_PowerContainment);
 240         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 241                         PHM_PlatformCaps_DiDtSupport);
 242         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 243                         PHM_PlatformCaps_SQRamping);
 244         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 245                         PHM_PlatformCaps_DBRamping);
 246         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 247                         PHM_PlatformCaps_TDRamping);
 248         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 249                         PHM_PlatformCaps_TCPRamping);
 250         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 251                         PHM_PlatformCaps_DBRRamping);
 252         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 253                         PHM_PlatformCaps_DiDtEDCEnable);
 254         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 255                         PHM_PlatformCaps_GCEDC);
 256         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 257                         PHM_PlatformCaps_PSM);
 258
 259         if (data->registry_data.didt_support) {
 260                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 261                 if (data->registry_data.sq_ramping_support)
 262                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 263                 if (data->registry_data.db_ramping_support)
 264                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 265                 if (data->registry_data.td_ramping_support)
 266                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 267                 if (data->registry_data.tcp_ramping_support)
 268                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 269                 if (data->registry_data.dbr_ramping_support)
 270                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 271                 if (data->registry_data.edc_didt_support)
 272                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 273                 if (data->registry_data.gc_didt_support)
 274                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 275                 if (data->registry_data.psm_didt_support)
 276                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 277         }
 278
 279         if (data->registry_data.power_containment_support)
 280                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 281                                 PHM_PlatformCaps_PowerContainment);
 282         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 283                         PHM_PlatformCaps_CAC);
 284
 285         if (table_info->tdp_table->usClockStretchAmount &&
 286                         data->registry_data.clock_stretcher_support)
 287                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 288                                 PHM_PlatformCaps_ClockStretcher);
 289
 290         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 291                         PHM_PlatformCaps_RegulatorHot);
 292         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 293                         PHM_PlatformCaps_AutomaticDCTransition);
 294
 295         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 296                         PHM_PlatformCaps_UVDDPM);
 297         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 298                         PHM_PlatformCaps_VCEDPM);
 299
 300         return 0;
 301 }
 302
 303 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 304 {
 305         struct vega10_hwmgr *data = hwmgr->backend;
 306         struct phm_ppt_v2_information *table_info =
 307                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 308         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 309         struct vega10_odn_vddc_lookup_table *od_lookup_table;
 310         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 311         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
 312         struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
 313         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
 314         uint32_t i;
 315         int result;
 316
 317         result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
 318         if (!result) {
 319                 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
 320                 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
 321         }
 322
 323         od_lookup_table = &odn_table->vddc_lookup_table;
 324         vddc_lookup_table = table_info->vddc_lookup_table;
 325
 326         for (i = 0; i < vddc_lookup_table->count; i++)
 327                 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
 328
 329         od_lookup_table->count = vddc_lookup_table->count;
 330
 331         dep_table[0] = table_info->vdd_dep_on_sclk;
 332         dep_table[1] = table_info->vdd_dep_on_mclk;
 333         dep_table[2] = table_info->vdd_dep_on_socclk;
 334         od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
 335         od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
 336         od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
 337
 338         for (i = 0; i < 3; i++)
 339                 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
 340
 341         if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
 342                 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
 343         if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
 344                 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
 345
 346         i = od_table[2]->count - 1;
 347         od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
 348                                         hwmgr->platform_descriptor.overdriveLimit.memoryClock :
 349                                         od_table[2]->entries[i].clk;
 350         od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
 351                                         odn_table->max_vddc :
 352                                         od_table[2]->entries[i].vddc;
 353
 354         return 0;
 355 }
 356
 357 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 358 {
 359         struct vega10_hwmgr *data = hwmgr->backend;
 360         int i;
 361         uint32_t sub_vendor_id, hw_revision;
 362         uint32_t top32, bottom32;
 363         struct amdgpu_device *adev = hwmgr->adev;
 364
 365         vega10_initialize_power_tune_defaults(hwmgr);
 366
 367         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 368                 data->smu_features[i].smu_feature_id = 0xffff;
 369                 data->smu_features[i].smu_feature_bitmap = 1 << i;
 370                 data->smu_features[i].enabled = false;
 371                 data->smu_features[i].supported = false;
 372         }
 373
 374         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 375                         FEATURE_DPM_PREFETCHER_BIT;
 376         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 377                         FEATURE_DPM_GFXCLK_BIT;
 378         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 379                         FEATURE_DPM_UCLK_BIT;
 380         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 381                         FEATURE_DPM_SOCCLK_BIT;
 382         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 383                         FEATURE_DPM_UVD_BIT;
 384         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 385                         FEATURE_DPM_VCE_BIT;
 386         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 387                         FEATURE_DPM_MP0CLK_BIT;
 388         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 389                         FEATURE_DPM_LINK_BIT;
 390         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 391                         FEATURE_DPM_DCEFCLK_BIT;
 392         data->smu_features[GNLD_ULV].smu_feature_id =
 393                         FEATURE_ULV_BIT;
 394         data->smu_features[GNLD_AVFS].smu_feature_id =
 395                         FEATURE_AVFS_BIT;
 396         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 397                         FEATURE_DS_GFXCLK_BIT;
 398         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 399                         FEATURE_DS_SOCCLK_BIT;
 400         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 401                         FEATURE_DS_LCLK_BIT;
 402         data->smu_features[GNLD_PPT].smu_feature_id =
 403                         FEATURE_PPT_BIT;
 404         data->smu_features[GNLD_TDC].smu_feature_id =
 405                         FEATURE_TDC_BIT;
 406         data->smu_features[GNLD_THERMAL].smu_feature_id =
 407                         FEATURE_THERMAL_BIT;
 408         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 409                         FEATURE_GFX_PER_CU_CG_BIT;
 410         data->smu_features[GNLD_RM].smu_feature_id =
 411                         FEATURE_RM_BIT;
 412         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 413                         FEATURE_DS_DCEFCLK_BIT;
 414         data->smu_features[GNLD_ACDC].smu_feature_id =
 415                         FEATURE_ACDC_BIT;
 416         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 417                         FEATURE_VR0HOT_BIT;
 418         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 419                         FEATURE_VR1HOT_BIT;
 420         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 421                         FEATURE_FW_CTF_BIT;
 422         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 423                         FEATURE_LED_DISPLAY_BIT;
 424         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 425                         FEATURE_FAN_CONTROL_BIT;
 426         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 427         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 428         data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
 429
 430         if (!data->registry_data.prefetcher_dpm_key_disabled)
 431                 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
 432
 433         if (!data->registry_data.sclk_dpm_key_disabled)
 434                 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
 435
 436         if (!data->registry_data.mclk_dpm_key_disabled)
 437                 data->smu_features[GNLD_DPM_UCLK].supported = true;
 438
 439         if (!data->registry_data.socclk_dpm_key_disabled)
 440                 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
 441
 442         if (PP_CAP(PHM_PlatformCaps_UVDDPM))
 443                 data->smu_features[GNLD_DPM_UVD].supported = true;
 444
 445         if (PP_CAP(PHM_PlatformCaps_VCEDPM))
 446                 data->smu_features[GNLD_DPM_VCE].supported = true;
 447
 448         data->smu_features[GNLD_DPM_LINK].supported = true;
 449
 450         if (!data->registry_data.dcefclk_dpm_key_disabled)
 451                 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
 452
 453         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
 454             data->registry_data.sclk_deep_sleep_support) {
 455                 data->smu_features[GNLD_DS_GFXCLK].supported = true;
 456                 data->smu_features[GNLD_DS_SOCCLK].supported = true;
 457                 data->smu_features[GNLD_DS_LCLK].supported = true;
 458                 data->smu_features[GNLD_DS_DCEFCLK].supported = true;
 459         }
 460
 461         if (data->registry_data.enable_pkg_pwr_tracking_feature)
 462                 data->smu_features[GNLD_PPT].supported = true;
 463
 464         if (data->registry_data.enable_tdc_limit_feature)
 465                 data->smu_features[GNLD_TDC].supported = true;
 466
 467         if (data->registry_data.thermal_support)
 468                 data->smu_features[GNLD_THERMAL].supported = true;
 469
 470         if (data->registry_data.fan_control_support)
 471                 data->smu_features[GNLD_FAN_CONTROL].supported = true;
 472
 473         if (data->registry_data.fw_ctf_enabled)
 474                 data->smu_features[GNLD_FW_CTF].supported = true;
 475
 476         if (data->registry_data.avfs_support)
 477                 data->smu_features[GNLD_AVFS].supported = true;
 478
 479         if (data->registry_data.led_dpm_enabled)
 480                 data->smu_features[GNLD_LED_DISPLAY].supported = true;
 481
 482         if (data->registry_data.vr1hot_enabled)
 483                 data->smu_features[GNLD_VR1HOT].supported = true;
 484
 485         if (data->registry_data.vr0hot_enabled)
 486                 data->smu_features[GNLD_VR0HOT].supported = true;
 487
 488         smum_send_msg_to_smc(hwmgr,
 489                         PPSMC_MSG_GetSmuVersion,
 490                         &hwmgr->smu_version);
 491                 /* ACG firmware has major version 5 */
 492         if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
 493                 data->smu_features[GNLD_ACG].supported = true;
 494         if (data->registry_data.didt_support)
 495                 data->smu_features[GNLD_DIDT].supported = true;
 496
 497         hw_revision = adev->pdev->revision;
 498         sub_vendor_id = adev->pdev->subsystem_vendor;
 499
 500         if ((hwmgr->chip_id == 0x6862 ||
 501                 hwmgr->chip_id == 0x6861 ||
 502                 hwmgr->chip_id == 0x6868) &&
 503                 (hw_revision == 0) &&
 504                 (sub_vendor_id != 0x1002))
 505                 data->smu_features[GNLD_PCC_LIMIT].supported = true;
 506
 507         /* Get the SN to turn into a Unique ID */
 508         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
 509         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
 510
 511         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
 512 }
 513
 514 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 515 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 516         phm_ppt_v1_voltage_lookup_table *lookup_table,
 517         uint16_t virtual_voltage_id, int32_t *socclk)
 518 {
 519         uint8_t entry_id;
 520         uint8_t voltage_id;
 521         struct phm_ppt_v2_information *table_info =
 522                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 523
 524         PP_ASSERT_WITH_CODE(lookup_table->count != 0,
 525                         "Lookup table is empty",
 526                         return -EINVAL);
 527
 528         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
 529         for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
 530                 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
 531                 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
 532                         break;
 533         }
 534
 535         PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
 536                         "Can't find requested voltage id in vdd_dep_on_socclk table!",
 537                         return -EINVAL);
 538
 539         *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
 540
 541         return 0;
 542 }
 543
 544 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
 545 /**
 546  * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID.
 547  *
 548  * @hwmgr:  the address of the powerplay hardware manager.
 549  * return:  always 0.
 550  */
 551 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
 552 {
 553         struct vega10_hwmgr *data = hwmgr->backend;
 554         uint16_t vv_id;
 555         uint32_t vddc = 0;
 556         uint16_t i, j;
 557         uint32_t sclk = 0;
 558         struct phm_ppt_v2_information *table_info =
 559                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 560         struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
 561                         table_info->vdd_dep_on_socclk;
 562         int result;
 563
 564         for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
 565                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 566
 567                 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
 568                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 569                         if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
 570                                 for (j = 1; j < socclk_table->count; j++) {
 571                                         if (socclk_table->entries[j].clk == sclk &&
 572                                                         socclk_table->entries[j].cks_enable == 0) {
 573                                                 sclk += 5000;
 574                                                 break;
 575                                         }
 576                                 }
 577                         }
 578
 579                         PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
 580                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
 581                                         "Error retrieving EVV voltage value!",
 582                                         continue);
 583
 584
 585                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 586                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
 587                                         "Invalid VDDC value", result = -EINVAL;);
 588
 589                         /* the voltage should not be zero nor equal to leakage ID */
 590                         if (vddc != 0 && vddc != vv_id) {
 591                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
 592                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
 593                                 data->vddc_leakage.count++;
 594                         }
 595                 }
 596         }
 597
 598         return 0;
 599 }
 600
 601 /**
 602  * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value.
 603  *
 604  * @hwmgr:         the address of the powerplay hardware manager.
 605  * @voltage:       pointer to changing voltage
 606  * @leakage_table: pointer to leakage table
 607  */
 608 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 609                 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
 610 {
 611         uint32_t index;
 612
 613         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 614         for (index = 0; index < leakage_table->count; index++) {
 615                 /* if this voltage matches a leakage voltage ID */
 616                 /* patch with actual leakage voltage */
 617                 if (leakage_table->leakage_id[index] == *voltage) {
 618                         *voltage = leakage_table->actual_voltage[index];
 619                         break;
 620                 }
 621         }
 622
 623         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 624                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
 625 }
 626
 627 /**
 628  * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages.
 629  *
 630  * @hwmgr:         the address of the powerplay hardware manager.
 631  * @lookup_table:  pointer to voltage lookup table
 632  * @leakage_table: pointer to leakage table
 633  * return:         always 0
 634  */
 635 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 636                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 637                 struct vega10_leakage_voltage *leakage_table)
 638 {
 639         uint32_t i;
 640
 641         for (i = 0; i < lookup_table->count; i++)
 642                 vega10_patch_with_vdd_leakage(hwmgr,
 643                                 &lookup_table->entries[i].us_vdd, leakage_table);
 644
 645         return 0;
 646 }
 647
 648 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
 649                 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
 650                 uint16_t *vddc)
 651 {
 652         vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 653
 654         return 0;
 655 }
 656 #endif
 657
 658 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
 659                 struct pp_hwmgr *hwmgr)
 660 {
 661         uint8_t entry_id, voltage_id;
 662         unsigned i;
 663         struct phm_ppt_v2_information *table_info =
 664                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 665         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 666                         table_info->mm_dep_table;
 667         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 668                         table_info->vdd_dep_on_mclk;
 669
 670         for (i = 0; i < 6; i++) {
 671                 struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
 672                 switch (i) {
 673                         case 0: vdt = table_info->vdd_dep_on_socclk; break;
 674                         case 1: vdt = table_info->vdd_dep_on_sclk; break;
 675                         case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
 676                         case 3: vdt = table_info->vdd_dep_on_pixclk; break;
 677                         case 4: vdt = table_info->vdd_dep_on_dispclk; break;
 678                         case 5: vdt = table_info->vdd_dep_on_phyclk; break;
 679                 }
 680
 681                 for (entry_id = 0; entry_id < vdt->count; entry_id++) {
 682                         voltage_id = vdt->entries[entry_id].vddInd;
 683                         vdt->entries[entry_id].vddc =
 684                                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 685                 }
 686         }
 687
 688         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
 689                 voltage_id = mm_table->entries[entry_id].vddcInd;
 690                 mm_table->entries[entry_id].vddc =
 691                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 692         }
 693
 694         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
 695                 voltage_id = mclk_table->entries[entry_id].vddInd;
 696                 mclk_table->entries[entry_id].vddc =
 697                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 698                 voltage_id = mclk_table->entries[entry_id].vddciInd;
 699                 mclk_table->entries[entry_id].vddci =
 700                                 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
 701                 voltage_id = mclk_table->entries[entry_id].mvddInd;
 702                 mclk_table->entries[entry_id].mvdd =
 703                                 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
 704         }
 705
 706
 707         return 0;
 708
 709 }
 710
 711 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
 712                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 713 {
 714         uint32_t table_size, i, j;
 715
 716         PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
 717                 "Lookup table is empty", return -EINVAL);
 718
 719         table_size = lookup_table->count;
 720
 721         /* Sorting voltages */
 722         for (i = 0; i < table_size - 1; i++) {
 723                 for (j = i + 1; j > 0; j--) {
 724                         if (lookup_table->entries[j].us_vdd <
 725                                         lookup_table->entries[j - 1].us_vdd) {
 726                                 swap(lookup_table->entries[j - 1],
 727                                      lookup_table->entries[j]);
 728                         }
 729                 }
 730         }
 731
 732         return 0;
 733 }
 734
 735 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 736 {
 737         int result = 0;
 738         int tmp_result;
 739         struct phm_ppt_v2_information *table_info =
 740                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 741 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 742         struct vega10_hwmgr *data = hwmgr->backend;
 743
 744         tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
 745                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 746         if (tmp_result)
 747                 result = tmp_result;
 748
 749         tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 750                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 751         if (tmp_result)
 752                 result = tmp_result;
 753 #endif
 754
 755         tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 756         if (tmp_result)
 757                 result = tmp_result;
 758
 759         tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 760         if (tmp_result)
 761                 result = tmp_result;
 762
 763         return result;
 764 }
 765
 766 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 767 {
 768         struct phm_ppt_v2_information *table_info =
 769                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 770         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 771                         table_info->vdd_dep_on_socclk;
 772         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 773                         table_info->vdd_dep_on_mclk;
 774
 775         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
 776                 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
 777         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 778                 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
 779
 780         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
 781                 "VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
 782         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 783                 "VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
 784
 785         table_info->max_clock_voltage_on_ac.sclk =
 786                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 787         table_info->max_clock_voltage_on_ac.mclk =
 788                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 789         table_info->max_clock_voltage_on_ac.vddc =
 790                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 791         table_info->max_clock_voltage_on_ac.vddci =
 792                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 793
 794         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 795                 table_info->max_clock_voltage_on_ac.sclk;
 796         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 797                 table_info->max_clock_voltage_on_ac.mclk;
 798         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 799                 table_info->max_clock_voltage_on_ac.vddc;
 800         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 801                 table_info->max_clock_voltage_on_ac.vddci;
 802
 803         return 0;
 804 }
 805
 806 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 807 {
 808         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 809         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 810
 811         kfree(hwmgr->backend);
 812         hwmgr->backend = NULL;
 813
 814         return 0;
 815 }
 816
 817 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 818 {
 819         int result = 0;
 820         struct vega10_hwmgr *data;
 821         uint32_t config_telemetry = 0;
 822         struct pp_atomfwctrl_voltage_table vol_table;
 823         struct amdgpu_device *adev = hwmgr->adev;
 824
 825         data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
 826         if (data == NULL)
 827                 return -ENOMEM;
 828
 829         hwmgr->backend = data;
 830
 831         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 832         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 833         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 834
 835         vega10_set_default_registry_data(hwmgr);
 836         data->disable_dpm_mask = 0xff;
 837
 838         /* need to set voltage control types before EVV patching */
 839         data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
 840         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
 841         data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
 842
 843         /* VDDCR_SOC */
 844         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 845                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
 846                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 847                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
 848                                 &vol_table)) {
 849                         config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
 850                                         (vol_table.telemetry_offset & 0xff);
 851                         data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 852                 }
 853         } else {
 854                 kfree(hwmgr->backend);
 855                 hwmgr->backend = NULL;
 856                 PP_ASSERT_WITH_CODE(false,
 857                                 "VDDCR_SOC is not SVID2!",
 858                                 return -1);
 859         }
 860
 861         /* MVDDC */
 862         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 863                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
 864                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 865                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
 866                                 &vol_table)) {
 867                         config_telemetry |=
 868                                         ((vol_table.telemetry_slope << 24) & 0xff000000) |
 869                                         ((vol_table.telemetry_offset << 16) & 0xff0000);
 870                         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 871                 }
 872         }
 873
 874          /* VDDCI_MEM */
 875         if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
 876                 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 877                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 878                         data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
 879         }
 880
 881         data->config_telemetry = config_telemetry;
 882
 883         vega10_set_features_platform_caps(hwmgr);
 884
 885         vega10_init_dpm_defaults(hwmgr);
 886
 887 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 888         /* Get leakage voltage based on leakage ID. */
 889         PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
 890                         "Get EVV Voltage Failed.  Abort Driver loading!",
 891                         return -1);
 892 #endif
 893
 894         /* Patch our voltage dependency table with actual leakage voltage
 895          * We need to perform leakage translation before it's used by other functions
 896          */
 897         vega10_complete_dependency_tables(hwmgr);
 898
 899         /* Parse pptable data read from VBIOS */
 900         vega10_set_private_data_based_on_pptable(hwmgr);
 901
 902         data->is_tlu_enabled = false;
 903
 904         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 905                         VEGA10_MAX_HARDWARE_POWERLEVELS;
 906         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 907         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 908
 909         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 910         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 911         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 912         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 913
 914         data->total_active_cus = adev->gfx.cu_info.number;
 915         if (!hwmgr->not_vf)
 916                 return result;
 917
 918         /* Setup default Overdrive Fan control settings */
 919         data->odn_fan_table.target_fan_speed =
 920                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 921         data->odn_fan_table.target_temperature =
 922                         hwmgr->thermal_controller.
 923                         advanceFanControlParameters.ucTargetTemperature;
 924         data->odn_fan_table.min_performance_clock =
 925                         hwmgr->thermal_controller.advanceFanControlParameters.
 926                         ulMinFanSCLKAcousticLimit;
 927         data->odn_fan_table.min_fan_limit =
 928                         hwmgr->thermal_controller.
 929                         advanceFanControlParameters.usFanPWMMinLimit *
 930                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 931
 932         data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
 933                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
 934                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 935         PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
 936                         "Mem Channel Index Exceeded maximum!",
 937                         return -EINVAL);
 938
 939         return result;
 940 }
 941
 942 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 943 {
 944         struct vega10_hwmgr *data = hwmgr->backend;
 945
 946         data->low_sclk_interrupt_threshold = 0;
 947
 948         return 0;
 949 }
 950
 951 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
 952 {
 953         struct vega10_hwmgr *data = hwmgr->backend;
 954         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 955
 956         struct pp_atomfwctrl_voltage_table table;
 957         uint8_t i, j;
 958         uint32_t mask = 0;
 959         uint32_t tmp;
 960         int32_t ret = 0;
 961
 962         ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
 963                                                 VOLTAGE_OBJ_GPIO_LUT, &table);
 964
 965         if (!ret) {
 966                 tmp = table.mask_low;
 967                 for (i = 0, j = 0; i < 32; i++) {
 968                         if (tmp & 1) {
 969                                 mask |= (uint32_t)(i << (8 * j));
 970                                 if (++j >= 3)
 971                                         break;
 972                         }
 973                         tmp >>= 1;
 974                 }
 975         }
 976
 977         pp_table->LedPin0 = (uint8_t)(mask & 0xff);
 978         pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
 979         pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
 980         return 0;
 981 }
 982
 983 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
 984 {
 985         if (!hwmgr->not_vf)
 986                 return 0;
 987
 988         PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
 989                         "Failed to init sclk threshold!",
 990                         return -EINVAL);
 991
 992         PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
 993                         "Failed to set up led dpm config!",
 994                         return -EINVAL);
 995
 996         smum_send_msg_to_smc_with_parameter(hwmgr,
 997                                 PPSMC_MSG_NumOfDisplays,
 998                                 0,
 999                                 NULL);
1000
1001         return 0;
1002 }
1003
1004 /**
1005  * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values.
1006  *
1007  * @hwmgr:      the address of the powerplay hardware manager.
1008  * @vol_table:  the pointer to changing voltage table
1009  * return:      0 in success
1010  */
1011 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
1012                 struct pp_atomfwctrl_voltage_table *vol_table)
1013 {
1014         uint32_t i, j;
1015         uint16_t vvalue;
1016         bool found = false;
1017         struct pp_atomfwctrl_voltage_table *table;
1018
1019         PP_ASSERT_WITH_CODE(vol_table,
1020                         "Voltage Table empty.", return -EINVAL);
1021         table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
1022                         GFP_KERNEL);
1023
1024         if (!table)
1025                 return -ENOMEM;
1026
1027         table->mask_low = vol_table->mask_low;
1028         table->phase_delay = vol_table->phase_delay;
1029
1030         for (i = 0; i < vol_table->count; i++) {
1031                 vvalue = vol_table->entries[i].value;
1032                 found = false;
1033
1034                 for (j = 0; j < table->count; j++) {
1035                         if (vvalue == table->entries[j].value) {
1036                                 found = true;
1037                                 break;
1038                         }
1039                 }
1040
1041                 if (!found) {
1042                         table->entries[table->count].value = vvalue;
1043                         table->entries[table->count].smio_low =
1044                                         vol_table->entries[i].smio_low;
1045                         table->count++;
1046                 }
1047         }
1048
1049         memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1050         kfree(table);
1051
1052         return 0;
1053 }
1054
1055 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1056                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1057                 struct pp_atomfwctrl_voltage_table *vol_table)
1058 {
1059         int i;
1060
1061         PP_ASSERT_WITH_CODE(dep_table->count,
1062                         "Voltage Dependency Table empty.",
1063                         return -EINVAL);
1064
1065         vol_table->mask_low = 0;
1066         vol_table->phase_delay = 0;
1067         vol_table->count = dep_table->count;
1068
1069         for (i = 0; i < vol_table->count; i++) {
1070                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
1071                 vol_table->entries[i].smio_low = 0;
1072         }
1073
1074         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1075                         vol_table),
1076                         "Failed to trim MVDD Table!",
1077                         return -1);
1078
1079         return 0;
1080 }
1081
1082 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1083                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1084                 struct pp_atomfwctrl_voltage_table *vol_table)
1085 {
1086         uint32_t i;
1087
1088         PP_ASSERT_WITH_CODE(dep_table->count,
1089                         "Voltage Dependency Table empty.",
1090                         return -EINVAL);
1091
1092         vol_table->mask_low = 0;
1093         vol_table->phase_delay = 0;
1094         vol_table->count = dep_table->count;
1095
1096         for (i = 0; i < dep_table->count; i++) {
1097                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1098                 vol_table->entries[i].smio_low = 0;
1099         }
1100
1101         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1102                         "Failed to trim VDDCI table.",
1103                         return -1);
1104
1105         return 0;
1106 }
1107
1108 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1109                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1110                 struct pp_atomfwctrl_voltage_table *vol_table)
1111 {
1112         int i;
1113
1114         PP_ASSERT_WITH_CODE(dep_table->count,
1115                         "Voltage Dependency Table empty.",
1116                         return -EINVAL);
1117
1118         vol_table->mask_low = 0;
1119         vol_table->phase_delay = 0;
1120         vol_table->count = dep_table->count;
1121
1122         for (i = 0; i < vol_table->count; i++) {
1123                 vol_table->entries[i].value = dep_table->entries[i].vddc;
1124                 vol_table->entries[i].smio_low = 0;
1125         }
1126
1127         return 0;
1128 }
1129
1130 /* ---- Voltage Tables ----
1131  * If the voltage table would be bigger than
1132  * what will fit into the state table on
1133  * the SMC keep only the higher entries.
1134  */
1135 static void vega10_trim_voltage_table_to_fit_state_table(
1136                 struct pp_hwmgr *hwmgr,
1137                 uint32_t max_vol_steps,
1138                 struct pp_atomfwctrl_voltage_table *vol_table)
1139 {
1140         unsigned int i, diff;
1141
1142         if (vol_table->count <= max_vol_steps)
1143                 return;
1144
1145         diff = vol_table->count - max_vol_steps;
1146
1147         for (i = 0; i < max_vol_steps; i++)
1148                 vol_table->entries[i] = vol_table->entries[i + diff];
1149
1150         vol_table->count = max_vol_steps;
1151 }
1152
1153 /**
1154  * vega10_construct_voltage_tables - Create Voltage Tables.
1155  *
1156  * @hwmgr:  the address of the powerplay hardware manager.
1157  * return:  always 0
1158  */
1159 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1160 {
1161         struct vega10_hwmgr *data = hwmgr->backend;
1162         struct phm_ppt_v2_information *table_info =
1163                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1164         int result;
1165
1166         if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1167                         data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1168                 result = vega10_get_mvdd_voltage_table(hwmgr,
1169                                 table_info->vdd_dep_on_mclk,
1170                                 &(data->mvdd_voltage_table));
1171                 PP_ASSERT_WITH_CODE(!result,
1172                                 "Failed to retrieve MVDDC table!",
1173                                 return result);
1174         }
1175
1176         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1177                 result = vega10_get_vddci_voltage_table(hwmgr,
1178                                 table_info->vdd_dep_on_mclk,
1179                                 &(data->vddci_voltage_table));
1180                 PP_ASSERT_WITH_CODE(!result,
1181                                 "Failed to retrieve VDDCI_MEM table!",
1182                                 return result);
1183         }
1184
1185         if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1186                         data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1187                 result = vega10_get_vdd_voltage_table(hwmgr,
1188                                 table_info->vdd_dep_on_sclk,
1189                                 &(data->vddc_voltage_table));
1190                 PP_ASSERT_WITH_CODE(!result,
1191                                 "Failed to retrieve VDDCR_SOC table!",
1192                                 return result);
1193         }
1194
1195         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1196                         "Too many voltage values for VDDC. Trimming to fit state table.",
1197                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1198                                         16, &(data->vddc_voltage_table)));
1199
1200         PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1201                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1202                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1203                                         16, &(data->vddci_voltage_table)));
1204
1205         PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1206                         "Too many voltage values for MVDD. Trimming to fit state table.",
1207                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1208                                         16, &(data->mvdd_voltage_table)));
1209
1210
1211         return 0;
1212 }
1213
1214 /*
1215  * vega10_init_dpm_state
1216  * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1217  *
1218  * @dpm_state: - the address of the DPM Table to initiailize.
1219  * return:   None.
1220  */
1221 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1222 {
1223         dpm_state->soft_min_level = 0xff;
1224         dpm_state->soft_max_level = 0xff;
1225         dpm_state->hard_min_level = 0xff;
1226         dpm_state->hard_max_level = 0xff;
1227 }
1228
1229 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1230                 struct vega10_single_dpm_table *dpm_table,
1231                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1232 {
1233         int i;
1234
1235         dpm_table->count = 0;
1236
1237         for (i = 0; i < dep_table->count; i++) {
1238                 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1239                                 dep_table->entries[i].clk) {
1240                         dpm_table->dpm_levels[dpm_table->count].value =
1241                                         dep_table->entries[i].clk;
1242                         dpm_table->dpm_levels[dpm_table->count].enabled = true;
1243                         dpm_table->count++;
1244                 }
1245         }
1246 }
1247 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1248 {
1249         struct vega10_hwmgr *data = hwmgr->backend;
1250         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1251         struct phm_ppt_v2_information *table_info =
1252                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1253         struct phm_ppt_v1_pcie_table *bios_pcie_table =
1254                         table_info->pcie_table;
1255         uint32_t i;
1256
1257         PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1258                         "Incorrect number of PCIE States from VBIOS!",
1259                         return -1);
1260
1261         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1262                 if (data->registry_data.pcieSpeedOverride)
1263                         pcie_table->pcie_gen[i] =
1264                                         data->registry_data.pcieSpeedOverride;
1265                 else
1266                         pcie_table->pcie_gen[i] =
1267                                         bios_pcie_table->entries[i].gen_speed;
1268
1269                 if (data->registry_data.pcieLaneOverride)
1270                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1271                                         data->registry_data.pcieLaneOverride);
1272                 else
1273                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1274                                                         bios_pcie_table->entries[i].lane_width);
1275                 if (data->registry_data.pcieClockOverride)
1276                         pcie_table->lclk[i] =
1277                                         data->registry_data.pcieClockOverride;
1278                 else
1279                         pcie_table->lclk[i] =
1280                                         bios_pcie_table->entries[i].pcie_sclk;
1281         }
1282
1283         pcie_table->count = NUM_LINK_LEVELS;
1284
1285         return 0;
1286 }
1287
1288 /*
1289  * This function is to initialize all DPM state tables
1290  * for SMU based on the dependency table.
1291  * Dynamic state patching function will then trim these
1292  * state tables to the allowed range based
1293  * on the power policy or external client requests,
1294  * such as UVD request, etc.
1295  */
1296 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1297 {
1298         struct vega10_hwmgr *data = hwmgr->backend;
1299         struct phm_ppt_v2_information *table_info =
1300                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1301         struct vega10_single_dpm_table *dpm_table;
1302         uint32_t i;
1303
1304         struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1305                         table_info->vdd_dep_on_socclk;
1306         struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1307                         table_info->vdd_dep_on_sclk;
1308         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1309                         table_info->vdd_dep_on_mclk;
1310         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1311                         table_info->mm_dep_table;
1312         struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1313                         table_info->vdd_dep_on_dcefclk;
1314         struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1315                         table_info->vdd_dep_on_pixclk;
1316         struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1317                         table_info->vdd_dep_on_dispclk;
1318         struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1319                         table_info->vdd_dep_on_phyclk;
1320
1321         PP_ASSERT_WITH_CODE(dep_soc_table,
1322                         "SOCCLK dependency table is missing. This table is mandatory",
1323                         return -EINVAL);
1324         PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1325                         "SOCCLK dependency table is empty. This table is mandatory",
1326                         return -EINVAL);
1327
1328         PP_ASSERT_WITH_CODE(dep_gfx_table,
1329                         "GFXCLK dependency table is missing. This table is mandatory",
1330                         return -EINVAL);
1331         PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1332                         "GFXCLK dependency table is empty. This table is mandatory",
1333                         return -EINVAL);
1334
1335         PP_ASSERT_WITH_CODE(dep_mclk_table,
1336                         "MCLK dependency table is missing. This table is mandatory",
1337                         return -EINVAL);
1338         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1339                         "MCLK dependency table has to have is missing. This table is mandatory",
1340                         return -EINVAL);
1341
1342         /* Initialize Sclk DPM table based on allow Sclk values */
1343         dpm_table = &(data->dpm_table.soc_table);
1344         vega10_setup_default_single_dpm_table(hwmgr,
1345                         dpm_table,
1346                         dep_soc_table);
1347
1348         vega10_init_dpm_state(&(dpm_table->dpm_state));
1349
1350         dpm_table = &(data->dpm_table.gfx_table);
1351         vega10_setup_default_single_dpm_table(hwmgr,
1352                         dpm_table,
1353                         dep_gfx_table);
1354         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
1355                 hwmgr->platform_descriptor.overdriveLimit.engineClock =
1356                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1357         vega10_init_dpm_state(&(dpm_table->dpm_state));
1358
1359         /* Initialize Mclk DPM table based on allow Mclk values */
1360         data->dpm_table.mem_table.count = 0;
1361         dpm_table = &(data->dpm_table.mem_table);
1362         vega10_setup_default_single_dpm_table(hwmgr,
1363                         dpm_table,
1364                         dep_mclk_table);
1365         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1366                 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1367                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1368         vega10_init_dpm_state(&(dpm_table->dpm_state));
1369
1370         data->dpm_table.eclk_table.count = 0;
1371         dpm_table = &(data->dpm_table.eclk_table);
1372         for (i = 0; i < dep_mm_table->count; i++) {
1373                 if (i == 0 || dpm_table->dpm_levels
1374                                 [dpm_table->count - 1].value <=
1375                                                 dep_mm_table->entries[i].eclk) {
1376                         dpm_table->dpm_levels[dpm_table->count].value =
1377                                         dep_mm_table->entries[i].eclk;
1378                         dpm_table->dpm_levels[dpm_table->count].enabled =
1379                                         (i == 0) ? true : false;
1380                         dpm_table->count++;
1381                 }
1382         }
1383         vega10_init_dpm_state(&(dpm_table->dpm_state));
1384
1385         data->dpm_table.vclk_table.count = 0;
1386         data->dpm_table.dclk_table.count = 0;
1387         dpm_table = &(data->dpm_table.vclk_table);
1388         for (i = 0; i < dep_mm_table->count; i++) {
1389                 if (i == 0 || dpm_table->dpm_levels
1390                                 [dpm_table->count - 1].value <=
1391                                                 dep_mm_table->entries[i].vclk) {
1392                         dpm_table->dpm_levels[dpm_table->count].value =
1393                                         dep_mm_table->entries[i].vclk;
1394                         dpm_table->dpm_levels[dpm_table->count].enabled =
1395                                         (i == 0) ? true : false;
1396                         dpm_table->count++;
1397                 }
1398         }
1399         vega10_init_dpm_state(&(dpm_table->dpm_state));
1400
1401         dpm_table = &(data->dpm_table.dclk_table);
1402         for (i = 0; i < dep_mm_table->count; i++) {
1403                 if (i == 0 || dpm_table->dpm_levels
1404                                 [dpm_table->count - 1].value <=
1405                                                 dep_mm_table->entries[i].dclk) {
1406                         dpm_table->dpm_levels[dpm_table->count].value =
1407                                         dep_mm_table->entries[i].dclk;
1408                         dpm_table->dpm_levels[dpm_table->count].enabled =
1409                                         (i == 0) ? true : false;
1410                         dpm_table->count++;
1411                 }
1412         }
1413         vega10_init_dpm_state(&(dpm_table->dpm_state));
1414
1415         /* Assume there is no headless Vega10 for now */
1416         dpm_table = &(data->dpm_table.dcef_table);
1417         vega10_setup_default_single_dpm_table(hwmgr,
1418                         dpm_table,
1419                         dep_dcef_table);
1420
1421         vega10_init_dpm_state(&(dpm_table->dpm_state));
1422
1423         dpm_table = &(data->dpm_table.pixel_table);
1424         vega10_setup_default_single_dpm_table(hwmgr,
1425                         dpm_table,
1426                         dep_pix_table);
1427
1428         vega10_init_dpm_state(&(dpm_table->dpm_state));
1429
1430         dpm_table = &(data->dpm_table.display_table);
1431         vega10_setup_default_single_dpm_table(hwmgr,
1432                         dpm_table,
1433                         dep_disp_table);
1434
1435         vega10_init_dpm_state(&(dpm_table->dpm_state));
1436
1437         dpm_table = &(data->dpm_table.phy_table);
1438         vega10_setup_default_single_dpm_table(hwmgr,
1439                         dpm_table,
1440                         dep_phy_table);
1441
1442         vega10_init_dpm_state(&(dpm_table->dpm_state));
1443
1444         vega10_setup_default_pcie_table(hwmgr);
1445
1446         /* Zero out the saved copy of the CUSTOM profile
1447          * This will be checked when trying to set the profile
1448          * and will require that new values be passed in
1449          */
1450         data->custom_profile_mode[0] = 0;
1451         data->custom_profile_mode[1] = 0;
1452         data->custom_profile_mode[2] = 0;
1453         data->custom_profile_mode[3] = 0;
1454
1455         /* save a copy of the default DPM table */
1456         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1457                         sizeof(struct vega10_dpm_table));
1458
1459         return 0;
1460 }
1461
1462 /*
1463  * vega10_populate_ulv_state
1464  * Function to provide parameters for Utral Low Voltage state to SMC.
1465  *
1466  * @hwmgr: - the address of the hardware manager.
1467  * return:   Always 0.
1468  */
1469 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1470 {
1471         struct vega10_hwmgr *data = hwmgr->backend;
1472         struct phm_ppt_v2_information *table_info =
1473                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1474
1475         data->smc_state_table.pp_table.UlvOffsetVid =
1476                         (uint8_t)table_info->us_ulv_voltage_offset;
1477
1478         data->smc_state_table.pp_table.UlvSmnclkDid =
1479                         (uint8_t)(table_info->us_ulv_smnclk_did);
1480         data->smc_state_table.pp_table.UlvMp1clkDid =
1481                         (uint8_t)(table_info->us_ulv_mp1clk_did);
1482         data->smc_state_table.pp_table.UlvGfxclkBypass =
1483                         (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1484         data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1485                         (uint8_t)(data->vddc_voltage_table.psi0_enable);
1486         data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1487                         (uint8_t)(data->vddc_voltage_table.psi1_enable);
1488
1489         return 0;
1490 }
1491
1492 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1493                 uint32_t lclock, uint8_t *curr_lclk_did)
1494 {
1495         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1496
1497         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1498                         hwmgr,
1499                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1500                         lclock, &dividers),
1501                         "Failed to get LCLK clock settings from VBIOS!",
1502                         return -1);
1503
1504         *curr_lclk_did = dividers.ulDid;
1505
1506         return 0;
1507 }
1508
1509 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr)
1510 {
1511         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
1512         struct vega10_hwmgr *data =
1513                         (struct vega10_hwmgr *)(hwmgr->backend);
1514         uint32_t pcie_gen = 0, pcie_width = 0;
1515         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1516         int i;
1517
1518         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1519                 pcie_gen = 3;
1520         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1521                 pcie_gen = 2;
1522         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1523                 pcie_gen = 1;
1524         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1525                 pcie_gen = 0;
1526
1527         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1528                 pcie_width = 6;
1529         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1530                 pcie_width = 5;
1531         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1532                 pcie_width = 4;
1533         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1534                 pcie_width = 3;
1535         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1536                 pcie_width = 2;
1537         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1538                 pcie_width = 1;
1539
1540         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1541                 if (pp_table->PcieGenSpeed[i] > pcie_gen)
1542                         pp_table->PcieGenSpeed[i] = pcie_gen;
1543
1544                 if (pp_table->PcieLaneCount[i] > pcie_width)
1545                         pp_table->PcieLaneCount[i] = pcie_width;
1546         }
1547
1548         if (data->registry_data.pcie_dpm_key_disabled) {
1549                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1550                         pp_table->PcieGenSpeed[i] = pcie_gen;
1551                         pp_table->PcieLaneCount[i] = pcie_width;
1552                 }
1553         }
1554
1555         return 0;
1556 }
1557
1558 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1559 {
1560         int result = -1;
1561         struct vega10_hwmgr *data = hwmgr->backend;
1562         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1563         struct vega10_pcie_table *pcie_table =
1564                         &(data->dpm_table.pcie_table);
1565         uint32_t i, j;
1566
1567         for (i = 0; i < pcie_table->count; i++) {
1568                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1569                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1570
1571                 result = vega10_populate_single_lclk_level(hwmgr,
1572                                 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1573                 if (result) {
1574                         pr_info("Populate LClock Level %d Failed!\n", i);
1575                         return result;
1576                 }
1577         }
1578
1579         j = i - 1;
1580         while (i < NUM_LINK_LEVELS) {
1581                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1582                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1583
1584                 result = vega10_populate_single_lclk_level(hwmgr,
1585                                 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1586                 if (result) {
1587                         pr_info("Populate LClock Level %d Failed!\n", i);
1588                         return result;
1589                 }
1590                 i++;
1591         }
1592
1593         return result;
1594 }
1595
1596 /**
1597  * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure
1598  *                                    using the provided engine clock
1599  *
1600  * @hwmgr:      the address of the hardware manager
1601  * @gfx_clock:  the GFX clock to use to populate the structure.
1602  * @current_gfxclk_level:  location in PPTable for the SMC GFXCLK structure.
1603  * @acg_freq:   ACG frequenty to return (MHz)
1604  */
1605 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1606                 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1607                 uint32_t *acg_freq)
1608 {
1609         struct phm_ppt_v2_information *table_info =
1610                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1611         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1612         struct vega10_hwmgr *data = hwmgr->backend;
1613         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1614         uint32_t gfx_max_clock =
1615                         hwmgr->platform_descriptor.overdriveLimit.engineClock;
1616         uint32_t i = 0;
1617
1618         if (hwmgr->od_enabled)
1619                 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1620                                                 &(data->odn_dpm_table.vdd_dep_on_sclk);
1621         else
1622                 dep_on_sclk = table_info->vdd_dep_on_sclk;
1623
1624         PP_ASSERT_WITH_CODE(dep_on_sclk,
1625                         "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1626                         return -EINVAL);
1627
1628         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1629                 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1630         else {
1631                 for (i = 0; i < dep_on_sclk->count; i++) {
1632                         if (dep_on_sclk->entries[i].clk == gfx_clock)
1633                                 break;
1634                 }
1635                 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1636                                 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1637                                 return -EINVAL);
1638         }
1639
1640         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1641                         COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1642                         gfx_clock, &dividers),
1643                         "Failed to get GFX Clock settings from VBIOS!",
1644                         return -EINVAL);
1645
1646         /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1647         current_gfxclk_level->FbMult =
1648                         cpu_to_le32(dividers.ulPll_fb_mult);
1649         /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1650         current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1651         current_gfxclk_level->SsFbMult =
1652                         cpu_to_le32(dividers.ulPll_ss_fbsmult);
1653         current_gfxclk_level->SsSlewFrac =
1654                         cpu_to_le16(dividers.usPll_ss_slew_frac);
1655         current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1656
1657         *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1658
1659         return 0;
1660 }
1661
1662 /**
1663  * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure
1664  *                                    using the provided clock.
1665  *
1666  * @hwmgr:     the address of the hardware manager.
1667  * @soc_clock: the SOC clock to use to populate the structure.
1668  * @current_soc_did:   DFS divider to pass back to caller
1669  * @current_vol_index: index of current VDD to pass back to caller
1670  * return:      0 on success
1671  */
1672 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1673                 uint32_t soc_clock, uint8_t *current_soc_did,
1674                 uint8_t *current_vol_index)
1675 {
1676         struct vega10_hwmgr *data = hwmgr->backend;
1677         struct phm_ppt_v2_information *table_info =
1678                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1679         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1680         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1681         uint32_t i;
1682
1683         if (hwmgr->od_enabled) {
1684                 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1685                                                 &data->odn_dpm_table.vdd_dep_on_socclk;
1686                 for (i = 0; i < dep_on_soc->count; i++) {
1687                         if (dep_on_soc->entries[i].clk >= soc_clock)
1688                                 break;
1689                 }
1690         } else {
1691                 dep_on_soc = table_info->vdd_dep_on_socclk;
1692                 for (i = 0; i < dep_on_soc->count; i++) {
1693                         if (dep_on_soc->entries[i].clk == soc_clock)
1694                                 break;
1695                 }
1696         }
1697
1698         PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1699                         "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1700                         return -EINVAL);
1701
1702         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1703                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1704                         soc_clock, &dividers),
1705                         "Failed to get SOC Clock settings from VBIOS!",
1706                         return -EINVAL);
1707
1708         *current_soc_did = (uint8_t)dividers.ulDid;
1709         *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1710         return 0;
1711 }
1712
1713 /**
1714  * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure
1715  *                                      based on the trimmed allowed dpm engine clock states
1716  *
1717  * @hwmgr:      the address of the hardware manager
1718  */
1719 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1720 {
1721         struct vega10_hwmgr *data = hwmgr->backend;
1722         struct phm_ppt_v2_information *table_info =
1723                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1724         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1725         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1726         int result = 0;
1727         uint32_t i, j;
1728
1729         for (i = 0; i < dpm_table->count; i++) {
1730                 result = vega10_populate_single_gfx_level(hwmgr,
1731                                 dpm_table->dpm_levels[i].value,
1732                                 &(pp_table->GfxclkLevel[i]),
1733                                 &(pp_table->AcgFreqTable[i]));
1734                 if (result)
1735                         return result;
1736         }
1737
1738         j = i - 1;
1739         while (i < NUM_GFXCLK_DPM_LEVELS) {
1740                 result = vega10_populate_single_gfx_level(hwmgr,
1741                                 dpm_table->dpm_levels[j].value,
1742                                 &(pp_table->GfxclkLevel[i]),
1743                                 &(pp_table->AcgFreqTable[i]));
1744                 if (result)
1745                         return result;
1746                 i++;
1747         }
1748
1749         pp_table->GfxclkSlewRate =
1750                         cpu_to_le16(table_info->us_gfxclk_slew_rate);
1751
1752         dpm_table = &(data->dpm_table.soc_table);
1753         for (i = 0; i < dpm_table->count; i++) {
1754                 result = vega10_populate_single_soc_level(hwmgr,
1755                                 dpm_table->dpm_levels[i].value,
1756                                 &(pp_table->SocclkDid[i]),
1757                                 &(pp_table->SocDpmVoltageIndex[i]));
1758                 if (result)
1759                         return result;
1760         }
1761
1762         j = i - 1;
1763         while (i < NUM_SOCCLK_DPM_LEVELS) {
1764                 result = vega10_populate_single_soc_level(hwmgr,
1765                                 dpm_table->dpm_levels[j].value,
1766                                 &(pp_table->SocclkDid[i]),
1767                                 &(pp_table->SocDpmVoltageIndex[i]));
1768                 if (result)
1769                         return result;
1770                 i++;
1771         }
1772
1773         return result;
1774 }
1775
1776 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1777 {
1778         struct vega10_hwmgr *data = hwmgr->backend;
1779         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1780         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1781         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1782
1783         uint8_t soc_vid = 0;
1784         uint32_t i, max_vddc_level;
1785
1786         if (hwmgr->od_enabled)
1787                 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1788         else
1789                 vddc_lookup_table = table_info->vddc_lookup_table;
1790
1791         max_vddc_level = vddc_lookup_table->count;
1792         for (i = 0; i < max_vddc_level; i++) {
1793                 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1794                 pp_table->SocVid[i] = soc_vid;
1795         }
1796         while (i < MAX_REGULAR_DPM_NUMBER) {
1797                 pp_table->SocVid[i] = soc_vid;
1798                 i++;
1799         }
1800 }
1801
1802 /*
1803  * Populates single SMC GFXCLK structure using the provided clock.
1804  *
1805  * @hwmgr:     the address of the hardware manager.
1806  * @mem_clock: the memory clock to use to populate the structure.
1807  * return:     0 on success..
1808  */
1809 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1810                 uint32_t mem_clock, uint8_t *current_mem_vid,
1811                 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1812 {
1813         struct vega10_hwmgr *data = hwmgr->backend;
1814         struct phm_ppt_v2_information *table_info =
1815                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1816         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1817         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1818         uint32_t mem_max_clock =
1819                         hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1820         uint32_t i = 0;
1821
1822         if (hwmgr->od_enabled)
1823                 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1824                                         &data->odn_dpm_table.vdd_dep_on_mclk;
1825         else
1826                 dep_on_mclk = table_info->vdd_dep_on_mclk;
1827
1828         PP_ASSERT_WITH_CODE(dep_on_mclk,
1829                         "Invalid SOC_VDD-UCLK Dependency Table!",
1830                         return -EINVAL);
1831
1832         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1833                 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1834         } else {
1835                 for (i = 0; i < dep_on_mclk->count; i++) {
1836                         if (dep_on_mclk->entries[i].clk == mem_clock)
1837                                 break;
1838                 }
1839                 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1840                                 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1841                                 return -EINVAL);
1842         }
1843
1844         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1845                         hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
1846                         "Failed to get UCLK settings from VBIOS!",
1847                         return -1);
1848
1849         *current_mem_vid =
1850                         (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1851         *current_mem_soc_vind =
1852                         (uint8_t)(dep_on_mclk->entries[i].vddInd);
1853         current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1854         current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1855
1856         PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1857                         "Invalid Divider ID!",
1858                         return -EINVAL);
1859
1860         return 0;
1861 }
1862
1863 /**
1864  * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure
1865  *                                     based on the trimmed allowed dpm memory clock states.
1866  *
1867  * @hwmgr:  the address of the hardware manager.
1868  * return:   PP_Result_OK on success.
1869  */
1870 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1871 {
1872         struct vega10_hwmgr *data = hwmgr->backend;
1873         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1874         struct vega10_single_dpm_table *dpm_table =
1875                         &(data->dpm_table.mem_table);
1876         int result = 0;
1877         uint32_t i, j;
1878
1879         for (i = 0; i < dpm_table->count; i++) {
1880                 result = vega10_populate_single_memory_level(hwmgr,
1881                                 dpm_table->dpm_levels[i].value,
1882                                 &(pp_table->MemVid[i]),
1883                                 &(pp_table->UclkLevel[i]),
1884                                 &(pp_table->MemSocVoltageIndex[i]));
1885                 if (result)
1886                         return result;
1887         }
1888
1889         j = i - 1;
1890         while (i < NUM_UCLK_DPM_LEVELS) {
1891                 result = vega10_populate_single_memory_level(hwmgr,
1892                                 dpm_table->dpm_levels[j].value,
1893                                 &(pp_table->MemVid[i]),
1894                                 &(pp_table->UclkLevel[i]),
1895                                 &(pp_table->MemSocVoltageIndex[i]));
1896                 if (result)
1897                         return result;
1898                 i++;
1899         }
1900
1901         pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1902         pp_table->MemoryChannelWidth =
1903                         (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1904                                         channel_number[data->mem_channels]);
1905
1906         pp_table->LowestUclkReservedForUlv =
1907                         (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1908
1909         return result;
1910 }
1911
1912 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1913                 DSPCLK_e disp_clock)
1914 {
1915         struct vega10_hwmgr *data = hwmgr->backend;
1916         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1917         struct phm_ppt_v2_information *table_info =
1918                         (struct phm_ppt_v2_information *)
1919                         (hwmgr->pptable);
1920         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1921         uint32_t i;
1922         uint16_t clk = 0, vddc = 0;
1923         uint8_t vid = 0;
1924
1925         switch (disp_clock) {
1926         case DSPCLK_DCEFCLK:
1927                 dep_table = table_info->vdd_dep_on_dcefclk;
1928                 break;
1929         case DSPCLK_DISPCLK:
1930                 dep_table = table_info->vdd_dep_on_dispclk;
1931                 break;
1932         case DSPCLK_PIXCLK:
1933                 dep_table = table_info->vdd_dep_on_pixclk;
1934                 break;
1935         case DSPCLK_PHYCLK:
1936                 dep_table = table_info->vdd_dep_on_phyclk;
1937                 break;
1938         default:
1939                 return -1;
1940         }
1941
1942         PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1943                         "Number Of Entries Exceeded maximum!",
1944                         return -1);
1945
1946         for (i = 0; i < dep_table->count; i++) {
1947                 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1948                 vddc = table_info->vddc_lookup_table->
1949                                 entries[dep_table->entries[i].vddInd].us_vdd;
1950                 vid = (uint8_t)convert_to_vid(vddc);
1951                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1952                                 cpu_to_le16(clk);
1953                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1954                                 cpu_to_le16(vid);
1955         }
1956
1957         while (i < NUM_DSPCLK_LEVELS) {
1958                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1959                                 cpu_to_le16(clk);
1960                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1961                                 cpu_to_le16(vid);
1962                 i++;
1963         }
1964
1965         return 0;
1966 }
1967
1968 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1969 {
1970         uint32_t i;
1971
1972         for (i = 0; i < DSPCLK_COUNT; i++) {
1973                 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1974                                 "Failed to populate Clock in DisplayClockTable!",
1975                                 return -1);
1976         }
1977
1978         return 0;
1979 }
1980
1981 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1982                 uint32_t eclock, uint8_t *current_eclk_did,
1983                 uint8_t *current_soc_vol)
1984 {
1985         struct phm_ppt_v2_information *table_info =
1986                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1987         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1988                         table_info->mm_dep_table;
1989         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1990         uint32_t i;
1991
1992         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1993                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1994                         eclock, &dividers),
1995                         "Failed to get ECLK clock settings from VBIOS!",
1996                         return -1);
1997
1998         *current_eclk_did = (uint8_t)dividers.ulDid;
1999
2000         for (i = 0; i < dep_table->count; i++) {
2001                 if (dep_table->entries[i].eclk == eclock)
2002                         *current_soc_vol = dep_table->entries[i].vddcInd;
2003         }
2004
2005         return 0;
2006 }
2007
2008 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
2009 {
2010         struct vega10_hwmgr *data = hwmgr->backend;
2011         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2012         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
2013         int result = -EINVAL;
2014         uint32_t i, j;
2015
2016         for (i = 0; i < dpm_table->count; i++) {
2017                 result = vega10_populate_single_eclock_level(hwmgr,
2018                                 dpm_table->dpm_levels[i].value,
2019                                 &(pp_table->EclkDid[i]),
2020                                 &(pp_table->VceDpmVoltageIndex[i]));
2021                 if (result)
2022                         return result;
2023         }
2024
2025         j = i - 1;
2026         while (i < NUM_VCE_DPM_LEVELS) {
2027                 result = vega10_populate_single_eclock_level(hwmgr,
2028                                 dpm_table->dpm_levels[j].value,
2029                                 &(pp_table->EclkDid[i]),
2030                                 &(pp_table->VceDpmVoltageIndex[i]));
2031                 if (result)
2032                         return result;
2033                 i++;
2034         }
2035
2036         return result;
2037 }
2038
2039 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
2040                 uint32_t vclock, uint8_t *current_vclk_did)
2041 {
2042         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2043
2044         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2045                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2046                         vclock, &dividers),
2047                         "Failed to get VCLK clock settings from VBIOS!",
2048                         return -EINVAL);
2049
2050         *current_vclk_did = (uint8_t)dividers.ulDid;
2051
2052         return 0;
2053 }
2054
2055 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
2056                 uint32_t dclock, uint8_t *current_dclk_did)
2057 {
2058         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2059
2060         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2061                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2062                         dclock, &dividers),
2063                         "Failed to get DCLK clock settings from VBIOS!",
2064                         return -EINVAL);
2065
2066         *current_dclk_did = (uint8_t)dividers.ulDid;
2067
2068         return 0;
2069 }
2070
2071 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
2072 {
2073         struct vega10_hwmgr *data = hwmgr->backend;
2074         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2075         struct vega10_single_dpm_table *vclk_dpm_table =
2076                         &(data->dpm_table.vclk_table);
2077         struct vega10_single_dpm_table *dclk_dpm_table =
2078                         &(data->dpm_table.dclk_table);
2079         struct phm_ppt_v2_information *table_info =
2080                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2081         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
2082                         table_info->mm_dep_table;
2083         int result = -EINVAL;
2084         uint32_t i, j;
2085
2086         for (i = 0; i < vclk_dpm_table->count; i++) {
2087                 result = vega10_populate_single_vclock_level(hwmgr,
2088                                 vclk_dpm_table->dpm_levels[i].value,
2089                                 &(pp_table->VclkDid[i]));
2090                 if (result)
2091                         return result;
2092         }
2093
2094         j = i - 1;
2095         while (i < NUM_UVD_DPM_LEVELS) {
2096                 result = vega10_populate_single_vclock_level(hwmgr,
2097                                 vclk_dpm_table->dpm_levels[j].value,
2098                                 &(pp_table->VclkDid[i]));
2099                 if (result)
2100                         return result;
2101                 i++;
2102         }
2103
2104         for (i = 0; i < dclk_dpm_table->count; i++) {
2105                 result = vega10_populate_single_dclock_level(hwmgr,
2106                                 dclk_dpm_table->dpm_levels[i].value,
2107                                 &(pp_table->DclkDid[i]));
2108                 if (result)
2109                         return result;
2110         }
2111
2112         j = i - 1;
2113         while (i < NUM_UVD_DPM_LEVELS) {
2114                 result = vega10_populate_single_dclock_level(hwmgr,
2115                                 dclk_dpm_table->dpm_levels[j].value,
2116                                 &(pp_table->DclkDid[i]));
2117                 if (result)
2118                         return result;
2119                 i++;
2120         }
2121
2122         for (i = 0; i < dep_table->count; i++) {
2123                 if (dep_table->entries[i].vclk ==
2124                                 vclk_dpm_table->dpm_levels[i].value &&
2125                         dep_table->entries[i].dclk ==
2126                                 dclk_dpm_table->dpm_levels[i].value)
2127                         pp_table->UvdDpmVoltageIndex[i] =
2128                                         dep_table->entries[i].vddcInd;
2129                 else
2130                         return -1;
2131         }
2132
2133         j = i - 1;
2134         while (i < NUM_UVD_DPM_LEVELS) {
2135                 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2136                 i++;
2137         }
2138
2139         return 0;
2140 }
2141
2142 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2143 {
2144         struct vega10_hwmgr *data = hwmgr->backend;
2145         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2146         struct phm_ppt_v2_information *table_info =
2147                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2148         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2149                         table_info->vdd_dep_on_sclk;
2150         uint32_t i;
2151
2152         for (i = 0; i < dep_table->count; i++) {
2153                 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2154                 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2155                                 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2162 {
2163         struct vega10_hwmgr *data = hwmgr->backend;
2164         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2165         struct phm_ppt_v2_information *table_info =
2166                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2167         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2168                         table_info->vdd_dep_on_sclk;
2169         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2170         int result = 0;
2171         uint32_t i;
2172
2173         pp_table->MinVoltageVid = (uint8_t)0xff;
2174         pp_table->MaxVoltageVid = (uint8_t)0;
2175
2176         if (data->smu_features[GNLD_AVFS].supported) {
2177                 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2178                 if (!result) {
2179                         pp_table->MinVoltageVid = (uint8_t)
2180                                         convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2181                         pp_table->MaxVoltageVid = (uint8_t)
2182                                         convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2183
2184                         pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2185                         pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2186                         pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2187                         pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2188                         pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2189                         pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2190                         pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2191
2192                         pp_table->BtcGbVdroopTableCksOff.a0 =
2193                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2194                         pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2195                         pp_table->BtcGbVdroopTableCksOff.a1 =
2196                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2197                         pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2198                         pp_table->BtcGbVdroopTableCksOff.a2 =
2199                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2200                         pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2201
2202                         pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2203                         pp_table->BtcGbVdroopTableCksOn.a0 =
2204                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2205                         pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2206                         pp_table->BtcGbVdroopTableCksOn.a1 =
2207                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2208                         pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2209                         pp_table->BtcGbVdroopTableCksOn.a2 =
2210                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2211                         pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2212
2213                         pp_table->AvfsGbCksOn.m1 =
2214                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2215                         pp_table->AvfsGbCksOn.m2 =
2216                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2217                         pp_table->AvfsGbCksOn.b =
2218                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2219                         pp_table->AvfsGbCksOn.m1_shift = 24;
2220                         pp_table->AvfsGbCksOn.m2_shift = 12;
2221                         pp_table->AvfsGbCksOn.b_shift = 0;
2222
2223                         pp_table->OverrideAvfsGbCksOn =
2224                                         avfs_params.ucEnableGbFuseTableCkson;
2225                         pp_table->AvfsGbCksOff.m1 =
2226                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2227                         pp_table->AvfsGbCksOff.m2 =
2228                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2229                         pp_table->AvfsGbCksOff.b =
2230                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2231                         pp_table->AvfsGbCksOff.m1_shift = 24;
2232                         pp_table->AvfsGbCksOff.m2_shift = 12;
2233                         pp_table->AvfsGbCksOff.b_shift = 0;
2234
2235                         for (i = 0; i < dep_table->count; i++)
2236                                 pp_table->StaticVoltageOffsetVid[i] =
2237                                                 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2238
2239                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2240                                         data->disp_clk_quad_eqn_a) &&
2241                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2242                                         data->disp_clk_quad_eqn_b)) {
2243                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2244                                                 (int32_t)data->disp_clk_quad_eqn_a;
2245                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2246                                                 (int32_t)data->disp_clk_quad_eqn_b;
2247                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2248                                                 (int32_t)data->disp_clk_quad_eqn_c;
2249                         } else {
2250                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2251                                                 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2252                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2253                                                 (int32_t)avfs_params.ulDispclk2GfxclkM2;
2254                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2255                                                 (int32_t)avfs_params.ulDispclk2GfxclkB;
2256                         }
2257
2258                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2259                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2260                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2261
2262                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2263                                         data->dcef_clk_quad_eqn_a) &&
2264                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2265                                         data->dcef_clk_quad_eqn_b)) {
2266                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2267                                                 (int32_t)data->dcef_clk_quad_eqn_a;
2268                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2269                                                 (int32_t)data->dcef_clk_quad_eqn_b;
2270                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2271                                                 (int32_t)data->dcef_clk_quad_eqn_c;
2272                         } else {
2273                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2274                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2275                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2276                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM2;
2277                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2278                                                 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2279                         }
2280
2281                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2282                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2283                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2284
2285                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2286                                         data->pixel_clk_quad_eqn_a) &&
2287                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2288                                         data->pixel_clk_quad_eqn_b)) {
2289                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2290                                                 (int32_t)data->pixel_clk_quad_eqn_a;
2291                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2292                                                 (int32_t)data->pixel_clk_quad_eqn_b;
2293                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2294                                                 (int32_t)data->pixel_clk_quad_eqn_c;
2295                         } else {
2296                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2297                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2298                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2299                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM2;
2300                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2301                                                 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2302                         }
2303
2304                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2305                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2306                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2307                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2308                                         data->phy_clk_quad_eqn_a) &&
2309                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2310                                         data->phy_clk_quad_eqn_b)) {
2311                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2312                                                 (int32_t)data->phy_clk_quad_eqn_a;
2313                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2314                                                 (int32_t)data->phy_clk_quad_eqn_b;
2315                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2316                                                 (int32_t)data->phy_clk_quad_eqn_c;
2317                         } else {
2318                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2319                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2320                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2321                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM2;
2322                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2323                                                 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2324                         }
2325
2326                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2327                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2328                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2329
2330                         pp_table->AcgBtcGbVdroopTable.a0       = avfs_params.ulAcgGbVdroopTableA0;
2331                         pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2332                         pp_table->AcgBtcGbVdroopTable.a1       = avfs_params.ulAcgGbVdroopTableA1;
2333                         pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2334                         pp_table->AcgBtcGbVdroopTable.a2       = avfs_params.ulAcgGbVdroopTableA2;
2335                         pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2336
2337                         pp_table->AcgAvfsGb.m1                   = avfs_params.ulAcgGbFuseTableM1;
2338                         pp_table->AcgAvfsGb.m2                   = avfs_params.ulAcgGbFuseTableM2;
2339                         pp_table->AcgAvfsGb.b                    = avfs_params.ulAcgGbFuseTableB;
2340                         pp_table->AcgAvfsGb.m1_shift             = 24;
2341                         pp_table->AcgAvfsGb.m2_shift             = 12;
2342                         pp_table->AcgAvfsGb.b_shift              = 0;
2343
2344                 } else {
2345                         data->smu_features[GNLD_AVFS].supported = false;
2346                 }
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2353 {
2354         struct vega10_hwmgr *data = hwmgr->backend;
2355         uint32_t agc_btc_response;
2356
2357         if (data->smu_features[GNLD_ACG].supported) {
2358                 if (0 == vega10_enable_smc_features(hwmgr, true,
2359                                         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2360                         data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2361
2362                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL);
2363
2364                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response);
2365
2366                 if (1 == agc_btc_response) {
2367                         if (1 == data->acg_loop_state)
2368                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL);
2369                         else if (2 == data->acg_loop_state)
2370                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL);
2371                         if (0 == vega10_enable_smc_features(hwmgr, true,
2372                                 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2373                                         data->smu_features[GNLD_ACG].enabled = true;
2374                 } else {
2375                         pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2376                         data->smu_features[GNLD_ACG].enabled = false;
2377                 }
2378         }
2379
2380         return 0;
2381 }
2382
2383 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2384 {
2385         struct vega10_hwmgr *data = hwmgr->backend;
2386
2387         if (data->smu_features[GNLD_ACG].supported &&
2388             data->smu_features[GNLD_ACG].enabled)
2389                 if (!vega10_enable_smc_features(hwmgr, false,
2390                         data->smu_features[GNLD_ACG].smu_feature_bitmap))
2391                         data->smu_features[GNLD_ACG].enabled = false;
2392
2393         return 0;
2394 }
2395
2396 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2397 {
2398         struct vega10_hwmgr *data = hwmgr->backend;
2399         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2400         struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2401         int result;
2402
2403         result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2404         if (!result) {
2405                 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2406                     data->registry_data.regulator_hot_gpio_support) {
2407                         pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2408                         pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2409                         pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2410                         pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2411                 } else {
2412                         pp_table->VR0HotGpio = 0;
2413                         pp_table->VR0HotPolarity = 0;
2414                         pp_table->VR1HotGpio = 0;
2415                         pp_table->VR1HotPolarity = 0;
2416                 }
2417
2418                 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2419                     data->registry_data.ac_dc_switch_gpio_support) {
2420                         pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2421                         pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2422                 } else {
2423                         pp_table->AcDcGpio = 0;
2424                         pp_table->AcDcPolarity = 0;
2425                 }
2426         }
2427
2428         return result;
2429 }
2430
2431 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2432 {
2433         struct vega10_hwmgr *data = hwmgr->backend;
2434
2435         if (data->smu_features[GNLD_AVFS].supported) {
2436                 /* Already enabled or disabled */
2437                 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))
2438                         return 0;
2439
2440                 if (enable) {
2441                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2442                                         true,
2443                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2444                                         "[avfs_control] Attempt to Enable AVFS feature Failed!",
2445                                         return -1);
2446                         data->smu_features[GNLD_AVFS].enabled = true;
2447                 } else {
2448                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2449                                         false,
2450                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2451                                         "[avfs_control] Attempt to Disable AVFS feature Failed!",
2452                                         return -1);
2453                         data->smu_features[GNLD_AVFS].enabled = false;
2454                 }
2455         }
2456
2457         return 0;
2458 }
2459
2460 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2461 {
2462         struct vega10_hwmgr *data = hwmgr->backend;
2463
2464         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2465                 vega10_avfs_enable(hwmgr, false);
2466         } else if (data->need_update_dpm_table) {
2467                 vega10_avfs_enable(hwmgr, false);
2468                 vega10_avfs_enable(hwmgr, true);
2469         } else {
2470                 vega10_avfs_enable(hwmgr, true);
2471         }
2472
2473         return 0;
2474 }
2475
2476 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2477 {
2478         int result = 0;
2479
2480         uint64_t serial_number = 0;
2481         uint32_t top32, bottom32;
2482         struct phm_fuses_default fuse;
2483
2484         struct vega10_hwmgr *data = hwmgr->backend;
2485         AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2486
2487         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
2488
2489         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
2490
2491         serial_number = ((uint64_t)bottom32 << 32) | top32;
2492
2493         if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2494                 avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
2495                 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2496                 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2497                 avfs_fuse_table->VFT1_b  = fuse.VFT1_b;
2498                 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2499                 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2500                 avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
2501                 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2502                 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2503                 result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
2504                                                 AVFSFUSETABLE, false);
2505                 PP_ASSERT_WITH_CODE(!result,
2506                         "Failed to upload FuseOVerride!",
2507                         );
2508         }
2509
2510         return result;
2511 }
2512
2513 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
2514 {
2515         struct vega10_hwmgr *data = hwmgr->backend;
2516         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2517         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
2518         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
2519         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
2520         uint32_t i;
2521
2522         dep_table = table_info->vdd_dep_on_mclk;
2523         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
2524
2525         for (i = 0; i < dep_table->count; i++) {
2526                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2527                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
2528                         return;
2529                 }
2530         }
2531
2532         dep_table = table_info->vdd_dep_on_sclk;
2533         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
2534         for (i = 0; i < dep_table->count; i++) {
2535                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2536                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
2537                         return;
2538                 }
2539         }
2540 }
2541
2542 /**
2543  * vega10_init_smc_table - Initializes the SMC table and uploads it
2544  *
2545  * @hwmgr:  the address of the powerplay hardware manager.
2546  * return:  always 0
2547  */
2548 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2549 {
2550         int result;
2551         struct vega10_hwmgr *data = hwmgr->backend;
2552         struct phm_ppt_v2_information *table_info =
2553                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2554         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2555         struct pp_atomfwctrl_voltage_table voltage_table;
2556         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2557         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2558
2559         result = vega10_setup_default_dpm_tables(hwmgr);
2560         PP_ASSERT_WITH_CODE(!result,
2561                         "Failed to setup default DPM tables!",
2562                         return result);
2563
2564         if (!hwmgr->not_vf)
2565                 return 0;
2566
2567         /* initialize ODN table */
2568         if (hwmgr->od_enabled) {
2569                 if (odn_table->max_vddc) {
2570                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2571                         vega10_check_dpm_table_updated(hwmgr);
2572                 } else {
2573                         vega10_odn_initial_default_setting(hwmgr);
2574                 }
2575         }
2576
2577         pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2578                         VOLTAGE_OBJ_SVID2,  &voltage_table);
2579         pp_table->MaxVidStep = voltage_table.max_vid_step;
2580
2581         pp_table->GfxDpmVoltageMode =
2582                         (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2583         pp_table->SocDpmVoltageMode =
2584                         (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2585         pp_table->UclkDpmVoltageMode =
2586                         (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2587         pp_table->UvdDpmVoltageMode =
2588                         (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2589         pp_table->VceDpmVoltageMode =
2590                         (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2591         pp_table->Mp0DpmVoltageMode =
2592                         (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2593
2594         pp_table->DisplayDpmVoltageMode =
2595                         (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2596
2597         data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2598         data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2599
2600         if (data->registry_data.ulv_support &&
2601                         table_info->us_ulv_voltage_offset) {
2602                 result = vega10_populate_ulv_state(hwmgr);
2603                 PP_ASSERT_WITH_CODE(!result,
2604                                 "Failed to initialize ULV state!",
2605                                 return result);
2606         }
2607
2608         result = vega10_populate_smc_link_levels(hwmgr);
2609         PP_ASSERT_WITH_CODE(!result,
2610                         "Failed to initialize Link Level!",
2611                         return result);
2612
2613         result = vega10_override_pcie_parameters(hwmgr);
2614         PP_ASSERT_WITH_CODE(!result,
2615                         "Failed to override pcie parameters!",
2616                         return result);
2617
2618         result = vega10_populate_all_graphic_levels(hwmgr);
2619         PP_ASSERT_WITH_CODE(!result,
2620                         "Failed to initialize Graphics Level!",
2621                         return result);
2622
2623         result = vega10_populate_all_memory_levels(hwmgr);
2624         PP_ASSERT_WITH_CODE(!result,
2625                         "Failed to initialize Memory Level!",
2626                         return result);
2627
2628         vega10_populate_vddc_soc_levels(hwmgr);
2629
2630         result = vega10_populate_all_display_clock_levels(hwmgr);
2631         PP_ASSERT_WITH_CODE(!result,
2632                         "Failed to initialize Display Level!",
2633                         return result);
2634
2635         result = vega10_populate_smc_vce_levels(hwmgr);
2636         PP_ASSERT_WITH_CODE(!result,
2637                         "Failed to initialize VCE Level!",
2638                         return result);
2639
2640         result = vega10_populate_smc_uvd_levels(hwmgr);
2641         PP_ASSERT_WITH_CODE(!result,
2642                         "Failed to initialize UVD Level!",
2643                         return result);
2644
2645         if (data->registry_data.clock_stretcher_support) {
2646                 result = vega10_populate_clock_stretcher_table(hwmgr);
2647                 PP_ASSERT_WITH_CODE(!result,
2648                                 "Failed to populate Clock Stretcher Table!",
2649                                 return result);
2650         }
2651
2652         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2653         if (!result) {
2654                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
2655                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
2656                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
2657                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2658                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2659                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2660                                 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk);
2661
2662                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2663                                 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk);
2664
2665                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2666                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2667                 if (0 != boot_up_values.usVddc) {
2668                         smum_send_msg_to_smc_with_parameter(hwmgr,
2669                                                 PPSMC_MSG_SetFloorSocVoltage,
2670                                                 (boot_up_values.usVddc * 4),
2671                                                 NULL);
2672                         data->vbios_boot_state.bsoc_vddc_lock = true;
2673                 } else {
2674                         data->vbios_boot_state.bsoc_vddc_lock = false;
2675                 }
2676                 smum_send_msg_to_smc_with_parameter(hwmgr,
2677                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
2678                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
2679                                 NULL);
2680         }
2681
2682         result = vega10_populate_avfs_parameters(hwmgr);
2683         PP_ASSERT_WITH_CODE(!result,
2684                         "Failed to initialize AVFS Parameters!",
2685                         return result);
2686
2687         result = vega10_populate_gpio_parameters(hwmgr);
2688         PP_ASSERT_WITH_CODE(!result,
2689                         "Failed to initialize GPIO Parameters!",
2690                         return result);
2691
2692         pp_table->GfxclkAverageAlpha = (uint8_t)
2693                         (data->gfxclk_average_alpha);
2694         pp_table->SocclkAverageAlpha = (uint8_t)
2695                         (data->socclk_average_alpha);
2696         pp_table->UclkAverageAlpha = (uint8_t)
2697                         (data->uclk_average_alpha);
2698         pp_table->GfxActivityAverageAlpha = (uint8_t)
2699                         (data->gfx_activity_average_alpha);
2700
2701         vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2702
2703         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2704
2705         PP_ASSERT_WITH_CODE(!result,
2706                         "Failed to upload PPtable!", return result);
2707
2708         result = vega10_avfs_enable(hwmgr, true);
2709         PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2710                                         return result);
2711         vega10_acg_enable(hwmgr);
2712
2713         return 0;
2714 }
2715
2716 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2717 {
2718         struct vega10_hwmgr *data = hwmgr->backend;
2719
2720         if (data->smu_features[GNLD_THERMAL].supported) {
2721                 if (data->smu_features[GNLD_THERMAL].enabled)
2722                         pr_info("THERMAL Feature Already enabled!");
2723
2724                 PP_ASSERT_WITH_CODE(
2725                                 !vega10_enable_smc_features(hwmgr,
2726                                 true,
2727                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2728                                 "Enable THERMAL Feature Failed!",
2729                                 return -1);
2730                 data->smu_features[GNLD_THERMAL].enabled = true;
2731         }
2732
2733         return 0;
2734 }
2735
2736 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2737 {
2738         struct vega10_hwmgr *data = hwmgr->backend;
2739
2740         if (data->smu_features[GNLD_THERMAL].supported) {
2741                 if (!data->smu_features[GNLD_THERMAL].enabled)
2742                         pr_info("THERMAL Feature Already disabled!");
2743
2744                 PP_ASSERT_WITH_CODE(
2745                                 !vega10_enable_smc_features(hwmgr,
2746                                 false,
2747                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2748                                 "disable THERMAL Feature Failed!",
2749                                 return -1);
2750                 data->smu_features[GNLD_THERMAL].enabled = false;
2751         }
2752
2753         return 0;
2754 }
2755
2756 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2757 {
2758         struct vega10_hwmgr *data = hwmgr->backend;
2759
2760         if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2761                 if (data->smu_features[GNLD_VR0HOT].supported) {
2762                         PP_ASSERT_WITH_CODE(
2763                                         !vega10_enable_smc_features(hwmgr,
2764                                         true,
2765                                         data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2766                                         "Attempt to Enable VR0 Hot feature Failed!",
2767                                         return -1);
2768                         data->smu_features[GNLD_VR0HOT].enabled = true;
2769                 } else {
2770                         if (data->smu_features[GNLD_VR1HOT].supported) {
2771                                 PP_ASSERT_WITH_CODE(
2772                                                 !vega10_enable_smc_features(hwmgr,
2773                                                 true,
2774                                                 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2775                                                 "Attempt to Enable VR0 Hot feature Failed!",
2776                                                 return -1);
2777                                 data->smu_features[GNLD_VR1HOT].enabled = true;
2778                         }
2779                 }
2780         }
2781         return 0;
2782 }
2783
2784 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2785 {
2786         struct vega10_hwmgr *data = hwmgr->backend;
2787
2788         if (data->registry_data.ulv_support) {
2789                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2790                                 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2791                                 "Enable ULV Feature Failed!",
2792                                 return -1);
2793                 data->smu_features[GNLD_ULV].enabled = true;
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2800 {
2801         struct vega10_hwmgr *data = hwmgr->backend;
2802
2803         if (data->registry_data.ulv_support) {
2804                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2805                                 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2806                                 "disable ULV Feature Failed!",
2807                                 return -EINVAL);
2808                 data->smu_features[GNLD_ULV].enabled = false;
2809         }
2810
2811         return 0;
2812 }
2813
2814 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2815 {
2816         struct vega10_hwmgr *data = hwmgr->backend;
2817
2818         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2819                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2820                                 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2821                                 "Attempt to Enable DS_GFXCLK Feature Failed!",
2822                                 return -EINVAL);
2823                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2824         }
2825
2826         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2827                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2828                                 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2829                                 "Attempt to Enable DS_SOCCLK Feature Failed!",
2830                                 return -EINVAL);
2831                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2832         }
2833
2834         if (data->smu_features[GNLD_DS_LCLK].supported) {
2835                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2836                                 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2837                                 "Attempt to Enable DS_LCLK Feature Failed!",
2838                                 return -EINVAL);
2839                 data->smu_features[GNLD_DS_LCLK].enabled = true;
2840         }
2841
2842         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2843                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2844                                 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2845                                 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2846                                 return -EINVAL);
2847                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2848         }
2849
2850         return 0;
2851 }
2852
2853 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2854 {
2855         struct vega10_hwmgr *data = hwmgr->backend;
2856
2857         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2858                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2859                                 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2860                                 "Attempt to disable DS_GFXCLK Feature Failed!",
2861                                 return -EINVAL);
2862                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2863         }
2864
2865         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2866                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2867                                 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2868                                 "Attempt to disable DS_ Feature Failed!",
2869                                 return -EINVAL);
2870                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2871         }
2872
2873         if (data->smu_features[GNLD_DS_LCLK].supported) {
2874                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2875                                 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2876                                 "Attempt to disable DS_LCLK Feature Failed!",
2877                                 return -EINVAL);
2878                 data->smu_features[GNLD_DS_LCLK].enabled = false;
2879         }
2880
2881         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2882                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2883                                 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2884                                 "Attempt to disable DS_DCEFCLK Feature Failed!",
2885                                 return -EINVAL);
2886                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2887         }
2888
2889         return 0;
2890 }
2891
2892 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2893 {
2894         struct vega10_hwmgr *data = hwmgr->backend;
2895         uint32_t i, feature_mask = 0;
2896
2897         if (!hwmgr->not_vf)
2898                 return 0;
2899
2900         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2901                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2902                                 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2903                 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2904                 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2905         }
2906
2907         for (i = 0; i < GNLD_DPM_MAX; i++) {
2908                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2909                         if (data->smu_features[i].supported) {
2910                                 if (data->smu_features[i].enabled) {
2911                                         feature_mask |= data->smu_features[i].
2912                                                         smu_feature_bitmap;
2913                                         data->smu_features[i].enabled = false;
2914                                 }
2915                         }
2916                 }
2917         }
2918
2919         vega10_enable_smc_features(hwmgr, false, feature_mask);
2920
2921         return 0;
2922 }
2923
2924 /**
2925  * vega10_start_dpm - Tell SMC to enabled the supported DPMs.
2926  *
2927  * @hwmgr:   the address of the powerplay hardware manager.
2928  * @bitmap:  bitmap for the features to enabled.
2929  * return:  0 on at least one DPM is successfully enabled.
2930  */
2931 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2932 {
2933         struct vega10_hwmgr *data = hwmgr->backend;
2934         uint32_t i, feature_mask = 0;
2935
2936         for (i = 0; i < GNLD_DPM_MAX; i++) {
2937                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2938                         if (data->smu_features[i].supported) {
2939                                 if (!data->smu_features[i].enabled) {
2940                                         feature_mask |= data->smu_features[i].
2941                                                         smu_feature_bitmap;
2942                                         data->smu_features[i].enabled = true;
2943                                 }
2944                         }
2945                 }
2946         }
2947
2948         if (vega10_enable_smc_features(hwmgr,
2949                         true, feature_mask)) {
2950                 for (i = 0; i < GNLD_DPM_MAX; i++) {
2951                         if (data->smu_features[i].smu_feature_bitmap &
2952                                         feature_mask)
2953                                 data->smu_features[i].enabled = false;
2954                 }
2955         }
2956
2957         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2958                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2959                                 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2960                 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2961                 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2962         }
2963
2964         if (data->vbios_boot_state.bsoc_vddc_lock) {
2965                 smum_send_msg_to_smc_with_parameter(hwmgr,
2966                                                 PPSMC_MSG_SetFloorSocVoltage, 0,
2967                                                 NULL);
2968                 data->vbios_boot_state.bsoc_vddc_lock = false;
2969         }
2970
2971         if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2972                 if (data->smu_features[GNLD_ACDC].supported) {
2973                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2974                                         true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2975                                         "Attempt to Enable DS_GFXCLK Feature Failed!",
2976                                         return -1);
2977                         data->smu_features[GNLD_ACDC].enabled = true;
2978                 }
2979         }
2980
2981         if (data->registry_data.pcie_dpm_key_disabled) {
2982                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2983                                 false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap),
2984                 "Attempt to Disable Link DPM feature Failed!", return -EINVAL);
2985                 data->smu_features[GNLD_DPM_LINK].enabled = false;
2986                 data->smu_features[GNLD_DPM_LINK].supported = false;
2987         }
2988
2989         return 0;
2990 }
2991
2992
2993 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2994 {
2995         struct vega10_hwmgr *data = hwmgr->backend;
2996
2997         if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2998                 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2999                         pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
3000                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3001                                 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
3002                                 "Attempt to Enable PCC Limit feature Failed!",
3003                                 return -EINVAL);
3004                 data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
3005         }
3006
3007         return 0;
3008 }
3009
3010 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3011 {
3012         struct vega10_hwmgr *data = hwmgr->backend;
3013         int tmp_result, result = 0;
3014
3015         if (hwmgr->not_vf) {
3016                 vega10_enable_disable_PCC_limit_feature(hwmgr, true);
3017
3018                 smum_send_msg_to_smc_with_parameter(hwmgr,
3019                         PPSMC_MSG_ConfigureTelemetry, data->config_telemetry,
3020                         NULL);
3021
3022                 tmp_result = vega10_construct_voltage_tables(hwmgr);
3023                 PP_ASSERT_WITH_CODE(!tmp_result,
3024                                     "Failed to construct voltage tables!",
3025                                     result = tmp_result);
3026         }
3027
3028         if (hwmgr->not_vf || hwmgr->pp_one_vf) {
3029                 tmp_result = vega10_init_smc_table(hwmgr);
3030                 PP_ASSERT_WITH_CODE(!tmp_result,
3031                                     "Failed to initialize SMC table!",
3032                                     result = tmp_result);
3033         }
3034
3035         if (hwmgr->not_vf) {
3036                 if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
3037                         tmp_result = vega10_enable_thermal_protection(hwmgr);
3038                         PP_ASSERT_WITH_CODE(!tmp_result,
3039                                             "Failed to enable thermal protection!",
3040                                             result = tmp_result);
3041                 }
3042
3043                 tmp_result = vega10_enable_vrhot_feature(hwmgr);
3044                 PP_ASSERT_WITH_CODE(!tmp_result,
3045                                     "Failed to enable VR hot feature!",
3046                                     result = tmp_result);
3047
3048                 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
3049                 PP_ASSERT_WITH_CODE(!tmp_result,
3050                                     "Failed to enable deep sleep master switch!",
3051                                     result = tmp_result);
3052         }
3053
3054         if (hwmgr->not_vf) {
3055                 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
3056                 PP_ASSERT_WITH_CODE(!tmp_result,
3057                                     "Failed to start DPM!", result = tmp_result);
3058         }
3059
3060         if (hwmgr->not_vf) {
3061                 /* enable didt, do not abort if failed didt */
3062                 tmp_result = vega10_enable_didt_config(hwmgr);
3063                 PP_ASSERT(!tmp_result,
3064                           "Failed to enable didt config!");
3065         }
3066
3067         tmp_result = vega10_enable_power_containment(hwmgr);
3068         PP_ASSERT_WITH_CODE(!tmp_result,
3069                             "Failed to enable power containment!",
3070                             result = tmp_result);
3071
3072         if (hwmgr->not_vf) {
3073                 tmp_result = vega10_power_control_set_level(hwmgr);
3074                 PP_ASSERT_WITH_CODE(!tmp_result,
3075                                     "Failed to power control set level!",
3076                                     result = tmp_result);
3077
3078                 tmp_result = vega10_enable_ulv(hwmgr);
3079                 PP_ASSERT_WITH_CODE(!tmp_result,
3080                                     "Failed to enable ULV!",
3081                                     result = tmp_result);
3082         }
3083
3084         return result;
3085 }
3086
3087 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
3088 {
3089         return sizeof(struct vega10_power_state);
3090 }
3091
3092 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3093                 void *state, struct pp_power_state *power_state,
3094                 void *pp_table, uint32_t classification_flag)
3095 {
3096         ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
3097         struct vega10_power_state *vega10_ps =
3098                         cast_phw_vega10_power_state(&(power_state->hardware));
3099         struct vega10_performance_level *performance_level;
3100         ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
3101         ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
3102                         (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
3103         ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
3104                         (ATOM_Vega10_SOCCLK_Dependency_Table *)
3105                         (((unsigned long)powerplay_table) +
3106                         le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
3107         ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
3108                         (ATOM_Vega10_GFXCLK_Dependency_Table *)
3109                         (((unsigned long)powerplay_table) +
3110                         le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
3111         ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
3112                         (ATOM_Vega10_MCLK_Dependency_Table *)
3113                         (((unsigned long)powerplay_table) +
3114                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3115
3116
3117         /* The following fields are not initialized here:
3118          * id orderedList allStatesList
3119          */
3120         power_state->classification.ui_label =
3121                         (le16_to_cpu(state_entry->usClassification) &
3122                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3123                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3124         power_state->classification.flags = classification_flag;
3125         /* NOTE: There is a classification2 flag in BIOS
3126          * that is not being used right now
3127          */
3128         power_state->classification.temporary_state = false;
3129         power_state->classification.to_be_deleted = false;
3130
3131         power_state->validation.disallowOnDC =
3132                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3133                                         ATOM_Vega10_DISALLOW_ON_DC) != 0);
3134
3135         power_state->display.disableFrameModulation = false;
3136         power_state->display.limitRefreshrate = false;
3137         power_state->display.enableVariBright =
3138                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3139                                         ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
3140
3141         power_state->validation.supportedPowerLevels = 0;
3142         power_state->uvd_clocks.VCLK = 0;
3143         power_state->uvd_clocks.DCLK = 0;
3144         power_state->temperatures.min = 0;
3145         power_state->temperatures.max = 0;
3146
3147         performance_level = &(vega10_ps->performance_levels
3148                         [vega10_ps->performance_level_count++]);
3149
3150         PP_ASSERT_WITH_CODE(
3151                         (vega10_ps->performance_level_count <
3152                                         NUM_GFXCLK_DPM_LEVELS),
3153                         "Performance levels exceeds SMC limit!",
3154                         return -1);
3155
3156         PP_ASSERT_WITH_CODE(
3157                         (vega10_ps->performance_level_count <
3158                                         hwmgr->platform_descriptor.
3159                                         hardwareActivityPerformanceLevels),
3160                         "Performance levels exceeds Driver limit!",
3161                         return -1);
3162
3163         /* Performance levels are arranged from low to high. */
3164         performance_level->soc_clock = socclk_dep_table->entries
3165                         [state_entry->ucSocClockIndexLow].ulClk;
3166         performance_level->gfx_clock = gfxclk_dep_table->entries
3167                         [state_entry->ucGfxClockIndexLow].ulClk;
3168         performance_level->mem_clock = mclk_dep_table->entries
3169                         [state_entry->ucMemClockIndexLow].ulMemClk;
3170
3171         performance_level = &(vega10_ps->performance_levels
3172                                 [vega10_ps->performance_level_count++]);
3173         performance_level->soc_clock = socclk_dep_table->entries
3174                                 [state_entry->ucSocClockIndexHigh].ulClk;
3175         if (gfxclk_dep_table->ucRevId == 0) {
3176                 /* under vega10 pp one vf mode, the gfx clk dpm need be lower
3177                  * to level-4 due to the limited 110w-power
3178                  */
3179                 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3180                         performance_level->gfx_clock =
3181                                 gfxclk_dep_table->entries[4].ulClk;
3182                 else
3183                         performance_level->gfx_clock = gfxclk_dep_table->entries
3184                                 [state_entry->ucGfxClockIndexHigh].ulClk;
3185         } else if (gfxclk_dep_table->ucRevId == 1) {
3186                 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3187                 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3188                         performance_level->gfx_clock = patom_record_V2[4].ulClk;
3189                 else
3190                         performance_level->gfx_clock =
3191                                 patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3192         }
3193
3194         performance_level->mem_clock = mclk_dep_table->entries
3195                         [state_entry->ucMemClockIndexHigh].ulMemClk;
3196         return 0;
3197 }
3198
3199 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3200                 unsigned long entry_index, struct pp_power_state *state)
3201 {
3202         int result;
3203         struct vega10_power_state *vega10_ps;
3204
3205         state->hardware.magic = PhwVega10_Magic;
3206
3207         vega10_ps = cast_phw_vega10_power_state(&state->hardware);
3208
3209         result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3210                         vega10_get_pp_table_entry_callback_func);
3211         if (result)
3212                 return result;
3213
3214         /*
3215          * This is the earliest time we have all the dependency table
3216          * and the VBIOS boot state
3217          */
3218         /* set DC compatible flag if this state supports DC */
3219         if (!state->validation.disallowOnDC)
3220                 vega10_ps->dc_compatible = true;
3221
3222         vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3223         vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3224
3225         return 0;
3226 }
3227
3228 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3229              struct pp_hw_power_state *hw_ps)
3230 {
3231         return 0;
3232 }
3233
3234 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3235                                 struct pp_power_state  *request_ps,
3236                         const struct pp_power_state *current_ps)
3237 {
3238         struct amdgpu_device *adev = hwmgr->adev;
3239         struct vega10_power_state *vega10_ps =
3240                                 cast_phw_vega10_power_state(&request_ps->hardware);
3241         uint32_t sclk;
3242         uint32_t mclk;
3243         struct PP_Clocks minimum_clocks = {0};
3244         bool disable_mclk_switching;
3245         bool disable_mclk_switching_for_frame_lock;
3246         bool disable_mclk_switching_for_vr;
3247         bool force_mclk_high;
3248         const struct phm_clock_and_voltage_limits *max_limits;
3249         uint32_t i;
3250         struct vega10_hwmgr *data = hwmgr->backend;
3251         struct phm_ppt_v2_information *table_info =
3252                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3253         int32_t count;
3254         uint32_t stable_pstate_sclk_dpm_percentage;
3255         uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3256         uint32_t latency;
3257
3258         data->battery_state = (PP_StateUILabel_Battery ==
3259                         request_ps->classification.ui_label);
3260
3261         if (vega10_ps->performance_level_count != 2)
3262                 pr_info("VI should always have 2 performance levels");
3263
3264         max_limits = adev->pm.ac_power ?
3265                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3266                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3267
3268         /* Cap clock DPM tables at DC MAX if it is in DC. */
3269         if (!adev->pm.ac_power) {
3270                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3271                         if (vega10_ps->performance_levels[i].mem_clock >
3272                                 max_limits->mclk)
3273                                 vega10_ps->performance_levels[i].mem_clock =
3274                                                 max_limits->mclk;
3275                         if (vega10_ps->performance_levels[i].gfx_clock >
3276                                 max_limits->sclk)
3277                                 vega10_ps->performance_levels[i].gfx_clock =
3278                                                 max_limits->sclk;
3279                 }
3280         }
3281
3282         /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3283         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3284         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3285
3286         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3287                 stable_pstate_sclk_dpm_percentage =
3288                         data->registry_data.stable_pstate_sclk_dpm_percentage;
3289                 PP_ASSERT_WITH_CODE(
3290                         data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3291                         data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3292                         "percent sclk value must range from 1% to 100%, setting default value",
3293                         stable_pstate_sclk_dpm_percentage = 75);
3294
3295                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3296                 stable_pstate_sclk = (max_limits->sclk *
3297                                 stable_pstate_sclk_dpm_percentage) / 100;
3298
3299                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3300                                 count >= 0; count--) {
3301                         if (stable_pstate_sclk >=
3302                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3303                                 stable_pstate_sclk =
3304                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3305                                 break;
3306                         }
3307                 }
3308
3309                 if (count < 0)
3310                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3311
3312                 stable_pstate_mclk = max_limits->mclk;
3313
3314                 minimum_clocks.engineClock = stable_pstate_sclk;
3315                 minimum_clocks.memoryClock = stable_pstate_mclk;
3316         }
3317
3318         disable_mclk_switching_for_frame_lock =
3319                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3320         disable_mclk_switching_for_vr =
3321                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3322         force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3323
3324         if (hwmgr->display_config->num_display == 0)
3325                 disable_mclk_switching = false;
3326         else
3327                 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3328                                           !hwmgr->display_config->multi_monitor_in_sync) ||
3329                         disable_mclk_switching_for_frame_lock ||
3330                         disable_mclk_switching_for_vr ||
3331                         force_mclk_high;
3332
3333         sclk = vega10_ps->performance_levels[0].gfx_clock;
3334         mclk = vega10_ps->performance_levels[0].mem_clock;
3335
3336         if (sclk < minimum_clocks.engineClock)
3337                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3338                                 max_limits->sclk : minimum_clocks.engineClock;
3339
3340         if (mclk < minimum_clocks.memoryClock)
3341                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3342                                 max_limits->mclk : minimum_clocks.memoryClock;
3343
3344         vega10_ps->performance_levels[0].gfx_clock = sclk;
3345         vega10_ps->performance_levels[0].mem_clock = mclk;
3346
3347         if (vega10_ps->performance_levels[1].gfx_clock <
3348                         vega10_ps->performance_levels[0].gfx_clock)
3349                 vega10_ps->performance_levels[0].gfx_clock =
3350                                 vega10_ps->performance_levels[1].gfx_clock;
3351
3352         if (disable_mclk_switching) {
3353                 /* Set Mclk the max of level 0 and level 1 */
3354                 if (mclk < vega10_ps->performance_levels[1].mem_clock)
3355                         mclk = vega10_ps->performance_levels[1].mem_clock;
3356
3357                 /* Find the lowest MCLK frequency that is within
3358                  * the tolerable latency defined in DAL
3359                  */
3360                 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3361                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3362                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3363                                 (data->mclk_latency_table.entries[i].frequency >=
3364                                                 vega10_ps->performance_levels[0].mem_clock) &&
3365                                 (data->mclk_latency_table.entries[i].frequency <=
3366                                                 vega10_ps->performance_levels[1].mem_clock))
3367                                 mclk = data->mclk_latency_table.entries[i].frequency;
3368                 }
3369                 vega10_ps->performance_levels[0].mem_clock = mclk;
3370         } else {
3371                 if (vega10_ps->performance_levels[1].mem_clock <
3372                                 vega10_ps->performance_levels[0].mem_clock)
3373                         vega10_ps->performance_levels[0].mem_clock =
3374                                         vega10_ps->performance_levels[1].mem_clock;
3375         }
3376
3377         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3378                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3379                         vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3380                         vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3381                 }
3382         }
3383
3384         return 0;
3385 }
3386
3387 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3388 {
3389         struct vega10_hwmgr *data = hwmgr->backend;
3390         const struct phm_set_power_state_input *states =
3391                         (const struct phm_set_power_state_input *)input;
3392         const struct vega10_power_state *vega10_ps =
3393                         cast_const_phw_vega10_power_state(states->pnew_state);
3394         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
3395         uint32_t sclk = vega10_ps->performance_levels
3396                         [vega10_ps->performance_level_count - 1].gfx_clock;
3397         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
3398         uint32_t mclk = vega10_ps->performance_levels
3399                         [vega10_ps->performance_level_count - 1].mem_clock;
3400         uint32_t i;
3401
3402         for (i = 0; i < sclk_table->count; i++) {
3403                 if (sclk == sclk_table->dpm_levels[i].value)
3404                         break;
3405         }
3406
3407         if (i >= sclk_table->count) {
3408                 if (sclk > sclk_table->dpm_levels[i-1].value) {
3409                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3410                         sclk_table->dpm_levels[i-1].value = sclk;
3411                 }
3412         }
3413
3414         for (i = 0; i < mclk_table->count; i++) {
3415                 if (mclk == mclk_table->dpm_levels[i].value)
3416                         break;
3417         }
3418
3419         if (i >= mclk_table->count) {
3420                 if (mclk > mclk_table->dpm_levels[i-1].value) {
3421                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3422                         mclk_table->dpm_levels[i-1].value = mclk;
3423                 }
3424         }
3425
3426         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3427                 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3428
3429         return 0;
3430 }
3431
3432 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3433                 struct pp_hwmgr *hwmgr, const void *input)
3434 {
3435         int result = 0;
3436         struct vega10_hwmgr *data = hwmgr->backend;
3437         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3438         struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
3439         struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
3440         int count;
3441
3442         if (!data->need_update_dpm_table)
3443                 return 0;
3444
3445         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3446                 for (count = 0; count < dpm_table->gfx_table.count; count++)
3447                         dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3448         }
3449
3450         odn_clk_table = &odn_table->vdd_dep_on_mclk;
3451         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3452                 for (count = 0; count < dpm_table->mem_table.count; count++)
3453                         dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3454         }
3455
3456         if (data->need_update_dpm_table &
3457                         (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) {
3458                 result = vega10_populate_all_graphic_levels(hwmgr);
3459                 PP_ASSERT_WITH_CODE((0 == result),
3460                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3461                                 return result);
3462         }
3463
3464         if (data->need_update_dpm_table &
3465                         (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3466                 result = vega10_populate_all_memory_levels(hwmgr);
3467                 PP_ASSERT_WITH_CODE((0 == result),
3468                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3469                                 return result);
3470         }
3471
3472         vega10_populate_vddc_soc_levels(hwmgr);
3473
3474         return result;
3475 }
3476
3477 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3478                 struct vega10_single_dpm_table *dpm_table,
3479                 uint32_t low_limit, uint32_t high_limit)
3480 {
3481         uint32_t i;
3482
3483         for (i = 0; i < dpm_table->count; i++) {
3484                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3485                     (dpm_table->dpm_levels[i].value > high_limit))
3486                         dpm_table->dpm_levels[i].enabled = false;
3487                 else
3488                         dpm_table->dpm_levels[i].enabled = true;
3489         }
3490         return 0;
3491 }
3492
3493 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3494                 struct vega10_single_dpm_table *dpm_table,
3495                 uint32_t low_limit, uint32_t high_limit,
3496                 uint32_t disable_dpm_mask)
3497 {
3498         uint32_t i;
3499
3500         for (i = 0; i < dpm_table->count; i++) {
3501                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3502                     (dpm_table->dpm_levels[i].value > high_limit))
3503                         dpm_table->dpm_levels[i].enabled = false;
3504                 else if (!((1 << i) & disable_dpm_mask))
3505                         dpm_table->dpm_levels[i].enabled = false;
3506                 else
3507                         dpm_table->dpm_levels[i].enabled = true;
3508         }
3509         return 0;
3510 }
3511
3512 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3513                 const struct vega10_power_state *vega10_ps)
3514 {
3515         struct vega10_hwmgr *data = hwmgr->backend;
3516         uint32_t high_limit_count;
3517
3518         PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3519                         "power state did not have any performance level",
3520                         return -1);
3521
3522         high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3523
3524         vega10_trim_single_dpm_states(hwmgr,
3525                         &(data->dpm_table.soc_table),
3526                         vega10_ps->performance_levels[0].soc_clock,
3527                         vega10_ps->performance_levels[high_limit_count].soc_clock);
3528
3529         vega10_trim_single_dpm_states_with_mask(hwmgr,
3530                         &(data->dpm_table.gfx_table),
3531                         vega10_ps->performance_levels[0].gfx_clock,
3532                         vega10_ps->performance_levels[high_limit_count].gfx_clock,
3533                         data->disable_dpm_mask);
3534
3535         vega10_trim_single_dpm_states(hwmgr,
3536                         &(data->dpm_table.mem_table),
3537                         vega10_ps->performance_levels[0].mem_clock,
3538                         vega10_ps->performance_levels[high_limit_count].mem_clock);
3539
3540         return 0;
3541 }
3542
3543 static uint32_t vega10_find_lowest_dpm_level(
3544                 struct vega10_single_dpm_table *table)
3545 {
3546         uint32_t i;
3547
3548         for (i = 0; i < table->count; i++) {
3549                 if (table->dpm_levels[i].enabled)
3550                         break;
3551         }
3552
3553         return i;
3554 }
3555
3556 static uint32_t vega10_find_highest_dpm_level(
3557                 struct vega10_single_dpm_table *table)
3558 {
3559         uint32_t i = 0;
3560
3561         if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3562                 for (i = table->count; i > 0; i--) {
3563                         if (table->dpm_levels[i - 1].enabled)
3564                                 return i - 1;
3565                 }
3566         } else {
3567                 pr_info("DPM Table Has Too Many Entries!");
3568                 return MAX_REGULAR_DPM_NUMBER - 1;
3569         }
3570
3571         return i;
3572 }
3573
3574 static void vega10_apply_dal_minimum_voltage_request(
3575                 struct pp_hwmgr *hwmgr)
3576 {
3577         return;
3578 }
3579
3580 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3581 {
3582         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3583         struct phm_ppt_v2_information *table_info =
3584                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3585
3586         vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
3587
3588         return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3589 }
3590
3591 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3592 {
3593         struct vega10_hwmgr *data = hwmgr->backend;
3594         uint32_t socclk_idx;
3595
3596         vega10_apply_dal_minimum_voltage_request(hwmgr);
3597
3598         if (!data->registry_data.sclk_dpm_key_disabled) {
3599                 if (data->smc_state_table.gfx_boot_level !=
3600                                 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3601                         smum_send_msg_to_smc_with_parameter(hwmgr,
3602                                 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3603                                 data->smc_state_table.gfx_boot_level,
3604                                 NULL);
3605
3606                         data->dpm_table.gfx_table.dpm_state.soft_min_level =
3607                                         data->smc_state_table.gfx_boot_level;
3608                 }
3609         }
3610
3611         if (!data->registry_data.mclk_dpm_key_disabled) {
3612                 if (data->smc_state_table.mem_boot_level !=
3613                                 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3614                         if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)
3615                             && hwmgr->not_vf) {
3616                                 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3617                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3618                                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3619                                                 socclk_idx,
3620                                                 NULL);
3621                         } else {
3622                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3623                                                 PPSMC_MSG_SetSoftMinUclkByIndex,
3624                                                 data->smc_state_table.mem_boot_level,
3625                                                 NULL);
3626                         }
3627                         data->dpm_table.mem_table.dpm_state.soft_min_level =
3628                                         data->smc_state_table.mem_boot_level;
3629                 }
3630         }
3631
3632         if (!hwmgr->not_vf)
3633                 return 0;
3634
3635         if (!data->registry_data.socclk_dpm_key_disabled) {
3636                 if (data->smc_state_table.soc_boot_level !=
3637                                 data->dpm_table.soc_table.dpm_state.soft_min_level) {
3638                         smum_send_msg_to_smc_with_parameter(hwmgr,
3639                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3640                                 data->smc_state_table.soc_boot_level,
3641                                 NULL);
3642                         data->dpm_table.soc_table.dpm_state.soft_min_level =
3643                                         data->smc_state_table.soc_boot_level;
3644                 }
3645         }
3646
3647         return 0;
3648 }
3649
3650 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3651 {
3652         struct vega10_hwmgr *data = hwmgr->backend;
3653
3654         vega10_apply_dal_minimum_voltage_request(hwmgr);
3655
3656         if (!data->registry_data.sclk_dpm_key_disabled) {
3657                 if (data->smc_state_table.gfx_max_level !=
3658                         data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3659                         smum_send_msg_to_smc_with_parameter(hwmgr,
3660                                 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3661                                 data->smc_state_table.gfx_max_level,
3662                                 NULL);
3663                         data->dpm_table.gfx_table.dpm_state.soft_max_level =
3664                                         data->smc_state_table.gfx_max_level;
3665                 }
3666         }
3667
3668         if (!data->registry_data.mclk_dpm_key_disabled) {
3669                 if (data->smc_state_table.mem_max_level !=
3670                         data->dpm_table.mem_table.dpm_state.soft_max_level) {
3671                         smum_send_msg_to_smc_with_parameter(hwmgr,
3672                                         PPSMC_MSG_SetSoftMaxUclkByIndex,
3673                                         data->smc_state_table.mem_max_level,
3674                                         NULL);
3675                         data->dpm_table.mem_table.dpm_state.soft_max_level =
3676                                         data->smc_state_table.mem_max_level;
3677                 }
3678         }
3679
3680         if (!hwmgr->not_vf)
3681                 return 0;
3682
3683         if (!data->registry_data.socclk_dpm_key_disabled) {
3684                 if (data->smc_state_table.soc_max_level !=
3685                         data->dpm_table.soc_table.dpm_state.soft_max_level) {
3686                         smum_send_msg_to_smc_with_parameter(hwmgr,
3687                                 PPSMC_MSG_SetSoftMaxSocclkByIndex,
3688                                 data->smc_state_table.soc_max_level,
3689                                 NULL);
3690                         data->dpm_table.soc_table.dpm_state.soft_max_level =
3691                                         data->smc_state_table.soc_max_level;
3692                 }
3693         }
3694
3695         return 0;
3696 }
3697
3698 static int vega10_generate_dpm_level_enable_mask(
3699                 struct pp_hwmgr *hwmgr, const void *input)
3700 {
3701         struct vega10_hwmgr *data = hwmgr->backend;
3702         const struct phm_set_power_state_input *states =
3703                         (const struct phm_set_power_state_input *)input;
3704         const struct vega10_power_state *vega10_ps =
3705                         cast_const_phw_vega10_power_state(states->pnew_state);
3706         int i;
3707
3708         PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3709                         "Attempt to Trim DPM States Failed!",
3710                         return -1);
3711
3712         data->smc_state_table.gfx_boot_level =
3713                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3714         data->smc_state_table.gfx_max_level =
3715                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3716         data->smc_state_table.mem_boot_level =
3717                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3718         data->smc_state_table.mem_max_level =
3719                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3720         data->smc_state_table.soc_boot_level =
3721                         vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table));
3722         data->smc_state_table.soc_max_level =
3723                         vega10_find_highest_dpm_level(&(data->dpm_table.soc_table));
3724
3725         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3726                         "Attempt to upload DPM Bootup Levels Failed!",
3727                         return -1);
3728         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3729                         "Attempt to upload DPM Max Levels Failed!",
3730                         return -1);
3731         for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3732                 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3733
3734
3735         for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3736                 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3737
3738         for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++)
3739                 data->dpm_table.soc_table.dpm_levels[i].enabled = true;
3740
3741         return 0;
3742 }
3743
3744 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3745 {
3746         struct vega10_hwmgr *data = hwmgr->backend;
3747
3748         if (data->smu_features[GNLD_DPM_VCE].supported) {
3749                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3750                                 enable,
3751                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3752                                 "Attempt to Enable/Disable DPM VCE Failed!",
3753                                 return -1);
3754                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3755         }
3756
3757         return 0;
3758 }
3759
3760 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3761 {
3762         struct vega10_hwmgr *data = hwmgr->backend;
3763         uint32_t low_sclk_interrupt_threshold = 0;
3764
3765         if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3766                 (data->low_sclk_interrupt_threshold != 0)) {
3767                 low_sclk_interrupt_threshold =
3768                                 data->low_sclk_interrupt_threshold;
3769
3770                 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3771                                 cpu_to_le32(low_sclk_interrupt_threshold);
3772
3773                 /* This message will also enable SmcToHost Interrupt */
3774                 smum_send_msg_to_smc_with_parameter(hwmgr,
3775                                 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3776                                 (uint32_t)low_sclk_interrupt_threshold,
3777                                 NULL);
3778         }
3779
3780         return 0;
3781 }
3782
3783 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3784                 const void *input)
3785 {
3786         int tmp_result, result = 0;
3787         struct vega10_hwmgr *data = hwmgr->backend;
3788         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3789
3790         tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3791         PP_ASSERT_WITH_CODE(!tmp_result,
3792                         "Failed to find DPM states clocks in DPM table!",
3793                         result = tmp_result);
3794
3795         tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3796         PP_ASSERT_WITH_CODE(!tmp_result,
3797                         "Failed to populate and upload SCLK MCLK DPM levels!",
3798                         result = tmp_result);
3799
3800         tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3801         PP_ASSERT_WITH_CODE(!tmp_result,
3802                         "Failed to generate DPM level enabled mask!",
3803                         result = tmp_result);
3804
3805         tmp_result = vega10_update_sclk_threshold(hwmgr);
3806         PP_ASSERT_WITH_CODE(!tmp_result,
3807                         "Failed to update SCLK threshold!",
3808                         result = tmp_result);
3809
3810         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3811         PP_ASSERT_WITH_CODE(!result,
3812                         "Failed to upload PPtable!", return result);
3813
3814         /*
3815          * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
3816          * That effectively disables AVFS feature.
3817          */
3818         if(hwmgr->hardcode_pp_table != NULL)
3819                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
3820
3821         vega10_update_avfs(hwmgr);
3822
3823         /*
3824          * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC.
3825          * That will help to keep AVFS disabled.
3826          */
3827         data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3828
3829         return 0;
3830 }
3831
3832 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3833 {
3834         struct pp_power_state *ps;
3835         struct vega10_power_state *vega10_ps;
3836
3837         if (hwmgr == NULL)
3838                 return -EINVAL;
3839
3840         ps = hwmgr->request_ps;
3841
3842         if (ps == NULL)
3843                 return -EINVAL;
3844
3845         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3846
3847         if (low)
3848                 return vega10_ps->performance_levels[0].gfx_clock;
3849         else
3850                 return vega10_ps->performance_levels
3851                                 [vega10_ps->performance_level_count - 1].gfx_clock;
3852 }
3853
3854 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3855 {
3856         struct pp_power_state *ps;
3857         struct vega10_power_state *vega10_ps;
3858
3859         if (hwmgr == NULL)
3860                 return -EINVAL;
3861
3862         ps = hwmgr->request_ps;
3863
3864         if (ps == NULL)
3865                 return -EINVAL;
3866
3867         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3868
3869         if (low)
3870                 return vega10_ps->performance_levels[0].mem_clock;
3871         else
3872                 return vega10_ps->performance_levels
3873                                 [vega10_ps->performance_level_count-1].mem_clock;
3874 }
3875
3876 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3877                 uint32_t *query)
3878 {
3879         uint32_t value;
3880
3881         if (!query)
3882                 return -EINVAL;
3883
3884         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value);
3885
3886         /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3887         *query = value << 8;
3888
3889         return 0;
3890 }
3891
3892 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3893                               void *value, int *size)
3894 {
3895         struct amdgpu_device *adev = hwmgr->adev;
3896         uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3897         struct vega10_hwmgr *data = hwmgr->backend;
3898         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3899         int ret = 0;
3900         uint32_t val_vid;
3901
3902         switch (idx) {
3903         case AMDGPU_PP_SENSOR_GFX_SCLK:
3904                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz);
3905                 *((uint32_t *)value) = sclk_mhz * 100;
3906                 break;
3907         case AMDGPU_PP_SENSOR_GFX_MCLK:
3908                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx);
3909                 if (mclk_idx < dpm_table->mem_table.count) {
3910                         *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3911                         *size = 4;
3912                 } else {
3913                         ret = -EINVAL;
3914                 }
3915                 break;
3916         case AMDGPU_PP_SENSOR_GPU_LOAD:
3917                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0,
3918                                                 &activity_percent);
3919                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3920                 *size = 4;
3921                 break;
3922         case AMDGPU_PP_SENSOR_GPU_TEMP:
3923                 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3924                 *size = 4;
3925                 break;
3926         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3927                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value);
3928                 *((uint32_t *)value) = *((uint32_t *)value) *
3929                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3930                 *size = 4;
3931                 break;
3932         case AMDGPU_PP_SENSOR_MEM_TEMP:
3933                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value);
3934                 *((uint32_t *)value) = *((uint32_t *)value) *
3935                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3936                 *size = 4;
3937                 break;
3938         case AMDGPU_PP_SENSOR_UVD_POWER:
3939                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3940                 *size = 4;
3941                 break;
3942         case AMDGPU_PP_SENSOR_VCE_POWER:
3943                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3944                 *size = 4;
3945                 break;
3946         case AMDGPU_PP_SENSOR_GPU_POWER:
3947                 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3948                 break;
3949         case AMDGPU_PP_SENSOR_VDDGFX:
3950                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3951                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3952                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3953                 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3954                 return 0;
3955         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3956                 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
3957                 if (!ret)
3958                         *size = 8;
3959                 break;
3960         default:
3961                 ret = -EOPNOTSUPP;
3962                 break;
3963         }
3964
3965         return ret;
3966 }
3967
3968 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3969                 bool has_disp)
3970 {
3971         smum_send_msg_to_smc_with_parameter(hwmgr,
3972                         PPSMC_MSG_SetUclkFastSwitch,
3973                         has_disp ? 1 : 0,
3974                         NULL);
3975 }
3976
3977 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
3978                 struct pp_display_clock_request *clock_req)
3979 {
3980         int result = 0;
3981         enum amd_pp_clock_type clk_type = clock_req->clock_type;
3982         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
3983         DSPCLK_e clk_select = 0;
3984         uint32_t clk_request = 0;
3985
3986         switch (clk_type) {
3987         case amd_pp_dcef_clock:
3988                 clk_select = DSPCLK_DCEFCLK;
3989                 break;
3990         case amd_pp_disp_clock:
3991                 clk_select = DSPCLK_DISPCLK;
3992                 break;
3993         case amd_pp_pixel_clock:
3994                 clk_select = DSPCLK_PIXCLK;
3995                 break;
3996         case amd_pp_phy_clock:
3997                 clk_select = DSPCLK_PHYCLK;
3998                 break;
3999         default:
4000                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
4001                 result = -1;
4002                 break;
4003         }
4004
4005         if (!result) {
4006                 clk_request = (clk_freq << 16) | clk_select;
4007                 smum_send_msg_to_smc_with_parameter(hwmgr,
4008                                 PPSMC_MSG_RequestDisplayClockByFreq,
4009                                 clk_request,
4010                                 NULL);
4011         }
4012
4013         return result;
4014 }
4015
4016 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
4017                         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
4018                                                 uint32_t frequency)
4019 {
4020         uint8_t count;
4021         uint8_t i;
4022
4023         if (mclk_table == NULL || mclk_table->count == 0)
4024                 return 0;
4025
4026         count = (uint8_t)(mclk_table->count);
4027
4028         for(i = 0; i < count; i++) {
4029                 if(mclk_table->entries[i].clk >= frequency)
4030                         return i;
4031         }
4032
4033         return i-1;
4034 }
4035
4036 static int vega10_notify_smc_display_config_after_ps_adjustment(
4037                 struct pp_hwmgr *hwmgr)
4038 {
4039         struct vega10_hwmgr *data = hwmgr->backend;
4040         struct vega10_single_dpm_table *dpm_table =
4041                         &data->dpm_table.dcef_table;
4042         struct phm_ppt_v2_information *table_info =
4043                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4044         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
4045         uint32_t idx;
4046         struct PP_Clocks min_clocks = {0};
4047         uint32_t i;
4048         struct pp_display_clock_request clock_req;
4049
4050         if ((hwmgr->display_config->num_display > 1) &&
4051              !hwmgr->display_config->multi_monitor_in_sync &&
4052              !hwmgr->display_config->nb_pstate_switch_disable)
4053                 vega10_notify_smc_display_change(hwmgr, false);
4054         else
4055                 vega10_notify_smc_display_change(hwmgr, true);
4056
4057         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
4058         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
4059         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
4060
4061         for (i = 0; i < dpm_table->count; i++) {
4062                 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
4063                         break;
4064         }
4065
4066         if (i < dpm_table->count) {
4067                 clock_req.clock_type = amd_pp_dcef_clock;
4068                 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10;
4069                 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
4070                         smum_send_msg_to_smc_with_parameter(
4071                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
4072                                         min_clocks.dcefClockInSR / 100,
4073                                         NULL);
4074                 } else {
4075                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
4076                 }
4077         } else {
4078                 pr_debug("Cannot find requested DCEFCLK!");
4079         }
4080
4081         if (min_clocks.memoryClock != 0) {
4082                 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
4083                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx,
4084                                                 NULL);
4085                 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
4086         }
4087
4088         return 0;
4089 }
4090
4091 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
4092 {
4093         struct vega10_hwmgr *data = hwmgr->backend;
4094
4095         data->smc_state_table.gfx_boot_level =
4096         data->smc_state_table.gfx_max_level =
4097                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4098         data->smc_state_table.mem_boot_level =
4099         data->smc_state_table.mem_max_level =
4100                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4101
4102         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4103                         "Failed to upload boot level to highest!",
4104                         return -1);
4105
4106         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4107                         "Failed to upload dpm max level to highest!",
4108                         return -1);
4109
4110         return 0;
4111 }
4112
4113 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
4114 {
4115         struct vega10_hwmgr *data = hwmgr->backend;
4116
4117         data->smc_state_table.gfx_boot_level =
4118         data->smc_state_table.gfx_max_level =
4119                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4120         data->smc_state_table.mem_boot_level =
4121         data->smc_state_table.mem_max_level =
4122                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4123
4124         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4125                         "Failed to upload boot level to highest!",
4126                         return -1);
4127
4128         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4129                         "Failed to upload dpm max level to highest!",
4130                         return -1);
4131
4132         return 0;
4133
4134 }
4135
4136 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
4137 {
4138         struct vega10_hwmgr *data = hwmgr->backend;
4139
4140         data->smc_state_table.gfx_boot_level =
4141                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4142         data->smc_state_table.gfx_max_level =
4143                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4144         data->smc_state_table.mem_boot_level =
4145                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4146         data->smc_state_table.mem_max_level =
4147                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4148
4149         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4150                         "Failed to upload DPM Bootup Levels!",
4151                         return -1);
4152
4153         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4154                         "Failed to upload DPM Max Levels!",
4155                         return -1);
4156         return 0;
4157 }
4158
4159 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
4160                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4161 {
4162         struct phm_ppt_v2_information *table_info =
4163                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
4164
4165         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
4166                 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
4167                 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
4168                 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
4169                 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
4170                 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
4171                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
4172                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
4173         }
4174
4175         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
4176                 *sclk_mask = 0;
4177         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
4178                 *mclk_mask = 0;
4179         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
4180                 /* under vega10  pp one vf mode, the gfx clk dpm need be lower
4181                  * to level-4 due to the limited power
4182                  */
4183                 if (hwmgr->pp_one_vf)
4184                         *sclk_mask = 4;
4185                 else
4186                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
4187                 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
4188                 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4189         }
4190
4191         return 0;
4192 }
4193
4194 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4195 {
4196         if (!hwmgr->not_vf)
4197                 return;
4198
4199         switch (mode) {
4200         case AMD_FAN_CTRL_NONE:
4201                 vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
4202                 break;
4203         case AMD_FAN_CTRL_MANUAL:
4204                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4205                         vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
4206                 break;
4207         case AMD_FAN_CTRL_AUTO:
4208                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4209                         vega10_fan_ctrl_start_smc_fan_control(hwmgr);
4210                 break;
4211         default:
4212                 break;
4213         }
4214 }
4215
4216 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
4217                 enum pp_clock_type type, uint32_t mask)
4218 {
4219         struct vega10_hwmgr *data = hwmgr->backend;
4220
4221         switch (type) {
4222         case PP_SCLK:
4223                 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
4224                 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
4225
4226                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4227                         "Failed to upload boot level to lowest!",
4228                         return -EINVAL);
4229
4230                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4231                         "Failed to upload dpm max level to highest!",
4232                         return -EINVAL);
4233                 break;
4234
4235         case PP_MCLK:
4236                 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
4237                 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
4238
4239                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4240                         "Failed to upload boot level to lowest!",
4241                         return -EINVAL);
4242
4243                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4244                         "Failed to upload dpm max level to highest!",
4245                         return -EINVAL);
4246
4247                 break;
4248
4249         case PP_SOCCLK:
4250                 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;
4251                 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
4252
4253                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4254                         "Failed to upload boot level to lowest!",
4255                         return -EINVAL);
4256
4257                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4258                         "Failed to upload dpm max level to highest!",
4259                         return -EINVAL);
4260
4261                 break;
4262
4263         case PP_DCEFCLK:
4264                 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
4265                 break;
4266
4267         case PP_PCIE:
4268         default:
4269                 break;
4270         }
4271
4272         return 0;
4273 }
4274
4275 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
4276                                 enum amd_dpm_forced_level level)
4277 {
4278         int ret = 0;
4279         uint32_t sclk_mask = 0;
4280         uint32_t mclk_mask = 0;
4281         uint32_t soc_mask = 0;
4282
4283         if (hwmgr->pstate_sclk == 0)
4284                 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4285
4286         switch (level) {
4287         case AMD_DPM_FORCED_LEVEL_HIGH:
4288                 ret = vega10_force_dpm_highest(hwmgr);
4289                 break;
4290         case AMD_DPM_FORCED_LEVEL_LOW:
4291                 ret = vega10_force_dpm_lowest(hwmgr);
4292                 break;
4293         case AMD_DPM_FORCED_LEVEL_AUTO:
4294                 ret = vega10_unforce_dpm_levels(hwmgr);
4295                 break;
4296         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
4297         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
4298         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
4299         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
4300                 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4301                 if (ret)
4302                         return ret;
4303                 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
4304                 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4305                 break;
4306         case AMD_DPM_FORCED_LEVEL_MANUAL:
4307         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
4308         default:
4309                 break;
4310         }
4311
4312         if (!hwmgr->not_vf)
4313                 return ret;
4314
4315         if (!ret) {
4316                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4317                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
4318                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4319                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
4320         }
4321
4322         return ret;
4323 }
4324
4325 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4326 {
4327         struct vega10_hwmgr *data = hwmgr->backend;
4328
4329         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4330                 return AMD_FAN_CTRL_MANUAL;
4331         else
4332                 return AMD_FAN_CTRL_AUTO;
4333 }
4334
4335 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
4336                 struct amd_pp_simple_clock_info *info)
4337 {
4338         struct phm_ppt_v2_information *table_info =
4339                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4340         struct phm_clock_and_voltage_limits *max_limits =
4341                         &table_info->max_clock_voltage_on_ac;
4342
4343         info->engine_max_clock = max_limits->sclk;
4344         info->memory_max_clock = max_limits->mclk;
4345
4346         return 0;
4347 }
4348
4349 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4350                 struct pp_clock_levels_with_latency *clocks)
4351 {
4352         struct phm_ppt_v2_information *table_info =
4353                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4354         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4355                         table_info->vdd_dep_on_sclk;
4356         uint32_t i;
4357
4358         clocks->num_levels = 0;
4359         for (i = 0; i < dep_table->count; i++) {
4360                 if (dep_table->entries[i].clk) {
4361                         clocks->data[clocks->num_levels].clocks_in_khz =
4362                                         dep_table->entries[i].clk * 10;
4363                         clocks->num_levels++;
4364                 }
4365         }
4366
4367 }
4368
4369 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4370                 struct pp_clock_levels_with_latency *clocks)
4371 {
4372         struct phm_ppt_v2_information *table_info =
4373                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4374         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4375                         table_info->vdd_dep_on_mclk;
4376         struct vega10_hwmgr *data = hwmgr->backend;
4377         uint32_t j = 0;
4378         uint32_t i;
4379
4380         for (i = 0; i < dep_table->count; i++) {
4381                 if (dep_table->entries[i].clk) {
4382
4383                         clocks->data[j].clocks_in_khz =
4384                                                 dep_table->entries[i].clk * 10;
4385                         data->mclk_latency_table.entries[j].frequency =
4386                                                         dep_table->entries[i].clk;
4387                         clocks->data[j].latency_in_us =
4388                                 data->mclk_latency_table.entries[j].latency = 25;
4389                         j++;
4390                 }
4391         }
4392         clocks->num_levels = data->mclk_latency_table.count = j;
4393 }
4394
4395 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4396                 struct pp_clock_levels_with_latency *clocks)
4397 {
4398         struct phm_ppt_v2_information *table_info =
4399                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4400         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4401                         table_info->vdd_dep_on_dcefclk;
4402         uint32_t i;
4403
4404         for (i = 0; i < dep_table->count; i++) {
4405                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4406                 clocks->data[i].latency_in_us = 0;
4407                 clocks->num_levels++;
4408         }
4409 }
4410
4411 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4412                 struct pp_clock_levels_with_latency *clocks)
4413 {
4414         struct phm_ppt_v2_information *table_info =
4415                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4416         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4417                         table_info->vdd_dep_on_socclk;
4418         uint32_t i;
4419
4420         for (i = 0; i < dep_table->count; i++) {
4421                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4422                 clocks->data[i].latency_in_us = 0;
4423                 clocks->num_levels++;
4424         }
4425 }
4426
4427 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4428                 enum amd_pp_clock_type type,
4429                 struct pp_clock_levels_with_latency *clocks)
4430 {
4431         switch (type) {
4432         case amd_pp_sys_clock:
4433                 vega10_get_sclks(hwmgr, clocks);
4434                 break;
4435         case amd_pp_mem_clock:
4436                 vega10_get_memclocks(hwmgr, clocks);
4437                 break;
4438         case amd_pp_dcef_clock:
4439                 vega10_get_dcefclocks(hwmgr, clocks);
4440                 break;
4441         case amd_pp_soc_clock:
4442                 vega10_get_socclocks(hwmgr, clocks);
4443                 break;
4444         default:
4445                 return -1;
4446         }
4447
4448         return 0;
4449 }
4450
4451 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4452                 enum amd_pp_clock_type type,
4453                 struct pp_clock_levels_with_voltage *clocks)
4454 {
4455         struct phm_ppt_v2_information *table_info =
4456                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4457         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4458         uint32_t i;
4459
4460         switch (type) {
4461         case amd_pp_mem_clock:
4462                 dep_table = table_info->vdd_dep_on_mclk;
4463                 break;
4464         case amd_pp_dcef_clock:
4465                 dep_table = table_info->vdd_dep_on_dcefclk;
4466                 break;
4467         case amd_pp_disp_clock:
4468                 dep_table = table_info->vdd_dep_on_dispclk;
4469                 break;
4470         case amd_pp_pixel_clock:
4471                 dep_table = table_info->vdd_dep_on_pixclk;
4472                 break;
4473         case amd_pp_phy_clock:
4474                 dep_table = table_info->vdd_dep_on_phyclk;
4475                 break;
4476         default:
4477                 return -1;
4478         }
4479
4480         for (i = 0; i < dep_table->count; i++) {
4481                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
4482                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4483                                 entries[dep_table->entries[i].vddInd].us_vdd);
4484                 clocks->num_levels++;
4485         }
4486
4487         if (i < dep_table->count)
4488                 return -1;
4489
4490         return 0;
4491 }
4492
4493 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4494                                                         void *clock_range)
4495 {
4496         struct vega10_hwmgr *data = hwmgr->backend;
4497         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
4498         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4499
4500         if (!data->registry_data.disable_water_mark) {
4501                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4502                 data->water_marks_bitmap = WaterMarksExist;
4503         }
4504
4505         return 0;
4506 }
4507
4508 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
4509 {
4510         static const char *ppfeature_name[] = {
4511                                 "DPM_PREFETCHER",
4512                                 "GFXCLK_DPM",
4513                                 "UCLK_DPM",
4514                                 "SOCCLK_DPM",
4515                                 "UVD_DPM",
4516                                 "VCE_DPM",
4517                                 "ULV",
4518                                 "MP0CLK_DPM",
4519                                 "LINK_DPM",
4520                                 "DCEFCLK_DPM",
4521                                 "AVFS",
4522                                 "GFXCLK_DS",
4523                                 "SOCCLK_DS",
4524                                 "LCLK_DS",
4525                                 "PPT",
4526                                 "TDC",
4527                                 "THERMAL",
4528                                 "GFX_PER_CU_CG",
4529                                 "RM",
4530                                 "DCEFCLK_DS",
4531                                 "ACDC",
4532                                 "VR0HOT",
4533                                 "VR1HOT",
4534                                 "FW_CTF",
4535                                 "LED_DISPLAY",
4536                                 "FAN_CONTROL",
4537                                 "FAST_PPT",
4538                                 "DIDT",
4539                                 "ACG",
4540                                 "PCC_LIMIT"};
4541         static const char *output_title[] = {
4542                                 "FEATURES",
4543                                 "BITMASK",
4544                                 "ENABLEMENT"};
4545         uint64_t features_enabled;
4546         int i;
4547         int ret = 0;
4548         int size = 0;
4549
4550         phm_get_sysfs_buf(&buf, &size);
4551
4552         ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4553         PP_ASSERT_WITH_CODE(!ret,
4554                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
4555                         return ret);
4556
4557         size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
4558         size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
4559                                 output_title[0],
4560                                 output_title[1],
4561                                 output_title[2]);
4562         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
4563                 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
4564                                         ppfeature_name[i],
4565                                         1ULL << i,
4566                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
4567         }
4568
4569         return size;
4570 }
4571
4572 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
4573 {
4574         uint64_t features_enabled;
4575         uint64_t features_to_enable;
4576         uint64_t features_to_disable;
4577         int ret = 0;
4578
4579         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
4580                 return -EINVAL;
4581
4582         ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4583         if (ret)
4584                 return ret;
4585
4586         features_to_disable =
4587                 features_enabled & ~new_ppfeature_masks;
4588         features_to_enable =
4589                 ~features_enabled & new_ppfeature_masks;
4590
4591         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
4592         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
4593
4594         if (features_to_disable) {
4595                 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
4596                 if (ret)
4597                         return ret;
4598         }
4599
4600         if (features_to_enable) {
4601                 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
4602                 if (ret)
4603                         return ret;
4604         }
4605
4606         return 0;
4607 }
4608
4609 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
4610 {
4611         struct amdgpu_device *adev = hwmgr->adev;
4612
4613         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
4614                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
4615                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4616 }
4617
4618 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
4619 {
4620         struct amdgpu_device *adev = hwmgr->adev;
4621
4622         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
4623                 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
4624                 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4625 }
4626
4627 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr,
4628                                     enum pp_clock_type type, char *buf, int *offset)
4629 {
4630         struct vega10_hwmgr *data = hwmgr->backend;
4631         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4632         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4633         struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4634         struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4635         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4636         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4637         PPTable_t *pptable = &(data->smc_state_table.pp_table);
4638
4639         uint32_t i, now, count = 0;
4640         int ret = 0;
4641
4642         switch (type) {
4643         case PP_SCLK:
4644                 if (data->registry_data.sclk_dpm_key_disabled)
4645                         return -EOPNOTSUPP;
4646
4647                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4648                 if (unlikely(ret != 0))
4649                         return ret;
4650
4651                 if (hwmgr->pp_one_vf &&
4652                     (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4653                         count = 5;
4654                 else
4655                         count = sclk_table->count;
4656                 for (i = 0; i < count; i++)
4657                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4658                                         i, sclk_table->dpm_levels[i].value / 100,
4659                                         (i == now) ? "*" : "");
4660                 break;
4661         case PP_MCLK:
4662                 if (data->registry_data.mclk_dpm_key_disabled)
4663                         return -EOPNOTSUPP;
4664
4665                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4666                 if (unlikely(ret != 0))
4667                         return ret;
4668
4669                 for (i = 0; i < mclk_table->count; i++)
4670                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4671                                         i, mclk_table->dpm_levels[i].value / 100,
4672                                         (i == now) ? "*" : "");
4673                 break;
4674         case PP_SOCCLK:
4675                 if (data->registry_data.socclk_dpm_key_disabled)
4676                         return -EOPNOTSUPP;
4677
4678                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4679                 if (unlikely(ret != 0))
4680                         return ret;
4681
4682                 for (i = 0; i < soc_table->count; i++)
4683                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4684                                         i, soc_table->dpm_levels[i].value / 100,
4685                                         (i == now) ? "*" : "");
4686                 break;
4687         case PP_DCEFCLK:
4688                 if (data->registry_data.dcefclk_dpm_key_disabled)
4689                         return -EOPNOTSUPP;
4690
4691                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4692                                                           PPSMC_MSG_GetClockFreqMHz,
4693                                                           CLK_DCEFCLK, &now);
4694                 if (unlikely(ret != 0))
4695                         return ret;
4696
4697                 for (i = 0; i < dcef_table->count; i++)
4698                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4699                                         i, dcef_table->dpm_levels[i].value / 100,
4700                                         (dcef_table->dpm_levels[i].value / 100 == now) ?
4701                                         "*" : "");
4702                 break;
4703         case PP_PCIE:
4704                 current_gen_speed =
4705                         vega10_get_current_pcie_link_speed_level(hwmgr);
4706                 current_lane_width =
4707                         vega10_get_current_pcie_link_width_level(hwmgr);
4708                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
4709                         gen_speed = pptable->PcieGenSpeed[i];
4710                         lane_width = pptable->PcieLaneCount[i];
4711
4712                         *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i,
4713                                         (gen_speed == 0) ? "2.5GT/s," :
4714                                         (gen_speed == 1) ? "5.0GT/s," :
4715                                         (gen_speed == 2) ? "8.0GT/s," :
4716                                         (gen_speed == 3) ? "16.0GT/s," : "",
4717                                         (lane_width == 1) ? "x1" :
4718                                         (lane_width == 2) ? "x2" :
4719                                         (lane_width == 3) ? "x4" :
4720                                         (lane_width == 4) ? "x8" :
4721                                         (lane_width == 5) ? "x12" :
4722                                         (lane_width == 6) ? "x16" : "",
4723                                         (current_gen_speed == gen_speed) &&
4724                                         (current_lane_width == lane_width) ?
4725                                         "*" : "");
4726                 }
4727                 break;
4728
4729         case OD_SCLK:
4730                 if (!hwmgr->od_enabled)
4731                         return -EOPNOTSUPP;
4732
4733                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK");
4734                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4735                 for (i = 0; i < podn_vdd_dep->count; i++)
4736                         *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4737                                                  i, podn_vdd_dep->entries[i].clk / 100,
4738                                                  podn_vdd_dep->entries[i].vddc);
4739                 break;
4740         case OD_MCLK:
4741                 if (!hwmgr->od_enabled)
4742                         return -EOPNOTSUPP;
4743
4744                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK");
4745                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4746                 for (i = 0; i < podn_vdd_dep->count; i++)
4747                         *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4748                                                  i, podn_vdd_dep->entries[i].clk/100,
4749                                                  podn_vdd_dep->entries[i].vddc);
4750                 break;
4751         case OD_RANGE:
4752                 if (!hwmgr->od_enabled)
4753                         return -EOPNOTSUPP;
4754
4755                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
4756                 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n",
4757                                          data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4758                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4759                 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n",
4760                                          data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4761                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4762                 *offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n",
4763                                          data->odn_dpm_table.min_vddc,
4764                                          data->odn_dpm_table.max_vddc);
4765                 break;
4766         default:
4767                 ret = -ENOENT;
4768                 break;
4769         }
4770         return ret;
4771 }
4772
4773 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4774                 enum pp_clock_type type, char *buf)
4775 {
4776         struct vega10_hwmgr *data = hwmgr->backend;
4777         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4778         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4779         struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4780         struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4781         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4782         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4783         PPTable_t *pptable = &(data->smc_state_table.pp_table);
4784
4785         int i, now, size = 0, count = 0;
4786
4787         switch (type) {
4788         case PP_SCLK:
4789                 if (data->registry_data.sclk_dpm_key_disabled)
4790                         break;
4791
4792                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4793
4794                 if (hwmgr->pp_one_vf &&
4795                     (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4796                         count = 5;
4797                 else
4798                         count = sclk_table->count;
4799                 for (i = 0; i < count; i++)
4800                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4801                                         i, sclk_table->dpm_levels[i].value / 100,
4802                                         (i == now) ? "*" : "");
4803                 break;
4804         case PP_MCLK:
4805                 if (data->registry_data.mclk_dpm_key_disabled)
4806                         break;
4807
4808                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4809
4810                 for (i = 0; i < mclk_table->count; i++)
4811                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4812                                         i, mclk_table->dpm_levels[i].value / 100,
4813                                         (i == now) ? "*" : "");
4814                 break;
4815         case PP_SOCCLK:
4816                 if (data->registry_data.socclk_dpm_key_disabled)
4817                         break;
4818
4819                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4820
4821                 for (i = 0; i < soc_table->count; i++)
4822                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4823                                         i, soc_table->dpm_levels[i].value / 100,
4824                                         (i == now) ? "*" : "");
4825                 break;
4826         case PP_DCEFCLK:
4827                 if (data->registry_data.dcefclk_dpm_key_disabled)
4828                         break;
4829
4830                 smum_send_msg_to_smc_with_parameter(hwmgr,
4831                                 PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now);
4832
4833                 for (i = 0; i < dcef_table->count; i++)
4834                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4835                                         i, dcef_table->dpm_levels[i].value / 100,
4836                                         (dcef_table->dpm_levels[i].value / 100 == now) ?
4837                                         "*" : "");
4838                 break;
4839         case PP_PCIE:
4840                 current_gen_speed =
4841                         vega10_get_current_pcie_link_speed_level(hwmgr);
4842                 current_lane_width =
4843                         vega10_get_current_pcie_link_width_level(hwmgr);
4844                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
4845                         gen_speed = pptable->PcieGenSpeed[i];
4846                         lane_width = pptable->PcieLaneCount[i];
4847
4848                         size += sprintf(buf + size, "%d: %s %s %s\n", i,
4849                                         (gen_speed == 0) ? "2.5GT/s," :
4850                                         (gen_speed == 1) ? "5.0GT/s," :
4851                                         (gen_speed == 2) ? "8.0GT/s," :
4852                                         (gen_speed == 3) ? "16.0GT/s," : "",
4853                                         (lane_width == 1) ? "x1" :
4854                                         (lane_width == 2) ? "x2" :
4855                                         (lane_width == 3) ? "x4" :
4856                                         (lane_width == 4) ? "x8" :
4857                                         (lane_width == 5) ? "x12" :
4858                                         (lane_width == 6) ? "x16" : "",
4859                                         (current_gen_speed == gen_speed) &&
4860                                         (current_lane_width == lane_width) ?
4861                                         "*" : "");
4862                 }
4863                 break;
4864
4865         case OD_SCLK:
4866                 if (hwmgr->od_enabled) {
4867                         size += sprintf(buf + size, "%s:\n", "OD_SCLK");
4868                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4869                         for (i = 0; i < podn_vdd_dep->count; i++)
4870                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4871                                         i, podn_vdd_dep->entries[i].clk / 100,
4872                                                 podn_vdd_dep->entries[i].vddc);
4873                 }
4874                 break;
4875         case OD_MCLK:
4876                 if (hwmgr->od_enabled) {
4877                         size += sprintf(buf + size, "%s:\n", "OD_MCLK");
4878                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4879                         for (i = 0; i < podn_vdd_dep->count; i++)
4880                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4881                                         i, podn_vdd_dep->entries[i].clk/100,
4882                                                 podn_vdd_dep->entries[i].vddc);
4883                 }
4884                 break;
4885         case OD_RANGE:
4886                 if (hwmgr->od_enabled) {
4887                         size += sprintf(buf + size, "%s:\n", "OD_RANGE");
4888                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4889                                 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4890                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4891                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4892                                 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4893                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4894                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4895                                 data->odn_dpm_table.min_vddc,
4896                                 data->odn_dpm_table.max_vddc);
4897                 }
4898                 break;
4899         default:
4900                 break;
4901         }
4902         return size;
4903 }
4904
4905 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4906 {
4907         struct vega10_hwmgr *data = hwmgr->backend;
4908         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4909         int result = 0;
4910
4911         if ((data->water_marks_bitmap & WaterMarksExist) &&
4912                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
4913                 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4914                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
4915                 data->water_marks_bitmap |= WaterMarksLoaded;
4916         }
4917
4918         if (data->water_marks_bitmap & WaterMarksLoaded) {
4919                 smum_send_msg_to_smc_with_parameter(hwmgr,
4920                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
4921                         NULL);
4922         }
4923
4924         return result;
4925 }
4926
4927 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4928 {
4929         struct vega10_hwmgr *data = hwmgr->backend;
4930
4931         if (data->smu_features[GNLD_DPM_UVD].supported) {
4932                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4933                                 enable,
4934                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4935                                 "Attempt to Enable/Disable DPM UVD Failed!",
4936                                 return -1);
4937                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4938         }
4939         return 0;
4940 }
4941
4942 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4943 {
4944         struct vega10_hwmgr *data = hwmgr->backend;
4945
4946         data->vce_power_gated = bgate;
4947         vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4948 }
4949
4950 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4951 {
4952         struct vega10_hwmgr *data = hwmgr->backend;
4953
4954         data->uvd_power_gated = bgate;
4955         vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4956 }
4957
4958 static inline bool vega10_are_power_levels_equal(
4959                                 const struct vega10_performance_level *pl1,
4960                                 const struct vega10_performance_level *pl2)
4961 {
4962         return ((pl1->soc_clock == pl2->soc_clock) &&
4963                         (pl1->gfx_clock == pl2->gfx_clock) &&
4964                         (pl1->mem_clock == pl2->mem_clock));
4965 }
4966
4967 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4968                                 const struct pp_hw_power_state *pstate1,
4969                         const struct pp_hw_power_state *pstate2, bool *equal)
4970 {
4971         const struct vega10_power_state *vega10_psa;
4972         const struct vega10_power_state *vega10_psb;
4973         int i;
4974
4975         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4976                 return -EINVAL;
4977
4978         vega10_psa = cast_const_phw_vega10_power_state(pstate1);
4979         vega10_psb = cast_const_phw_vega10_power_state(pstate2);
4980
4981         /* If the two states don't even have the same number of performance levels
4982          * they cannot be the same state.
4983          */
4984         if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) {
4985                 *equal = false;
4986                 return 0;
4987         }
4988
4989         for (i = 0; i < vega10_psa->performance_level_count; i++) {
4990                 if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]),
4991                                                    &(vega10_psb->performance_levels[i]))) {
4992                         /* If we have found even one performance level pair
4993                          * that is different the states are different.
4994                          */
4995                         *equal = false;
4996                         return 0;
4997                 }
4998         }
4999
5000         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5001         *equal = ((vega10_psa->uvd_clks.vclk == vega10_psb->uvd_clks.vclk) &&
5002                   (vega10_psa->uvd_clks.dclk == vega10_psb->uvd_clks.dclk));
5003         *equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) &&
5004                    (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk));
5005         *equal &= (vega10_psa->sclk_threshold == vega10_psb->sclk_threshold);
5006
5007         return 0;
5008 }
5009
5010 static bool
5011 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5012 {
5013         struct vega10_hwmgr *data = hwmgr->backend;
5014         bool is_update_required = false;
5015
5016         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
5017                 is_update_required = true;
5018
5019         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
5020                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
5021                         is_update_required = true;
5022         }
5023
5024         return is_update_required;
5025 }
5026
5027 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
5028 {
5029         int tmp_result, result = 0;
5030
5031         if (!hwmgr->not_vf)
5032                 return 0;
5033
5034         if (PP_CAP(PHM_PlatformCaps_ThermalController))
5035                 vega10_disable_thermal_protection(hwmgr);
5036
5037         tmp_result = vega10_disable_power_containment(hwmgr);
5038         PP_ASSERT_WITH_CODE((tmp_result == 0),
5039                         "Failed to disable power containment!", result = tmp_result);
5040
5041         tmp_result = vega10_disable_didt_config(hwmgr);
5042         PP_ASSERT_WITH_CODE((tmp_result == 0),
5043                         "Failed to disable didt config!", result = tmp_result);
5044
5045         tmp_result = vega10_avfs_enable(hwmgr, false);
5046         PP_ASSERT_WITH_CODE((tmp_result == 0),
5047                         "Failed to disable AVFS!", result = tmp_result);
5048
5049         tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
5050         PP_ASSERT_WITH_CODE((tmp_result == 0),
5051                         "Failed to stop DPM!", result = tmp_result);
5052
5053         tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
5054         PP_ASSERT_WITH_CODE((tmp_result == 0),
5055                         "Failed to disable deep sleep!", result = tmp_result);
5056
5057         tmp_result = vega10_disable_ulv(hwmgr);
5058         PP_ASSERT_WITH_CODE((tmp_result == 0),
5059                         "Failed to disable ulv!", result = tmp_result);
5060
5061         tmp_result =  vega10_acg_disable(hwmgr);
5062         PP_ASSERT_WITH_CODE((tmp_result == 0),
5063                         "Failed to disable acg!", result = tmp_result);
5064
5065         vega10_enable_disable_PCC_limit_feature(hwmgr, false);
5066         return result;
5067 }
5068
5069 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
5070 {
5071         struct vega10_hwmgr *data = hwmgr->backend;
5072         int result;
5073
5074         result = vega10_disable_dpm_tasks(hwmgr);
5075         PP_ASSERT_WITH_CODE((0 == result),
5076                         "[disable_dpm_tasks] Failed to disable DPM!",
5077                         );
5078         data->water_marks_bitmap &= ~(WaterMarksLoaded);
5079
5080         return result;
5081 }
5082
5083 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
5084 {
5085         struct vega10_hwmgr *data = hwmgr->backend;
5086         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
5087         struct vega10_single_dpm_table *golden_sclk_table =
5088                         &(data->golden_dpm_table.gfx_table);
5089         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
5090         int golden_value = golden_sclk_table->dpm_levels
5091                         [golden_sclk_table->count - 1].value;
5092
5093         value -= golden_value;
5094         value = DIV_ROUND_UP(value * 100, golden_value);
5095
5096         return value;
5097 }
5098
5099 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5100 {
5101         struct vega10_hwmgr *data = hwmgr->backend;
5102         struct vega10_single_dpm_table *golden_sclk_table =
5103                         &(data->golden_dpm_table.gfx_table);
5104         struct pp_power_state *ps;
5105         struct vega10_power_state *vega10_ps;
5106
5107         ps = hwmgr->request_ps;
5108
5109         if (ps == NULL)
5110                 return -EINVAL;
5111
5112         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5113
5114         vega10_ps->performance_levels
5115         [vega10_ps->performance_level_count - 1].gfx_clock =
5116                         golden_sclk_table->dpm_levels
5117                         [golden_sclk_table->count - 1].value *
5118                         value / 100 +
5119                         golden_sclk_table->dpm_levels
5120                         [golden_sclk_table->count - 1].value;
5121
5122         if (vega10_ps->performance_levels
5123                         [vega10_ps->performance_level_count - 1].gfx_clock >
5124                         hwmgr->platform_descriptor.overdriveLimit.engineClock) {
5125                 vega10_ps->performance_levels
5126                 [vega10_ps->performance_level_count - 1].gfx_clock =
5127                                 hwmgr->platform_descriptor.overdriveLimit.engineClock;
5128                 pr_warn("max sclk supported by vbios is %d\n",
5129                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
5130         }
5131         return 0;
5132 }
5133
5134 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
5135 {
5136         struct vega10_hwmgr *data = hwmgr->backend;
5137         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
5138         struct vega10_single_dpm_table *golden_mclk_table =
5139                         &(data->golden_dpm_table.mem_table);
5140         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
5141         int golden_value = golden_mclk_table->dpm_levels
5142                         [golden_mclk_table->count - 1].value;
5143
5144         value -= golden_value;
5145         value = DIV_ROUND_UP(value * 100, golden_value);
5146
5147         return value;
5148 }
5149
5150 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5151 {
5152         struct vega10_hwmgr *data = hwmgr->backend;
5153         struct vega10_single_dpm_table *golden_mclk_table =
5154                         &(data->golden_dpm_table.mem_table);
5155         struct pp_power_state  *ps;
5156         struct vega10_power_state  *vega10_ps;
5157
5158         ps = hwmgr->request_ps;
5159
5160         if (ps == NULL)
5161                 return -EINVAL;
5162
5163         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5164
5165         vega10_ps->performance_levels
5166         [vega10_ps->performance_level_count - 1].mem_clock =
5167                         golden_mclk_table->dpm_levels
5168                         [golden_mclk_table->count - 1].value *
5169                         value / 100 +
5170                         golden_mclk_table->dpm_levels
5171                         [golden_mclk_table->count - 1].value;
5172
5173         if (vega10_ps->performance_levels
5174                         [vega10_ps->performance_level_count - 1].mem_clock >
5175                         hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
5176                 vega10_ps->performance_levels
5177                 [vega10_ps->performance_level_count - 1].mem_clock =
5178                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
5179                 pr_warn("max mclk supported by vbios is %d\n",
5180                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
5181         }
5182
5183         return 0;
5184 }
5185
5186 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
5187                                         uint32_t virtual_addr_low,
5188                                         uint32_t virtual_addr_hi,
5189                                         uint32_t mc_addr_low,
5190                                         uint32_t mc_addr_hi,
5191                                         uint32_t size)
5192 {
5193         smum_send_msg_to_smc_with_parameter(hwmgr,
5194                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
5195                                         virtual_addr_hi,
5196                                         NULL);
5197         smum_send_msg_to_smc_with_parameter(hwmgr,
5198                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
5199                                         virtual_addr_low,
5200                                         NULL);
5201         smum_send_msg_to_smc_with_parameter(hwmgr,
5202                                         PPSMC_MSG_DramLogSetDramAddrHigh,
5203                                         mc_addr_hi,
5204                                         NULL);
5205
5206         smum_send_msg_to_smc_with_parameter(hwmgr,
5207                                         PPSMC_MSG_DramLogSetDramAddrLow,
5208                                         mc_addr_low,
5209                                         NULL);
5210
5211         smum_send_msg_to_smc_with_parameter(hwmgr,
5212                                         PPSMC_MSG_DramLogSetDramSize,
5213                                         size,
5214                                         NULL);
5215         return 0;
5216 }
5217
5218 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
5219                 struct PP_TemperatureRange *thermal_data)
5220 {
5221         struct vega10_hwmgr *data = hwmgr->backend;
5222         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
5223
5224         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
5225
5226         thermal_data->max = pp_table->TedgeLimit *
5227                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5228         thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
5229                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5230         thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
5231                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5232         thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
5233                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5234         thermal_data->mem_crit_max = pp_table->ThbmLimit *
5235                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5236         thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
5237                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5238
5239         return 0;
5240 }
5241
5242 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
5243 {
5244         struct vega10_hwmgr *data = hwmgr->backend;
5245         uint32_t i, size = 0;
5246         static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
5247                                                 {70, 60, 1, 3,},
5248                                                 {90, 60, 0, 0,},
5249                                                 {70, 60, 0, 0,},
5250                                                 {70, 90, 0, 0,},
5251                                                 {30, 60, 0, 6,},
5252                                                 };
5253         static const char *title[6] = {"NUM",
5254                         "MODE_NAME",
5255                         "BUSY_SET_POINT",
5256                         "FPS",
5257                         "USE_RLC_BUSY",
5258                         "MIN_ACTIVE_LEVEL"};
5259
5260         if (!buf)
5261                 return -EINVAL;
5262
5263         phm_get_sysfs_buf(&buf, &size);
5264
5265         size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0],
5266                         title[1], title[2], title[3], title[4], title[5]);
5267
5268         for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
5269                 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n",
5270                         i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5271                         profile_mode_setting[i][0], profile_mode_setting[i][1],
5272                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
5273
5274         size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
5275                         amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5276                         data->custom_profile_mode[0], data->custom_profile_mode[1],
5277                         data->custom_profile_mode[2], data->custom_profile_mode[3]);
5278         return size;
5279 }
5280
5281 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr)
5282 {
5283         struct amdgpu_device *adev = hwmgr->adev;
5284
5285         return (adev->pdev->device == 0x6860);
5286 }
5287
5288 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5289 {
5290         struct vega10_hwmgr *data = hwmgr->backend;
5291         uint8_t busy_set_point;
5292         uint8_t FPS;
5293         uint8_t use_rlc_busy;
5294         uint8_t min_active_level;
5295         uint32_t power_profile_mode = input[size];
5296
5297         if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
5298                 if (size != 0 && size != 4)
5299                         return -EINVAL;
5300
5301                 /* If size = 0 and the CUSTOM profile has been set already
5302                  * then just apply the profile. The copy stored in the hwmgr
5303                  * is zeroed out on init
5304                  */
5305                 if (size == 0) {
5306                         if (data->custom_profile_mode[0] != 0)
5307                                 goto out;
5308                         else
5309                                 return -EINVAL;
5310                 }
5311
5312                 data->custom_profile_mode[0] = busy_set_point = input[0];
5313                 data->custom_profile_mode[1] = FPS = input[1];
5314                 data->custom_profile_mode[2] = use_rlc_busy = input[2];
5315                 data->custom_profile_mode[3] = min_active_level = input[3];
5316                 smum_send_msg_to_smc_with_parameter(hwmgr,
5317                                         PPSMC_MSG_SetCustomGfxDpmParameters,
5318                                         busy_set_point | FPS<<8 |
5319                                         use_rlc_busy << 16 | min_active_level<<24,
5320                                         NULL);
5321         }
5322
5323 out:
5324         if (vega10_get_power_profile_mode_quirks(hwmgr))
5325                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5326                                                 1 << power_profile_mode,
5327                                                 NULL);
5328         else
5329                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5330                                                 (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1),
5331                                                 NULL);
5332
5333         hwmgr->power_profile_mode = power_profile_mode;
5334
5335         return 0;
5336 }
5337
5338
5339 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
5340                                         enum PP_OD_DPM_TABLE_COMMAND type,
5341                                         uint32_t clk,
5342                                         uint32_t voltage)
5343 {
5344         struct vega10_hwmgr *data = hwmgr->backend;
5345         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
5346         struct vega10_single_dpm_table *golden_table;
5347
5348         if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
5349                 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
5350                 return false;
5351         }
5352
5353         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5354                 golden_table = &(data->golden_dpm_table.gfx_table);
5355                 if (golden_table->dpm_levels[0].value > clk ||
5356                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5357                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5358                                 golden_table->dpm_levels[0].value/100,
5359                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5360                         return false;
5361                 }
5362         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5363                 golden_table = &(data->golden_dpm_table.mem_table);
5364                 if (golden_table->dpm_levels[0].value > clk ||
5365                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5366                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5367                                 golden_table->dpm_levels[0].value/100,
5368                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5369                         return false;
5370                 }
5371         } else {
5372                 return false;
5373         }
5374
5375         return true;
5376 }
5377
5378 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
5379 {
5380         struct vega10_hwmgr *data = hwmgr->backend;
5381         struct pp_power_state *ps = hwmgr->request_ps;
5382         struct vega10_power_state *vega10_ps;
5383         struct vega10_single_dpm_table *gfx_dpm_table =
5384                 &data->dpm_table.gfx_table;
5385         struct vega10_single_dpm_table *soc_dpm_table =
5386                 &data->dpm_table.soc_table;
5387         struct vega10_single_dpm_table *mem_dpm_table =
5388                 &data->dpm_table.mem_table;
5389         int max_level;
5390
5391         if (!ps)
5392                 return;
5393
5394         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5395         max_level = vega10_ps->performance_level_count - 1;
5396
5397         if (vega10_ps->performance_levels[max_level].gfx_clock !=
5398             gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5399                 vega10_ps->performance_levels[max_level].gfx_clock =
5400                         gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5401
5402         if (vega10_ps->performance_levels[max_level].soc_clock !=
5403             soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5404                 vega10_ps->performance_levels[max_level].soc_clock =
5405                         soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5406
5407         if (vega10_ps->performance_levels[max_level].mem_clock !=
5408             mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5409                 vega10_ps->performance_levels[max_level].mem_clock =
5410                         mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5411
5412         if (!hwmgr->ps)
5413                 return;
5414
5415         ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
5416         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5417         max_level = vega10_ps->performance_level_count - 1;
5418
5419         if (vega10_ps->performance_levels[max_level].gfx_clock !=
5420             gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5421                 vega10_ps->performance_levels[max_level].gfx_clock =
5422                         gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5423
5424         if (vega10_ps->performance_levels[max_level].soc_clock !=
5425             soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5426                 vega10_ps->performance_levels[max_level].soc_clock =
5427                         soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5428
5429         if (vega10_ps->performance_levels[max_level].mem_clock !=
5430             mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5431                 vega10_ps->performance_levels[max_level].mem_clock =
5432                         mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5433 }
5434
5435 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
5436                                                 enum PP_OD_DPM_TABLE_COMMAND type)
5437 {
5438         struct vega10_hwmgr *data = hwmgr->backend;
5439         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
5440         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
5441         struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table;
5442
5443         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
5444                                                         &data->odn_dpm_table.vdd_dep_on_socclk;
5445         struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
5446
5447         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
5448         uint8_t i, j;
5449
5450         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5451                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
5452                 for (i = 0; i < podn_vdd_dep->count; i++)
5453                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
5454         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5455                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
5456                 for (i = 0; i < dpm_table->count; i++) {
5457                         for (j = 0; j < od_vddc_lookup_table->count; j++) {
5458                                 if (od_vddc_lookup_table->entries[j].us_vdd >
5459                                         podn_vdd_dep->entries[i].vddc)
5460                                         break;
5461                         }
5462                         if (j == od_vddc_lookup_table->count) {
5463                                 j = od_vddc_lookup_table->count - 1;
5464                                 od_vddc_lookup_table->entries[j].us_vdd =
5465                                         podn_vdd_dep->entries[i].vddc;
5466                                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
5467                         }
5468                         podn_vdd_dep->entries[i].vddInd = j;
5469                 }
5470                 dpm_table = &data->dpm_table.soc_table;
5471                 for (i = 0; i < dep_table->count; i++) {
5472                         if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd &&
5473                                         dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) {
5474                                 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5475                                 for (; (i < dep_table->count) &&
5476                                        (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) {
5477                                         podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk;
5478                                         dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
5479                                 }
5480                                 break;
5481                         } else {
5482                                 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk;
5483                                 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc;
5484                                 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd;
5485                                 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk;
5486                         }
5487                 }
5488                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
5489                                         podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) {
5490                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5491                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk =
5492                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5493                         dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value =
5494                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5495                 }
5496                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
5497                                         podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) {
5498                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5499                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd =
5500                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
5501                 }
5502         }
5503         vega10_odn_update_power_state(hwmgr);
5504 }
5505
5506 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5507                                         enum PP_OD_DPM_TABLE_COMMAND type,
5508                                         long *input, uint32_t size)
5509 {
5510         struct vega10_hwmgr *data = hwmgr->backend;
5511         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
5512         struct vega10_single_dpm_table *dpm_table;
5513
5514         uint32_t input_clk;
5515         uint32_t input_vol;
5516         uint32_t input_level;
5517         uint32_t i;
5518
5519         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5520                                 return -EINVAL);
5521
5522         if (!hwmgr->od_enabled) {
5523                 pr_info("OverDrive feature not enabled\n");
5524                 return -EINVAL;
5525         }
5526
5527         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5528                 dpm_table = &data->dpm_table.gfx_table;
5529                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
5530                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5531         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5532                 dpm_table = &data->dpm_table.mem_table;
5533                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
5534                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5535         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5536                 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
5537                 vega10_odn_initial_default_setting(hwmgr);
5538                 vega10_odn_update_power_state(hwmgr);
5539                 /* force to update all clock tables */
5540                 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK |
5541                                               DPMTABLE_UPDATE_MCLK |
5542                                               DPMTABLE_UPDATE_SOCCLK;
5543                 return 0;
5544         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
5545                 vega10_check_dpm_table_updated(hwmgr);
5546                 return 0;
5547         } else {
5548                 return -EINVAL;
5549         }
5550
5551         for (i = 0; i < size; i += 3) {
5552                 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
5553                         pr_info("invalid clock voltage input\n");
5554                         return 0;
5555                 }
5556                 input_level = input[i];
5557                 input_clk = input[i+1] * 100;
5558                 input_vol = input[i+2];
5559
5560                 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5561                         dpm_table->dpm_levels[input_level].value = input_clk;
5562                         podn_vdd_dep_table->entries[input_level].clk = input_clk;
5563                         podn_vdd_dep_table->entries[input_level].vddc = input_vol;
5564                 } else {
5565                         return -EINVAL;
5566                 }
5567         }
5568         vega10_odn_update_soc_table(hwmgr, type);
5569         return 0;
5570 }
5571
5572 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
5573                                 enum pp_mp1_state mp1_state)
5574 {
5575         uint16_t msg;
5576         int ret;
5577
5578         switch (mp1_state) {
5579         case PP_MP1_STATE_UNLOAD:
5580                 msg = PPSMC_MSG_PrepareMp1ForUnload;
5581                 break;
5582         case PP_MP1_STATE_SHUTDOWN:
5583         case PP_MP1_STATE_RESET:
5584         case PP_MP1_STATE_NONE:
5585         default:
5586                 return 0;
5587         }
5588
5589         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
5590                             "[PrepareMp1] Failed!",
5591                             return ret);
5592
5593         return 0;
5594 }
5595
5596 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5597                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
5598                                 PHM_PerformanceLevel *level)
5599 {
5600         const struct vega10_power_state *vega10_ps;
5601         uint32_t i;
5602
5603         if (level == NULL || hwmgr == NULL || state == NULL)
5604                 return -EINVAL;
5605
5606         vega10_ps = cast_const_phw_vega10_power_state(state);
5607
5608         i = index > vega10_ps->performance_level_count - 1 ?
5609                         vega10_ps->performance_level_count - 1 : index;
5610
5611         level->coreClock = vega10_ps->performance_levels[i].gfx_clock;
5612         level->memory_clock = vega10_ps->performance_levels[i].mem_clock;
5613
5614         return 0;
5615 }
5616
5617 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable)
5618 {
5619         struct vega10_hwmgr *data = hwmgr->backend;
5620         uint32_t feature_mask = 0;
5621
5622         if (disable) {
5623                 feature_mask |= data->smu_features[GNLD_ULV].enabled ?
5624                         data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5625                 feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
5626                         data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5627                 feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
5628                         data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5629                 feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
5630                         data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5631                 feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
5632                         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5633         } else {
5634                 feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
5635                         data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5636                 feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
5637                         data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5638                 feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
5639                         data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5640                 feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
5641                         data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5642                 feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
5643                         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5644         }
5645
5646         if (feature_mask)
5647                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
5648                                 !disable, feature_mask),
5649                                 "enable/disable power features for compute performance Failed!",
5650                                 return -EINVAL);
5651
5652         if (disable) {
5653                 data->smu_features[GNLD_ULV].enabled = false;
5654                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
5655                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
5656                 data->smu_features[GNLD_DS_LCLK].enabled = false;
5657                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
5658         } else {
5659                 data->smu_features[GNLD_ULV].enabled = true;
5660                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
5661                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
5662                 data->smu_features[GNLD_DS_LCLK].enabled = true;
5663                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
5664         }
5665
5666         return 0;
5667
5668 }
5669
5670 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
5671         .backend_init = vega10_hwmgr_backend_init,
5672         .backend_fini = vega10_hwmgr_backend_fini,
5673         .asic_setup = vega10_setup_asic_task,
5674         .dynamic_state_management_enable = vega10_enable_dpm_tasks,
5675         .dynamic_state_management_disable = vega10_disable_dpm_tasks,
5676         .get_num_of_pp_table_entries =
5677                         vega10_get_number_of_powerplay_table_entries,
5678         .get_power_state_size = vega10_get_power_state_size,
5679         .get_pp_table_entry = vega10_get_pp_table_entry,
5680         .patch_boot_state = vega10_patch_boot_state,
5681         .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
5682         .power_state_set = vega10_set_power_state_tasks,
5683         .get_sclk = vega10_dpm_get_sclk,
5684         .get_mclk = vega10_dpm_get_mclk,
5685         .notify_smc_display_config_after_ps_adjustment =
5686                         vega10_notify_smc_display_config_after_ps_adjustment,
5687         .force_dpm_level = vega10_dpm_force_dpm_level,
5688         .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
5689         .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
5690         .get_fan_speed_pwm = vega10_fan_ctrl_get_fan_speed_pwm,
5691         .set_fan_speed_pwm = vega10_fan_ctrl_set_fan_speed_pwm,
5692         .reset_fan_speed_to_default =
5693                         vega10_fan_ctrl_reset_fan_speed_to_default,
5694         .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
5695         .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
5696         .uninitialize_thermal_controller =
5697                         vega10_thermal_ctrl_uninitialize_thermal_controller,
5698         .set_fan_control_mode = vega10_set_fan_control_mode,
5699         .get_fan_control_mode = vega10_get_fan_control_mode,
5700         .read_sensor = vega10_read_sensor,
5701         .get_dal_power_level = vega10_get_dal_power_level,
5702         .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
5703         .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
5704         .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
5705         .display_clock_voltage_request = vega10_display_clock_voltage_request,
5706         .force_clock_level = vega10_force_clock_level,
5707         .emit_clock_levels = vega10_emit_clock_levels,
5708         .print_clock_levels = vega10_print_clock_levels,
5709         .display_config_changed = vega10_display_configuration_changed_task,
5710         .powergate_uvd = vega10_power_gate_uvd,
5711         .powergate_vce = vega10_power_gate_vce,
5712         .check_states_equal = vega10_check_states_equal,
5713         .check_smc_update_required_for_display_configuration =
5714                         vega10_check_smc_update_required_for_display_configuration,
5715         .power_off_asic = vega10_power_off_asic,
5716         .disable_smc_firmware_ctf = vega10_thermal_disable_alert,
5717         .get_sclk_od = vega10_get_sclk_od,
5718         .set_sclk_od = vega10_set_sclk_od,
5719         .get_mclk_od = vega10_get_mclk_od,
5720         .set_mclk_od = vega10_set_mclk_od,
5721         .avfs_control = vega10_avfs_enable,
5722         .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
5723         .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
5724         .register_irq_handlers = smu9_register_irq_handlers,
5725         .start_thermal_controller = vega10_start_thermal_controller,
5726         .get_power_profile_mode = vega10_get_power_profile_mode,
5727         .set_power_profile_mode = vega10_set_power_profile_mode,
5728         .set_power_limit = vega10_set_power_limit,
5729         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
5730         .get_performance_level = vega10_get_performance_level,
5731         .get_asic_baco_capability = smu9_baco_get_capability,
5732         .get_asic_baco_state = smu9_baco_get_state,
5733         .set_asic_baco_state = vega10_baco_set_state,
5734         .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
5735         .get_ppfeature_status = vega10_get_ppfeature_status,
5736         .set_ppfeature_status = vega10_set_ppfeature_status,
5737         .set_mp1_state = vega10_set_mp1_state,
5738         .disable_power_features_for_compute_performance =
5739                         vega10_disable_power_features_for_compute_performance,
5740 };
5741
5742 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
5743 {
5744         struct amdgpu_device *adev = hwmgr->adev;
5745
5746         hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
5747         hwmgr->pptable_func = &vega10_pptable_funcs;
5748         if (amdgpu_passthrough(adev))
5749                 return vega10_baco_set_cap(hwmgr);
5750
5751         return 0;
5752 }