drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/delay.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27 #include <linux/slab.h>
  28 #include <asm/div64.h>
  29 #if IS_ENABLED(CONFIG_X86_64)
  30 #include <asm/intel-family.h>
  31 #endif
  32 #include <drm/amdgpu_drm.h>
  33 #include "ppatomctrl.h"
  34 #include "atombios.h"
  35 #include "pptable_v1_0.h"
  36 #include "pppcielanes.h"
  37 #include "amd_pcie_helpers.h"
  38 #include "hardwaremanager.h"
  39 #include "process_pptables_v1_0.h"
  40 #include "cgs_common.h"
  41
  42 #include "smu7_common.h"
  43
  44 #include "hwmgr.h"
  45 #include "smu7_hwmgr.h"
  46 #include "smu_ucode_xfer_vi.h"
  47 #include "smu7_powertune.h"
  48 #include "smu7_dyn_defaults.h"
  49 #include "smu7_thermal.h"
  50 #include "smu7_clockpowergating.h"
  51 #include "processpptables.h"
  52 #include "pp_thermal.h"
  53 #include "smu7_baco.h"
  54 #include "smu7_smumgr.h"
  55 #include "polaris10_smumgr.h"
  56
  57 #include "ivsrcid/ivsrcid_vislands30.h"
  58
  59 #define MC_CG_ARB_FREQ_F0           0x0a
  60 #define MC_CG_ARB_FREQ_F1           0x0b
  61 #define MC_CG_ARB_FREQ_F2           0x0c
  62 #define MC_CG_ARB_FREQ_F3           0x0d
  63
  64 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  65 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  66 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  67 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  68
  69 #define SMC_CG_IND_START            0xc0030000
  70 #define SMC_CG_IND_END              0xc0040000
  71
  72 #define MEM_FREQ_LOW_LATENCY        25000
  73 #define MEM_FREQ_HIGH_LATENCY       80000
  74
  75 #define MEM_LATENCY_HIGH            45
  76 #define MEM_LATENCY_LOW             35
  77 #define MEM_LATENCY_ERR             0xFFFF
  78
  79 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  80 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  81 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  82
  83 #define PCIE_BUS_CLK                10000
  84 #define TCLK                        (PCIE_BUS_CLK / 10)
  85
  86 static struct profile_mode_setting smu7_profiling[7] =
  87                                         {{0, 0, 0, 0, 0, 0, 0, 0},
  88                                          {1, 0, 100, 30, 1, 0, 100, 10},
  89                                          {1, 10, 0, 30, 0, 0, 0, 0},
  90                                          {0, 0, 0, 0, 1, 10, 16, 31},
  91                                          {1, 0, 11, 50, 1, 0, 100, 10},
  92                                          {1, 0, 5, 30, 0, 0, 0, 0},
  93                                          {0, 0, 0, 0, 0, 0, 0, 0},
  94                                         };
  95
  96 #define PPSMC_MSG_SetVBITimeout_VEGAM    ((uint16_t) 0x310)
  97
  98 #define ixPWR_SVI2_PLANE1_LOAD                     0xC0200280
  99 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK                    0x00000020L
 100 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK                 0x00000040L
 101 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT                  0x00000005
 102 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT               0x00000006
 103
 104 #define STRAP_EVV_REVISION_MSB          2211
 105 #define STRAP_EVV_REVISION_LSB          2208
 106
 107 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 108 enum DPM_EVENT_SRC {
 109         DPM_EVENT_SRC_ANALOG = 0,
 110         DPM_EVENT_SRC_EXTERNAL = 1,
 111         DPM_EVENT_SRC_DIGITAL = 2,
 112         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 113         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 114 };
 115
 116 #define ixDIDT_SQ_EDC_CTRL                         0x0013
 117 #define ixDIDT_SQ_EDC_THRESHOLD                    0x0014
 118 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2            0x0015
 119 #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4            0x0016
 120 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6            0x0017
 121 #define ixDIDT_SQ_EDC_STALL_PATTERN_7              0x0018
 122
 123 #define ixDIDT_TD_EDC_CTRL                         0x0053
 124 #define ixDIDT_TD_EDC_THRESHOLD                    0x0054
 125 #define ixDIDT_TD_EDC_STALL_PATTERN_1_2            0x0055
 126 #define ixDIDT_TD_EDC_STALL_PATTERN_3_4            0x0056
 127 #define ixDIDT_TD_EDC_STALL_PATTERN_5_6            0x0057
 128 #define ixDIDT_TD_EDC_STALL_PATTERN_7              0x0058
 129
 130 #define ixDIDT_TCP_EDC_CTRL                        0x0073
 131 #define ixDIDT_TCP_EDC_THRESHOLD                   0x0074
 132 #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2           0x0075
 133 #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4           0x0076
 134 #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6           0x0077
 135 #define ixDIDT_TCP_EDC_STALL_PATTERN_7             0x0078
 136
 137 #define ixDIDT_DB_EDC_CTRL                         0x0033
 138 #define ixDIDT_DB_EDC_THRESHOLD                    0x0034
 139 #define ixDIDT_DB_EDC_STALL_PATTERN_1_2            0x0035
 140 #define ixDIDT_DB_EDC_STALL_PATTERN_3_4            0x0036
 141 #define ixDIDT_DB_EDC_STALL_PATTERN_5_6            0x0037
 142 #define ixDIDT_DB_EDC_STALL_PATTERN_7              0x0038
 143
 144 uint32_t DIDTEDCConfig_P12[] = {
 145     ixDIDT_SQ_EDC_STALL_PATTERN_1_2,
 146     ixDIDT_SQ_EDC_STALL_PATTERN_3_4,
 147     ixDIDT_SQ_EDC_STALL_PATTERN_5_6,
 148     ixDIDT_SQ_EDC_STALL_PATTERN_7,
 149     ixDIDT_SQ_EDC_THRESHOLD,
 150     ixDIDT_SQ_EDC_CTRL,
 151     ixDIDT_TD_EDC_STALL_PATTERN_1_2,
 152     ixDIDT_TD_EDC_STALL_PATTERN_3_4,
 153     ixDIDT_TD_EDC_STALL_PATTERN_5_6,
 154     ixDIDT_TD_EDC_STALL_PATTERN_7,
 155     ixDIDT_TD_EDC_THRESHOLD,
 156     ixDIDT_TD_EDC_CTRL,
 157     ixDIDT_TCP_EDC_STALL_PATTERN_1_2,
 158     ixDIDT_TCP_EDC_STALL_PATTERN_3_4,
 159     ixDIDT_TCP_EDC_STALL_PATTERN_5_6,
 160     ixDIDT_TCP_EDC_STALL_PATTERN_7,
 161     ixDIDT_TCP_EDC_THRESHOLD,
 162     ixDIDT_TCP_EDC_CTRL,
 163     ixDIDT_DB_EDC_STALL_PATTERN_1_2,
 164     ixDIDT_DB_EDC_STALL_PATTERN_3_4,
 165     ixDIDT_DB_EDC_STALL_PATTERN_5_6,
 166     ixDIDT_DB_EDC_STALL_PATTERN_7,
 167     ixDIDT_DB_EDC_THRESHOLD,
 168     ixDIDT_DB_EDC_CTRL,
 169     0xFFFFFFFF // End of list
 170 };
 171
 172 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
 173 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
 174                 enum pp_clock_type type, uint32_t mask);
 175 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr);
 176
 177 static struct smu7_power_state *cast_phw_smu7_power_state(
 178                                   struct pp_hw_power_state *hw_ps)
 179 {
 180         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 181                                 "Invalid Powerstate Type!",
 182                                  return NULL);
 183
 184         return (struct smu7_power_state *)hw_ps;
 185 }
 186
 187 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
 188                                  const struct pp_hw_power_state *hw_ps)
 189 {
 190         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 191                                 "Invalid Powerstate Type!",
 192                                  return NULL);
 193
 194         return (const struct smu7_power_state *)hw_ps;
 195 }
 196
 197 /**
 198  * smu7_get_mc_microcode_version - Find the MC microcode version and store it in the HwMgr struct
 199  *
 200  * @hwmgr:  the address of the powerplay hardware manager.
 201  * Return:   always 0
 202  */
 203 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
 204 {
 205         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 206
 207         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 208
 209         return 0;
 210 }
 211
 212 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 213 {
 214         uint32_t speedCntl = 0;
 215
 216         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 217         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 218                         ixPCIE_LC_SPEED_CNTL);
 219         return((uint16_t)PHM_GET_FIELD(speedCntl,
 220                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 221 }
 222
 223 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 224 {
 225         uint32_t link_width;
 226
 227         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 228         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 229                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 230
 231         PP_ASSERT_WITH_CODE((7 >= link_width),
 232                         "Invalid PCIe lane width!", return 0);
 233
 234         return decode_pcie_lane_width(link_width);
 235 }
 236
 237 /**
 238  * smu7_enable_smc_voltage_controller - Enable voltage control
 239  *
 240  * @hwmgr:  the address of the powerplay hardware manager.
 241  * Return:   always PP_Result_OK
 242  */
 243 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 244 {
 245         if (hwmgr->chip_id >= CHIP_POLARIS10 &&
 246             hwmgr->chip_id <= CHIP_VEGAM) {
 247                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 248                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
 249                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 250                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
 251         }
 252
 253         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
 254                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL);
 255
 256         return 0;
 257 }
 258
 259 /**
 260  * smu7_voltage_control - Checks if we want to support voltage control
 261  *
 262  * @hwmgr:  the address of the powerplay hardware manager.
 263  */
 264 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
 265 {
 266         const struct smu7_hwmgr *data =
 267                         (const struct smu7_hwmgr *)(hwmgr->backend);
 268
 269         return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
 270 }
 271
 272 /**
 273  * smu7_enable_voltage_control - Enable voltage control
 274  *
 275  * @hwmgr:  the address of the powerplay hardware manager.
 276  * Return:   always 0
 277  */
 278 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
 279 {
 280         /* enable voltage control */
 281         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 282                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 283
 284         return 0;
 285 }
 286
 287 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
 288                 struct phm_clock_voltage_dependency_table *voltage_dependency_table
 289                 )
 290 {
 291         uint32_t i;
 292
 293         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 294                         "Voltage Dependency Table empty.", return -EINVAL;);
 295
 296         voltage_table->mask_low = 0;
 297         voltage_table->phase_delay = 0;
 298         voltage_table->count = voltage_dependency_table->count;
 299
 300         for (i = 0; i < voltage_dependency_table->count; i++) {
 301                 voltage_table->entries[i].value =
 302                         voltage_dependency_table->entries[i].v;
 303                 voltage_table->entries[i].smio_low = 0;
 304         }
 305
 306         return 0;
 307 }
 308
 309
 310 /**
 311  * smu7_construct_voltage_tables - Create Voltage Tables.
 312  *
 313  * @hwmgr:  the address of the powerplay hardware manager.
 314  * Return:   always 0
 315  */
 316 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 317 {
 318         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 319         struct phm_ppt_v1_information *table_info =
 320                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 321         int result = 0;
 322         uint32_t tmp;
 323
 324         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 325                 result = atomctrl_get_voltage_table_v3(hwmgr,
 326                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 327                                 &(data->mvdd_voltage_table));
 328                 PP_ASSERT_WITH_CODE((0 == result),
 329                                 "Failed to retrieve MVDD table.",
 330                                 return result);
 331         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 332                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 333                         result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 334                                         table_info->vdd_dep_on_mclk);
 335                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 336                         result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
 337                                         hwmgr->dyn_state.mvdd_dependency_on_mclk);
 338
 339                 PP_ASSERT_WITH_CODE((0 == result),
 340                                 "Failed to retrieve SVI2 MVDD table from dependency table.",
 341                                 return result;);
 342         }
 343
 344         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 345                 result = atomctrl_get_voltage_table_v3(hwmgr,
 346                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 347                                 &(data->vddci_voltage_table));
 348                 PP_ASSERT_WITH_CODE((0 == result),
 349                                 "Failed to retrieve VDDCI table.",
 350                                 return result);
 351         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 352                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 353                         result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 354                                         table_info->vdd_dep_on_mclk);
 355                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 356                         result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
 357                                         hwmgr->dyn_state.vddci_dependency_on_mclk);
 358                 PP_ASSERT_WITH_CODE((0 == result),
 359                                 "Failed to retrieve SVI2 VDDCI table from dependency table.",
 360                                 return result);
 361         }
 362
 363         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
 364                 /* VDDGFX has only SVI2 voltage control */
 365                 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
 366                                         table_info->vddgfx_lookup_table);
 367                 PP_ASSERT_WITH_CODE((0 == result),
 368                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
 369         }
 370
 371
 372         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
 373                 result = atomctrl_get_voltage_table_v3(hwmgr,
 374                                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
 375                                         &data->vddc_voltage_table);
 376                 PP_ASSERT_WITH_CODE((0 == result),
 377                         "Failed to retrieve VDDC table.", return result;);
 378         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 379
 380                 if (hwmgr->pp_table_version == PP_TABLE_V0)
 381                         result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
 382                                         hwmgr->dyn_state.vddc_dependency_on_mclk);
 383                 else if (hwmgr->pp_table_version == PP_TABLE_V1)
 384                         result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 385                                 table_info->vddc_lookup_table);
 386
 387                 PP_ASSERT_WITH_CODE((0 == result),
 388                         "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
 389         }
 390
 391         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
 392         PP_ASSERT_WITH_CODE(
 393                         (data->vddc_voltage_table.count <= tmp),
 394                 "Too many voltage values for VDDC. Trimming to fit state table.",
 395                         phm_trim_voltage_table_to_fit_state_table(tmp,
 396                                                 &(data->vddc_voltage_table)));
 397
 398         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
 399         PP_ASSERT_WITH_CODE(
 400                         (data->vddgfx_voltage_table.count <= tmp),
 401                 "Too many voltage values for VDDC. Trimming to fit state table.",
 402                         phm_trim_voltage_table_to_fit_state_table(tmp,
 403                                                 &(data->vddgfx_voltage_table)));
 404
 405         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
 406         PP_ASSERT_WITH_CODE(
 407                         (data->vddci_voltage_table.count <= tmp),
 408                 "Too many voltage values for VDDCI. Trimming to fit state table.",
 409                         phm_trim_voltage_table_to_fit_state_table(tmp,
 410                                         &(data->vddci_voltage_table)));
 411
 412         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
 413         PP_ASSERT_WITH_CODE(
 414                         (data->mvdd_voltage_table.count <= tmp),
 415                 "Too many voltage values for MVDD. Trimming to fit state table.",
 416                         phm_trim_voltage_table_to_fit_state_table(tmp,
 417                                                 &(data->mvdd_voltage_table)));
 418
 419         return 0;
 420 }
 421
 422 /**
 423  * smu7_program_static_screen_threshold_parameters - Programs static screed detection parameters
 424  *
 425  * @hwmgr:  the address of the powerplay hardware manager.
 426  * Return:   always 0
 427  */
 428 static int smu7_program_static_screen_threshold_parameters(
 429                                                         struct pp_hwmgr *hwmgr)
 430 {
 431         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 432
 433         /* Set static screen threshold unit */
 434         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 435                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 436                         data->static_screen_threshold_unit);
 437         /* Set static screen threshold */
 438         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 439                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 440                         data->static_screen_threshold);
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * smu7_enable_display_gap - Setup display gap for glitch free memory clock switching.
 447  *
 448  * @hwmgr:  the address of the powerplay hardware manager.
 449  * Return:   always  0
 450  */
 451 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
 452 {
 453         uint32_t display_gap =
 454                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 455                                         ixCG_DISPLAY_GAP_CNTL);
 456
 457         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 458                         DISP_GAP, DISPLAY_GAP_IGNORE);
 459
 460         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 461                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 462
 463         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 464                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 465
 466         return 0;
 467 }
 468
 469 /**
 470  * smu7_program_voting_clients - Programs activity state transition voting clients
 471  *
 472  * @hwmgr:  the address of the powerplay hardware manager.
 473  * Return:   always  0
 474  */
 475 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
 476 {
 477         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 478         int i;
 479
 480         /* Clear reset for voting clients before enabling DPM */
 481         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 482                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 483         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 484                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 485
 486         for (i = 0; i < 8; i++)
 487                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 488                                         ixCG_FREQ_TRAN_VOTING_0 + i * 4,
 489                                         data->voting_rights_clients[i]);
 490         return 0;
 491 }
 492
 493 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
 494 {
 495         int i;
 496
 497         /* Reset voting clients before disabling DPM */
 498         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 499                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
 500         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 501                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
 502
 503         for (i = 0; i < 8; i++)
 504                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 505                                 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
 506
 507         return 0;
 508 }
 509
 510 /* Copy one arb setting to another and then switch the active set.
 511  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 512  */
 513 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 514                 uint32_t arb_src, uint32_t arb_dest)
 515 {
 516         uint32_t mc_arb_dram_timing;
 517         uint32_t mc_arb_dram_timing2;
 518         uint32_t burst_time;
 519         uint32_t mc_cg_config;
 520
 521         switch (arb_src) {
 522         case MC_CG_ARB_FREQ_F0:
 523                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 524                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 525                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 526                 break;
 527         case MC_CG_ARB_FREQ_F1:
 528                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 529                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 530                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 531                 break;
 532         default:
 533                 return -EINVAL;
 534         }
 535
 536         switch (arb_dest) {
 537         case MC_CG_ARB_FREQ_F0:
 538                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 539                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 540                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 541                 break;
 542         case MC_CG_ARB_FREQ_F1:
 543                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 544                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 545                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 546                 break;
 547         default:
 548                 return -EINVAL;
 549         }
 550
 551         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 552         mc_cg_config |= 0x0000000F;
 553         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 554         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 555
 556         return 0;
 557 }
 558
 559 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
 560 {
 561         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL);
 562 }
 563
 564 /**
 565  * smu7_initial_switch_from_arbf0_to_f1 - Initial switch from ARB F0->F1
 566  *
 567  * @hwmgr:  the address of the powerplay hardware manager.
 568  * Return:   always 0
 569  * This function is to be called from the SetPowerState table.
 570  */
 571 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 572 {
 573         return smu7_copy_and_switch_arb_sets(hwmgr,
 574                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 575 }
 576
 577 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
 578 {
 579         uint32_t tmp;
 580
 581         tmp = (cgs_read_ind_register(hwmgr->device,
 582                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
 583                         0x0000ff00) >> 8;
 584
 585         if (tmp == MC_CG_ARB_FREQ_F0)
 586                 return 0;
 587
 588         return smu7_copy_and_switch_arb_sets(hwmgr,
 589                         tmp, MC_CG_ARB_FREQ_F0);
 590 }
 591
 592 static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr)
 593 {
 594         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 595         uint16_t pcie_gen = 0;
 596
 597         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 &&
 598             adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4)
 599                 pcie_gen = 3;
 600         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 &&
 601                 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
 602                 pcie_gen = 2;
 603         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 &&
 604                 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2)
 605                 pcie_gen = 1;
 606         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 &&
 607                 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1)
 608                 pcie_gen = 0;
 609
 610         return pcie_gen;
 611 }
 612
 613 static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr)
 614 {
 615         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 616         uint16_t pcie_width = 0;
 617
 618         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 619                 pcie_width = 16;
 620         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 621                 pcie_width = 12;
 622         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 623                 pcie_width = 8;
 624         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 625                 pcie_width = 4;
 626         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 627                 pcie_width = 2;
 628         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 629                 pcie_width = 1;
 630
 631         return pcie_width;
 632 }
 633
 634 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 635 {
 636         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 637
 638         struct phm_ppt_v1_information *table_info =
 639                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 640         struct phm_ppt_v1_pcie_table *pcie_table = NULL;
 641
 642         uint32_t i, max_entry;
 643         uint32_t tmp;
 644
 645         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 646                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 647                         return -EINVAL);
 648
 649         if (table_info != NULL)
 650                 pcie_table = table_info->pcie_table;
 651
 652         if (data->use_pcie_performance_levels &&
 653                         !data->use_pcie_power_saving_levels) {
 654                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 655                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 656         } else if (!data->use_pcie_performance_levels &&
 657                         data->use_pcie_power_saving_levels) {
 658                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 659                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 660         }
 661         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
 662         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 663                                         tmp,
 664                                         MAX_REGULAR_DPM_NUMBER);
 665
 666         if (pcie_table != NULL) {
 667                 /* max_entry is used to make sure we reserve one PCIE level
 668                  * for boot level (fix for A+A PSPP issue).
 669                  * If PCIE table from PPTable have ULV entry + 8 entries,
 670                  * then ignore the last entry.*/
 671                 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
 672                 for (i = 1; i < max_entry; i++) {
 673                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 674                                         get_pcie_gen_support(data->pcie_gen_cap,
 675                                                         pcie_table->entries[i].gen_speed),
 676                                         get_pcie_lane_support(data->pcie_lane_cap,
 677                                                         pcie_table->entries[i].lane_width));
 678                 }
 679                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 680                 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
 681         } else {
 682                 /* Hardcode Pcie Table */
 683                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 684                                 get_pcie_gen_support(data->pcie_gen_cap,
 685                                                 PP_Min_PCIEGen),
 686                                 get_pcie_lane_support(data->pcie_lane_cap,
 687                                                 PP_Max_PCIELane));
 688                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 689                                 get_pcie_gen_support(data->pcie_gen_cap,
 690                                                 PP_Min_PCIEGen),
 691                                 get_pcie_lane_support(data->pcie_lane_cap,
 692                                                 PP_Max_PCIELane));
 693                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 694                                 get_pcie_gen_support(data->pcie_gen_cap,
 695                                                 PP_Max_PCIEGen),
 696                                 get_pcie_lane_support(data->pcie_lane_cap,
 697                                                 PP_Max_PCIELane));
 698                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 699                                 get_pcie_gen_support(data->pcie_gen_cap,
 700                                                 PP_Max_PCIEGen),
 701                                 get_pcie_lane_support(data->pcie_lane_cap,
 702                                                 PP_Max_PCIELane));
 703                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 704                                 get_pcie_gen_support(data->pcie_gen_cap,
 705                                                 PP_Max_PCIEGen),
 706                                 get_pcie_lane_support(data->pcie_lane_cap,
 707                                                 PP_Max_PCIELane));
 708                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 709                                 get_pcie_gen_support(data->pcie_gen_cap,
 710                                                 PP_Max_PCIEGen),
 711                                 get_pcie_lane_support(data->pcie_lane_cap,
 712                                                 PP_Max_PCIELane));
 713
 714                 data->dpm_table.pcie_speed_table.count = 6;
 715         }
 716         /* Populate last level for boot PCIE level, but do not increment count. */
 717         if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
 718                 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
 719                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
 720                                 get_pcie_gen_support(data->pcie_gen_cap,
 721                                                 PP_Max_PCIEGen),
 722                                 data->vbios_boot_state.pcie_lane_bootup_value);
 723         } else {
 724                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 725                         data->dpm_table.pcie_speed_table.count,
 726                         get_pcie_gen_support(data->pcie_gen_cap,
 727                                         PP_Min_PCIEGen),
 728                         get_pcie_lane_support(data->pcie_lane_cap,
 729                                         PP_Max_PCIELane));
 730
 731                 if (data->pcie_dpm_key_disabled)
 732                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 733                                 data->dpm_table.pcie_speed_table.count,
 734                                 smu7_override_pcie_speed(hwmgr), smu7_override_pcie_width(hwmgr));
 735         }
 736         return 0;
 737 }
 738
 739 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
 740 {
 741         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 742
 743         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
 744
 745         phm_reset_single_dpm_table(
 746                         &data->dpm_table.sclk_table,
 747                                 smum_get_mac_definition(hwmgr,
 748                                         SMU_MAX_LEVELS_GRAPHICS),
 749                                         MAX_REGULAR_DPM_NUMBER);
 750         phm_reset_single_dpm_table(
 751                         &data->dpm_table.mclk_table,
 752                         smum_get_mac_definition(hwmgr,
 753                                 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
 754
 755         phm_reset_single_dpm_table(
 756                         &data->dpm_table.vddc_table,
 757                                 smum_get_mac_definition(hwmgr,
 758                                         SMU_MAX_LEVELS_VDDC),
 759                                         MAX_REGULAR_DPM_NUMBER);
 760         phm_reset_single_dpm_table(
 761                         &data->dpm_table.vddci_table,
 762                         smum_get_mac_definition(hwmgr,
 763                                 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
 764
 765         phm_reset_single_dpm_table(
 766                         &data->dpm_table.mvdd_table,
 767                                 smum_get_mac_definition(hwmgr,
 768                                         SMU_MAX_LEVELS_MVDD),
 769                                         MAX_REGULAR_DPM_NUMBER);
 770         return 0;
 771 }
 772 /*
 773  * This function is to initialize all DPM state tables
 774  * for SMU7 based on the dependency table.
 775  * Dynamic state patching function will then trim these
 776  * state tables to the allowed range based
 777  * on the power policy or external client requests,
 778  * such as UVD request, etc.
 779  */
 780
 781 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
 782 {
 783         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 784         struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
 785                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 786         struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
 787                 hwmgr->dyn_state.vddc_dependency_on_mclk;
 788         struct phm_cac_leakage_table *std_voltage_table =
 789                 hwmgr->dyn_state.cac_leakage_table;
 790         uint32_t i;
 791
 792         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
 793                 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
 794         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
 795                 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 796
 797         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 798                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 799         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
 800                 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 801
 802
 803         /* Initialize Sclk DPM table based on allow Sclk values*/
 804         data->dpm_table.sclk_table.count = 0;
 805
 806         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 807                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
 808                                 allowed_vdd_sclk_table->entries[i].clk) {
 809                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 810                                 allowed_vdd_sclk_table->entries[i].clk;
 811                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
 812                         data->dpm_table.sclk_table.count++;
 813                 }
 814         }
 815
 816         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 817                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 818         /* Initialize Mclk DPM table based on allow Mclk values */
 819         data->dpm_table.mclk_table.count = 0;
 820         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 821                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
 822                         allowed_vdd_mclk_table->entries[i].clk) {
 823                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 824                                 allowed_vdd_mclk_table->entries[i].clk;
 825                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
 826                         data->dpm_table.mclk_table.count++;
 827                 }
 828         }
 829
 830         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
 831         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 832                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 833                 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
 834                 /* param1 is for corresponding std voltage */
 835                 data->dpm_table.vddc_table.dpm_levels[i].enabled = true;
 836         }
 837
 838         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
 839         allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
 840
 841         if (NULL != allowed_vdd_mclk_table) {
 842                 /* Initialize Vddci DPM table based on allow Mclk values */
 843                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 844                         data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 845                         data->dpm_table.vddci_table.dpm_levels[i].enabled = true;
 846                 }
 847                 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
 848         }
 849
 850         allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
 851
 852         if (NULL != allowed_vdd_mclk_table) {
 853                 /*
 854                  * Initialize MVDD DPM table based on allow Mclk
 855                  * values
 856                  */
 857                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 858                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 859                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
 860                 }
 861                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
 868 {
 869         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 870         struct phm_ppt_v1_information *table_info =
 871                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 872         uint32_t i;
 873
 874         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 875         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 876
 877         if (table_info == NULL)
 878                 return -EINVAL;
 879
 880         dep_sclk_table = table_info->vdd_dep_on_sclk;
 881         dep_mclk_table = table_info->vdd_dep_on_mclk;
 882
 883         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 884                         "SCLK dependency table is missing.",
 885                         return -EINVAL);
 886         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 887                         "SCLK dependency table count is 0.",
 888                         return -EINVAL);
 889
 890         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 891                         "MCLK dependency table is missing.",
 892                         return -EINVAL);
 893         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 894                         "MCLK dependency table count is 0",
 895                         return -EINVAL);
 896
 897         /* Initialize Sclk DPM table based on allow Sclk values */
 898         data->dpm_table.sclk_table.count = 0;
 899         for (i = 0; i < dep_sclk_table->count; i++) {
 900                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 901                                                 dep_sclk_table->entries[i].clk) {
 902
 903                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 904                                         dep_sclk_table->entries[i].clk;
 905
 906                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 907                                         (i == 0) ? true : false;
 908                         data->dpm_table.sclk_table.count++;
 909                 }
 910         }
 911         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
 912                 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
 913         /* Initialize Mclk DPM table based on allow Mclk values */
 914         data->dpm_table.mclk_table.count = 0;
 915         for (i = 0; i < dep_mclk_table->count; i++) {
 916                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 917                                 [data->dpm_table.mclk_table.count - 1].value !=
 918                                                 dep_mclk_table->entries[i].clk) {
 919                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 920                                                         dep_mclk_table->entries[i].clk;
 921                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 922                                                         (i == 0) ? true : false;
 923                         data->dpm_table.mclk_table.count++;
 924                 }
 925         }
 926
 927         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
 928                 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
 929         return 0;
 930 }
 931
 932 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 933 {
 934         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 935         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 936         struct phm_ppt_v1_information *table_info =
 937                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 938         uint32_t i;
 939
 940         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 941         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 942         struct phm_odn_performance_level *entries;
 943
 944         if (table_info == NULL)
 945                 return -EINVAL;
 946
 947         dep_sclk_table = table_info->vdd_dep_on_sclk;
 948         dep_mclk_table = table_info->vdd_dep_on_mclk;
 949
 950         odn_table->odn_core_clock_dpm_levels.num_of_pl =
 951                                                 data->golden_dpm_table.sclk_table.count;
 952         entries = odn_table->odn_core_clock_dpm_levels.entries;
 953         for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
 954                 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
 955                 entries[i].enabled = true;
 956                 entries[i].vddc = dep_sclk_table->entries[i].vddc;
 957         }
 958
 959         smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
 960                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
 961
 962         odn_table->odn_memory_clock_dpm_levels.num_of_pl =
 963                                                 data->golden_dpm_table.mclk_table.count;
 964         entries = odn_table->odn_memory_clock_dpm_levels.entries;
 965         for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
 966                 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
 967                 entries[i].enabled = true;
 968                 entries[i].vddc = dep_mclk_table->entries[i].vddc;
 969         }
 970
 971         smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
 972                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
 973
 974         return 0;
 975 }
 976
 977 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
 978 {
 979         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 980         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 981         struct phm_ppt_v1_information *table_info =
 982                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 983         uint32_t min_vddc = 0;
 984         uint32_t max_vddc = 0;
 985
 986         if (!table_info)
 987                 return;
 988
 989         dep_sclk_table = table_info->vdd_dep_on_sclk;
 990
 991         atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
 992
 993         if (min_vddc == 0 || min_vddc > 2000
 994                 || min_vddc > dep_sclk_table->entries[0].vddc)
 995                 min_vddc = dep_sclk_table->entries[0].vddc;
 996
 997         if (max_vddc == 0 || max_vddc > 2000
 998                 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
 999                 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
1000
1001         data->odn_dpm_table.min_vddc = min_vddc;
1002         data->odn_dpm_table.max_vddc = max_vddc;
1003 }
1004
1005 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
1006 {
1007         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1008         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
1009         struct phm_ppt_v1_information *table_info =
1010                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1011         uint32_t i;
1012
1013         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1014         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
1015
1016         if (table_info == NULL)
1017                 return;
1018
1019         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1020                 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
1021                                         data->dpm_table.sclk_table.dpm_levels[i].value) {
1022                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
1023                         break;
1024                 }
1025         }
1026
1027         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1028                 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
1029                                         data->dpm_table.mclk_table.dpm_levels[i].value) {
1030                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
1031                         break;
1032                 }
1033         }
1034
1035         dep_table = table_info->vdd_dep_on_mclk;
1036         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
1037
1038         for (i = 0; i < dep_table->count; i++) {
1039                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
1040                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
1041                         return;
1042                 }
1043         }
1044
1045         dep_table = table_info->vdd_dep_on_sclk;
1046         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
1047         for (i = 0; i < dep_table->count; i++) {
1048                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
1049                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
1050                         return;
1051                 }
1052         }
1053         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1054                 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
1055                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
1056         }
1057 }
1058
1059 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1060 {
1061         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1062
1063         smu7_reset_dpm_tables(hwmgr);
1064
1065         if (hwmgr->pp_table_version == PP_TABLE_V1)
1066                 smu7_setup_dpm_tables_v1(hwmgr);
1067         else if (hwmgr->pp_table_version == PP_TABLE_V0)
1068                 smu7_setup_dpm_tables_v0(hwmgr);
1069
1070         smu7_setup_default_pcie_table(hwmgr);
1071
1072         /* save a copy of the default DPM table */
1073         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1074                         sizeof(struct smu7_dpm_table));
1075
1076         /* initialize ODN table */
1077         if (hwmgr->od_enabled) {
1078                 if (data->odn_dpm_table.max_vddc) {
1079                         smu7_check_dpm_table_updated(hwmgr);
1080                 } else {
1081                         smu7_setup_voltage_range_from_vbios(hwmgr);
1082                         smu7_odn_initial_default_setting(hwmgr);
1083                 }
1084         }
1085         return 0;
1086 }
1087
1088 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
1089 {
1090
1091         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1092                         PHM_PlatformCaps_RegulatorHot))
1093                 return smum_send_msg_to_smc(hwmgr,
1094                                 PPSMC_MSG_EnableVRHotGPIOInterrupt,
1095                                 NULL);
1096
1097         return 0;
1098 }
1099
1100 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
1101 {
1102         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1103                         SCLK_PWRMGT_OFF, 0);
1104         return 0;
1105 }
1106
1107 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
1108 {
1109         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1110
1111         if (data->ulv_supported)
1112                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL);
1113
1114         return 0;
1115 }
1116
1117 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1118 {
1119         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1120
1121         if (data->ulv_supported)
1122                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL);
1123
1124         return 0;
1125 }
1126
1127 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1128 {
1129         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1130                         PHM_PlatformCaps_SclkDeepSleep)) {
1131                 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL))
1132                         PP_ASSERT_WITH_CODE(false,
1133                                         "Attempt to enable Master Deep Sleep switch failed!",
1134                                         return -EINVAL);
1135         } else {
1136                 if (smum_send_msg_to_smc(hwmgr,
1137                                 PPSMC_MSG_MASTER_DeepSleep_OFF,
1138                                 NULL)) {
1139                         PP_ASSERT_WITH_CODE(false,
1140                                         "Attempt to disable Master Deep Sleep switch failed!",
1141                                         return -EINVAL);
1142                 }
1143         }
1144
1145         return 0;
1146 }
1147
1148 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1149 {
1150         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1151                         PHM_PlatformCaps_SclkDeepSleep)) {
1152                 if (smum_send_msg_to_smc(hwmgr,
1153                                 PPSMC_MSG_MASTER_DeepSleep_OFF,
1154                                 NULL)) {
1155                         PP_ASSERT_WITH_CODE(false,
1156                                         "Attempt to disable Master Deep Sleep switch failed!",
1157                                         return -EINVAL);
1158                 }
1159         }
1160
1161         return 0;
1162 }
1163
1164 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1165 {
1166         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1167         uint32_t soft_register_value = 0;
1168         uint32_t handshake_disables_offset = data->soft_regs_start
1169                                 + smum_get_offsetof(hwmgr,
1170                                         SMU_SoftRegisters, HandshakeDisables);
1171
1172         soft_register_value = cgs_read_ind_register(hwmgr->device,
1173                                 CGS_IND_REG__SMC, handshake_disables_offset);
1174         soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1175         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1176                         handshake_disables_offset, soft_register_value);
1177         return 0;
1178 }
1179
1180 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1181 {
1182         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1183         uint32_t soft_register_value = 0;
1184         uint32_t handshake_disables_offset = data->soft_regs_start
1185                                 + smum_get_offsetof(hwmgr,
1186                                         SMU_SoftRegisters, HandshakeDisables);
1187
1188         soft_register_value = cgs_read_ind_register(hwmgr->device,
1189                                 CGS_IND_REG__SMC, handshake_disables_offset);
1190         soft_register_value |= smum_get_mac_definition(hwmgr,
1191                                         SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1192         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1193                         handshake_disables_offset, soft_register_value);
1194         return 0;
1195 }
1196
1197 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1198 {
1199         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1200
1201         /* enable SCLK dpm */
1202         if (!data->sclk_dpm_key_disabled) {
1203                 if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1204                     hwmgr->chip_id <= CHIP_VEGAM)
1205                         smu7_disable_sclk_vce_handshake(hwmgr);
1206
1207                 PP_ASSERT_WITH_CODE(
1208                 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)),
1209                 "Failed to enable SCLK DPM during DPM Start Function!",
1210                 return -EINVAL);
1211         }
1212
1213         /* enable MCLK dpm */
1214         if (0 == data->mclk_dpm_key_disabled) {
1215                 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1216                         smu7_disable_handshake_uvd(hwmgr);
1217
1218                 PP_ASSERT_WITH_CODE(
1219                                 (0 == smum_send_msg_to_smc(hwmgr,
1220                                                 PPSMC_MSG_MCLKDPM_Enable,
1221                                                 NULL)),
1222                                 "Failed to enable MCLK DPM during DPM Start Function!",
1223                                 return -EINVAL);
1224
1225                 if ((hwmgr->chip_family == AMDGPU_FAMILY_CI) ||
1226                     (hwmgr->chip_id == CHIP_POLARIS10) ||
1227                     (hwmgr->chip_id == CHIP_POLARIS11) ||
1228                     (hwmgr->chip_id == CHIP_POLARIS12) ||
1229                     (hwmgr->chip_id == CHIP_TONGA) ||
1230                     (hwmgr->chip_id == CHIP_TOPAZ))
1231                         PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1232
1233
1234                 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1235                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1236                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1237                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1238                         udelay(10);
1239                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1240                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1241                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1242                 } else {
1243                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1244                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1245                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1246                         udelay(10);
1247                         if (hwmgr->chip_id == CHIP_VEGAM) {
1248                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1249                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1250                         } else {
1251                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1252                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1253                         }
1254                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1255                 }
1256         }
1257
1258         return 0;
1259 }
1260
1261 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1262 {
1263         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1264
1265         /*enable general power management */
1266
1267         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1268                         GLOBAL_PWRMGT_EN, 1);
1269
1270         /* enable sclk deep sleep */
1271
1272         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1273                         DYNAMIC_PM_EN, 1);
1274
1275         /* prepare for PCIE DPM */
1276
1277         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1278                         data->soft_regs_start +
1279                         smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1280                                                 VoltageChangeTimeout), 0x1000);
1281         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1282                         SWRST_COMMAND_1, RESETLC, 0x0);
1283
1284         if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1285                 cgs_write_register(hwmgr->device, 0x1488,
1286                         (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1287
1288         if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1289                 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1290                 return -EINVAL;
1291         }
1292
1293         /* enable PCIE dpm */
1294         if (0 == data->pcie_dpm_key_disabled) {
1295                 PP_ASSERT_WITH_CODE(
1296                                 (0 == smum_send_msg_to_smc(hwmgr,
1297                                                 PPSMC_MSG_PCIeDPM_Enable,
1298                                                 NULL)),
1299                                 "Failed to enable pcie DPM during DPM Start Function!",
1300                                 return -EINVAL);
1301         } else {
1302                 PP_ASSERT_WITH_CODE(
1303                                 (0 == smum_send_msg_to_smc(hwmgr,
1304                                                 PPSMC_MSG_PCIeDPM_Disable,
1305                                                 NULL)),
1306                                 "Failed to disable pcie DPM during DPM Start Function!",
1307                                 return -EINVAL);
1308         }
1309
1310         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1311                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
1312                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1313                                 PPSMC_MSG_EnableACDCGPIOInterrupt,
1314                                 NULL)),
1315                                 "Failed to enable AC DC GPIO Interrupt!",
1316                                 );
1317         }
1318
1319         return 0;
1320 }
1321
1322 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1323 {
1324         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1325
1326         /* disable SCLK dpm */
1327         if (!data->sclk_dpm_key_disabled) {
1328                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1329                                 "Trying to disable SCLK DPM when DPM is disabled",
1330                                 return 0);
1331                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL);
1332         }
1333
1334         /* disable MCLK dpm */
1335         if (!data->mclk_dpm_key_disabled) {
1336                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1337                                 "Trying to disable MCLK DPM when DPM is disabled",
1338                                 return 0);
1339                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL);
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1346 {
1347         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1348
1349         /* disable general power management */
1350         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1351                         GLOBAL_PWRMGT_EN, 0);
1352         /* disable sclk deep sleep */
1353         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1354                         DYNAMIC_PM_EN, 0);
1355
1356         /* disable PCIE dpm */
1357         if (!data->pcie_dpm_key_disabled) {
1358                 PP_ASSERT_WITH_CODE(
1359                                 (smum_send_msg_to_smc(hwmgr,
1360                                                 PPSMC_MSG_PCIeDPM_Disable,
1361                                                 NULL) == 0),
1362                                 "Failed to disable pcie DPM during DPM Stop Function!",
1363                                 return -EINVAL);
1364         }
1365
1366         smu7_disable_sclk_mclk_dpm(hwmgr);
1367
1368         PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1369                         "Trying to disable voltage DPM when DPM is disabled",
1370                         return 0);
1371
1372         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL);
1373
1374         return 0;
1375 }
1376
1377 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1378 {
1379         bool protection;
1380         enum DPM_EVENT_SRC src;
1381
1382         switch (sources) {
1383         default:
1384                 pr_err("Unknown throttling event sources.");
1385                 fallthrough;
1386         case 0:
1387                 protection = false;
1388                 /* src is unused */
1389                 break;
1390         case (1 << PHM_AutoThrottleSource_Thermal):
1391                 protection = true;
1392                 src = DPM_EVENT_SRC_DIGITAL;
1393                 break;
1394         case (1 << PHM_AutoThrottleSource_External):
1395                 protection = true;
1396                 src = DPM_EVENT_SRC_EXTERNAL;
1397                 break;
1398         case (1 << PHM_AutoThrottleSource_External) |
1399                         (1 << PHM_AutoThrottleSource_Thermal):
1400                 protection = true;
1401                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1402                 break;
1403         }
1404         /* Order matters - don't enable thermal protection for the wrong source. */
1405         if (protection) {
1406                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1407                                 DPM_EVENT_SRC, src);
1408                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1409                                 THERMAL_PROTECTION_DIS,
1410                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1411                                                 PHM_PlatformCaps_ThermalController));
1412         } else
1413                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1414                                 THERMAL_PROTECTION_DIS, 1);
1415 }
1416
1417 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1418                 PHM_AutoThrottleSource source)
1419 {
1420         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1421
1422         if (!(data->active_auto_throttle_sources & (1 << source))) {
1423                 data->active_auto_throttle_sources |= 1 << source;
1424                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1425         }
1426         return 0;
1427 }
1428
1429 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1430 {
1431         return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1432 }
1433
1434 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1435                 PHM_AutoThrottleSource source)
1436 {
1437         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1438
1439         if (data->active_auto_throttle_sources & (1 << source)) {
1440                 data->active_auto_throttle_sources &= ~(1 << source);
1441                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1442         }
1443         return 0;
1444 }
1445
1446 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1447 {
1448         return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1449 }
1450
1451 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1452 {
1453         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1454         data->pcie_performance_request = true;
1455
1456         return 0;
1457 }
1458
1459 static int smu7_program_edc_didt_registers(struct pp_hwmgr *hwmgr,
1460                                            uint32_t *cac_config_regs,
1461                                            AtomCtrl_EDCLeakgeTable *edc_leakage_table)
1462 {
1463         uint32_t data, i = 0;
1464
1465         while (cac_config_regs[i] != 0xFFFFFFFF) {
1466                 data = edc_leakage_table->DIDT_REG[i];
1467                 cgs_write_ind_register(hwmgr->device,
1468                                        CGS_IND_REG__DIDT,
1469                                        cac_config_regs[i],
1470                                        data);
1471                 i++;
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr)
1478 {
1479         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1480         int ret = 0;
1481
1482         if (!data->disable_edc_leakage_controller &&
1483             data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset &&
1484             data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) {
1485                 ret = smu7_program_edc_didt_registers(hwmgr,
1486                                                       DIDTEDCConfig_P12,
1487                                                       &data->edc_leakage_table);
1488                 if (ret)
1489                         return ret;
1490
1491                 ret = smum_send_msg_to_smc(hwmgr,
1492                                            (PPSMC_Msg)PPSMC_MSG_EnableEDCController,
1493                                            NULL);
1494         } else {
1495                 ret = smum_send_msg_to_smc(hwmgr,
1496                                            (PPSMC_Msg)PPSMC_MSG_DisableEDCController,
1497                                            NULL);
1498         }
1499
1500         return ret;
1501 }
1502
1503 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1504 {
1505         int tmp_result = 0;
1506         int result = 0;
1507
1508         if (smu7_voltage_control(hwmgr)) {
1509                 tmp_result = smu7_enable_voltage_control(hwmgr);
1510                 PP_ASSERT_WITH_CODE(tmp_result == 0,
1511                                 "Failed to enable voltage control!",
1512                                 result = tmp_result);
1513
1514                 tmp_result = smu7_construct_voltage_tables(hwmgr);
1515                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1516                                 "Failed to construct voltage tables!",
1517                                 result = tmp_result);
1518         }
1519         smum_initialize_mc_reg_table(hwmgr);
1520
1521         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1522                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1523                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1524                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1525
1526         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1527                         PHM_PlatformCaps_ThermalController))
1528                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1529                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1530
1531         tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1532         PP_ASSERT_WITH_CODE((0 == tmp_result),
1533                         "Failed to program static screen threshold parameters!",
1534                         result = tmp_result);
1535
1536         tmp_result = smu7_enable_display_gap(hwmgr);
1537         PP_ASSERT_WITH_CODE((0 == tmp_result),
1538                         "Failed to enable display gap!", result = tmp_result);
1539
1540         tmp_result = smu7_program_voting_clients(hwmgr);
1541         PP_ASSERT_WITH_CODE((0 == tmp_result),
1542                         "Failed to program voting clients!", result = tmp_result);
1543
1544         tmp_result = smum_process_firmware_header(hwmgr);
1545         PP_ASSERT_WITH_CODE((0 == tmp_result),
1546                         "Failed to process firmware header!", result = tmp_result);
1547
1548         if (hwmgr->chip_id != CHIP_VEGAM) {
1549                 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1550                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1551                                 "Failed to initialize switch from ArbF0 to F1!",
1552                                 result = tmp_result);
1553         }
1554
1555         result = smu7_setup_default_dpm_tables(hwmgr);
1556         PP_ASSERT_WITH_CODE(0 == result,
1557                         "Failed to setup default DPM tables!", return result);
1558
1559         tmp_result = smum_init_smc_table(hwmgr);
1560         PP_ASSERT_WITH_CODE((0 == tmp_result),
1561                         "Failed to initialize SMC table!", result = tmp_result);
1562
1563         tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1564         PP_ASSERT_WITH_CODE((0 == tmp_result),
1565                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1566
1567         if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1568             hwmgr->chip_id <= CHIP_VEGAM) {
1569                 tmp_result = smu7_notify_has_display(hwmgr);
1570                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1571                                 "Failed to enable display setting!", result = tmp_result);
1572         } else {
1573                 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL);
1574         }
1575
1576         if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1577             hwmgr->chip_id <= CHIP_VEGAM) {
1578                 tmp_result = smu7_populate_edc_leakage_registers(hwmgr);
1579                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1580                                 "Failed to populate edc leakage registers!", result = tmp_result);
1581         }
1582
1583         tmp_result = smu7_enable_sclk_control(hwmgr);
1584         PP_ASSERT_WITH_CODE((0 == tmp_result),
1585                         "Failed to enable SCLK control!", result = tmp_result);
1586
1587         tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1588         PP_ASSERT_WITH_CODE((0 == tmp_result),
1589                         "Failed to enable voltage control!", result = tmp_result);
1590
1591         tmp_result = smu7_enable_ulv(hwmgr);
1592         PP_ASSERT_WITH_CODE((0 == tmp_result),
1593                         "Failed to enable ULV!", result = tmp_result);
1594
1595         tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1596         PP_ASSERT_WITH_CODE((0 == tmp_result),
1597                         "Failed to enable deep sleep master switch!", result = tmp_result);
1598
1599         tmp_result = smu7_enable_didt_config(hwmgr);
1600         PP_ASSERT_WITH_CODE((tmp_result == 0),
1601                         "Failed to enable deep sleep master switch!", result = tmp_result);
1602
1603         tmp_result = smu7_start_dpm(hwmgr);
1604         PP_ASSERT_WITH_CODE((0 == tmp_result),
1605                         "Failed to start DPM!", result = tmp_result);
1606
1607         tmp_result = smu7_enable_smc_cac(hwmgr);
1608         PP_ASSERT_WITH_CODE((0 == tmp_result),
1609                         "Failed to enable SMC CAC!", result = tmp_result);
1610
1611         tmp_result = smu7_enable_power_containment(hwmgr);
1612         PP_ASSERT_WITH_CODE((0 == tmp_result),
1613                         "Failed to enable power containment!", result = tmp_result);
1614
1615         tmp_result = smu7_power_control_set_level(hwmgr);
1616         PP_ASSERT_WITH_CODE((0 == tmp_result),
1617                         "Failed to power control set level!", result = tmp_result);
1618
1619         tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1620         PP_ASSERT_WITH_CODE((0 == tmp_result),
1621                         "Failed to enable thermal auto throttle!", result = tmp_result);
1622
1623         tmp_result = smu7_pcie_performance_request(hwmgr);
1624         PP_ASSERT_WITH_CODE((0 == tmp_result),
1625                         "pcie performance request failed!", result = tmp_result);
1626
1627         return 0;
1628 }
1629
1630 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1631 {
1632         if (!hwmgr->avfs_supported)
1633                 return 0;
1634
1635         if (enable) {
1636                 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1637                                 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1638                         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1639                                         hwmgr, PPSMC_MSG_EnableAvfs, NULL),
1640                                         "Failed to enable AVFS!",
1641                                         return -EINVAL);
1642                 }
1643         } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1644                         CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1645                 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1646                                 hwmgr, PPSMC_MSG_DisableAvfs, NULL),
1647                                 "Failed to disable AVFS!",
1648                                 return -EINVAL);
1649         }
1650
1651         return 0;
1652 }
1653
1654 static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1655 {
1656         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1657
1658         if (!hwmgr->avfs_supported)
1659                 return 0;
1660
1661         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1662                 smu7_avfs_control(hwmgr, false);
1663         } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1664                 smu7_avfs_control(hwmgr, false);
1665                 smu7_avfs_control(hwmgr, true);
1666         } else {
1667                 smu7_avfs_control(hwmgr, true);
1668         }
1669
1670         return 0;
1671 }
1672
1673 static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1674 {
1675         int tmp_result, result = 0;
1676
1677         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1678                         PHM_PlatformCaps_ThermalController))
1679                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1680                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1681
1682         tmp_result = smu7_disable_power_containment(hwmgr);
1683         PP_ASSERT_WITH_CODE((tmp_result == 0),
1684                         "Failed to disable power containment!", result = tmp_result);
1685
1686         tmp_result = smu7_disable_smc_cac(hwmgr);
1687         PP_ASSERT_WITH_CODE((tmp_result == 0),
1688                         "Failed to disable SMC CAC!", result = tmp_result);
1689
1690         tmp_result = smu7_disable_didt_config(hwmgr);
1691         PP_ASSERT_WITH_CODE((tmp_result == 0),
1692                         "Failed to disable DIDT!", result = tmp_result);
1693
1694         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1695                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1696         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1697                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1698
1699         tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1700         PP_ASSERT_WITH_CODE((tmp_result == 0),
1701                         "Failed to disable thermal auto throttle!", result = tmp_result);
1702
1703         tmp_result = smu7_avfs_control(hwmgr, false);
1704         PP_ASSERT_WITH_CODE((tmp_result == 0),
1705                         "Failed to disable AVFS!", result = tmp_result);
1706
1707         tmp_result = smu7_stop_dpm(hwmgr);
1708         PP_ASSERT_WITH_CODE((tmp_result == 0),
1709                         "Failed to stop DPM!", result = tmp_result);
1710
1711         tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1712         PP_ASSERT_WITH_CODE((tmp_result == 0),
1713                         "Failed to disable deep sleep master switch!", result = tmp_result);
1714
1715         tmp_result = smu7_disable_ulv(hwmgr);
1716         PP_ASSERT_WITH_CODE((tmp_result == 0),
1717                         "Failed to disable ULV!", result = tmp_result);
1718
1719         tmp_result = smu7_clear_voting_clients(hwmgr);
1720         PP_ASSERT_WITH_CODE((tmp_result == 0),
1721                         "Failed to clear voting clients!", result = tmp_result);
1722
1723         tmp_result = smu7_reset_to_default(hwmgr);
1724         PP_ASSERT_WITH_CODE((tmp_result == 0),
1725                         "Failed to reset to default!", result = tmp_result);
1726
1727         tmp_result = smum_stop_smc(hwmgr);
1728         PP_ASSERT_WITH_CODE((tmp_result == 0),
1729                         "Failed to stop smc!", result = tmp_result);
1730
1731         tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1732         PP_ASSERT_WITH_CODE((tmp_result == 0),
1733                         "Failed to force to switch arbf0!", result = tmp_result);
1734
1735         return result;
1736 }
1737
1738 static bool intel_core_rkl_chk(void)
1739 {
1740 #if IS_ENABLED(CONFIG_X86_64)
1741         struct cpuinfo_x86 *c = &cpu_data(0);
1742
1743         return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE);
1744 #else
1745         return false;
1746 #endif
1747 }
1748
1749 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1750 {
1751         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1752         struct phm_ppt_v1_information *table_info =
1753                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1754         struct amdgpu_device *adev = hwmgr->adev;
1755         uint8_t tmp1, tmp2;
1756         uint16_t tmp3 = 0;
1757
1758         data->dll_default_on = false;
1759         data->mclk_dpm0_activity_target = 0xa;
1760         data->vddc_vddgfx_delta = 300;
1761         data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1762         data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1763         data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1764         data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1765         data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1766         data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1767         data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1768         data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1769         data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1770         data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1771
1772         data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1773         data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1774         data->pcie_dpm_key_disabled =
1775                 intel_core_rkl_chk() || !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
1776         /* need to set voltage control types before EVV patching */
1777         data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1778         data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1779         data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1780         data->enable_tdc_limit_feature = true;
1781         data->enable_pkg_pwr_tracking_feature = true;
1782         data->force_pcie_gen = PP_PCIEGenInvalid;
1783         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1784         data->current_profile_setting.bupdate_sclk = 1;
1785         data->current_profile_setting.sclk_up_hyst = 0;
1786         data->current_profile_setting.sclk_down_hyst = 100;
1787         data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1788         data->current_profile_setting.bupdate_mclk = 1;
1789         if (hwmgr->chip_id >= CHIP_POLARIS10) {
1790                 if (adev->gmc.vram_width == 256) {
1791                         data->current_profile_setting.mclk_up_hyst = 10;
1792                         data->current_profile_setting.mclk_down_hyst = 60;
1793                         data->current_profile_setting.mclk_activity = 25;
1794                 } else if (adev->gmc.vram_width == 128) {
1795                         data->current_profile_setting.mclk_up_hyst = 5;
1796                         data->current_profile_setting.mclk_down_hyst = 16;
1797                         data->current_profile_setting.mclk_activity = 20;
1798                 } else if (adev->gmc.vram_width == 64) {
1799                         data->current_profile_setting.mclk_up_hyst = 3;
1800                         data->current_profile_setting.mclk_down_hyst = 16;
1801                         data->current_profile_setting.mclk_activity = 20;
1802                 }
1803         } else {
1804                 data->current_profile_setting.mclk_up_hyst = 0;
1805                 data->current_profile_setting.mclk_down_hyst = 100;
1806                 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1807         }
1808         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1809         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1810         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1811
1812         if (hwmgr->chip_id  == CHIP_HAWAII) {
1813                 data->thermal_temp_setting.temperature_low = 94500;
1814                 data->thermal_temp_setting.temperature_high = 95000;
1815                 data->thermal_temp_setting.temperature_shutdown = 104000;
1816         } else {
1817                 data->thermal_temp_setting.temperature_low = 99500;
1818                 data->thermal_temp_setting.temperature_high = 100000;
1819                 data->thermal_temp_setting.temperature_shutdown = 104000;
1820         }
1821
1822         data->fast_watermark_threshold = 100;
1823         if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1824                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1825                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1826         else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1827                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1828                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1829
1830         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1831                         PHM_PlatformCaps_ControlVDDGFX)) {
1832                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1833                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1834                         data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1835                 }
1836         }
1837
1838         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1839                         PHM_PlatformCaps_EnableMVDDControl)) {
1840                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1841                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1842                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1843                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1844                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1845                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1846         }
1847
1848         if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1849                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1850                         PHM_PlatformCaps_ControlVDDGFX);
1851
1852         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1853                         PHM_PlatformCaps_ControlVDDCI)) {
1854                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1855                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1856                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1857                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1858                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1859                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1860         }
1861
1862         if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1863                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1864                                 PHM_PlatformCaps_EnableMVDDControl);
1865
1866         if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1867                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1868                                 PHM_PlatformCaps_ControlVDDCI);
1869
1870         data->vddc_phase_shed_control = 1;
1871         if ((hwmgr->chip_id == CHIP_POLARIS12) ||
1872             ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1873             ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
1874             ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
1875             ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
1876                 if (data->voltage_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1877                         atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1878                                                         &tmp3);
1879                         tmp3 = (tmp3 >> 5) & 0x3;
1880                         data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1881                 }
1882         } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1883                 data->vddc_phase_shed_control = 1;
1884         }
1885
1886         if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1887                 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1888                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1889                                         PHM_PlatformCaps_ClockStretcher);
1890
1891         data->pcie_gen_performance.max = PP_PCIEGen1;
1892         data->pcie_gen_performance.min = PP_PCIEGen3;
1893         data->pcie_gen_power_saving.max = PP_PCIEGen1;
1894         data->pcie_gen_power_saving.min = PP_PCIEGen3;
1895         data->pcie_lane_performance.max = 0;
1896         data->pcie_lane_performance.min = 16;
1897         data->pcie_lane_power_saving.max = 0;
1898         data->pcie_lane_power_saving.min = 16;
1899
1900
1901         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1902                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1903                               PHM_PlatformCaps_UVDPowerGating);
1904         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1905                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1906                               PHM_PlatformCaps_VCEPowerGating);
1907
1908         data->disable_edc_leakage_controller = true;
1909         if (((adev->asic_type == CHIP_POLARIS10) && hwmgr->is_kicker) ||
1910             ((adev->asic_type == CHIP_POLARIS11) && hwmgr->is_kicker) ||
1911             (adev->asic_type == CHIP_POLARIS12) ||
1912             (adev->asic_type == CHIP_VEGAM))
1913                 data->disable_edc_leakage_controller = false;
1914
1915         if (!atomctrl_is_asic_internal_ss_supported(hwmgr)) {
1916                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1917                         PHM_PlatformCaps_MemorySpreadSpectrumSupport);
1918                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1919                         PHM_PlatformCaps_EngineSpreadSpectrumSupport);
1920         }
1921
1922         if ((adev->pdev->device == 0x699F) &&
1923             (adev->pdev->revision == 0xCF)) {
1924                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1925                                 PHM_PlatformCaps_PowerContainment);
1926                 data->enable_tdc_limit_feature = false;
1927                 data->enable_pkg_pwr_tracking_feature = false;
1928                 data->disable_edc_leakage_controller = true;
1929                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1930                                         PHM_PlatformCaps_ClockStretcher);
1931         }
1932 }
1933
1934 static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)
1935 {
1936         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1937         struct amdgpu_device *adev = hwmgr->adev;
1938         uint32_t asicrev1, evv_revision, max = 0, min = 0;
1939
1940         atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB, STRAP_EVV_REVISION_MSB,
1941                         &evv_revision);
1942
1943         atomctrl_read_efuse(hwmgr, 568, 579, &asicrev1);
1944
1945         if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1946             ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) {
1947                 min = 1200;
1948                 max = 2500;
1949         } else if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
1950                    ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
1951                 min = 900;
1952                 max= 2100;
1953         } else if (hwmgr->chip_id == CHIP_POLARIS10) {
1954                 if (adev->pdev->subsystem_vendor == 0x106B) {
1955                         min = 1000;
1956                         max = 2300;
1957                 } else {
1958                         if (evv_revision == 0) {
1959                                 min = 1000;
1960                                 max = 2300;
1961                         } else if (evv_revision == 1) {
1962                                 if (asicrev1 == 326) {
1963                                         min = 1200;
1964                                         max = 2500;
1965                                         /* TODO: PATCH RO in VBIOS */
1966                                 } else {
1967                                         min = 1200;
1968                                         max = 2000;
1969                                 }
1970                         } else if (evv_revision == 2) {
1971                                 min = 1200;
1972                                 max = 2500;
1973                         }
1974                 }
1975         } else {
1976                 min = 1100;
1977                 max = 2100;
1978         }
1979
1980         data->ro_range_minimum = min;
1981         data->ro_range_maximum = max;
1982
1983         /* TODO: PATCH RO in VBIOS here */
1984
1985         return 0;
1986 }
1987
1988 /**
1989  * smu7_get_evv_voltages - Get Leakage VDDC based on leakage ID.
1990  *
1991  * @hwmgr:  the address of the powerplay hardware manager.
1992  * Return:   always 0
1993  */
1994 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1995 {
1996         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1997         uint16_t vv_id;
1998         uint16_t vddc = 0;
1999         uint16_t vddgfx = 0;
2000         uint16_t i, j;
2001         uint32_t sclk = 0;
2002         struct phm_ppt_v1_information *table_info =
2003                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2004         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
2005
2006         if (hwmgr->chip_id == CHIP_POLARIS10 ||
2007             hwmgr->chip_id == CHIP_POLARIS11 ||
2008             hwmgr->chip_id == CHIP_POLARIS12)
2009                 smu7_calculate_ro_range(hwmgr);
2010
2011         for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2012                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2013
2014                 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2015                         if ((hwmgr->pp_table_version == PP_TABLE_V1)
2016                             && !phm_get_sclk_for_voltage_evv(hwmgr,
2017                                                 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
2018                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2019                                                         PHM_PlatformCaps_ClockStretcher)) {
2020                                         sclk_table = table_info->vdd_dep_on_sclk;
2021
2022                                         for (j = 1; j < sclk_table->count; j++) {
2023                                                 if (sclk_table->entries[j].clk == sclk &&
2024                                                                 sclk_table->entries[j].cks_enable == 0) {
2025                                                         sclk += 5000;
2026                                                         break;
2027                                                 }
2028                                         }
2029                                 }
2030                                 if (0 == atomctrl_get_voltage_evv_on_sclk
2031                                     (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
2032                                      vv_id, &vddgfx)) {
2033                                         /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
2034                                         PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
2035
2036                                         /* the voltage should not be zero nor equal to leakage ID */
2037                                         if (vddgfx != 0 && vddgfx != vv_id) {
2038                                                 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
2039                                                 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
2040                                                 data->vddcgfx_leakage.count++;
2041                                         }
2042                                 } else {
2043                                         pr_info("Error retrieving EVV voltage value!\n");
2044                                 }
2045                         }
2046                 } else {
2047                         if ((hwmgr->pp_table_version == PP_TABLE_V0)
2048                                 || !phm_get_sclk_for_voltage_evv(hwmgr,
2049                                         table_info->vddc_lookup_table, vv_id, &sclk)) {
2050                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2051                                                 PHM_PlatformCaps_ClockStretcher)) {
2052                                         if (table_info == NULL)
2053                                                 return -EINVAL;
2054                                         sclk_table = table_info->vdd_dep_on_sclk;
2055
2056                                         for (j = 1; j < sclk_table->count; j++) {
2057                                                 if (sclk_table->entries[j].clk == sclk &&
2058                                                                 sclk_table->entries[j].cks_enable == 0) {
2059                                                         sclk += 5000;
2060                                                         break;
2061                                                 }
2062                                         }
2063                                 }
2064
2065                                 if (phm_get_voltage_evv_on_sclk(hwmgr,
2066                                                         VOLTAGE_TYPE_VDDC,
2067                                                         sclk, vv_id, &vddc) == 0) {
2068                                         if (vddc >= 2000 || vddc == 0)
2069                                                 return -EINVAL;
2070                                 } else {
2071                                         pr_debug("failed to retrieving EVV voltage!\n");
2072                                         continue;
2073                                 }
2074
2075                                 /* the voltage should not be zero nor equal to leakage ID */
2076                                 if (vddc != 0 && vddc != vv_id) {
2077                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
2078                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2079                                         data->vddc_leakage.count++;
2080                                 }
2081                         }
2082                 }
2083         }
2084
2085         return 0;
2086 }
2087
2088 /**
2089  * smu7_patch_ppt_v1_with_vdd_leakage - Change virtual leakage voltage to actual value.
2090  *
2091  * @hwmgr:  the address of the powerplay hardware manager.
2092  * @voltage: pointer to changing voltage
2093  * @leakage_table: pointer to leakage table
2094  */
2095 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2096                 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
2097 {
2098         uint32_t index;
2099
2100         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2101         for (index = 0; index < leakage_table->count; index++) {
2102                 /* if this voltage matches a leakage voltage ID */
2103                 /* patch with actual leakage voltage */
2104                 if (leakage_table->leakage_id[index] == *voltage) {
2105                         *voltage = leakage_table->actual_voltage[index];
2106                         break;
2107                 }
2108         }
2109
2110         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2111                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
2112 }
2113
2114 /**
2115  * smu7_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages.
2116  *
2117  * @hwmgr:  the address of the powerplay hardware manager.
2118  * @lookup_table: pointer to voltage lookup table
2119  * @leakage_table: pointer to leakage table
2120  * Return:     always 0
2121  */
2122 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2123                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2124                 struct smu7_leakage_voltage *leakage_table)
2125 {
2126         uint32_t i;
2127
2128         for (i = 0; i < lookup_table->count; i++)
2129                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2130                                 &lookup_table->entries[i].us_vdd, leakage_table);
2131
2132         return 0;
2133 }
2134
2135 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
2136                 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
2137                 uint16_t *vddc)
2138 {
2139         struct phm_ppt_v1_information *table_info =
2140                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2141         smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2142         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2143                         table_info->max_clock_voltage_on_dc.vddc;
2144         return 0;
2145 }
2146
2147 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
2148                 struct pp_hwmgr *hwmgr)
2149 {
2150         uint8_t entry_id;
2151         uint8_t voltage_id;
2152         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2153         struct phm_ppt_v1_information *table_info =
2154                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2155
2156         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2157                         table_info->vdd_dep_on_sclk;
2158         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2159                         table_info->vdd_dep_on_mclk;
2160         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2161                         table_info->mm_dep_table;
2162
2163         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2164                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2165                         voltage_id = sclk_table->entries[entry_id].vddInd;
2166                         sclk_table->entries[entry_id].vddgfx =
2167                                 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
2168                 }
2169         } else {
2170                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2171                         voltage_id = sclk_table->entries[entry_id].vddInd;
2172                         sclk_table->entries[entry_id].vddc =
2173                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2174                 }
2175         }
2176
2177         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
2178                 voltage_id = mclk_table->entries[entry_id].vddInd;
2179                 mclk_table->entries[entry_id].vddc =
2180                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2181         }
2182
2183         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
2184                 voltage_id = mm_table->entries[entry_id].vddcInd;
2185                 mm_table->entries[entry_id].vddc =
2186                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2187         }
2188
2189         return 0;
2190
2191 }
2192
2193 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
2194                         phm_ppt_v1_voltage_lookup_table *look_up_table,
2195                         phm_ppt_v1_voltage_lookup_record *record)
2196 {
2197         uint32_t i;
2198
2199         PP_ASSERT_WITH_CODE((NULL != look_up_table),
2200                 "Lookup Table empty.", return -EINVAL);
2201         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
2202                 "Lookup Table empty.", return -EINVAL);
2203
2204         i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
2205         PP_ASSERT_WITH_CODE((i >= look_up_table->count),
2206                 "Lookup Table is full.", return -EINVAL);
2207
2208         /* This is to avoid entering duplicate calculated records. */
2209         for (i = 0; i < look_up_table->count; i++) {
2210                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
2211                         if (look_up_table->entries[i].us_calculated == 1)
2212                                 return 0;
2213                         break;
2214                 }
2215         }
2216
2217         look_up_table->entries[i].us_calculated = 1;
2218         look_up_table->entries[i].us_vdd = record->us_vdd;
2219         look_up_table->entries[i].us_cac_low = record->us_cac_low;
2220         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
2221         look_up_table->entries[i].us_cac_high = record->us_cac_high;
2222         /* Only increment the count when we're appending, not replacing duplicate entry. */
2223         if (i == look_up_table->count)
2224                 look_up_table->count++;
2225
2226         return 0;
2227 }
2228
2229
2230 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2231 {
2232         uint8_t entry_id;
2233         struct phm_ppt_v1_voltage_lookup_record v_record;
2234         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2235         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2236
2237         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
2238         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
2239
2240         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2241                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2242                         if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
2243                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
2244                                         sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
2245                         else
2246                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
2247                                         sclk_table->entries[entry_id].vdd_offset;
2248
2249                         sclk_table->entries[entry_id].vddc =
2250                                 v_record.us_cac_low = v_record.us_cac_mid =
2251                                 v_record.us_cac_high = v_record.us_vdd;
2252
2253                         phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
2254                 }
2255
2256                 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
2257                         if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
2258                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
2259                                         mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
2260                         else
2261                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
2262                                         mclk_table->entries[entry_id].vdd_offset;
2263
2264                         mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
2265                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
2266                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
2267                 }
2268         }
2269         return 0;
2270 }
2271
2272 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2273 {
2274         uint8_t entry_id;
2275         struct phm_ppt_v1_voltage_lookup_record v_record;
2276         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2277         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2278         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
2279
2280         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2281                 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
2282                         if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
2283                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
2284                                         mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
2285                         else
2286                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
2287                                         mm_table->entries[entry_id].vddgfx_offset;
2288
2289                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
2290                         mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
2291                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
2292                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
2293                 }
2294         }
2295         return 0;
2296 }
2297
2298 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
2299                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2300 {
2301         uint32_t table_size, i, j;
2302         table_size = lookup_table->count;
2303
2304         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2305                 "Lookup table is empty", return -EINVAL);
2306
2307         /* Sorting voltages */
2308         for (i = 0; i < table_size - 1; i++) {
2309                 for (j = i + 1; j > 0; j--) {
2310                         if (lookup_table->entries[j].us_vdd <
2311                                         lookup_table->entries[j - 1].us_vdd) {
2312                                 swap(lookup_table->entries[j - 1],
2313                                      lookup_table->entries[j]);
2314                         }
2315                 }
2316         }
2317
2318         return 0;
2319 }
2320
2321 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2322 {
2323         int result = 0;
2324         int tmp_result;
2325         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2326         struct phm_ppt_v1_information *table_info =
2327                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2328
2329         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2330                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2331                         table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
2332                 if (tmp_result != 0)
2333                         result = tmp_result;
2334
2335                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2336                         &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
2337         } else {
2338
2339                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2340                                 table_info->vddc_lookup_table, &(data->vddc_leakage));
2341                 if (tmp_result)
2342                         result = tmp_result;
2343
2344                 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2345                                 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2346                 if (tmp_result)
2347                         result = tmp_result;
2348         }
2349
2350         tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2351         if (tmp_result)
2352                 result = tmp_result;
2353
2354         tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2355         if (tmp_result)
2356                 result = tmp_result;
2357
2358         tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2359         if (tmp_result)
2360                 result = tmp_result;
2361
2362         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
2363         if (tmp_result)
2364                 result = tmp_result;
2365
2366         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2367         if (tmp_result)
2368                 result = tmp_result;
2369
2370         return result;
2371 }
2372
2373 static int smu7_find_highest_vddc(struct pp_hwmgr *hwmgr)
2374 {
2375         struct phm_ppt_v1_information *table_info =
2376                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2377         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2378                                                 table_info->vdd_dep_on_sclk;
2379         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
2380                                                 table_info->vddc_lookup_table;
2381         uint16_t highest_voltage;
2382         uint32_t i;
2383
2384         highest_voltage = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2385
2386         for (i = 0; i < lookup_table->count; i++) {
2387                 if (lookup_table->entries[i].us_vdd < ATOM_VIRTUAL_VOLTAGE_ID0 &&
2388                     lookup_table->entries[i].us_vdd > highest_voltage)
2389                         highest_voltage = lookup_table->entries[i].us_vdd;
2390         }
2391
2392         return highest_voltage;
2393 }
2394
2395 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2396 {
2397         struct phm_ppt_v1_information *table_info =
2398                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2399
2400         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2401                                                 table_info->vdd_dep_on_sclk;
2402         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2403                                                 table_info->vdd_dep_on_mclk;
2404
2405         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2406                 "VDD dependency on SCLK table is missing.",
2407                 return -EINVAL);
2408         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2409                 "VDD dependency on SCLK table has to have is missing.",
2410                 return -EINVAL);
2411
2412         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2413                 "VDD dependency on MCLK table is missing",
2414                 return -EINVAL);
2415         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2416                 "VDD dependency on MCLK table has to have is missing.",
2417                 return -EINVAL);
2418
2419         table_info->max_clock_voltage_on_ac.sclk =
2420                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2421         table_info->max_clock_voltage_on_ac.mclk =
2422                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2423         if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM)
2424                 table_info->max_clock_voltage_on_ac.vddc =
2425                         smu7_find_highest_vddc(hwmgr);
2426         else
2427                 table_info->max_clock_voltage_on_ac.vddc =
2428                         allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2429         table_info->max_clock_voltage_on_ac.vddci =
2430                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2431
2432         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2433         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2434         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2435         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2436
2437         return 0;
2438 }
2439
2440 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2441 {
2442         struct phm_ppt_v1_information *table_info =
2443                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
2444         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2445         struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2446         uint32_t i;
2447         uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2448         struct amdgpu_device *adev = hwmgr->adev;
2449
2450         if (table_info != NULL) {
2451                 dep_mclk_table = table_info->vdd_dep_on_mclk;
2452                 lookup_table = table_info->vddc_lookup_table;
2453         } else
2454                 return 0;
2455
2456         hw_revision = adev->pdev->revision;
2457         sub_sys_id = adev->pdev->subsystem_device;
2458         sub_vendor_id = adev->pdev->subsystem_vendor;
2459
2460         if (adev->pdev->device == 0x67DF && hw_revision == 0xC7 &&
2461             ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2462              (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2463              (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2464
2465                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
2466                                               CGS_IND_REG__SMC,
2467                                               PWR_CKS_CNTL,
2468                                               CKS_STRETCH_AMOUNT,
2469                                               0x3);
2470
2471                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2472                         return 0;
2473
2474                 for (i = 0; i < lookup_table->count; i++) {
2475                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2476                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2477                                 return 0;
2478                         }
2479                 }
2480         }
2481         return 0;
2482 }
2483
2484 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2485 {
2486         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2487         uint32_t temp_reg;
2488         struct phm_ppt_v1_information *table_info =
2489                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2490
2491
2492         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2493                 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2494                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2495                 case 0:
2496                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2497                         break;
2498                 case 1:
2499                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2500                         break;
2501                 case 2:
2502                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2503                         break;
2504                 case 3:
2505                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2506                         break;
2507                 case 4:
2508                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2509                         break;
2510                 default:
2511                         break;
2512                 }
2513                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2514         }
2515
2516         if (table_info == NULL)
2517                 return 0;
2518
2519         if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2520                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2521                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2522                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2523
2524                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2525                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2526
2527                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2528
2529                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2530
2531                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2532                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2533
2534                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2535
2536                 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2537                                                                 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2538
2539                 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2540                 table_info->cac_dtp_table->usOperatingTempStep = 1;
2541                 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2542
2543                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2544                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2545
2546                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2547                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2548
2549                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2550                                table_info->cac_dtp_table->usOperatingTempMinLimit;
2551
2552                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2553                                table_info->cac_dtp_table->usOperatingTempMaxLimit;
2554
2555                 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2556                                table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2557
2558                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2559                                table_info->cac_dtp_table->usOperatingTempStep;
2560
2561                 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2562                                table_info->cac_dtp_table->usTargetOperatingTemp;
2563                 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2564                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2565                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
2566         }
2567
2568         return 0;
2569 }
2570
2571 /**
2572  * smu7_patch_ppt_v0_with_vdd_leakage - Change virtual leakage voltage to actual value.
2573  *
2574  * @hwmgr:  the address of the powerplay hardware manager.
2575  * @voltage: pointer to changing voltage
2576  * @leakage_table: pointer to leakage table
2577  */
2578 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2579                 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2580 {
2581         uint32_t index;
2582
2583         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2584         for (index = 0; index < leakage_table->count; index++) {
2585                 /* if this voltage matches a leakage voltage ID */
2586                 /* patch with actual leakage voltage */
2587                 if (leakage_table->leakage_id[index] == *voltage) {
2588                         *voltage = leakage_table->actual_voltage[index];
2589                         break;
2590                 }
2591         }
2592
2593         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2594                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
2595 }
2596
2597
2598 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2599                               struct phm_clock_voltage_dependency_table *tab)
2600 {
2601         uint16_t i;
2602         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2603
2604         if (tab)
2605                 for (i = 0; i < tab->count; i++)
2606                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2607                                                 &data->vddc_leakage);
2608
2609         return 0;
2610 }
2611
2612 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2613                                struct phm_clock_voltage_dependency_table *tab)
2614 {
2615         uint16_t i;
2616         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2617
2618         if (tab)
2619                 for (i = 0; i < tab->count; i++)
2620                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2621                                                         &data->vddci_leakage);
2622
2623         return 0;
2624 }
2625
2626 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2627                                   struct phm_vce_clock_voltage_dependency_table *tab)
2628 {
2629         uint16_t i;
2630         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2631
2632         if (tab)
2633                 for (i = 0; i < tab->count; i++)
2634                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2635                                                         &data->vddc_leakage);
2636
2637         return 0;
2638 }
2639
2640
2641 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2642                                   struct phm_uvd_clock_voltage_dependency_table *tab)
2643 {
2644         uint16_t i;
2645         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2646
2647         if (tab)
2648                 for (i = 0; i < tab->count; i++)
2649                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2650                                                         &data->vddc_leakage);
2651
2652         return 0;
2653 }
2654
2655 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2656                                          struct phm_phase_shedding_limits_table *tab)
2657 {
2658         uint16_t i;
2659         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2660
2661         if (tab)
2662                 for (i = 0; i < tab->count; i++)
2663                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2664                                                         &data->vddc_leakage);
2665
2666         return 0;
2667 }
2668
2669 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2670                                    struct phm_samu_clock_voltage_dependency_table *tab)
2671 {
2672         uint16_t i;
2673         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2674
2675         if (tab)
2676                 for (i = 0; i < tab->count; i++)
2677                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2678                                                         &data->vddc_leakage);
2679
2680         return 0;
2681 }
2682
2683 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2684                                   struct phm_acp_clock_voltage_dependency_table *tab)
2685 {
2686         uint16_t i;
2687         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2688
2689         if (tab)
2690                 for (i = 0; i < tab->count; i++)
2691                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2692                                         &data->vddc_leakage);
2693
2694         return 0;
2695 }
2696
2697 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2698                                   struct phm_clock_and_voltage_limits *tab)
2699 {
2700         uint32_t vddc, vddci;
2701         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2702
2703         if (tab) {
2704                 vddc = tab->vddc;
2705                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2706                                                    &data->vddc_leakage);
2707                 tab->vddc = vddc;
2708                 vddci = tab->vddci;
2709                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2710                                                    &data->vddci_leakage);
2711                 tab->vddci = vddci;
2712         }
2713
2714         return 0;
2715 }
2716
2717 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2718 {
2719         uint32_t i;
2720         uint32_t vddc;
2721         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2722
2723         if (tab) {
2724                 for (i = 0; i < tab->count; i++) {
2725                         vddc = (uint32_t)(tab->entries[i].Vddc);
2726                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2727                         tab->entries[i].Vddc = (uint16_t)vddc;
2728                 }
2729         }
2730
2731         return 0;
2732 }
2733
2734 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2735 {
2736         int tmp;
2737
2738         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2739         if (tmp)
2740                 return -EINVAL;
2741
2742         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2743         if (tmp)
2744                 return -EINVAL;
2745
2746         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2747         if (tmp)
2748                 return -EINVAL;
2749
2750         tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2751         if (tmp)
2752                 return -EINVAL;
2753
2754         tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2755         if (tmp)
2756                 return -EINVAL;
2757
2758         tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2759         if (tmp)
2760                 return -EINVAL;
2761
2762         tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2763         if (tmp)
2764                 return -EINVAL;
2765
2766         tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2767         if (tmp)
2768                 return -EINVAL;
2769
2770         tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2771         if (tmp)
2772                 return -EINVAL;
2773
2774         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2775         if (tmp)
2776                 return -EINVAL;
2777
2778         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2779         if (tmp)
2780                 return -EINVAL;
2781
2782         tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2783         if (tmp)
2784                 return -EINVAL;
2785
2786         return 0;
2787 }
2788
2789
2790 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2791 {
2792         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2793
2794         struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2795         struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2796         struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2797
2798         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2799                 "VDDC dependency on SCLK table is missing. This table is mandatory",
2800                 return -EINVAL);
2801         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2802                 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2803                 return -EINVAL);
2804
2805         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2806                 "VDDC dependency on MCLK table is missing. This table is mandatory",
2807                 return -EINVAL);
2808         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2809                 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2810                 return -EINVAL);
2811
2812         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2813         data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2814
2815         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2816                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2817         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2818                 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2819         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2820                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2821
2822         if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2823                 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2824                 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2825         }
2826
2827         if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2828                 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2829
2830         return 0;
2831 }
2832
2833 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2834 {
2835         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2836         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2837         kfree(hwmgr->backend);
2838         hwmgr->backend = NULL;
2839
2840         return 0;
2841 }
2842
2843 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2844 {
2845         uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2846         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2847         int i;
2848
2849         if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2850                 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2851                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2852                         if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2853                                                                 virtual_voltage_id,
2854                                                                 efuse_voltage_id) == 0) {
2855                                 if (vddc != 0 && vddc != virtual_voltage_id) {
2856                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2857                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2858                                         data->vddc_leakage.count++;
2859                                 }
2860                                 if (vddci != 0 && vddci != virtual_voltage_id) {
2861                                         data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2862                                         data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2863                                         data->vddci_leakage.count++;
2864                                 }
2865                         }
2866                 }
2867         }
2868         return 0;
2869 }
2870
2871 #define LEAKAGE_ID_MSB                  463
2872 #define LEAKAGE_ID_LSB                  454
2873
2874 static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr)
2875 {
2876         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2877         uint32_t efuse;
2878         uint16_t offset;
2879         int ret = 0;
2880
2881         if (data->disable_edc_leakage_controller)
2882                 return 0;
2883
2884         ret = atomctrl_get_edc_hilo_leakage_offset_table(hwmgr,
2885                                                          &data->edc_hilo_leakage_offset_from_vbios);
2886         if (ret)
2887                 return ret;
2888
2889         if (data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset &&
2890             data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) {
2891                 atomctrl_read_efuse(hwmgr, LEAKAGE_ID_LSB, LEAKAGE_ID_MSB, &efuse);
2892                 if (efuse < data->edc_hilo_leakage_offset_from_vbios.usHiLoLeakageThreshold)
2893                         offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset;
2894                 else
2895                         offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset;
2896
2897                 ret = atomctrl_get_edc_leakage_table(hwmgr,
2898                                                      &data->edc_leakage_table,
2899                                                      offset);
2900                 if (ret)
2901                         return ret;
2902         }
2903
2904         return ret;
2905 }
2906
2907 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2908 {
2909         struct smu7_hwmgr *data;
2910         int result = 0;
2911
2912         data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2913         if (data == NULL)
2914                 return -ENOMEM;
2915
2916         hwmgr->backend = data;
2917         smu7_patch_voltage_workaround(hwmgr);
2918         smu7_init_dpm_defaults(hwmgr);
2919
2920         /* Get leakage voltage based on leakage ID. */
2921         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2922                         PHM_PlatformCaps_EVV)) {
2923                 result = smu7_get_evv_voltages(hwmgr);
2924                 if (result) {
2925                         pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
2926                         return -EINVAL;
2927                 }
2928         } else {
2929                 smu7_get_elb_voltages(hwmgr);
2930         }
2931
2932         if (hwmgr->pp_table_version == PP_TABLE_V1) {
2933                 smu7_complete_dependency_tables(hwmgr);
2934                 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2935         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2936                 smu7_patch_dependency_tables_with_leakage(hwmgr);
2937                 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2938         }
2939
2940         /* Initalize Dynamic State Adjustment Rule Settings */
2941         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2942
2943         if (0 == result) {
2944                 struct amdgpu_device *adev = hwmgr->adev;
2945
2946                 data->is_tlu_enabled = false;
2947
2948                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2949                                                         SMU7_MAX_HARDWARE_POWERLEVELS;
2950                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2951                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2952
2953                 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
2954                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2955                         data->pcie_spc_cap = 20;
2956                 else
2957                         data->pcie_spc_cap = 16;
2958                 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
2959
2960                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2961 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2962                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2963                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2964                 smu7_thermal_parameter_init(hwmgr);
2965         } else {
2966                 /* Ignore return value in here, we are cleaning up a mess. */
2967                 smu7_hwmgr_backend_fini(hwmgr);
2968         }
2969
2970         result = smu7_update_edc_leakage_table(hwmgr);
2971         if (result)
2972                 return result;
2973
2974         return 0;
2975 }
2976
2977 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2978 {
2979         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2980         uint32_t level, tmp;
2981
2982         if (!data->pcie_dpm_key_disabled) {
2983                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2984                         level = 0;
2985                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2986                         while (tmp >>= 1)
2987                                 level++;
2988
2989                         if (level)
2990                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2991                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level,
2992                                                 NULL);
2993                 }
2994         }
2995
2996         if (!data->sclk_dpm_key_disabled) {
2997                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2998                         level = 0;
2999                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3000                         while (tmp >>= 1)
3001                                 level++;
3002
3003                         if (level)
3004                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3005                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3006                                                 (1 << level),
3007                                                 NULL);
3008                 }
3009         }
3010
3011         if (!data->mclk_dpm_key_disabled) {
3012                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3013                         level = 0;
3014                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3015                         while (tmp >>= 1)
3016                                 level++;
3017
3018                         if (level)
3019                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3020                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3021                                                 (1 << level),
3022                                                 NULL);
3023                 }
3024         }
3025
3026         return 0;
3027 }
3028
3029 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3030 {
3031         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3032
3033         if (hwmgr->pp_table_version == PP_TABLE_V1)
3034                 phm_apply_dal_min_voltage_request(hwmgr);
3035 /* TO DO  for v0 iceland and Ci*/
3036
3037         if (!data->sclk_dpm_key_disabled) {
3038                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3039                         smum_send_msg_to_smc_with_parameter(hwmgr,
3040                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3041                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask,
3042                                         NULL);
3043         }
3044
3045         if (!data->mclk_dpm_key_disabled) {
3046                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3047                         smum_send_msg_to_smc_with_parameter(hwmgr,
3048                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3049                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask,
3050                                         NULL);
3051         }
3052
3053         return 0;
3054 }
3055
3056 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3057 {
3058         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3059
3060         if (!smum_is_dpm_running(hwmgr))
3061                 return -EINVAL;
3062
3063         if (!data->pcie_dpm_key_disabled) {
3064                 smum_send_msg_to_smc(hwmgr,
3065                                 PPSMC_MSG_PCIeDPM_UnForceLevel,
3066                                 NULL);
3067         }
3068
3069         return smu7_upload_dpm_level_enable_mask(hwmgr);
3070 }
3071
3072 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3073 {
3074         struct smu7_hwmgr *data =
3075                         (struct smu7_hwmgr *)(hwmgr->backend);
3076         uint32_t level;
3077
3078         if (!data->sclk_dpm_key_disabled)
3079                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3080                         level = phm_get_lowest_enabled_level(hwmgr,
3081                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3082                         smum_send_msg_to_smc_with_parameter(hwmgr,
3083                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3084                                                             (1 << level),
3085                                                             NULL);
3086
3087         }
3088
3089         if (!data->mclk_dpm_key_disabled) {
3090                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3091                         level = phm_get_lowest_enabled_level(hwmgr,
3092                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3093                         smum_send_msg_to_smc_with_parameter(hwmgr,
3094                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3095                                                             (1 << level),
3096                                                             NULL);
3097                 }
3098         }
3099
3100         if (!data->pcie_dpm_key_disabled) {
3101                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3102                         level = phm_get_lowest_enabled_level(hwmgr,
3103                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3104                         smum_send_msg_to_smc_with_parameter(hwmgr,
3105                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3106                                                             (level),
3107                                                             NULL);
3108                 }
3109         }
3110
3111         return 0;
3112 }
3113
3114 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
3115                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
3116 {
3117         uint32_t percentage;
3118         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3119         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3120         int32_t tmp_mclk;
3121         int32_t tmp_sclk;
3122         int32_t count;
3123
3124         if (golden_dpm_table->mclk_table.count < 1)
3125                 return -EINVAL;
3126
3127         percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
3128                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
3129
3130         if (golden_dpm_table->mclk_table.count == 1) {
3131                 percentage = 70;
3132                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
3133                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
3134         } else {
3135                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
3136                 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
3137         }
3138
3139         tmp_sclk = tmp_mclk * percentage / 100;
3140
3141         if (hwmgr->pp_table_version == PP_TABLE_V0) {
3142                 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
3143                         count >= 0; count--) {
3144                         if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
3145                                 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
3146                                 *sclk_mask = count;
3147                                 break;
3148                         }
3149                 }
3150                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3151                         *sclk_mask = 0;
3152                         tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
3153                 }
3154
3155                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3156                         *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
3157         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3158                 struct phm_ppt_v1_information *table_info =
3159                                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3160
3161                 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
3162                         if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
3163                                 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
3164                                 *sclk_mask = count;
3165                                 break;
3166                         }
3167                 }
3168                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3169                         *sclk_mask = 0;
3170                         tmp_sclk =  table_info->vdd_dep_on_sclk->entries[0].clk;
3171                 }
3172
3173                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3174                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
3175         }
3176
3177         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
3178                 *mclk_mask = 0;
3179         else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3180                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
3181
3182         *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
3183         hwmgr->pstate_sclk = tmp_sclk;
3184         hwmgr->pstate_mclk = tmp_mclk;
3185
3186         return 0;
3187 }
3188
3189 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
3190                                 enum amd_dpm_forced_level level)
3191 {
3192         int ret = 0;
3193         uint32_t sclk_mask = 0;
3194         uint32_t mclk_mask = 0;
3195         uint32_t pcie_mask = 0;
3196
3197         if (hwmgr->pstate_sclk == 0)
3198                 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
3199
3200         switch (level) {
3201         case AMD_DPM_FORCED_LEVEL_HIGH:
3202                 ret = smu7_force_dpm_highest(hwmgr);
3203                 break;
3204         case AMD_DPM_FORCED_LEVEL_LOW:
3205                 ret = smu7_force_dpm_lowest(hwmgr);
3206                 break;
3207         case AMD_DPM_FORCED_LEVEL_AUTO:
3208                 ret = smu7_unforce_dpm_levels(hwmgr);
3209                 break;
3210         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
3211         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
3212         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
3213         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
3214                 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
3215                 if (ret)
3216                         return ret;
3217                 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
3218                 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
3219                 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
3220                 break;
3221         case AMD_DPM_FORCED_LEVEL_MANUAL:
3222         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
3223         default:
3224                 break;
3225         }
3226
3227         if (!ret) {
3228                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3229                         smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
3230                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3231                         smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
3232         }
3233         return ret;
3234 }
3235
3236 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
3237 {
3238         return sizeof(struct smu7_power_state);
3239 }
3240
3241 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
3242                                  uint32_t vblank_time_us)
3243 {
3244         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3245         uint32_t switch_limit_us;
3246
3247         switch (hwmgr->chip_id) {
3248         case CHIP_POLARIS10:
3249         case CHIP_POLARIS11:
3250         case CHIP_POLARIS12:
3251                 if (hwmgr->is_kicker || (hwmgr->chip_id == CHIP_POLARIS12))
3252                         switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
3253                 else
3254                         switch_limit_us = data->is_memory_gddr5 ? 200 : 150;
3255                 break;
3256         case CHIP_VEGAM:
3257                 switch_limit_us = 30;
3258                 break;
3259         default:
3260                 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
3261                 break;
3262         }
3263
3264         if (vblank_time_us < switch_limit_us)
3265                 return true;
3266         else
3267                 return false;
3268 }
3269
3270 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3271                                 struct pp_power_state *request_ps,
3272                         const struct pp_power_state *current_ps)
3273 {
3274         struct amdgpu_device *adev = hwmgr->adev;
3275         struct smu7_power_state *smu7_ps =
3276                                 cast_phw_smu7_power_state(&request_ps->hardware);
3277         uint32_t sclk;
3278         uint32_t mclk;
3279         struct PP_Clocks minimum_clocks = {0};
3280         bool disable_mclk_switching;
3281         bool disable_mclk_switching_for_frame_lock;
3282         bool disable_mclk_switching_for_display;
3283         const struct phm_clock_and_voltage_limits *max_limits;
3284         uint32_t i;
3285         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3286         struct phm_ppt_v1_information *table_info =
3287                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3288         int32_t count;
3289         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3290         uint32_t latency;
3291         bool latency_allowed = false;
3292
3293         data->battery_state = (PP_StateUILabel_Battery ==
3294                         request_ps->classification.ui_label);
3295         data->mclk_ignore_signal = false;
3296
3297         max_limits = adev->pm.ac_power ?
3298                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3299                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3300
3301         /* Cap clock DPM tables at DC MAX if it is in DC. */
3302         if (!adev->pm.ac_power) {
3303                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3304                         if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
3305                                 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
3306                         if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
3307                                 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
3308                 }
3309         }
3310
3311         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3312         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3313
3314         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3315                         PHM_PlatformCaps_StablePState)) {
3316                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3317                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3318
3319                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3320                                 count >= 0; count--) {
3321                         if (stable_pstate_sclk >=
3322                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3323                                 stable_pstate_sclk =
3324                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3325                                 break;
3326                         }
3327                 }
3328
3329                 if (count < 0)
3330                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3331
3332                 stable_pstate_mclk = max_limits->mclk;
3333
3334                 minimum_clocks.engineClock = stable_pstate_sclk;
3335                 minimum_clocks.memoryClock = stable_pstate_mclk;
3336         }
3337
3338         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3339                                     hwmgr->platform_descriptor.platformCaps,
3340                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3341
3342         disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) &&
3343                                                 !hwmgr->display_config->multi_monitor_in_sync) ||
3344                                                 (hwmgr->display_config->num_display &&
3345                                                 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));
3346
3347         disable_mclk_switching = disable_mclk_switching_for_frame_lock ||
3348                                          disable_mclk_switching_for_display;
3349
3350         if (hwmgr->display_config->num_display == 0) {
3351                 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM)
3352                         data->mclk_ignore_signal = true;
3353                 else
3354                         disable_mclk_switching = false;
3355         }
3356
3357         sclk = smu7_ps->performance_levels[0].engine_clock;
3358         mclk = smu7_ps->performance_levels[0].memory_clock;
3359
3360         if (disable_mclk_switching &&
3361             (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
3362             hwmgr->chip_id <= CHIP_VEGAM)))
3363                 mclk = smu7_ps->performance_levels
3364                 [smu7_ps->performance_level_count - 1].memory_clock;
3365
3366         if (sclk < minimum_clocks.engineClock)
3367                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3368                                 max_limits->sclk : minimum_clocks.engineClock;
3369
3370         if (mclk < minimum_clocks.memoryClock)
3371                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3372                                 max_limits->mclk : minimum_clocks.memoryClock;
3373
3374         smu7_ps->performance_levels[0].engine_clock = sclk;
3375         smu7_ps->performance_levels[0].memory_clock = mclk;
3376
3377         smu7_ps->performance_levels[1].engine_clock =
3378                 (smu7_ps->performance_levels[1].engine_clock >=
3379                                 smu7_ps->performance_levels[0].engine_clock) ?
3380                                                 smu7_ps->performance_levels[1].engine_clock :
3381                                                 smu7_ps->performance_levels[0].engine_clock;
3382
3383         if (disable_mclk_switching) {
3384                 if (mclk < smu7_ps->performance_levels[1].memory_clock)
3385                         mclk = smu7_ps->performance_levels[1].memory_clock;
3386
3387                 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) {
3388                         if (disable_mclk_switching_for_display) {
3389                                 /* Find the lowest MCLK frequency that is within
3390                                  * the tolerable latency defined in DAL
3391                                  */
3392                                 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3393                                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3394                                         if (data->mclk_latency_table.entries[i].latency <= latency) {
3395                                                 latency_allowed = true;
3396
3397                                                 if ((data->mclk_latency_table.entries[i].frequency >=
3398                                                                 smu7_ps->performance_levels[0].memory_clock) &&
3399                                                     (data->mclk_latency_table.entries[i].frequency <=
3400                                                                 smu7_ps->performance_levels[1].memory_clock)) {
3401                                                         mclk = data->mclk_latency_table.entries[i].frequency;
3402                                                         break;
3403                                                 }
3404                                         }
3405                                 }
3406                                 if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) {
3407                                         data->mclk_ignore_signal = true;
3408                                 } else {
3409                                         data->mclk_ignore_signal = false;
3410                                 }
3411                         }
3412
3413                         if (disable_mclk_switching_for_frame_lock)
3414                                 mclk = smu7_ps->performance_levels[1].memory_clock;
3415                 }
3416
3417                 smu7_ps->performance_levels[0].memory_clock = mclk;
3418
3419                 if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
3420                       hwmgr->chip_id <= CHIP_VEGAM))
3421                         smu7_ps->performance_levels[1].memory_clock = mclk;
3422         } else {
3423                 if (smu7_ps->performance_levels[1].memory_clock <
3424                                 smu7_ps->performance_levels[0].memory_clock)
3425                         smu7_ps->performance_levels[1].memory_clock =
3426                                         smu7_ps->performance_levels[0].memory_clock;
3427         }
3428
3429         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3430                         PHM_PlatformCaps_StablePState)) {
3431                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3432                         smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3433                         smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3434                         smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3435                         smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3436                 }
3437         }
3438         return 0;
3439 }
3440
3441
3442 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3443 {
3444         struct pp_power_state  *ps;
3445         struct smu7_power_state  *smu7_ps;
3446
3447         if (hwmgr == NULL)
3448                 return -EINVAL;
3449
3450         ps = hwmgr->request_ps;
3451
3452         if (ps == NULL)
3453                 return -EINVAL;
3454
3455         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3456
3457         if (low)
3458                 return smu7_ps->performance_levels[0].memory_clock;
3459         else
3460                 return smu7_ps->performance_levels
3461                                 [smu7_ps->performance_level_count-1].memory_clock;
3462 }
3463
3464 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3465 {
3466         struct pp_power_state  *ps;
3467         struct smu7_power_state  *smu7_ps;
3468
3469         if (hwmgr == NULL)
3470                 return -EINVAL;
3471
3472         ps = hwmgr->request_ps;
3473
3474         if (ps == NULL)
3475                 return -EINVAL;
3476
3477         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3478
3479         if (low)
3480                 return smu7_ps->performance_levels[0].engine_clock;
3481         else
3482                 return smu7_ps->performance_levels
3483                                 [smu7_ps->performance_level_count-1].engine_clock;
3484 }
3485
3486 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3487                                         struct pp_hw_power_state *hw_ps)
3488 {
3489         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3490         struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
3491         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3492         uint16_t size;
3493         uint8_t frev, crev;
3494         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3495
3496         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3497          * We assume here that fw_info is unchanged if this call fails.
3498          */
3499         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
3500                         &size, &frev, &crev);
3501         if (!fw_info)
3502                 /* During a test, there is no firmware info table. */
3503                 return 0;
3504
3505         /* Patch the state. */
3506         data->vbios_boot_state.sclk_bootup_value =
3507                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3508         data->vbios_boot_state.mclk_bootup_value =
3509                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3510         data->vbios_boot_state.mvdd_bootup_value =
3511                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3512         data->vbios_boot_state.vddc_bootup_value =
3513                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3514         data->vbios_boot_state.vddci_bootup_value =
3515                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3516         data->vbios_boot_state.pcie_gen_bootup_value =
3517                         smu7_get_current_pcie_speed(hwmgr);
3518
3519         data->vbios_boot_state.pcie_lane_bootup_value =
3520                         (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
3521
3522         /* set boot power state */
3523         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3524         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3525         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3526         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3527
3528         return 0;
3529 }
3530
3531 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
3532 {
3533         int result;
3534         unsigned long ret = 0;
3535
3536         if (hwmgr->pp_table_version == PP_TABLE_V0) {
3537                 result = pp_tables_get_num_of_entries(hwmgr, &ret);
3538                 return result ? 0 : ret;
3539         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3540                 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
3541                 return result;
3542         }
3543         return 0;
3544 }
3545
3546 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
3547                 void *state, struct pp_power_state *power_state,
3548                 void *pp_table, uint32_t classification_flag)
3549 {
3550         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3551         struct smu7_power_state  *smu7_power_state =
3552                         (struct smu7_power_state *)(&(power_state->hardware));
3553         struct smu7_performance_level *performance_level;
3554         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3555         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3556                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3557         PPTable_Generic_SubTable_Header *sclk_dep_table =
3558                         (PPTable_Generic_SubTable_Header *)
3559                         (((unsigned long)powerplay_table) +
3560                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3561
3562         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3563                         (ATOM_Tonga_MCLK_Dependency_Table *)
3564                         (((unsigned long)powerplay_table) +
3565                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3566
3567         /* The following fields are not initialized here: id orderedList allStatesList */
3568         power_state->classification.ui_label =
3569                         (le16_to_cpu(state_entry->usClassification) &
3570                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3571                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3572         power_state->classification.flags = classification_flag;
3573         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3574
3575         power_state->classification.temporary_state = false;
3576         power_state->classification.to_be_deleted = false;
3577
3578         power_state->validation.disallowOnDC =
3579                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3580                                         ATOM_Tonga_DISALLOW_ON_DC));
3581
3582         power_state->pcie.lanes = 0;
3583
3584         power_state->display.disableFrameModulation = false;
3585         power_state->display.limitRefreshrate = false;
3586         power_state->display.enableVariBright =
3587                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3588                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3589
3590         power_state->validation.supportedPowerLevels = 0;
3591         power_state->uvd_clocks.VCLK = 0;
3592         power_state->uvd_clocks.DCLK = 0;
3593         power_state->temperatures.min = 0;
3594         power_state->temperatures.max = 0;
3595
3596         performance_level = &(smu7_power_state->performance_levels
3597                         [smu7_power_state->performance_level_count++]);
3598
3599         PP_ASSERT_WITH_CODE(
3600                         (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3601                         "Performance levels exceeds SMC limit!",
3602                         return -EINVAL);
3603
3604         PP_ASSERT_WITH_CODE(
3605                         (smu7_power_state->performance_level_count <
3606                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3607                         "Performance levels exceeds Driver limit!",
3608                         return -EINVAL);
3609
3610         /* Performance levels are arranged from low to high. */
3611         performance_level->memory_clock = mclk_dep_table->entries
3612                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3613         if (sclk_dep_table->ucRevId == 0)
3614                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3615                         [state_entry->ucEngineClockIndexLow].ulSclk;
3616         else if (sclk_dep_table->ucRevId == 1)
3617                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3618                         [state_entry->ucEngineClockIndexLow].ulSclk;
3619         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3620                         state_entry->ucPCIEGenLow);
3621         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3622                         state_entry->ucPCIELaneLow);
3623
3624         performance_level = &(smu7_power_state->performance_levels
3625                         [smu7_power_state->performance_level_count++]);
3626         performance_level->memory_clock = mclk_dep_table->entries
3627                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3628
3629         if (sclk_dep_table->ucRevId == 0)
3630                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3631                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3632         else if (sclk_dep_table->ucRevId == 1)
3633                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3634                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3635
3636         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3637                         state_entry->ucPCIEGenHigh);
3638         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3639                         state_entry->ucPCIELaneHigh);
3640
3641         return 0;
3642 }
3643
3644 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
3645                 unsigned long entry_index, struct pp_power_state *state)
3646 {
3647         int result;
3648         struct smu7_power_state *ps;
3649         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3650         struct phm_ppt_v1_information *table_info =
3651                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3652         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3653                         table_info->vdd_dep_on_mclk;
3654
3655         state->hardware.magic = PHM_VIslands_Magic;
3656
3657         ps = (struct smu7_power_state *)(&state->hardware);
3658
3659         result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
3660                         smu7_get_pp_table_entry_callback_func_v1);
3661
3662         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3663          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3664          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3665          */
3666         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3667                 if (dep_mclk_table->entries[0].clk !=
3668                                 data->vbios_boot_state.mclk_bootup_value)
3669                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3670                                         "does not match VBIOS boot MCLK level");
3671                 if (dep_mclk_table->entries[0].vddci !=
3672                                 data->vbios_boot_state.vddci_bootup_value)
3673                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3674                                         "does not match VBIOS boot VDDCI level");
3675         }
3676
3677         /* set DC compatible flag if this state supports DC */
3678         if (!state->validation.disallowOnDC)
3679                 ps->dc_compatible = true;
3680
3681         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3682                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3683
3684         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3685         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3686
3687         if (!result) {
3688                 uint32_t i;
3689
3690                 switch (state->classification.ui_label) {
3691                 case PP_StateUILabel_Performance:
3692                         data->use_pcie_performance_levels = true;
3693                         for (i = 0; i < ps->performance_level_count; i++) {
3694                                 if (data->pcie_gen_performance.max <
3695                                                 ps->performance_levels[i].pcie_gen)
3696                                         data->pcie_gen_performance.max =
3697                                                         ps->performance_levels[i].pcie_gen;
3698
3699                                 if (data->pcie_gen_performance.min >
3700                                                 ps->performance_levels[i].pcie_gen)
3701                                         data->pcie_gen_performance.min =
3702                                                         ps->performance_levels[i].pcie_gen;
3703
3704                                 if (data->pcie_lane_performance.max <
3705                                                 ps->performance_levels[i].pcie_lane)
3706                                         data->pcie_lane_performance.max =
3707                                                         ps->performance_levels[i].pcie_lane;
3708                                 if (data->pcie_lane_performance.min >
3709                                                 ps->performance_levels[i].pcie_lane)
3710                                         data->pcie_lane_performance.min =
3711                                                         ps->performance_levels[i].pcie_lane;
3712                         }
3713                         break;
3714                 case PP_StateUILabel_Battery:
3715                         data->use_pcie_power_saving_levels = true;
3716
3717                         for (i = 0; i < ps->performance_level_count; i++) {
3718                                 if (data->pcie_gen_power_saving.max <
3719                                                 ps->performance_levels[i].pcie_gen)
3720                                         data->pcie_gen_power_saving.max =
3721                                                         ps->performance_levels[i].pcie_gen;
3722
3723                                 if (data->pcie_gen_power_saving.min >
3724                                                 ps->performance_levels[i].pcie_gen)
3725                                         data->pcie_gen_power_saving.min =
3726                                                         ps->performance_levels[i].pcie_gen;
3727
3728                                 if (data->pcie_lane_power_saving.max <
3729                                                 ps->performance_levels[i].pcie_lane)
3730                                         data->pcie_lane_power_saving.max =
3731                                                         ps->performance_levels[i].pcie_lane;
3732
3733                                 if (data->pcie_lane_power_saving.min >
3734                                                 ps->performance_levels[i].pcie_lane)
3735                                         data->pcie_lane_power_saving.min =
3736                                                         ps->performance_levels[i].pcie_lane;
3737                         }
3738                         break;
3739                 default:
3740                         break;
3741                 }
3742         }
3743         return 0;
3744 }
3745
3746 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3747                                         struct pp_hw_power_state *power_state,
3748                                         unsigned int index, const void *clock_info)
3749 {
3750         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3751         struct smu7_power_state  *ps = cast_phw_smu7_power_state(power_state);
3752         const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
3753         struct smu7_performance_level *performance_level;
3754         uint32_t engine_clock, memory_clock;
3755         uint16_t pcie_gen_from_bios;
3756
3757         engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
3758         memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
3759
3760         if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
3761                 data->highest_mclk = memory_clock;
3762
3763         PP_ASSERT_WITH_CODE(
3764                         (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3765                         "Performance levels exceeds SMC limit!",
3766                         return -EINVAL);
3767
3768         PP_ASSERT_WITH_CODE(
3769                         (ps->performance_level_count <
3770                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3771                         "Performance levels exceeds Driver limit, Skip!",
3772                         return 0);
3773
3774         performance_level = &(ps->performance_levels
3775                         [ps->performance_level_count++]);
3776
3777         /* Performance levels are arranged from low to high. */
3778         performance_level->memory_clock = memory_clock;
3779         performance_level->engine_clock = engine_clock;
3780
3781         pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
3782
3783         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
3784         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
3785
3786         return 0;
3787 }
3788
3789 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
3790                 unsigned long entry_index, struct pp_power_state *state)
3791 {
3792         int result;
3793         struct smu7_power_state *ps;
3794         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3795         struct phm_clock_voltage_dependency_table *dep_mclk_table =
3796                         hwmgr->dyn_state.vddci_dependency_on_mclk;
3797
3798         memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3799
3800         state->hardware.magic = PHM_VIslands_Magic;
3801
3802         ps = (struct smu7_power_state *)(&state->hardware);
3803
3804         result = pp_tables_get_entry(hwmgr, entry_index, state,
3805                         smu7_get_pp_table_entry_callback_func_v0);
3806
3807         /*
3808          * This is the earliest time we have all the dependency table
3809          * and the VBIOS boot state as
3810          * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3811          * state if there is only one VDDCI/MCLK level, check if it's
3812          * the same as VBIOS boot state
3813          */
3814         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3815                 if (dep_mclk_table->entries[0].clk !=
3816                                 data->vbios_boot_state.mclk_bootup_value)
3817                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3818                                         "does not match VBIOS boot MCLK level");
3819                 if (dep_mclk_table->entries[0].v !=
3820                                 data->vbios_boot_state.vddci_bootup_value)
3821                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3822                                         "does not match VBIOS boot VDDCI level");
3823         }
3824
3825         /* set DC compatible flag if this state supports DC */
3826         if (!state->validation.disallowOnDC)
3827                 ps->dc_compatible = true;
3828
3829         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3830                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3831
3832         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3833         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3834
3835         if (!result) {
3836                 uint32_t i;
3837
3838                 switch (state->classification.ui_label) {
3839                 case PP_StateUILabel_Performance:
3840                         data->use_pcie_performance_levels = true;
3841
3842                         for (i = 0; i < ps->performance_level_count; i++) {
3843                                 if (data->pcie_gen_performance.max <
3844                                                 ps->performance_levels[i].pcie_gen)
3845                                         data->pcie_gen_performance.max =
3846                                                         ps->performance_levels[i].pcie_gen;
3847
3848                                 if (data->pcie_gen_performance.min >
3849                                                 ps->performance_levels[i].pcie_gen)
3850                                         data->pcie_gen_performance.min =
3851                                                         ps->performance_levels[i].pcie_gen;
3852
3853                                 if (data->pcie_lane_performance.max <
3854                                                 ps->performance_levels[i].pcie_lane)
3855                                         data->pcie_lane_performance.max =
3856                                                         ps->performance_levels[i].pcie_lane;
3857
3858                                 if (data->pcie_lane_performance.min >
3859                                                 ps->performance_levels[i].pcie_lane)
3860                                         data->pcie_lane_performance.min =
3861                                                         ps->performance_levels[i].pcie_lane;
3862                         }
3863                         break;
3864                 case PP_StateUILabel_Battery:
3865                         data->use_pcie_power_saving_levels = true;
3866
3867                         for (i = 0; i < ps->performance_level_count; i++) {
3868                                 if (data->pcie_gen_power_saving.max <
3869                                                 ps->performance_levels[i].pcie_gen)
3870                                         data->pcie_gen_power_saving.max =
3871                                                         ps->performance_levels[i].pcie_gen;
3872
3873                                 if (data->pcie_gen_power_saving.min >
3874                                                 ps->performance_levels[i].pcie_gen)
3875                                         data->pcie_gen_power_saving.min =
3876                                                         ps->performance_levels[i].pcie_gen;
3877
3878                                 if (data->pcie_lane_power_saving.max <
3879                                                 ps->performance_levels[i].pcie_lane)
3880                                         data->pcie_lane_power_saving.max =
3881                                                         ps->performance_levels[i].pcie_lane;
3882
3883                                 if (data->pcie_lane_power_saving.min >
3884                                                 ps->performance_levels[i].pcie_lane)
3885                                         data->pcie_lane_power_saving.min =
3886                                                         ps->performance_levels[i].pcie_lane;
3887                         }
3888                         break;
3889                 default:
3890                         break;
3891                 }
3892         }
3893         return 0;
3894 }
3895
3896 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3897                 unsigned long entry_index, struct pp_power_state *state)
3898 {
3899         if (hwmgr->pp_table_version == PP_TABLE_V0)
3900                 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3901         else if (hwmgr->pp_table_version == PP_TABLE_V1)
3902                 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3903
3904         return 0;
3905 }
3906
3907 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
3908 {
3909         struct amdgpu_device *adev = hwmgr->adev;
3910         int i;
3911         u32 tmp = 0;
3912
3913         if (!query)
3914                 return -EINVAL;
3915
3916         /*
3917          * PPSMC_MSG_GetCurrPkgPwr is not supported on:
3918          *  - Hawaii
3919          *  - Bonaire
3920          *  - Fiji
3921          *  - Tonga
3922          */
3923         if ((adev->asic_type != CHIP_HAWAII) &&
3924             (adev->asic_type != CHIP_BONAIRE) &&
3925             (adev->asic_type != CHIP_FIJI) &&
3926             (adev->asic_type != CHIP_TONGA)) {
3927                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp);
3928                 *query = tmp;
3929
3930                 if (tmp != 0)
3931                         return 0;
3932         }
3933
3934         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL);
3935         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3936                                                         ixSMU_PM_STATUS_95, 0);
3937
3938         for (i = 0; i < 10; i++) {
3939                 msleep(500);
3940                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL);
3941                 tmp = cgs_read_ind_register(hwmgr->device,
3942                                                 CGS_IND_REG__SMC,
3943                                                 ixSMU_PM_STATUS_95);
3944                 if (tmp != 0)
3945                         break;
3946         }
3947         *query = tmp;
3948
3949         return 0;
3950 }
3951
3952 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3953                             void *value, int *size)
3954 {
3955         uint32_t sclk, mclk, activity_percent;
3956         uint32_t offset, val_vid;
3957         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3958
3959         /* size must be at least 4 bytes for all sensors */
3960         if (*size < 4)
3961                 return -EINVAL;
3962
3963         switch (idx) {
3964         case AMDGPU_PP_SENSOR_GFX_SCLK:
3965                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &sclk);
3966                 *((uint32_t *)value) = sclk;
3967                 *size = 4;
3968                 return 0;
3969         case AMDGPU_PP_SENSOR_GFX_MCLK:
3970                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &mclk);
3971                 *((uint32_t *)value) = mclk;
3972                 *size = 4;
3973                 return 0;
3974         case AMDGPU_PP_SENSOR_GPU_LOAD:
3975         case AMDGPU_PP_SENSOR_MEM_LOAD:
3976                 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
3977                                                                 SMU_SoftRegisters,
3978                                                                 (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ?
3979                                                                 AverageGraphicsActivity:
3980                                                                 AverageMemoryActivity);
3981
3982                 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3983                 activity_percent += 0x80;
3984                 activity_percent >>= 8;
3985                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3986                 *size = 4;
3987                 return 0;
3988         case AMDGPU_PP_SENSOR_GPU_TEMP:
3989                 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
3990                 *size = 4;
3991                 return 0;
3992         case AMDGPU_PP_SENSOR_UVD_POWER:
3993                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3994                 *size = 4;
3995                 return 0;
3996         case AMDGPU_PP_SENSOR_VCE_POWER:
3997                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3998                 *size = 4;
3999                 return 0;
4000         case AMDGPU_PP_SENSOR_GPU_POWER:
4001                 return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
4002         case AMDGPU_PP_SENSOR_VDDGFX:
4003                 if ((data->vr_config & VRCONF_VDDGFX_MASK) ==
4004                     (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT))
4005                         val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4006                                         CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
4007                 else
4008                         val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4009                                         CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID);
4010
4011                 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);
4012                 return 0;
4013         default:
4014                 return -EOPNOTSUPP;
4015         }
4016 }
4017
4018 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4019 {
4020         const struct phm_set_power_state_input *states =
4021                         (const struct phm_set_power_state_input *)input;
4022         const struct smu7_power_state *smu7_ps =
4023                         cast_const_phw_smu7_power_state(states->pnew_state);
4024         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4025         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4026         uint32_t sclk = smu7_ps->performance_levels
4027                         [smu7_ps->performance_level_count - 1].engine_clock;
4028         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4029         uint32_t mclk = smu7_ps->performance_levels
4030                         [smu7_ps->performance_level_count - 1].memory_clock;
4031         struct PP_Clocks min_clocks = {0};
4032         uint32_t i;
4033
4034         for (i = 0; i < sclk_table->count; i++) {
4035                 if (sclk == sclk_table->dpm_levels[i].value)
4036                         break;
4037         }
4038
4039         if (i >= sclk_table->count) {
4040                 if (sclk > sclk_table->dpm_levels[i-1].value) {
4041                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4042                         sclk_table->dpm_levels[i-1].value = sclk;
4043                 }
4044         } else {
4045         /* TODO: Check SCLK in DAL's minimum clocks
4046          * in case DeepSleep divider update is required.
4047          */
4048                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4049                         (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
4050                                 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4051                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4052         }
4053
4054         for (i = 0; i < mclk_table->count; i++) {
4055                 if (mclk == mclk_table->dpm_levels[i].value)
4056                         break;
4057         }
4058
4059         if (i >= mclk_table->count) {
4060                 if (mclk > mclk_table->dpm_levels[i-1].value) {
4061                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4062                         mclk_table->dpm_levels[i-1].value = mclk;
4063                 }
4064         }
4065
4066         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4067                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4068
4069         return 0;
4070 }
4071
4072 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4073                 const struct smu7_power_state *smu7_ps)
4074 {
4075         uint32_t i;
4076         uint32_t sclk, max_sclk = 0;
4077         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4078         struct smu7_dpm_table *dpm_table = &data->dpm_table;
4079
4080         for (i = 0; i < smu7_ps->performance_level_count; i++) {
4081                 sclk = smu7_ps->performance_levels[i].engine_clock;
4082                 if (max_sclk < sclk)
4083                         max_sclk = sclk;
4084         }
4085
4086         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4087                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4088                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4089                                         dpm_table->pcie_speed_table.dpm_levels
4090                                         [dpm_table->pcie_speed_table.count - 1].value :
4091                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4092         }
4093
4094         return 0;
4095 }
4096
4097 static int smu7_request_link_speed_change_before_state_change(
4098                 struct pp_hwmgr *hwmgr, const void *input)
4099 {
4100         const struct phm_set_power_state_input *states =
4101                         (const struct phm_set_power_state_input *)input;
4102         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4103         const struct smu7_power_state *smu7_nps =
4104                         cast_const_phw_smu7_power_state(states->pnew_state);
4105         const struct smu7_power_state *polaris10_cps =
4106                         cast_const_phw_smu7_power_state(states->pcurrent_state);
4107
4108         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
4109         uint16_t current_link_speed;
4110
4111         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4112                 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
4113         else
4114                 current_link_speed = data->force_pcie_gen;
4115
4116         data->force_pcie_gen = PP_PCIEGenInvalid;
4117         data->pspp_notify_required = false;
4118
4119         if (target_link_speed > current_link_speed) {
4120                 switch (target_link_speed) {
4121 #ifdef CONFIG_ACPI
4122                 case PP_PCIEGen3:
4123                         if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
4124                                 break;
4125                         data->force_pcie_gen = PP_PCIEGen2;
4126                         if (current_link_speed == PP_PCIEGen2)
4127                                 break;
4128                         fallthrough;
4129                 case PP_PCIEGen2:
4130                         if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
4131                                 break;
4132                         fallthrough;
4133 #endif
4134                 default:
4135                         data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
4136                         break;
4137                 }
4138         } else {
4139                 if (target_link_speed < current_link_speed)
4140                         data->pspp_notify_required = true;
4141         }
4142
4143         return 0;
4144 }
4145
4146 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4147 {
4148         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4149
4150         if (0 == data->need_update_smu7_dpm_table)
4151                 return 0;
4152
4153         if ((0 == data->sclk_dpm_key_disabled) &&
4154                 (data->need_update_smu7_dpm_table &
4155                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4156                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4157                                 "Trying to freeze SCLK DPM when DPM is disabled",
4158                                 );
4159                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4160                                 PPSMC_MSG_SCLKDPM_FreezeLevel,
4161                                 NULL),
4162                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4163                                 return -EINVAL);
4164         }
4165
4166         if ((0 == data->mclk_dpm_key_disabled) &&
4167                 !data->mclk_ignore_signal &&
4168                 (data->need_update_smu7_dpm_table &
4169                  DPMTABLE_OD_UPDATE_MCLK)) {
4170                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4171                                 "Trying to freeze MCLK DPM when DPM is disabled",
4172                                 );
4173                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4174                                 PPSMC_MSG_MCLKDPM_FreezeLevel,
4175                                 NULL),
4176                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4177                                 return -EINVAL);
4178         }
4179
4180         return 0;
4181 }
4182
4183 static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
4184                 struct pp_hwmgr *hwmgr, const void *input)
4185 {
4186         int result = 0;
4187         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4188         struct smu7_dpm_table *dpm_table = &data->dpm_table;
4189         uint32_t count;
4190         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4191         struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4192         struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4193
4194         if (0 == data->need_update_smu7_dpm_table)
4195                 return 0;
4196
4197         if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4198                 for (count = 0; count < dpm_table->sclk_table.count; count++) {
4199                         dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
4200                         dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
4201                 }
4202         }
4203
4204         if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4205                 for (count = 0; count < dpm_table->mclk_table.count; count++) {
4206                         dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
4207                         dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
4208                 }
4209         }
4210
4211         if (data->need_update_smu7_dpm_table &
4212                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4213                 result = smum_populate_all_graphic_levels(hwmgr);
4214                 PP_ASSERT_WITH_CODE((0 == result),
4215                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4216                                 return result);
4217         }
4218
4219         if (data->need_update_smu7_dpm_table &
4220                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4221                 /*populate MCLK dpm table to SMU7 */
4222                 result = smum_populate_all_memory_levels(hwmgr);
4223                 PP_ASSERT_WITH_CODE((0 == result),
4224                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4225                                 return result);
4226         }
4227
4228         return result;
4229 }
4230
4231 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4232                           struct smu7_single_dpm_table *dpm_table,
4233                         uint32_t low_limit, uint32_t high_limit)
4234 {
4235         uint32_t i;
4236
4237         /* force the trim if mclk_switching is disabled to prevent flicker */
4238         bool force_trim = (low_limit == high_limit);
4239         for (i = 0; i < dpm_table->count; i++) {
4240         /*skip the trim if od is enabled*/
4241                 if ((!hwmgr->od_enabled || force_trim)
4242                         && (dpm_table->dpm_levels[i].value < low_limit
4243                         || dpm_table->dpm_levels[i].value > high_limit))
4244                         dpm_table->dpm_levels[i].enabled = false;
4245                 else
4246                         dpm_table->dpm_levels[i].enabled = true;
4247         }
4248
4249         return 0;
4250 }
4251
4252 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
4253                 const struct smu7_power_state *smu7_ps)
4254 {
4255         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4256         uint32_t high_limit_count;
4257
4258         PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
4259                         "power state did not have any performance level",
4260                         return -EINVAL);
4261
4262         high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
4263
4264         smu7_trim_single_dpm_states(hwmgr,
4265                         &(data->dpm_table.sclk_table),
4266                         smu7_ps->performance_levels[0].engine_clock,
4267                         smu7_ps->performance_levels[high_limit_count].engine_clock);
4268
4269         smu7_trim_single_dpm_states(hwmgr,
4270                         &(data->dpm_table.mclk_table),
4271                         smu7_ps->performance_levels[0].memory_clock,
4272                         smu7_ps->performance_levels[high_limit_count].memory_clock);
4273
4274         return 0;
4275 }
4276
4277 static int smu7_generate_dpm_level_enable_mask(
4278                 struct pp_hwmgr *hwmgr, const void *input)
4279 {
4280         int result = 0;
4281         const struct phm_set_power_state_input *states =
4282                         (const struct phm_set_power_state_input *)input;
4283         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4284         const struct smu7_power_state *smu7_ps =
4285                         cast_const_phw_smu7_power_state(states->pnew_state);
4286
4287
4288         result = smu7_trim_dpm_states(hwmgr, smu7_ps);
4289         if (result)
4290                 return result;
4291
4292         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4293                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4294         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4295                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4296         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4297                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4298
4299         return 0;
4300 }
4301
4302 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4303 {
4304         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4305
4306         if (0 == data->need_update_smu7_dpm_table)
4307                 return 0;
4308
4309         if ((0 == data->sclk_dpm_key_disabled) &&
4310                 (data->need_update_smu7_dpm_table &
4311                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4312
4313                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4314                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4315                                 );
4316                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4317                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel,
4318                                 NULL),
4319                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4320                         return -EINVAL);
4321         }
4322
4323         if ((0 == data->mclk_dpm_key_disabled) &&
4324                 !data->mclk_ignore_signal &&
4325                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4326
4327                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4328                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4329                                 );
4330                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4331                                 PPSMC_MSG_MCLKDPM_UnfreezeLevel,
4332                                 NULL),
4333                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4334                     return -EINVAL);
4335         }
4336
4337         data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
4338
4339         return 0;
4340 }
4341
4342 static int smu7_notify_link_speed_change_after_state_change(
4343                 struct pp_hwmgr *hwmgr, const void *input)
4344 {
4345         const struct phm_set_power_state_input *states =
4346                         (const struct phm_set_power_state_input *)input;
4347         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4348         const struct smu7_power_state *smu7_ps =
4349                         cast_const_phw_smu7_power_state(states->pnew_state);
4350         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
4351         uint8_t  request;
4352
4353         if (data->pspp_notify_required) {
4354                 if (target_link_speed == PP_PCIEGen3)
4355                         request = PCIE_PERF_REQ_GEN3;
4356                 else if (target_link_speed == PP_PCIEGen2)
4357                         request = PCIE_PERF_REQ_GEN2;
4358                 else
4359                         request = PCIE_PERF_REQ_GEN1;
4360
4361                 if (request == PCIE_PERF_REQ_GEN1 &&
4362                                 smu7_get_current_pcie_speed(hwmgr) > 0)
4363                         return 0;
4364
4365 #ifdef CONFIG_ACPI
4366                 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
4367                         if (PP_PCIEGen2 == target_link_speed)
4368                                 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
4369                         else
4370                                 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
4371                 }
4372 #endif
4373         }
4374
4375         return 0;
4376 }
4377
4378 static int smu7_notify_no_display(struct pp_hwmgr *hwmgr)
4379 {
4380         return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL) == 0) ?  0 : -EINVAL;
4381 }
4382
4383 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr)
4384 {
4385         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4386
4387         if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
4388                 if (hwmgr->chip_id == CHIP_VEGAM)
4389                         smum_send_msg_to_smc_with_parameter(hwmgr,
4390                                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2,
4391                                         NULL);
4392                 else
4393                         smum_send_msg_to_smc_with_parameter(hwmgr,
4394                                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2,
4395                                         NULL);
4396                 data->last_sent_vbi_timeout = data->frame_time_x2;
4397         }
4398
4399         return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ?  0 : -EINVAL;
4400 }
4401
4402 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
4403 {
4404         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4405         int result = 0;
4406
4407         if (data->mclk_ignore_signal)
4408                 result = smu7_notify_no_display(hwmgr);
4409         else
4410                 result = smu7_notify_has_display(hwmgr);
4411
4412         return result;
4413 }
4414
4415 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4416 {
4417         int tmp_result, result = 0;
4418         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4419
4420         tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4421         PP_ASSERT_WITH_CODE((0 == tmp_result),
4422                         "Failed to find DPM states clocks in DPM table!",
4423                         result = tmp_result);
4424
4425         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4426                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4427                 tmp_result =
4428                         smu7_request_link_speed_change_before_state_change(hwmgr, input);
4429                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4430                                 "Failed to request link speed change before state change!",
4431                                 result = tmp_result);
4432         }
4433
4434         tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
4435         PP_ASSERT_WITH_CODE((0 == tmp_result),
4436                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4437
4438         tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4439         PP_ASSERT_WITH_CODE((0 == tmp_result),
4440                         "Failed to populate and upload SCLK MCLK DPM levels!",
4441                         result = tmp_result);
4442
4443         /*
4444          * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
4445          * That effectively disables AVFS feature.
4446          */
4447         if (hwmgr->hardcode_pp_table != NULL)
4448                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4449
4450         tmp_result = smu7_update_avfs(hwmgr);
4451         PP_ASSERT_WITH_CODE((0 == tmp_result),
4452                         "Failed to update avfs voltages!",
4453                         result = tmp_result);
4454
4455         tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
4456         PP_ASSERT_WITH_CODE((0 == tmp_result),
4457                         "Failed to generate DPM level enabled mask!",
4458                         result = tmp_result);
4459
4460         tmp_result = smum_update_sclk_threshold(hwmgr);
4461         PP_ASSERT_WITH_CODE((0 == tmp_result),
4462                         "Failed to update SCLK threshold!",
4463                         result = tmp_result);
4464
4465         tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
4466         PP_ASSERT_WITH_CODE((0 == tmp_result),
4467                         "Failed to unfreeze SCLK MCLK DPM!",
4468                         result = tmp_result);
4469
4470         tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
4471         PP_ASSERT_WITH_CODE((0 == tmp_result),
4472                         "Failed to upload DPM level enabled mask!",
4473                         result = tmp_result);
4474
4475         tmp_result = smu7_notify_smc_display(hwmgr);
4476         PP_ASSERT_WITH_CODE((0 == tmp_result),
4477                         "Failed to notify smc display settings!",
4478                         result = tmp_result);
4479
4480         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4481                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4482                 tmp_result =
4483                         smu7_notify_link_speed_change_after_state_change(hwmgr, input);
4484                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4485                                 "Failed to notify link speed change after state change!",
4486                                 result = tmp_result);
4487         }
4488         data->apply_optimized_settings = false;
4489         return result;
4490 }
4491
4492 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4493 {
4494         hwmgr->thermal_controller.
4495         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4496
4497         return smum_send_msg_to_smc_with_parameter(hwmgr,
4498                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm,
4499                         NULL);
4500 }
4501
4502 static int
4503 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4504 {
4505         return 0;
4506 }
4507
4508 /**
4509  * smu7_program_display_gap - Programs the display gap
4510  *
4511  * @hwmgr:  the address of the powerplay hardware manager.
4512  * Return:   always OK
4513  */
4514 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
4515 {
4516         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4517         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4518         uint32_t display_gap2;
4519         uint32_t pre_vbi_time_in_us;
4520         uint32_t frame_time_in_us;
4521         uint32_t ref_clock, refresh_rate;
4522
4523         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4524         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4525
4526         ref_clock =  amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
4527         refresh_rate = hwmgr->display_config->vrefresh;
4528
4529         if (0 == refresh_rate)
4530                 refresh_rate = 60;
4531
4532         frame_time_in_us = 1000000 / refresh_rate;
4533
4534         pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
4535
4536         data->frame_time_x2 = frame_time_in_us * 2 / 100;
4537
4538         if (data->frame_time_x2 < 280) {
4539                 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2);
4540                 data->frame_time_x2 = 280;
4541         }
4542
4543         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4544
4545         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4546
4547         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4548                         data->soft_regs_start + smum_get_offsetof(hwmgr,
4549                                                         SMU_SoftRegisters,
4550                                                         PreVBlankGap), 0x64);
4551
4552         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4553                         data->soft_regs_start + smum_get_offsetof(hwmgr,
4554                                                         SMU_SoftRegisters,
4555                                                         VBlankTimeout),
4556                                         (frame_time_in_us - pre_vbi_time_in_us));
4557
4558         return 0;
4559 }
4560
4561 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4562 {
4563         return smu7_program_display_gap(hwmgr);
4564 }
4565
4566 /**
4567  * smu7_set_max_fan_rpm_output - Set maximum target operating fan output RPM
4568  *
4569  * @hwmgr:  the address of the powerplay hardware manager.
4570  * @us_max_fan_rpm:  max operating fan RPM value.
4571  * Return:   The response that came from the SMC.
4572  */
4573 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4574 {
4575         hwmgr->thermal_controller.
4576         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4577
4578         return smum_send_msg_to_smc_with_parameter(hwmgr,
4579                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm,
4580                         NULL);
4581 }
4582
4583 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
4584         .process = phm_irq_process,
4585 };
4586
4587 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
4588 {
4589         struct amdgpu_irq_src *source =
4590                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
4591
4592         if (!source)
4593                 return -ENOMEM;
4594
4595         source->funcs = &smu7_irq_funcs;
4596
4597         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4598                         AMDGPU_IRQ_CLIENTID_LEGACY,
4599                         VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
4600                         source);
4601         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4602                         AMDGPU_IRQ_CLIENTID_LEGACY,
4603                         VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
4604                         source);
4605
4606         /* Register CTF(GPIO_19) interrupt */
4607         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4608                         AMDGPU_IRQ_CLIENTID_LEGACY,
4609                         VISLANDS30_IV_SRCID_GPIO_19,
4610                         source);
4611
4612         return 0;
4613 }
4614
4615 static bool
4616 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4617 {
4618         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4619         bool is_update_required = false;
4620
4621         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4622                 is_update_required = true;
4623
4624         if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
4625                 is_update_required = true;
4626
4627         if (hwmgr->chip_id >= CHIP_POLARIS10 &&
4628             hwmgr->chip_id <= CHIP_VEGAM &&
4629             data->last_sent_vbi_timeout != data->frame_time_x2)
4630                 is_update_required = true;
4631
4632         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4633                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4634                         (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
4635                         hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4636                         is_update_required = true;
4637         }
4638         return is_update_required;
4639 }
4640
4641 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
4642                                                            const struct smu7_performance_level *pl2)
4643 {
4644         return ((pl1->memory_clock == pl2->memory_clock) &&
4645                   (pl1->engine_clock == pl2->engine_clock) &&
4646                   (pl1->pcie_gen == pl2->pcie_gen) &&
4647                   (pl1->pcie_lane == pl2->pcie_lane));
4648 }
4649
4650 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
4651                 const struct pp_hw_power_state *pstate1,
4652                 const struct pp_hw_power_state *pstate2, bool *equal)
4653 {
4654         const struct smu7_power_state *psa;
4655         const struct smu7_power_state *psb;
4656         int i;
4657         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4658
4659         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4660                 return -EINVAL;
4661
4662         psa = cast_const_phw_smu7_power_state(pstate1);
4663         psb = cast_const_phw_smu7_power_state(pstate2);
4664         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4665         if (psa->performance_level_count != psb->performance_level_count) {
4666                 *equal = false;
4667                 return 0;
4668         }
4669
4670         for (i = 0; i < psa->performance_level_count; i++) {
4671                 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4672                         /* If we have found even one performance level pair that is different the states are different. */
4673                         *equal = false;
4674                         return 0;
4675                 }
4676         }
4677
4678         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4679         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4680         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4681         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4682         /* For OD call, set value based on flag */
4683         *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
4684                                                         DPMTABLE_OD_UPDATE_MCLK |
4685                                                         DPMTABLE_OD_UPDATE_VDDC));
4686
4687         return 0;
4688 }
4689
4690 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
4691 {
4692         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4693
4694         uint32_t tmp;
4695
4696         /* Read MC indirect register offset 0x9F bits [3:0] to see
4697          * if VBIOS has already loaded a full version of MC ucode
4698          * or not.
4699          */
4700
4701         smu7_get_mc_microcode_version(hwmgr);
4702
4703         data->need_long_memory_training = false;
4704
4705         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
4706                                                         ixMC_IO_DEBUG_UP_13);
4707         tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
4708
4709         if (tmp & (1 << 23)) {
4710                 data->mem_latency_high = MEM_LATENCY_HIGH;
4711                 data->mem_latency_low = MEM_LATENCY_LOW;
4712                 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4713                     (hwmgr->chip_id == CHIP_POLARIS11) ||
4714                     (hwmgr->chip_id == CHIP_POLARIS12))
4715                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL);
4716         } else {
4717                 data->mem_latency_high = 330;
4718                 data->mem_latency_low = 330;
4719                 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4720                     (hwmgr->chip_id == CHIP_POLARIS11) ||
4721                     (hwmgr->chip_id == CHIP_POLARIS12))
4722                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL);
4723         }
4724
4725         return 0;
4726 }
4727
4728 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
4729 {
4730         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4731
4732         data->clock_registers.vCG_SPLL_FUNC_CNTL         =
4733                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
4734         data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
4735                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
4736         data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
4737                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
4738         data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
4739                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
4740         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
4741                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
4742         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
4743                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
4744         data->clock_registers.vDLL_CNTL                  =
4745                 cgs_read_register(hwmgr->device, mmDLL_CNTL);
4746         data->clock_registers.vMCLK_PWRMGT_CNTL          =
4747                 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
4748         data->clock_registers.vMPLL_AD_FUNC_CNTL         =
4749                 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
4750         data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
4751                 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
4752         data->clock_registers.vMPLL_FUNC_CNTL            =
4753                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
4754         data->clock_registers.vMPLL_FUNC_CNTL_1          =
4755                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
4756         data->clock_registers.vMPLL_FUNC_CNTL_2          =
4757                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
4758         data->clock_registers.vMPLL_SS1                  =
4759                 cgs_read_register(hwmgr->device, mmMPLL_SS1);
4760         data->clock_registers.vMPLL_SS2                  =
4761                 cgs_read_register(hwmgr->device, mmMPLL_SS2);
4762         return 0;
4763
4764 }
4765
4766 /**
4767  * smu7_get_memory_type - Find out if memory is GDDR5.
4768  *
4769  * @hwmgr:  the address of the powerplay hardware manager.
4770  * Return:   always 0
4771  */
4772 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
4773 {
4774         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4775         struct amdgpu_device *adev = hwmgr->adev;
4776
4777         data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
4778
4779         return 0;
4780 }
4781
4782 /**
4783  * smu7_enable_acpi_power_management - Enables Dynamic Power Management by SMC
4784  *
4785  * @hwmgr:  the address of the powerplay hardware manager.
4786  * Return:   always 0
4787  */
4788 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4789 {
4790         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4791                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4792
4793         return 0;
4794 }
4795
4796 /**
4797  * smu7_init_power_gate_state - Initialize PowerGating States for different engines
4798  *
4799  * @hwmgr:  the address of the powerplay hardware manager.
4800  * Return:   always 0
4801  */
4802 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
4803 {
4804         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4805
4806         data->uvd_power_gated = false;
4807         data->vce_power_gated = false;
4808
4809         return 0;
4810 }
4811
4812 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4813 {
4814         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4815
4816         data->low_sclk_interrupt_threshold = 0;
4817         return 0;
4818 }
4819
4820 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
4821 {
4822         int tmp_result, result = 0;
4823
4824         smu7_check_mc_firmware(hwmgr);
4825
4826         tmp_result = smu7_read_clock_registers(hwmgr);
4827         PP_ASSERT_WITH_CODE((0 == tmp_result),
4828                         "Failed to read clock registers!", result = tmp_result);
4829
4830         tmp_result = smu7_get_memory_type(hwmgr);
4831         PP_ASSERT_WITH_CODE((0 == tmp_result),
4832                         "Failed to get memory type!", result = tmp_result);
4833
4834         tmp_result = smu7_enable_acpi_power_management(hwmgr);
4835         PP_ASSERT_WITH_CODE((0 == tmp_result),
4836                         "Failed to enable ACPI power management!", result = tmp_result);
4837
4838         tmp_result = smu7_init_power_gate_state(hwmgr);
4839         PP_ASSERT_WITH_CODE((0 == tmp_result),
4840                         "Failed to init power gate state!", result = tmp_result);
4841
4842         tmp_result = smu7_get_mc_microcode_version(hwmgr);
4843         PP_ASSERT_WITH_CODE((0 == tmp_result),
4844                         "Failed to get MC microcode version!", result = tmp_result);
4845
4846         tmp_result = smu7_init_sclk_threshold(hwmgr);
4847         PP_ASSERT_WITH_CODE((0 == tmp_result),
4848                         "Failed to init sclk threshold!", result = tmp_result);
4849
4850         return result;
4851 }
4852
4853 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4854                 enum pp_clock_type type, uint32_t mask)
4855 {
4856         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4857
4858         if (mask == 0)
4859                 return -EINVAL;
4860
4861         switch (type) {
4862         case PP_SCLK:
4863                 if (!data->sclk_dpm_key_disabled)
4864                         smum_send_msg_to_smc_with_parameter(hwmgr,
4865                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4866                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask,
4867                                         NULL);
4868                 break;
4869         case PP_MCLK:
4870                 if (!data->mclk_dpm_key_disabled)
4871                         smum_send_msg_to_smc_with_parameter(hwmgr,
4872                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4873                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask,
4874                                         NULL);
4875                 break;
4876         case PP_PCIE:
4877         {
4878                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4879
4880                 if (!data->pcie_dpm_key_disabled) {
4881                         if (fls(tmp) != ffs(tmp))
4882                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel,
4883                                                 NULL);
4884                         else
4885                                 smum_send_msg_to_smc_with_parameter(hwmgr,
4886                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4887                                         fls(tmp) - 1,
4888                                         NULL);
4889                 }
4890                 break;
4891         }
4892         default:
4893                 break;
4894         }
4895
4896         return 0;
4897 }
4898
4899 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4900                 enum pp_clock_type type, char *buf)
4901 {
4902         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4903         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4904         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4905         struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4906         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4907         struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4908         struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4909         int size = 0;
4910         uint32_t i, now, clock, pcie_speed;
4911
4912         switch (type) {
4913         case PP_SCLK:
4914                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock);
4915
4916                 for (i = 0; i < sclk_table->count; i++) {
4917                         if (clock > sclk_table->dpm_levels[i].value)
4918                                 continue;
4919                         break;
4920                 }
4921                 now = i;
4922
4923                 for (i = 0; i < sclk_table->count; i++)
4924                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4925                                         i, sclk_table->dpm_levels[i].value / 100,
4926                                         (i == now) ? "*" : "");
4927                 break;
4928         case PP_MCLK:
4929                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock);
4930
4931                 for (i = 0; i < mclk_table->count; i++) {
4932                         if (clock > mclk_table->dpm_levels[i].value)
4933                                 continue;
4934                         break;
4935                 }
4936                 now = i;
4937
4938                 for (i = 0; i < mclk_table->count; i++)
4939                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4940                                         i, mclk_table->dpm_levels[i].value / 100,
4941                                         (i == now) ? "*" : "");
4942                 break;
4943         case PP_PCIE:
4944                 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
4945                 for (i = 0; i < pcie_table->count; i++) {
4946                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4947                                 continue;
4948                         break;
4949                 }
4950                 now = i;
4951
4952                 for (i = 0; i < pcie_table->count; i++)
4953                         size += sprintf(buf + size, "%d: %s %s\n", i,
4954                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
4955                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
4956                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
4957                                         (i == now) ? "*" : "");
4958                 break;
4959         case OD_SCLK:
4960                 if (hwmgr->od_enabled) {
4961                         size += sprintf(buf + size, "%s:\n", "OD_SCLK");
4962                         for (i = 0; i < odn_sclk_table->num_of_pl; i++)
4963                                 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4964                                         i, odn_sclk_table->entries[i].clock/100,
4965                                         odn_sclk_table->entries[i].vddc);
4966                 }
4967                 break;
4968         case OD_MCLK:
4969                 if (hwmgr->od_enabled) {
4970                         size += sprintf(buf + size, "%s:\n", "OD_MCLK");
4971                         for (i = 0; i < odn_mclk_table->num_of_pl; i++)
4972                                 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4973                                         i, odn_mclk_table->entries[i].clock/100,
4974                                         odn_mclk_table->entries[i].vddc);
4975                 }
4976                 break;
4977         case OD_RANGE:
4978                 if (hwmgr->od_enabled) {
4979                         size += sprintf(buf + size, "%s:\n", "OD_RANGE");
4980                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4981                                 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4982                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4983                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4984                                 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4985                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4986                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4987                                 data->odn_dpm_table.min_vddc,
4988                                 data->odn_dpm_table.max_vddc);
4989                 }
4990                 break;
4991         default:
4992                 break;
4993         }
4994         return size;
4995 }
4996
4997 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4998 {
4999         switch (mode) {
5000         case AMD_FAN_CTRL_NONE:
5001                 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
5002                 break;
5003         case AMD_FAN_CTRL_MANUAL:
5004                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5005                         PHM_PlatformCaps_MicrocodeFanControl))
5006                         smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
5007                 break;
5008         case AMD_FAN_CTRL_AUTO:
5009                 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
5010                         smu7_fan_ctrl_start_smc_fan_control(hwmgr);
5011                 break;
5012         default:
5013                 break;
5014         }
5015 }
5016
5017 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5018 {
5019         return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
5020 }
5021
5022 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
5023 {
5024         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5025         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5026         struct smu7_single_dpm_table *golden_sclk_table =
5027                         &(data->golden_dpm_table.sclk_table);
5028         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
5029         int golden_value = golden_sclk_table->dpm_levels
5030                         [golden_sclk_table->count - 1].value;
5031
5032         value -= golden_value;
5033         value = DIV_ROUND_UP(value * 100, golden_value);
5034
5035         return value;
5036 }
5037
5038 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5039 {
5040         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5041         struct smu7_single_dpm_table *golden_sclk_table =
5042                         &(data->golden_dpm_table.sclk_table);
5043         struct pp_power_state  *ps;
5044         struct smu7_power_state  *smu7_ps;
5045
5046         if (value > 20)
5047                 value = 20;
5048
5049         ps = hwmgr->request_ps;
5050
5051         if (ps == NULL)
5052                 return -EINVAL;
5053
5054         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
5055
5056         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
5057                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5058                         value / 100 +
5059                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5060
5061         return 0;
5062 }
5063
5064 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
5065 {
5066         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5067         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5068         struct smu7_single_dpm_table *golden_mclk_table =
5069                         &(data->golden_dpm_table.mclk_table);
5070         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
5071         int golden_value = golden_mclk_table->dpm_levels
5072                         [golden_mclk_table->count - 1].value;
5073
5074         value -= golden_value;
5075         value = DIV_ROUND_UP(value * 100, golden_value);
5076
5077         return value;
5078 }
5079
5080 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5081 {
5082         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5083         struct smu7_single_dpm_table *golden_mclk_table =
5084                         &(data->golden_dpm_table.mclk_table);
5085         struct pp_power_state  *ps;
5086         struct smu7_power_state  *smu7_ps;
5087
5088         if (value > 20)
5089                 value = 20;
5090
5091         ps = hwmgr->request_ps;
5092
5093         if (ps == NULL)
5094                 return -EINVAL;
5095
5096         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
5097
5098         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
5099                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5100                         value / 100 +
5101                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5102
5103         return 0;
5104 }
5105
5106
5107 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
5108 {
5109         struct phm_ppt_v1_information *table_info =
5110                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5111         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
5112         struct phm_clock_voltage_dependency_table *sclk_table;
5113         int i;
5114
5115         if (hwmgr->pp_table_version == PP_TABLE_V1) {
5116                 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
5117                         return -EINVAL;
5118                 dep_sclk_table = table_info->vdd_dep_on_sclk;
5119                 for (i = 0; i < dep_sclk_table->count; i++)
5120                         clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
5121                 clocks->count = dep_sclk_table->count;
5122         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
5123                 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
5124                 for (i = 0; i < sclk_table->count; i++)
5125                         clocks->clock[i] = sclk_table->entries[i].clk * 10;
5126                 clocks->count = sclk_table->count;
5127         }
5128
5129         return 0;
5130 }
5131
5132 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
5133 {
5134         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5135
5136         if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
5137                 return data->mem_latency_high;
5138         else if (clk >= MEM_FREQ_HIGH_LATENCY)
5139                 return data->mem_latency_low;
5140         else
5141                 return MEM_LATENCY_ERR;
5142 }
5143
5144 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
5145 {
5146         struct phm_ppt_v1_information *table_info =
5147                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5148         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
5149         int i;
5150         struct phm_clock_voltage_dependency_table *mclk_table;
5151
5152         if (hwmgr->pp_table_version == PP_TABLE_V1) {
5153                 if (table_info == NULL)
5154                         return -EINVAL;
5155                 dep_mclk_table = table_info->vdd_dep_on_mclk;
5156                 for (i = 0; i < dep_mclk_table->count; i++) {
5157                         clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
5158                         clocks->latency[i] = smu7_get_mem_latency(hwmgr,
5159                                                 dep_mclk_table->entries[i].clk);
5160                 }
5161                 clocks->count = dep_mclk_table->count;
5162         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
5163                 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
5164                 for (i = 0; i < mclk_table->count; i++)
5165                         clocks->clock[i] = mclk_table->entries[i].clk * 10;
5166                 clocks->count = mclk_table->count;
5167         }
5168         return 0;
5169 }
5170
5171 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
5172                                                 struct amd_pp_clocks *clocks)
5173 {
5174         switch (type) {
5175         case amd_pp_sys_clock:
5176                 smu7_get_sclks(hwmgr, clocks);
5177                 break;
5178         case amd_pp_mem_clock:
5179                 smu7_get_mclks(hwmgr, clocks);
5180                 break;
5181         default:
5182                 return -EINVAL;
5183         }
5184
5185         return 0;
5186 }
5187
5188 static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr,
5189                                        struct pp_clock_levels_with_latency *clocks)
5190 {
5191         struct phm_ppt_v1_information *table_info =
5192                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5193         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
5194                         table_info->vdd_dep_on_sclk;
5195         int i;
5196
5197         clocks->num_levels = 0;
5198         for (i = 0; i < dep_sclk_table->count; i++) {
5199                 if (dep_sclk_table->entries[i].clk) {
5200                         clocks->data[clocks->num_levels].clocks_in_khz =
5201                                 dep_sclk_table->entries[i].clk * 10;
5202                         clocks->num_levels++;
5203                 }
5204         }
5205
5206         return 0;
5207 }
5208
5209 static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr,
5210                                        struct pp_clock_levels_with_latency *clocks)
5211 {
5212         struct phm_ppt_v1_information *table_info =
5213                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5214         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5215                         table_info->vdd_dep_on_mclk;
5216         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5217         int i;
5218
5219         clocks->num_levels = 0;
5220         data->mclk_latency_table.count = 0;
5221         for (i = 0; i < dep_mclk_table->count; i++) {
5222                 if (dep_mclk_table->entries[i].clk) {
5223                         clocks->data[clocks->num_levels].clocks_in_khz =
5224                                         dep_mclk_table->entries[i].clk * 10;
5225                         data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency =
5226                                         dep_mclk_table->entries[i].clk;
5227                         clocks->data[clocks->num_levels].latency_in_us =
5228                                 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency =
5229                                         smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk);
5230                         clocks->num_levels++;
5231                         data->mclk_latency_table.count++;
5232                 }
5233         }
5234
5235         return 0;
5236 }
5237
5238 static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
5239                                                enum amd_pp_clock_type type,
5240                                                struct pp_clock_levels_with_latency *clocks)
5241 {
5242         if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
5243               hwmgr->chip_id <= CHIP_VEGAM))
5244                 return -EINVAL;
5245
5246         switch (type) {
5247         case amd_pp_sys_clock:
5248                 smu7_get_sclks_with_latency(hwmgr, clocks);
5249                 break;
5250         case amd_pp_mem_clock:
5251                 smu7_get_mclks_with_latency(hwmgr, clocks);
5252                 break;
5253         default:
5254                 return -EINVAL;
5255         }
5256
5257         return 0;
5258 }
5259
5260 static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
5261                                                  void *clock_range)
5262 {
5263         struct phm_ppt_v1_information *table_info =
5264                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5265         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5266                         table_info->vdd_dep_on_mclk;
5267         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
5268                         table_info->vdd_dep_on_sclk;
5269         struct polaris10_smumgr *smu_data =
5270                         (struct polaris10_smumgr *)(hwmgr->smu_backend);
5271         SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
5272         struct dm_pp_wm_sets_with_clock_ranges *watermarks =
5273                         (struct dm_pp_wm_sets_with_clock_ranges *)clock_range;
5274         uint32_t i, j, k;
5275         bool valid_entry;
5276
5277         if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
5278               hwmgr->chip_id <= CHIP_VEGAM))
5279                 return -EINVAL;
5280
5281         for (i = 0; i < dep_mclk_table->count; i++) {
5282                 for (j = 0; j < dep_sclk_table->count; j++) {
5283                         valid_entry = false;
5284                         for (k = 0; k < watermarks->num_wm_sets; k++) {
5285                                 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 &&
5286                                     dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 &&
5287                                     dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 &&
5288                                     dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) {
5289                                         valid_entry = true;
5290                                         table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id;
5291                                         break;
5292                                 }
5293                         }
5294                         PP_ASSERT_WITH_CODE(valid_entry,
5295                                         "Clock is not in range of specified clock range for watermark from DAL!  Using highest water mark set.",
5296                                         table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id);
5297                 }
5298         }
5299
5300         return smu7_copy_bytes_to_smc(hwmgr,
5301                                       smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, DisplayWatermark),
5302                                       (uint8_t *)table->DisplayWatermark,
5303                                       sizeof(uint8_t) * SMU74_MAX_LEVELS_MEMORY * SMU74_MAX_LEVELS_GRAPHICS,
5304                                       SMC_RAM_END);
5305 }
5306
5307 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
5308                                         uint32_t virtual_addr_low,
5309                                         uint32_t virtual_addr_hi,
5310                                         uint32_t mc_addr_low,
5311                                         uint32_t mc_addr_hi,
5312                                         uint32_t size)
5313 {
5314         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5315
5316         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5317                                         data->soft_regs_start +
5318                                         smum_get_offsetof(hwmgr,
5319                                         SMU_SoftRegisters, DRAM_LOG_ADDR_H),
5320                                         mc_addr_hi);
5321
5322         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5323                                         data->soft_regs_start +
5324                                         smum_get_offsetof(hwmgr,
5325                                         SMU_SoftRegisters, DRAM_LOG_ADDR_L),
5326                                         mc_addr_low);
5327
5328         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5329                                         data->soft_regs_start +
5330                                         smum_get_offsetof(hwmgr,
5331                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
5332                                         virtual_addr_hi);
5333
5334         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5335                                         data->soft_regs_start +
5336                                         smum_get_offsetof(hwmgr,
5337                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
5338                                         virtual_addr_low);
5339
5340         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5341                                         data->soft_regs_start +
5342                                         smum_get_offsetof(hwmgr,
5343                                         SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
5344                                         size);
5345         return 0;
5346 }
5347
5348 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
5349                                         struct amd_pp_simple_clock_info *clocks)
5350 {
5351         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5352         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5353         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5354
5355         if (clocks == NULL)
5356                 return -EINVAL;
5357
5358         clocks->memory_max_clock = mclk_table->count > 1 ?
5359                                 mclk_table->dpm_levels[mclk_table->count-1].value :
5360                                 mclk_table->dpm_levels[0].value;
5361         clocks->engine_max_clock = sclk_table->count > 1 ?
5362                                 sclk_table->dpm_levels[sclk_table->count-1].value :
5363                                 sclk_table->dpm_levels[0].value;
5364         return 0;
5365 }
5366
5367 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
5368                 struct PP_TemperatureRange *thermal_data)
5369 {
5370         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5371         struct phm_ppt_v1_information *table_info =
5372                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5373
5374         memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
5375
5376         if (hwmgr->pp_table_version == PP_TABLE_V1)
5377                 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp *
5378                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5379         else if (hwmgr->pp_table_version == PP_TABLE_V0)
5380                 thermal_data->max = data->thermal_temp_setting.temperature_shutdown *
5381                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5382
5383         return 0;
5384 }
5385
5386 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
5387                                         enum PP_OD_DPM_TABLE_COMMAND type,
5388                                         uint32_t clk,
5389                                         uint32_t voltage)
5390 {
5391         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5392
5393         if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) {
5394                 pr_info("OD voltage is out of range [%d - %d] mV\n",
5395                                                 data->odn_dpm_table.min_vddc,
5396                                                 data->odn_dpm_table.max_vddc);
5397                 return false;
5398         }
5399
5400         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5401                 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk ||
5402                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5403                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5404                                 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
5405                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5406                         return false;
5407                 }
5408         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5409                 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk ||
5410                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5411                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5412                                 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
5413                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5414                         return false;
5415                 }
5416         } else {
5417                 return false;
5418         }
5419
5420         return true;
5421 }
5422
5423 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5424                                         enum PP_OD_DPM_TABLE_COMMAND type,
5425                                         long *input, uint32_t size)
5426 {
5427         uint32_t i;
5428         struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
5429         struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
5430         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5431
5432         uint32_t input_clk;
5433         uint32_t input_vol;
5434         uint32_t input_level;
5435
5436         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5437                                 return -EINVAL);
5438
5439         if (!hwmgr->od_enabled) {
5440                 pr_info("OverDrive feature not enabled\n");
5441                 return -EINVAL;
5442         }
5443
5444         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5445                 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
5446                 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
5447                 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
5448                                 "Failed to get ODN SCLK and Voltage tables",
5449                                 return -EINVAL);
5450         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5451                 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
5452                 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
5453
5454                 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
5455                         "Failed to get ODN MCLK and Voltage tables",
5456                         return -EINVAL);
5457         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5458                 smu7_odn_initial_default_setting(hwmgr);
5459                 return 0;
5460         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
5461                 smu7_check_dpm_table_updated(hwmgr);
5462                 return 0;
5463         } else {
5464                 return -EINVAL;
5465         }
5466
5467         for (i = 0; i < size; i += 3) {
5468                 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
5469                         pr_info("invalid clock voltage input \n");
5470                         return 0;
5471                 }
5472                 input_level = input[i];
5473                 input_clk = input[i+1] * 100;
5474                 input_vol = input[i+2];
5475
5476                 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5477                         podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
5478                         podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
5479                         podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
5480                         podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
5481                         podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol;
5482                 } else {
5483                         return -EINVAL;
5484                 }
5485         }
5486
5487         return 0;
5488 }
5489
5490 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
5491 {
5492         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5493         uint32_t i, size = 0;
5494         uint32_t len;
5495
5496         static const char *title[8] = {"NUM",
5497                         "MODE_NAME",
5498                         "SCLK_UP_HYST",
5499                         "SCLK_DOWN_HYST",
5500                         "SCLK_ACTIVE_LEVEL",
5501                         "MCLK_UP_HYST",
5502                         "MCLK_DOWN_HYST",
5503                         "MCLK_ACTIVE_LEVEL"};
5504
5505         if (!buf)
5506                 return -EINVAL;
5507
5508         phm_get_sysfs_buf(&buf, &size);
5509
5510         size += sysfs_emit_at(buf, size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
5511                         title[0], title[1], title[2], title[3],
5512                         title[4], title[5], title[6], title[7]);
5513
5514         len = ARRAY_SIZE(smu7_profiling);
5515
5516         for (i = 0; i < len; i++) {
5517                 if (i == hwmgr->power_profile_mode) {
5518                         size += sysfs_emit_at(buf, size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
5519                         i, amdgpu_pp_profile_name[i], "*",
5520                         data->current_profile_setting.sclk_up_hyst,
5521                         data->current_profile_setting.sclk_down_hyst,
5522                         data->current_profile_setting.sclk_activity,
5523                         data->current_profile_setting.mclk_up_hyst,
5524                         data->current_profile_setting.mclk_down_hyst,
5525                         data->current_profile_setting.mclk_activity);
5526                         continue;
5527                 }
5528                 if (smu7_profiling[i].bupdate_sclk)
5529                         size += sysfs_emit_at(buf, size, "%3d %16s: %8d %16d %16d ",
5530                         i, amdgpu_pp_profile_name[i], smu7_profiling[i].sclk_up_hyst,
5531                         smu7_profiling[i].sclk_down_hyst,
5532                         smu7_profiling[i].sclk_activity);
5533                 else
5534                         size += sysfs_emit_at(buf, size, "%3d %16s: %8s %16s %16s ",
5535                         i, amdgpu_pp_profile_name[i], "-", "-", "-");
5536
5537                 if (smu7_profiling[i].bupdate_mclk)
5538                         size += sysfs_emit_at(buf, size, "%16d %16d %16d\n",
5539                         smu7_profiling[i].mclk_up_hyst,
5540                         smu7_profiling[i].mclk_down_hyst,
5541                         smu7_profiling[i].mclk_activity);
5542                 else
5543                         size += sysfs_emit_at(buf, size, "%16s %16s %16s\n",
5544                         "-", "-", "-");
5545         }
5546
5547         return size;
5548 }
5549
5550 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
5551                                         enum PP_SMC_POWER_PROFILE requst)
5552 {
5553         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5554         uint32_t tmp, level;
5555
5556         if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
5557                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
5558                         level = 0;
5559                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
5560                         while (tmp >>= 1)
5561                                 level++;
5562                         if (level > 0)
5563                                 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
5564                 }
5565         } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
5566                 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
5567         }
5568 }
5569
5570 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5571 {
5572         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5573         struct profile_mode_setting tmp;
5574         enum PP_SMC_POWER_PROFILE mode;
5575
5576         if (input == NULL)
5577                 return -EINVAL;
5578
5579         mode = input[size];
5580         switch (mode) {
5581         case PP_SMC_POWER_PROFILE_CUSTOM:
5582                 if (size < 8 && size != 0)
5583                         return -EINVAL;
5584                 /* If only CUSTOM is passed in, use the saved values. Check
5585                  * that we actually have a CUSTOM profile by ensuring that
5586                  * the "use sclk" or the "use mclk" bits are set
5587                  */
5588                 tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM];
5589                 if (size == 0) {
5590                         if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0)
5591                                 return -EINVAL;
5592                 } else {
5593                         tmp.bupdate_sclk = input[0];
5594                         tmp.sclk_up_hyst = input[1];
5595                         tmp.sclk_down_hyst = input[2];
5596                         tmp.sclk_activity = input[3];
5597                         tmp.bupdate_mclk = input[4];
5598                         tmp.mclk_up_hyst = input[5];
5599                         tmp.mclk_down_hyst = input[6];
5600                         tmp.mclk_activity = input[7];
5601                         smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp;
5602                 }
5603                 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5604                         memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
5605                         hwmgr->power_profile_mode = mode;
5606                 }
5607                 break;
5608         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
5609         case PP_SMC_POWER_PROFILE_POWERSAVING:
5610         case PP_SMC_POWER_PROFILE_VIDEO:
5611         case PP_SMC_POWER_PROFILE_VR:
5612         case PP_SMC_POWER_PROFILE_COMPUTE:
5613                 if (mode == hwmgr->power_profile_mode)
5614                         return 0;
5615
5616                 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
5617                 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5618                         if (tmp.bupdate_sclk) {
5619                                 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
5620                                 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
5621                                 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
5622                                 data->current_profile_setting.sclk_activity = tmp.sclk_activity;
5623                         }
5624                         if (tmp.bupdate_mclk) {
5625                                 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
5626                                 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
5627                                 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
5628                                 data->current_profile_setting.mclk_activity = tmp.mclk_activity;
5629                         }
5630                         smu7_patch_compute_profile_mode(hwmgr, mode);
5631                         hwmgr->power_profile_mode = mode;
5632                 }
5633                 break;
5634         default:
5635                 return -EINVAL;
5636         }
5637
5638         return 0;
5639 }
5640
5641 static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5642                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
5643                                 PHM_PerformanceLevel *level)
5644 {
5645         const struct smu7_power_state *ps;
5646         uint32_t i;
5647
5648         if (level == NULL || hwmgr == NULL || state == NULL)
5649                 return -EINVAL;
5650
5651         ps = cast_const_phw_smu7_power_state(state);
5652
5653         i = index > ps->performance_level_count - 1 ?
5654                         ps->performance_level_count - 1 : index;
5655
5656         level->coreClock = ps->performance_levels[i].engine_clock;
5657         level->memory_clock = ps->performance_levels[i].memory_clock;
5658
5659         return 0;
5660 }
5661
5662 static int smu7_power_off_asic(struct pp_hwmgr *hwmgr)
5663 {
5664         int result;
5665
5666         result = smu7_disable_dpm_tasks(hwmgr);
5667         PP_ASSERT_WITH_CODE((0 == result),
5668                         "[disable_dpm_tasks] Failed to disable DPM!",
5669                         );
5670
5671         return result;
5672 }
5673
5674 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
5675         .backend_init = &smu7_hwmgr_backend_init,
5676         .backend_fini = &smu7_hwmgr_backend_fini,
5677         .asic_setup = &smu7_setup_asic_task,
5678         .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
5679         .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
5680         .force_dpm_level = &smu7_force_dpm_level,
5681         .power_state_set = smu7_set_power_state_tasks,
5682         .get_power_state_size = smu7_get_power_state_size,
5683         .get_mclk = smu7_dpm_get_mclk,
5684         .get_sclk = smu7_dpm_get_sclk,
5685         .patch_boot_state = smu7_dpm_patch_boot_state,
5686         .get_pp_table_entry = smu7_get_pp_table_entry,
5687         .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
5688         .powerdown_uvd = smu7_powerdown_uvd,
5689         .powergate_uvd = smu7_powergate_uvd,
5690         .powergate_vce = smu7_powergate_vce,
5691         .disable_clock_power_gating = smu7_disable_clock_power_gating,
5692         .update_clock_gatings = smu7_update_clock_gatings,
5693         .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
5694         .display_config_changed = smu7_display_configuration_changed_task,
5695         .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
5696         .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
5697         .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
5698         .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
5699         .get_fan_speed_pwm = smu7_fan_ctrl_get_fan_speed_pwm,
5700         .set_fan_speed_pwm = smu7_fan_ctrl_set_fan_speed_pwm,
5701         .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
5702         .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
5703         .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
5704         .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
5705         .register_irq_handlers = smu7_register_irq_handlers,
5706         .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
5707         .check_states_equal = smu7_check_states_equal,
5708         .set_fan_control_mode = smu7_set_fan_control_mode,
5709         .get_fan_control_mode = smu7_get_fan_control_mode,
5710         .force_clock_level = smu7_force_clock_level,
5711         .print_clock_levels = smu7_print_clock_levels,
5712         .powergate_gfx = smu7_powergate_gfx,
5713         .get_sclk_od = smu7_get_sclk_od,
5714         .set_sclk_od = smu7_set_sclk_od,
5715         .get_mclk_od = smu7_get_mclk_od,
5716         .set_mclk_od = smu7_set_mclk_od,
5717         .get_clock_by_type = smu7_get_clock_by_type,
5718         .get_clock_by_type_with_latency = smu7_get_clock_by_type_with_latency,
5719         .set_watermarks_for_clocks_ranges = smu7_set_watermarks_for_clocks_ranges,
5720         .read_sensor = smu7_read_sensor,
5721         .dynamic_state_management_disable = smu7_disable_dpm_tasks,
5722         .avfs_control = smu7_avfs_control,
5723         .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
5724         .start_thermal_controller = smu7_start_thermal_controller,
5725         .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
5726         .get_max_high_clocks = smu7_get_max_high_clocks,
5727         .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
5728         .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
5729         .set_power_limit = smu7_set_power_limit,
5730         .get_power_profile_mode = smu7_get_power_profile_mode,
5731         .set_power_profile_mode = smu7_set_power_profile_mode,
5732         .get_performance_level = smu7_get_performance_level,
5733         .get_asic_baco_capability = smu7_baco_get_capability,
5734         .get_asic_baco_state = smu7_baco_get_state,
5735         .set_asic_baco_state = smu7_baco_set_state,
5736         .power_off_asic = smu7_power_off_asic,
5737 };
5738
5739 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
5740                 uint32_t clock_insr)
5741 {
5742         uint8_t i;
5743         uint32_t temp;
5744         uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
5745
5746         PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
5747         for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
5748                 temp = clock >> i;
5749
5750                 if (temp >= min || i == 0)
5751                         break;
5752         }
5753         return i;
5754 }
5755
5756 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
5757 {
5758         hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
5759         if (hwmgr->pp_table_version == PP_TABLE_V0)
5760                 hwmgr->pptable_func = &pptable_funcs;
5761         else if (hwmgr->pp_table_version == PP_TABLE_V1)
5762                 hwmgr->pptable_func = &pptable_v1_0_funcs;
5763
5764         return 0;
5765 }