drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/delay.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27 #include <linux/slab.h>
  28 #include <asm/div64.h>
  29 #if IS_ENABLED(CONFIG_X86_64)
  30 #include <asm/intel-family.h>
  31 #endif
  32 #include <drm/amdgpu_drm.h>
  33 #include "ppatomctrl.h"
  34 #include "atombios.h"
  35 #include "pptable_v1_0.h"
  36 #include "pppcielanes.h"
  37 #include "amd_pcie_helpers.h"
  38 #include "hardwaremanager.h"
  39 #include "process_pptables_v1_0.h"
  40 #include "cgs_common.h"
  41
  42 #include "smu7_common.h"
  43
  44 #include "hwmgr.h"
  45 #include "smu7_hwmgr.h"
  46 #include "smu_ucode_xfer_vi.h"
  47 #include "smu7_powertune.h"
  48 #include "smu7_dyn_defaults.h"
  49 #include "smu7_thermal.h"
  50 #include "smu7_clockpowergating.h"
  51 #include "processpptables.h"
  52 #include "pp_thermal.h"
  53 #include "smu7_baco.h"
  54 #include "smu7_smumgr.h"
  55 #include "polaris10_smumgr.h"
  56
  57 #include "ivsrcid/ivsrcid_vislands30.h"
  58
  59 #define MC_CG_ARB_FREQ_F0           0x0a
  60 #define MC_CG_ARB_FREQ_F1           0x0b
  61 #define MC_CG_ARB_FREQ_F2           0x0c
  62 #define MC_CG_ARB_FREQ_F3           0x0d
  63
  64 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  65 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  66 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  67 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  68
  69 #define SMC_CG_IND_START            0xc0030000
  70 #define SMC_CG_IND_END              0xc0040000
  71
  72 #define MEM_FREQ_LOW_LATENCY        25000
  73 #define MEM_FREQ_HIGH_LATENCY       80000
  74
  75 #define MEM_LATENCY_HIGH            45
  76 #define MEM_LATENCY_LOW             35
  77 #define MEM_LATENCY_ERR             0xFFFF
  78
  79 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  80 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  81 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  82
  83 #define PCIE_BUS_CLK                10000
  84 #define TCLK                        (PCIE_BUS_CLK / 10)
  85
  86 static struct profile_mode_setting smu7_profiling[7] = {
  87                                          {0, 0, 0, 0, 0, 0, 0, 0},
  88                                          {1, 0, 100, 30, 1, 0, 100, 10},
  89                                          {1, 10, 0, 30, 0, 0, 0, 0},
  90                                          {0, 0, 0, 0, 1, 10, 16, 31},
  91                                          {1, 0, 11, 50, 1, 0, 100, 10},
  92                                          {1, 0, 5, 30, 0, 0, 0, 0},
  93                                          {0, 0, 0, 0, 0, 0, 0, 0},
  94 };
  95
  96 #define PPSMC_MSG_SetVBITimeout_VEGAM    ((uint16_t) 0x310)
  97
  98 #define ixPWR_SVI2_PLANE1_LOAD                     0xC0200280
  99 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK                    0x00000020L
 100 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK                 0x00000040L
 101 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT                  0x00000005
 102 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT               0x00000006
 103
 104 #define STRAP_EVV_REVISION_MSB          2211
 105 #define STRAP_EVV_REVISION_LSB          2208
 106
 107 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 108 enum DPM_EVENT_SRC {
 109         DPM_EVENT_SRC_ANALOG = 0,
 110         DPM_EVENT_SRC_EXTERNAL = 1,
 111         DPM_EVENT_SRC_DIGITAL = 2,
 112         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 113         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 114 };
 115
 116 #define ixDIDT_SQ_EDC_CTRL                         0x0013
 117 #define ixDIDT_SQ_EDC_THRESHOLD                    0x0014
 118 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2            0x0015
 119 #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4            0x0016
 120 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6            0x0017
 121 #define ixDIDT_SQ_EDC_STALL_PATTERN_7              0x0018
 122
 123 #define ixDIDT_TD_EDC_CTRL                         0x0053
 124 #define ixDIDT_TD_EDC_THRESHOLD                    0x0054
 125 #define ixDIDT_TD_EDC_STALL_PATTERN_1_2            0x0055
 126 #define ixDIDT_TD_EDC_STALL_PATTERN_3_4            0x0056
 127 #define ixDIDT_TD_EDC_STALL_PATTERN_5_6            0x0057
 128 #define ixDIDT_TD_EDC_STALL_PATTERN_7              0x0058
 129
 130 #define ixDIDT_TCP_EDC_CTRL                        0x0073
 131 #define ixDIDT_TCP_EDC_THRESHOLD                   0x0074
 132 #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2           0x0075
 133 #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4           0x0076
 134 #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6           0x0077
 135 #define ixDIDT_TCP_EDC_STALL_PATTERN_7             0x0078
 136
 137 #define ixDIDT_DB_EDC_CTRL                         0x0033
 138 #define ixDIDT_DB_EDC_THRESHOLD                    0x0034
 139 #define ixDIDT_DB_EDC_STALL_PATTERN_1_2            0x0035
 140 #define ixDIDT_DB_EDC_STALL_PATTERN_3_4            0x0036
 141 #define ixDIDT_DB_EDC_STALL_PATTERN_5_6            0x0037
 142 #define ixDIDT_DB_EDC_STALL_PATTERN_7              0x0038
 143
 144 uint32_t DIDTEDCConfig_P12[] = {
 145     ixDIDT_SQ_EDC_STALL_PATTERN_1_2,
 146     ixDIDT_SQ_EDC_STALL_PATTERN_3_4,
 147     ixDIDT_SQ_EDC_STALL_PATTERN_5_6,
 148     ixDIDT_SQ_EDC_STALL_PATTERN_7,
 149     ixDIDT_SQ_EDC_THRESHOLD,
 150     ixDIDT_SQ_EDC_CTRL,
 151     ixDIDT_TD_EDC_STALL_PATTERN_1_2,
 152     ixDIDT_TD_EDC_STALL_PATTERN_3_4,
 153     ixDIDT_TD_EDC_STALL_PATTERN_5_6,
 154     ixDIDT_TD_EDC_STALL_PATTERN_7,
 155     ixDIDT_TD_EDC_THRESHOLD,
 156     ixDIDT_TD_EDC_CTRL,
 157     ixDIDT_TCP_EDC_STALL_PATTERN_1_2,
 158     ixDIDT_TCP_EDC_STALL_PATTERN_3_4,
 159     ixDIDT_TCP_EDC_STALL_PATTERN_5_6,
 160     ixDIDT_TCP_EDC_STALL_PATTERN_7,
 161     ixDIDT_TCP_EDC_THRESHOLD,
 162     ixDIDT_TCP_EDC_CTRL,
 163     ixDIDT_DB_EDC_STALL_PATTERN_1_2,
 164     ixDIDT_DB_EDC_STALL_PATTERN_3_4,
 165     ixDIDT_DB_EDC_STALL_PATTERN_5_6,
 166     ixDIDT_DB_EDC_STALL_PATTERN_7,
 167     ixDIDT_DB_EDC_THRESHOLD,
 168     ixDIDT_DB_EDC_CTRL,
 169     0xFFFFFFFF // End of list
 170 };
 171
 172 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
 173 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
 174                 enum pp_clock_type type, uint32_t mask);
 175 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr);
 176
 177 static struct smu7_power_state *cast_phw_smu7_power_state(
 178                                   struct pp_hw_power_state *hw_ps)
 179 {
 180         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 181                                 "Invalid Powerstate Type!",
 182                                  return NULL);
 183
 184         return (struct smu7_power_state *)hw_ps;
 185 }
 186
 187 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
 188                                  const struct pp_hw_power_state *hw_ps)
 189 {
 190         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 191                                 "Invalid Powerstate Type!",
 192                                  return NULL);
 193
 194         return (const struct smu7_power_state *)hw_ps;
 195 }
 196
 197 /**
 198  * smu7_get_mc_microcode_version - Find the MC microcode version and store it in the HwMgr struct
 199  *
 200  * @hwmgr:  the address of the powerplay hardware manager.
 201  * Return:   always 0
 202  */
 203 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
 204 {
 205         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 206
 207         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 208
 209         return 0;
 210 }
 211
 212 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 213 {
 214         uint32_t speedCntl = 0;
 215
 216         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 217         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 218                         ixPCIE_LC_SPEED_CNTL);
 219         return((uint16_t)PHM_GET_FIELD(speedCntl,
 220                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 221 }
 222
 223 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 224 {
 225         uint32_t link_width;
 226
 227         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 228         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 229                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 230
 231         PP_ASSERT_WITH_CODE((7 >= link_width),
 232                         "Invalid PCIe lane width!", return 0);
 233
 234         return decode_pcie_lane_width(link_width);
 235 }
 236
 237 /**
 238  * smu7_enable_smc_voltage_controller - Enable voltage control
 239  *
 240  * @hwmgr:  the address of the powerplay hardware manager.
 241  * Return:   always PP_Result_OK
 242  */
 243 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 244 {
 245         if (hwmgr->chip_id >= CHIP_POLARIS10 &&
 246             hwmgr->chip_id <= CHIP_VEGAM) {
 247                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 248                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
 249                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 250                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
 251         }
 252
 253         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
 254                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL);
 255
 256         return 0;
 257 }
 258
 259 /**
 260  * smu7_voltage_control - Checks if we want to support voltage control
 261  *
 262  * @hwmgr:  the address of the powerplay hardware manager.
 263  */
 264 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
 265 {
 266         const struct smu7_hwmgr *data =
 267                         (const struct smu7_hwmgr *)(hwmgr->backend);
 268
 269         return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
 270 }
 271
 272 /**
 273  * smu7_enable_voltage_control - Enable voltage control
 274  *
 275  * @hwmgr:  the address of the powerplay hardware manager.
 276  * Return:   always 0
 277  */
 278 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
 279 {
 280         /* enable voltage control */
 281         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 282                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 283
 284         return 0;
 285 }
 286
 287 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
 288                 struct phm_clock_voltage_dependency_table *voltage_dependency_table
 289                 )
 290 {
 291         uint32_t i;
 292
 293         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 294                         "Voltage Dependency Table empty.", return -EINVAL;);
 295
 296         voltage_table->mask_low = 0;
 297         voltage_table->phase_delay = 0;
 298         voltage_table->count = voltage_dependency_table->count;
 299
 300         for (i = 0; i < voltage_dependency_table->count; i++) {
 301                 voltage_table->entries[i].value =
 302                         voltage_dependency_table->entries[i].v;
 303                 voltage_table->entries[i].smio_low = 0;
 304         }
 305
 306         return 0;
 307 }
 308
 309
 310 /**
 311  * smu7_construct_voltage_tables - Create Voltage Tables.
 312  *
 313  * @hwmgr:  the address of the powerplay hardware manager.
 314  * Return:   always 0
 315  */
 316 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 317 {
 318         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 319         struct phm_ppt_v1_information *table_info =
 320                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 321         int result = 0;
 322         uint32_t tmp;
 323
 324         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 325                 result = atomctrl_get_voltage_table_v3(hwmgr,
 326                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 327                                 &(data->mvdd_voltage_table));
 328                 PP_ASSERT_WITH_CODE((0 == result),
 329                                 "Failed to retrieve MVDD table.",
 330                                 return result);
 331         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 332                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 333                         result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 334                                         table_info->vdd_dep_on_mclk);
 335                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 336                         result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
 337                                         hwmgr->dyn_state.mvdd_dependency_on_mclk);
 338
 339                 PP_ASSERT_WITH_CODE((0 == result),
 340                                 "Failed to retrieve SVI2 MVDD table from dependency table.",
 341                                 return result;);
 342         }
 343
 344         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 345                 result = atomctrl_get_voltage_table_v3(hwmgr,
 346                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 347                                 &(data->vddci_voltage_table));
 348                 PP_ASSERT_WITH_CODE((0 == result),
 349                                 "Failed to retrieve VDDCI table.",
 350                                 return result);
 351         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 352                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 353                         result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 354                                         table_info->vdd_dep_on_mclk);
 355                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 356                         result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
 357                                         hwmgr->dyn_state.vddci_dependency_on_mclk);
 358                 PP_ASSERT_WITH_CODE((0 == result),
 359                                 "Failed to retrieve SVI2 VDDCI table from dependency table.",
 360                                 return result);
 361         }
 362
 363         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
 364                 /* VDDGFX has only SVI2 voltage control */
 365                 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
 366                                         table_info->vddgfx_lookup_table);
 367                 PP_ASSERT_WITH_CODE((0 == result),
 368                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
 369         }
 370
 371
 372         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
 373                 result = atomctrl_get_voltage_table_v3(hwmgr,
 374                                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
 375                                         &data->vddc_voltage_table);
 376                 PP_ASSERT_WITH_CODE((0 == result),
 377                         "Failed to retrieve VDDC table.", return result;);
 378         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 379
 380                 if (hwmgr->pp_table_version == PP_TABLE_V0)
 381                         result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
 382                                         hwmgr->dyn_state.vddc_dependency_on_mclk);
 383                 else if (hwmgr->pp_table_version == PP_TABLE_V1)
 384                         result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 385                                 table_info->vddc_lookup_table);
 386
 387                 PP_ASSERT_WITH_CODE((0 == result),
 388                         "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
 389         }
 390
 391         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
 392         PP_ASSERT_WITH_CODE(
 393                         (data->vddc_voltage_table.count <= tmp),
 394                 "Too many voltage values for VDDC. Trimming to fit state table.",
 395                         phm_trim_voltage_table_to_fit_state_table(tmp,
 396                                                 &(data->vddc_voltage_table)));
 397
 398         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
 399         PP_ASSERT_WITH_CODE(
 400                         (data->vddgfx_voltage_table.count <= tmp),
 401                 "Too many voltage values for VDDC. Trimming to fit state table.",
 402                         phm_trim_voltage_table_to_fit_state_table(tmp,
 403                                                 &(data->vddgfx_voltage_table)));
 404
 405         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
 406         PP_ASSERT_WITH_CODE(
 407                         (data->vddci_voltage_table.count <= tmp),
 408                 "Too many voltage values for VDDCI. Trimming to fit state table.",
 409                         phm_trim_voltage_table_to_fit_state_table(tmp,
 410                                         &(data->vddci_voltage_table)));
 411
 412         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
 413         PP_ASSERT_WITH_CODE(
 414                         (data->mvdd_voltage_table.count <= tmp),
 415                 "Too many voltage values for MVDD. Trimming to fit state table.",
 416                         phm_trim_voltage_table_to_fit_state_table(tmp,
 417                                                 &(data->mvdd_voltage_table)));
 418
 419         return 0;
 420 }
 421
 422 /**
 423  * smu7_program_static_screen_threshold_parameters - Programs static screed detection parameters
 424  *
 425  * @hwmgr:  the address of the powerplay hardware manager.
 426  * Return:   always 0
 427  */
 428 static int smu7_program_static_screen_threshold_parameters(
 429                                                         struct pp_hwmgr *hwmgr)
 430 {
 431         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 432
 433         /* Set static screen threshold unit */
 434         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 435                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 436                         data->static_screen_threshold_unit);
 437         /* Set static screen threshold */
 438         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 439                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 440                         data->static_screen_threshold);
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * smu7_enable_display_gap - Setup display gap for glitch free memory clock switching.
 447  *
 448  * @hwmgr:  the address of the powerplay hardware manager.
 449  * Return:   always  0
 450  */
 451 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
 452 {
 453         uint32_t display_gap =
 454                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 455                                         ixCG_DISPLAY_GAP_CNTL);
 456
 457         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 458                         DISP_GAP, DISPLAY_GAP_IGNORE);
 459
 460         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 461                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 462
 463         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 464                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 465
 466         return 0;
 467 }
 468
 469 /**
 470  * smu7_program_voting_clients - Programs activity state transition voting clients
 471  *
 472  * @hwmgr:  the address of the powerplay hardware manager.
 473  * Return:   always  0
 474  */
 475 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
 476 {
 477         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 478         int i;
 479
 480         /* Clear reset for voting clients before enabling DPM */
 481         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 482                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 483         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 484                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 485
 486         for (i = 0; i < 8; i++)
 487                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 488                                         ixCG_FREQ_TRAN_VOTING_0 + i * 4,
 489                                         data->voting_rights_clients[i]);
 490         return 0;
 491 }
 492
 493 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
 494 {
 495         int i;
 496
 497         /* Reset voting clients before disabling DPM */
 498         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 499                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
 500         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 501                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
 502
 503         for (i = 0; i < 8; i++)
 504                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 505                                 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
 506
 507         return 0;
 508 }
 509
 510 /* Copy one arb setting to another and then switch the active set.
 511  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 512  */
 513 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 514                 uint32_t arb_src, uint32_t arb_dest)
 515 {
 516         uint32_t mc_arb_dram_timing;
 517         uint32_t mc_arb_dram_timing2;
 518         uint32_t burst_time;
 519         uint32_t mc_cg_config;
 520
 521         switch (arb_src) {
 522         case MC_CG_ARB_FREQ_F0:
 523                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 524                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 525                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 526                 break;
 527         case MC_CG_ARB_FREQ_F1:
 528                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 529                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 530                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 531                 break;
 532         default:
 533                 return -EINVAL;
 534         }
 535
 536         switch (arb_dest) {
 537         case MC_CG_ARB_FREQ_F0:
 538                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 539                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 540                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 541                 break;
 542         case MC_CG_ARB_FREQ_F1:
 543                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 544                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 545                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 546                 break;
 547         default:
 548                 return -EINVAL;
 549         }
 550
 551         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 552         mc_cg_config |= 0x0000000F;
 553         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 554         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 555
 556         return 0;
 557 }
 558
 559 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
 560 {
 561         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL);
 562 }
 563
 564 /**
 565  * smu7_initial_switch_from_arbf0_to_f1 - Initial switch from ARB F0->F1
 566  *
 567  * @hwmgr:  the address of the powerplay hardware manager.
 568  * Return:   always 0
 569  * This function is to be called from the SetPowerState table.
 570  */
 571 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 572 {
 573         return smu7_copy_and_switch_arb_sets(hwmgr,
 574                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 575 }
 576
 577 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
 578 {
 579         uint32_t tmp;
 580
 581         tmp = (cgs_read_ind_register(hwmgr->device,
 582                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
 583                         0x0000ff00) >> 8;
 584
 585         if (tmp == MC_CG_ARB_FREQ_F0)
 586                 return 0;
 587
 588         return smu7_copy_and_switch_arb_sets(hwmgr,
 589                         tmp, MC_CG_ARB_FREQ_F0);
 590 }
 591
 592 static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr)
 593 {
 594         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 595         uint16_t pcie_gen = 0;
 596
 597         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 &&
 598             adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4)
 599                 pcie_gen = 3;
 600         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 &&
 601                 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
 602                 pcie_gen = 2;
 603         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 &&
 604                 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2)
 605                 pcie_gen = 1;
 606         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 &&
 607                 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1)
 608                 pcie_gen = 0;
 609
 610         return pcie_gen;
 611 }
 612
 613 static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr)
 614 {
 615         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 616         uint16_t pcie_width = 0;
 617
 618         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 619                 pcie_width = 16;
 620         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 621                 pcie_width = 12;
 622         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 623                 pcie_width = 8;
 624         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 625                 pcie_width = 4;
 626         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 627                 pcie_width = 2;
 628         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 629                 pcie_width = 1;
 630
 631         return pcie_width;
 632 }
 633
 634 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 635 {
 636         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 637
 638         struct phm_ppt_v1_information *table_info =
 639                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 640         struct phm_ppt_v1_pcie_table *pcie_table = NULL;
 641
 642         uint32_t i, max_entry;
 643         uint32_t tmp;
 644
 645         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 646                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 647                         return -EINVAL);
 648
 649         if (table_info != NULL)
 650                 pcie_table = table_info->pcie_table;
 651
 652         if (data->use_pcie_performance_levels &&
 653                         !data->use_pcie_power_saving_levels) {
 654                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 655                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 656         } else if (!data->use_pcie_performance_levels &&
 657                         data->use_pcie_power_saving_levels) {
 658                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 659                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 660         }
 661         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
 662         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 663                                         tmp,
 664                                         MAX_REGULAR_DPM_NUMBER);
 665
 666         if (pcie_table != NULL) {
 667                 /* max_entry is used to make sure we reserve one PCIE level
 668                  * for boot level (fix for A+A PSPP issue).
 669                  * If PCIE table from PPTable have ULV entry + 8 entries,
 670                  * then ignore the last entry.*/
 671                 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
 672                 for (i = 1; i < max_entry; i++) {
 673                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 674                                         get_pcie_gen_support(data->pcie_gen_cap,
 675                                                         pcie_table->entries[i].gen_speed),
 676                                         get_pcie_lane_support(data->pcie_lane_cap,
 677                                                         pcie_table->entries[i].lane_width));
 678                 }
 679                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 680                 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
 681         } else {
 682                 /* Hardcode Pcie Table */
 683                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 684                                 get_pcie_gen_support(data->pcie_gen_cap,
 685                                                 PP_Min_PCIEGen),
 686                                 get_pcie_lane_support(data->pcie_lane_cap,
 687                                                 PP_Max_PCIELane));
 688                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 689                                 get_pcie_gen_support(data->pcie_gen_cap,
 690                                                 PP_Min_PCIEGen),
 691                                 get_pcie_lane_support(data->pcie_lane_cap,
 692                                                 PP_Max_PCIELane));
 693                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 694                                 get_pcie_gen_support(data->pcie_gen_cap,
 695                                                 PP_Max_PCIEGen),
 696                                 get_pcie_lane_support(data->pcie_lane_cap,
 697                                                 PP_Max_PCIELane));
 698                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 699                                 get_pcie_gen_support(data->pcie_gen_cap,
 700                                                 PP_Max_PCIEGen),
 701                                 get_pcie_lane_support(data->pcie_lane_cap,
 702                                                 PP_Max_PCIELane));
 703                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 704                                 get_pcie_gen_support(data->pcie_gen_cap,
 705                                                 PP_Max_PCIEGen),
 706                                 get_pcie_lane_support(data->pcie_lane_cap,
 707                                                 PP_Max_PCIELane));
 708                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 709                                 get_pcie_gen_support(data->pcie_gen_cap,
 710                                                 PP_Max_PCIEGen),
 711                                 get_pcie_lane_support(data->pcie_lane_cap,
 712                                                 PP_Max_PCIELane));
 713
 714                 data->dpm_table.pcie_speed_table.count = 6;
 715         }
 716         /* Populate last level for boot PCIE level, but do not increment count. */
 717         if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
 718                 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
 719                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
 720                                 get_pcie_gen_support(data->pcie_gen_cap,
 721                                                 PP_Max_PCIEGen),
 722                                 data->vbios_boot_state.pcie_lane_bootup_value);
 723         } else {
 724                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 725                         data->dpm_table.pcie_speed_table.count,
 726                         get_pcie_gen_support(data->pcie_gen_cap,
 727                                         PP_Min_PCIEGen),
 728                         get_pcie_lane_support(data->pcie_lane_cap,
 729                                         PP_Max_PCIELane));
 730
 731                 if (data->pcie_dpm_key_disabled)
 732                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 733                                 data->dpm_table.pcie_speed_table.count,
 734                                 smu7_override_pcie_speed(hwmgr), smu7_override_pcie_width(hwmgr));
 735         }
 736         return 0;
 737 }
 738
 739 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
 740 {
 741         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 742
 743         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
 744
 745         phm_reset_single_dpm_table(
 746                         &data->dpm_table.sclk_table,
 747                                 smum_get_mac_definition(hwmgr,
 748                                         SMU_MAX_LEVELS_GRAPHICS),
 749                                         MAX_REGULAR_DPM_NUMBER);
 750         phm_reset_single_dpm_table(
 751                         &data->dpm_table.mclk_table,
 752                         smum_get_mac_definition(hwmgr,
 753                                 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
 754
 755         phm_reset_single_dpm_table(
 756                         &data->dpm_table.vddc_table,
 757                                 smum_get_mac_definition(hwmgr,
 758                                         SMU_MAX_LEVELS_VDDC),
 759                                         MAX_REGULAR_DPM_NUMBER);
 760         phm_reset_single_dpm_table(
 761                         &data->dpm_table.vddci_table,
 762                         smum_get_mac_definition(hwmgr,
 763                                 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
 764
 765         phm_reset_single_dpm_table(
 766                         &data->dpm_table.mvdd_table,
 767                                 smum_get_mac_definition(hwmgr,
 768                                         SMU_MAX_LEVELS_MVDD),
 769                                         MAX_REGULAR_DPM_NUMBER);
 770         return 0;
 771 }
 772 /*
 773  * This function is to initialize all DPM state tables
 774  * for SMU7 based on the dependency table.
 775  * Dynamic state patching function will then trim these
 776  * state tables to the allowed range based
 777  * on the power policy or external client requests,
 778  * such as UVD request, etc.
 779  */
 780
 781 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
 782 {
 783         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 784         struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
 785                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 786         struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
 787                 hwmgr->dyn_state.vddc_dependency_on_mclk;
 788         struct phm_cac_leakage_table *std_voltage_table =
 789                 hwmgr->dyn_state.cac_leakage_table;
 790         uint32_t i;
 791
 792         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
 793                 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
 794         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
 795                 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 796
 797         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 798                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 799         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
 800                 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 801
 802
 803         /* Initialize Sclk DPM table based on allow Sclk values*/
 804         data->dpm_table.sclk_table.count = 0;
 805
 806         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 807                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
 808                                 allowed_vdd_sclk_table->entries[i].clk) {
 809                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 810                                 allowed_vdd_sclk_table->entries[i].clk;
 811                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
 812                         data->dpm_table.sclk_table.count++;
 813                 }
 814         }
 815
 816         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 817                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 818         /* Initialize Mclk DPM table based on allow Mclk values */
 819         data->dpm_table.mclk_table.count = 0;
 820         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 821                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
 822                         allowed_vdd_mclk_table->entries[i].clk) {
 823                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 824                                 allowed_vdd_mclk_table->entries[i].clk;
 825                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
 826                         data->dpm_table.mclk_table.count++;
 827                 }
 828         }
 829
 830         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
 831         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 832                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 833                 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
 834                 /* param1 is for corresponding std voltage */
 835                 data->dpm_table.vddc_table.dpm_levels[i].enabled = true;
 836         }
 837
 838         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
 839         allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
 840
 841         if (NULL != allowed_vdd_mclk_table) {
 842                 /* Initialize Vddci DPM table based on allow Mclk values */
 843                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 844                         data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 845                         data->dpm_table.vddci_table.dpm_levels[i].enabled = true;
 846                 }
 847                 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
 848         }
 849
 850         allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
 851
 852         if (NULL != allowed_vdd_mclk_table) {
 853                 /*
 854                  * Initialize MVDD DPM table based on allow Mclk
 855                  * values
 856                  */
 857                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 858                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 859                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
 860                 }
 861                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
 868 {
 869         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 870         struct phm_ppt_v1_information *table_info =
 871                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 872         uint32_t i;
 873
 874         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 875         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 876
 877         if (table_info == NULL)
 878                 return -EINVAL;
 879
 880         dep_sclk_table = table_info->vdd_dep_on_sclk;
 881         dep_mclk_table = table_info->vdd_dep_on_mclk;
 882
 883         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 884                         "SCLK dependency table is missing.",
 885                         return -EINVAL);
 886         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 887                         "SCLK dependency table count is 0.",
 888                         return -EINVAL);
 889
 890         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 891                         "MCLK dependency table is missing.",
 892                         return -EINVAL);
 893         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 894                         "MCLK dependency table count is 0",
 895                         return -EINVAL);
 896
 897         /* Initialize Sclk DPM table based on allow Sclk values */
 898         data->dpm_table.sclk_table.count = 0;
 899         for (i = 0; i < dep_sclk_table->count; i++) {
 900                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 901                                                 dep_sclk_table->entries[i].clk) {
 902
 903                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 904                                         dep_sclk_table->entries[i].clk;
 905
 906                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 907                                         i == 0;
 908                         data->dpm_table.sclk_table.count++;
 909                 }
 910         }
 911         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
 912                 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
 913         /* Initialize Mclk DPM table based on allow Mclk values */
 914         data->dpm_table.mclk_table.count = 0;
 915         for (i = 0; i < dep_mclk_table->count; i++) {
 916                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 917                                 [data->dpm_table.mclk_table.count - 1].value !=
 918                                                 dep_mclk_table->entries[i].clk) {
 919                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 920                                                         dep_mclk_table->entries[i].clk;
 921                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 922                                                         i == 0;
 923                         data->dpm_table.mclk_table.count++;
 924                 }
 925         }
 926
 927         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
 928                 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
 929         return 0;
 930 }
 931
 932 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 933 {
 934         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 935         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 936         struct phm_ppt_v1_information *table_info =
 937                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 938         uint32_t i;
 939
 940         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 941         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 942         struct phm_odn_performance_level *entries;
 943
 944         if (table_info == NULL)
 945                 return -EINVAL;
 946
 947         dep_sclk_table = table_info->vdd_dep_on_sclk;
 948         dep_mclk_table = table_info->vdd_dep_on_mclk;
 949
 950         odn_table->odn_core_clock_dpm_levels.num_of_pl =
 951                                                 data->golden_dpm_table.sclk_table.count;
 952         entries = odn_table->odn_core_clock_dpm_levels.entries;
 953         for (i = 0; i < data->golden_dpm_table.sclk_table.count; i++) {
 954                 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
 955                 entries[i].enabled = true;
 956                 entries[i].vddc = dep_sclk_table->entries[i].vddc;
 957         }
 958
 959         smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
 960                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
 961
 962         odn_table->odn_memory_clock_dpm_levels.num_of_pl =
 963                                                 data->golden_dpm_table.mclk_table.count;
 964         entries = odn_table->odn_memory_clock_dpm_levels.entries;
 965         for (i = 0; i < data->golden_dpm_table.mclk_table.count; i++) {
 966                 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
 967                 entries[i].enabled = true;
 968                 entries[i].vddc = dep_mclk_table->entries[i].vddc;
 969         }
 970
 971         smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
 972                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
 973
 974         return 0;
 975 }
 976
 977 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
 978 {
 979         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 980         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 981         struct phm_ppt_v1_information *table_info =
 982                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 983         uint32_t min_vddc = 0;
 984         uint32_t max_vddc = 0;
 985
 986         if (!table_info)
 987                 return;
 988
 989         dep_sclk_table = table_info->vdd_dep_on_sclk;
 990
 991         atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
 992
 993         if (min_vddc == 0 || min_vddc > 2000
 994                 || min_vddc > dep_sclk_table->entries[0].vddc)
 995                 min_vddc = dep_sclk_table->entries[0].vddc;
 996
 997         if (max_vddc == 0 || max_vddc > 2000
 998                 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
 999                 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
1000
1001         data->odn_dpm_table.min_vddc = min_vddc;
1002         data->odn_dpm_table.max_vddc = max_vddc;
1003 }
1004
1005 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
1006 {
1007         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1008         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
1009         struct phm_ppt_v1_information *table_info =
1010                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1011         uint32_t i;
1012
1013         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1014         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
1015
1016         if (table_info == NULL)
1017                 return;
1018
1019         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1020                 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
1021                                         data->dpm_table.sclk_table.dpm_levels[i].value) {
1022                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
1023                         break;
1024                 }
1025         }
1026
1027         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1028                 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
1029                                         data->dpm_table.mclk_table.dpm_levels[i].value) {
1030                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
1031                         break;
1032                 }
1033         }
1034
1035         dep_table = table_info->vdd_dep_on_mclk;
1036         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
1037
1038         for (i = 0; i < dep_table->count; i++) {
1039                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
1040                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
1041                         return;
1042                 }
1043         }
1044
1045         dep_table = table_info->vdd_dep_on_sclk;
1046         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
1047         for (i = 0; i < dep_table->count; i++) {
1048                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
1049                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
1050                         return;
1051                 }
1052         }
1053         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1054                 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
1055                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
1056         }
1057 }
1058
1059 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1060 {
1061         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1062
1063         smu7_reset_dpm_tables(hwmgr);
1064
1065         if (hwmgr->pp_table_version == PP_TABLE_V1)
1066                 smu7_setup_dpm_tables_v1(hwmgr);
1067         else if (hwmgr->pp_table_version == PP_TABLE_V0)
1068                 smu7_setup_dpm_tables_v0(hwmgr);
1069
1070         smu7_setup_default_pcie_table(hwmgr);
1071
1072         /* save a copy of the default DPM table */
1073         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1074                         sizeof(struct smu7_dpm_table));
1075
1076         /* initialize ODN table */
1077         if (hwmgr->od_enabled) {
1078                 if (data->odn_dpm_table.max_vddc) {
1079                         smu7_check_dpm_table_updated(hwmgr);
1080                 } else {
1081                         smu7_setup_voltage_range_from_vbios(hwmgr);
1082                         smu7_odn_initial_default_setting(hwmgr);
1083                 }
1084         }
1085         return 0;
1086 }
1087
1088 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
1089 {
1090
1091         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1092                         PHM_PlatformCaps_RegulatorHot))
1093                 return smum_send_msg_to_smc(hwmgr,
1094                                 PPSMC_MSG_EnableVRHotGPIOInterrupt,
1095                                 NULL);
1096
1097         return 0;
1098 }
1099
1100 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
1101 {
1102         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1103                         SCLK_PWRMGT_OFF, 0);
1104         return 0;
1105 }
1106
1107 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
1108 {
1109         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1110
1111         if (data->ulv_supported)
1112                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL);
1113
1114         return 0;
1115 }
1116
1117 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1118 {
1119         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1120
1121         if (data->ulv_supported)
1122                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL);
1123
1124         return 0;
1125 }
1126
1127 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1128 {
1129         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1130                         PHM_PlatformCaps_SclkDeepSleep)) {
1131                 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL))
1132                         PP_ASSERT_WITH_CODE(false,
1133                                         "Attempt to enable Master Deep Sleep switch failed!",
1134                                         return -EINVAL);
1135         } else {
1136                 if (smum_send_msg_to_smc(hwmgr,
1137                                 PPSMC_MSG_MASTER_DeepSleep_OFF,
1138                                 NULL)) {
1139                         PP_ASSERT_WITH_CODE(false,
1140                                         "Attempt to disable Master Deep Sleep switch failed!",
1141                                         return -EINVAL);
1142                 }
1143         }
1144
1145         return 0;
1146 }
1147
1148 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1149 {
1150         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1151                         PHM_PlatformCaps_SclkDeepSleep)) {
1152                 if (smum_send_msg_to_smc(hwmgr,
1153                                 PPSMC_MSG_MASTER_DeepSleep_OFF,
1154                                 NULL)) {
1155                         PP_ASSERT_WITH_CODE(false,
1156                                         "Attempt to disable Master Deep Sleep switch failed!",
1157                                         return -EINVAL);
1158                 }
1159         }
1160
1161         return 0;
1162 }
1163
1164 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1165 {
1166         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1167         uint32_t soft_register_value = 0;
1168         uint32_t handshake_disables_offset = data->soft_regs_start
1169                                 + smum_get_offsetof(hwmgr,
1170                                         SMU_SoftRegisters, HandshakeDisables);
1171
1172         soft_register_value = cgs_read_ind_register(hwmgr->device,
1173                                 CGS_IND_REG__SMC, handshake_disables_offset);
1174         soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1175         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1176                         handshake_disables_offset, soft_register_value);
1177         return 0;
1178 }
1179
1180 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1181 {
1182         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1183         uint32_t soft_register_value = 0;
1184         uint32_t handshake_disables_offset = data->soft_regs_start
1185                                 + smum_get_offsetof(hwmgr,
1186                                         SMU_SoftRegisters, HandshakeDisables);
1187
1188         soft_register_value = cgs_read_ind_register(hwmgr->device,
1189                                 CGS_IND_REG__SMC, handshake_disables_offset);
1190         soft_register_value |= smum_get_mac_definition(hwmgr,
1191                                         SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1192         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1193                         handshake_disables_offset, soft_register_value);
1194         return 0;
1195 }
1196
1197 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1198 {
1199         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1200
1201         /* enable SCLK dpm */
1202         if (!data->sclk_dpm_key_disabled) {
1203                 if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1204                     hwmgr->chip_id <= CHIP_VEGAM)
1205                         smu7_disable_sclk_vce_handshake(hwmgr);
1206
1207                 PP_ASSERT_WITH_CODE(
1208                 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)),
1209                 "Failed to enable SCLK DPM during DPM Start Function!",
1210                 return -EINVAL);
1211         }
1212
1213         /* enable MCLK dpm */
1214         if (0 == data->mclk_dpm_key_disabled) {
1215                 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1216                         smu7_disable_handshake_uvd(hwmgr);
1217
1218                 PP_ASSERT_WITH_CODE(
1219                                 (0 == smum_send_msg_to_smc(hwmgr,
1220                                                 PPSMC_MSG_MCLKDPM_Enable,
1221                                                 NULL)),
1222                                 "Failed to enable MCLK DPM during DPM Start Function!",
1223                                 return -EINVAL);
1224
1225                 if ((hwmgr->chip_family == AMDGPU_FAMILY_CI) ||
1226                     (hwmgr->chip_id == CHIP_POLARIS10) ||
1227                     (hwmgr->chip_id == CHIP_POLARIS11) ||
1228                     (hwmgr->chip_id == CHIP_POLARIS12) ||
1229                     (hwmgr->chip_id == CHIP_TONGA) ||
1230                     (hwmgr->chip_id == CHIP_TOPAZ))
1231                         PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1232
1233
1234                 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1235                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1236                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1237                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1238                         udelay(10);
1239                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1240                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1241                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1242                 } else {
1243                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1244                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1245                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1246                         udelay(10);
1247                         if (hwmgr->chip_id == CHIP_VEGAM) {
1248                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1249                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1250                         } else {
1251                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1252                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1253                         }
1254                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1255                 }
1256         }
1257
1258         return 0;
1259 }
1260
1261 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1262 {
1263         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1264
1265         /*enable general power management */
1266
1267         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1268                         GLOBAL_PWRMGT_EN, 1);
1269
1270         /* enable sclk deep sleep */
1271
1272         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1273                         DYNAMIC_PM_EN, 1);
1274
1275         /* prepare for PCIE DPM */
1276
1277         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1278                         data->soft_regs_start +
1279                         smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1280                                                 VoltageChangeTimeout), 0x1000);
1281         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1282                         SWRST_COMMAND_1, RESETLC, 0x0);
1283
1284         if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1285                 cgs_write_register(hwmgr->device, 0x1488,
1286                         (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1287
1288         if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1289                 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1290                 return -EINVAL;
1291         }
1292
1293         /* enable PCIE dpm */
1294         if (0 == data->pcie_dpm_key_disabled) {
1295                 PP_ASSERT_WITH_CODE(
1296                                 (0 == smum_send_msg_to_smc(hwmgr,
1297                                                 PPSMC_MSG_PCIeDPM_Enable,
1298                                                 NULL)),
1299                                 "Failed to enable pcie DPM during DPM Start Function!",
1300                                 return -EINVAL);
1301         } else {
1302                 PP_ASSERT_WITH_CODE(
1303                                 (0 == smum_send_msg_to_smc(hwmgr,
1304                                                 PPSMC_MSG_PCIeDPM_Disable,
1305                                                 NULL)),
1306                                 "Failed to disable pcie DPM during DPM Start Function!",
1307                                 return -EINVAL);
1308         }
1309
1310         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1311                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
1312                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1313                                 PPSMC_MSG_EnableACDCGPIOInterrupt,
1314                                 NULL)),
1315                                 "Failed to enable AC DC GPIO Interrupt!",
1316                                 );
1317         }
1318
1319         return 0;
1320 }
1321
1322 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1323 {
1324         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1325
1326         /* disable SCLK dpm */
1327         if (!data->sclk_dpm_key_disabled) {
1328                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1329                                 "Trying to disable SCLK DPM when DPM is disabled",
1330                                 return 0);
1331                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL);
1332         }
1333
1334         /* disable MCLK dpm */
1335         if (!data->mclk_dpm_key_disabled) {
1336                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1337                                 "Trying to disable MCLK DPM when DPM is disabled",
1338                                 return 0);
1339                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL);
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1346 {
1347         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1348
1349         /* disable general power management */
1350         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1351                         GLOBAL_PWRMGT_EN, 0);
1352         /* disable sclk deep sleep */
1353         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1354                         DYNAMIC_PM_EN, 0);
1355
1356         /* disable PCIE dpm */
1357         if (!data->pcie_dpm_key_disabled) {
1358                 PP_ASSERT_WITH_CODE(
1359                                 (smum_send_msg_to_smc(hwmgr,
1360                                                 PPSMC_MSG_PCIeDPM_Disable,
1361                                                 NULL) == 0),
1362                                 "Failed to disable pcie DPM during DPM Stop Function!",
1363                                 return -EINVAL);
1364         }
1365
1366         smu7_disable_sclk_mclk_dpm(hwmgr);
1367
1368         PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1369                         "Trying to disable voltage DPM when DPM is disabled",
1370                         return 0);
1371
1372         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL);
1373
1374         return 0;
1375 }
1376
1377 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1378 {
1379         bool protection;
1380         enum DPM_EVENT_SRC src;
1381
1382         switch (sources) {
1383         default:
1384                 pr_err("Unknown throttling event sources.");
1385                 fallthrough;
1386         case 0:
1387                 protection = false;
1388                 /* src is unused */
1389                 break;
1390         case (1 << PHM_AutoThrottleSource_Thermal):
1391                 protection = true;
1392                 src = DPM_EVENT_SRC_DIGITAL;
1393                 break;
1394         case (1 << PHM_AutoThrottleSource_External):
1395                 protection = true;
1396                 src = DPM_EVENT_SRC_EXTERNAL;
1397                 break;
1398         case (1 << PHM_AutoThrottleSource_External) |
1399                         (1 << PHM_AutoThrottleSource_Thermal):
1400                 protection = true;
1401                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1402                 break;
1403         }
1404         /* Order matters - don't enable thermal protection for the wrong source. */
1405         if (protection) {
1406                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1407                                 DPM_EVENT_SRC, src);
1408                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1409                                 THERMAL_PROTECTION_DIS,
1410                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1411                                                 PHM_PlatformCaps_ThermalController));
1412         } else
1413                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1414                                 THERMAL_PROTECTION_DIS, 1);
1415 }
1416
1417 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1418                 PHM_AutoThrottleSource source)
1419 {
1420         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1421
1422         if (!(data->active_auto_throttle_sources & (1 << source))) {
1423                 data->active_auto_throttle_sources |= 1 << source;
1424                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1425         }
1426         return 0;
1427 }
1428
1429 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1430 {
1431         return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1432 }
1433
1434 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1435                 PHM_AutoThrottleSource source)
1436 {
1437         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1438
1439         if (data->active_auto_throttle_sources & (1 << source)) {
1440                 data->active_auto_throttle_sources &= ~(1 << source);
1441                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1442         }
1443         return 0;
1444 }
1445
1446 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1447 {
1448         return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1449 }
1450
1451 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1452 {
1453         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1454         data->pcie_performance_request = true;
1455
1456         return 0;
1457 }
1458
1459 static int smu7_program_edc_didt_registers(struct pp_hwmgr *hwmgr,
1460                                            uint32_t *cac_config_regs,
1461                                            AtomCtrl_EDCLeakgeTable *edc_leakage_table)
1462 {
1463         uint32_t data, i = 0;
1464
1465         while (cac_config_regs[i] != 0xFFFFFFFF) {
1466                 data = edc_leakage_table->DIDT_REG[i];
1467                 cgs_write_ind_register(hwmgr->device,
1468                                        CGS_IND_REG__DIDT,
1469                                        cac_config_regs[i],
1470                                        data);
1471                 i++;
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr)
1478 {
1479         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1480         int ret = 0;
1481
1482         if (!data->disable_edc_leakage_controller &&
1483             data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset &&
1484             data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) {
1485                 ret = smu7_program_edc_didt_registers(hwmgr,
1486                                                       DIDTEDCConfig_P12,
1487                                                       &data->edc_leakage_table);
1488                 if (ret)
1489                         return ret;
1490
1491                 ret = smum_send_msg_to_smc(hwmgr,
1492                                            (PPSMC_Msg)PPSMC_MSG_EnableEDCController,
1493                                            NULL);
1494         } else {
1495                 ret = smum_send_msg_to_smc(hwmgr,
1496                                            (PPSMC_Msg)PPSMC_MSG_DisableEDCController,
1497                                            NULL);
1498         }
1499
1500         return ret;
1501 }
1502
1503 static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
1504 {
1505         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1506         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
1507         int32_t tmp_sclk, count, percentage;
1508
1509         if (golden_dpm_table->mclk_table.count == 1) {
1510                 percentage = 70;
1511                 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[0].value;
1512         } else {
1513                 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
1514                                 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
1515                 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
1516         }
1517
1518         tmp_sclk = hwmgr->pstate_mclk * percentage / 100;
1519
1520         if (hwmgr->pp_table_version == PP_TABLE_V0) {
1521                 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk =
1522                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1523
1524                 for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) {
1525                         if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) {
1526                                 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk;
1527                                 break;
1528                         }
1529                 }
1530                 if (count < 0)
1531                         hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk;
1532
1533                 hwmgr->pstate_sclk_peak =
1534                         vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk;
1535         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
1536                 struct phm_ppt_v1_information *table_info =
1537                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1538                 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk =
1539                         table_info->vdd_dep_on_sclk;
1540
1541                 for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) {
1542                         if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) {
1543                                 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk;
1544                                 break;
1545                         }
1546                 }
1547                 if (count < 0)
1548                         hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk;
1549
1550                 hwmgr->pstate_sclk_peak =
1551                         vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk;
1552         }
1553
1554         hwmgr->pstate_mclk_peak =
1555                 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
1556
1557         /* make sure the output is in Mhz */
1558         hwmgr->pstate_sclk /= 100;
1559         hwmgr->pstate_mclk /= 100;
1560         hwmgr->pstate_sclk_peak /= 100;
1561         hwmgr->pstate_mclk_peak /= 100;
1562 }
1563
1564 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1565 {
1566         int tmp_result = 0;
1567         int result = 0;
1568
1569         if (smu7_voltage_control(hwmgr)) {
1570                 tmp_result = smu7_enable_voltage_control(hwmgr);
1571                 PP_ASSERT_WITH_CODE(tmp_result == 0,
1572                                 "Failed to enable voltage control!",
1573                                 result = tmp_result);
1574
1575                 tmp_result = smu7_construct_voltage_tables(hwmgr);
1576                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1577                                 "Failed to construct voltage tables!",
1578                                 result = tmp_result);
1579         }
1580         smum_initialize_mc_reg_table(hwmgr);
1581
1582         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1583                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1584                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1585                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1586
1587         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1588                         PHM_PlatformCaps_ThermalController))
1589                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1590                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1591
1592         tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1593         PP_ASSERT_WITH_CODE((0 == tmp_result),
1594                         "Failed to program static screen threshold parameters!",
1595                         result = tmp_result);
1596
1597         tmp_result = smu7_enable_display_gap(hwmgr);
1598         PP_ASSERT_WITH_CODE((0 == tmp_result),
1599                         "Failed to enable display gap!", result = tmp_result);
1600
1601         tmp_result = smu7_program_voting_clients(hwmgr);
1602         PP_ASSERT_WITH_CODE((0 == tmp_result),
1603                         "Failed to program voting clients!", result = tmp_result);
1604
1605         tmp_result = smum_process_firmware_header(hwmgr);
1606         PP_ASSERT_WITH_CODE((0 == tmp_result),
1607                         "Failed to process firmware header!", result = tmp_result);
1608
1609         if (hwmgr->chip_id != CHIP_VEGAM) {
1610                 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1611                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1612                                 "Failed to initialize switch from ArbF0 to F1!",
1613                                 result = tmp_result);
1614         }
1615
1616         result = smu7_setup_default_dpm_tables(hwmgr);
1617         PP_ASSERT_WITH_CODE(0 == result,
1618                         "Failed to setup default DPM tables!", return result);
1619
1620         tmp_result = smum_init_smc_table(hwmgr);
1621         PP_ASSERT_WITH_CODE((0 == tmp_result),
1622                         "Failed to initialize SMC table!", result = tmp_result);
1623
1624         tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1625         PP_ASSERT_WITH_CODE((0 == tmp_result),
1626                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1627
1628         if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1629             hwmgr->chip_id <= CHIP_VEGAM) {
1630                 tmp_result = smu7_notify_has_display(hwmgr);
1631                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1632                                 "Failed to enable display setting!", result = tmp_result);
1633         } else {
1634                 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL);
1635         }
1636
1637         if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1638             hwmgr->chip_id <= CHIP_VEGAM) {
1639                 tmp_result = smu7_populate_edc_leakage_registers(hwmgr);
1640                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1641                                 "Failed to populate edc leakage registers!", result = tmp_result);
1642         }
1643
1644         tmp_result = smu7_enable_sclk_control(hwmgr);
1645         PP_ASSERT_WITH_CODE((0 == tmp_result),
1646                         "Failed to enable SCLK control!", result = tmp_result);
1647
1648         tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1649         PP_ASSERT_WITH_CODE((0 == tmp_result),
1650                         "Failed to enable voltage control!", result = tmp_result);
1651
1652         tmp_result = smu7_enable_ulv(hwmgr);
1653         PP_ASSERT_WITH_CODE((0 == tmp_result),
1654                         "Failed to enable ULV!", result = tmp_result);
1655
1656         tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1657         PP_ASSERT_WITH_CODE((0 == tmp_result),
1658                         "Failed to enable deep sleep master switch!", result = tmp_result);
1659
1660         tmp_result = smu7_enable_didt_config(hwmgr);
1661         PP_ASSERT_WITH_CODE((tmp_result == 0),
1662                         "Failed to enable deep sleep master switch!", result = tmp_result);
1663
1664         tmp_result = smu7_start_dpm(hwmgr);
1665         PP_ASSERT_WITH_CODE((0 == tmp_result),
1666                         "Failed to start DPM!", result = tmp_result);
1667
1668         tmp_result = smu7_enable_smc_cac(hwmgr);
1669         PP_ASSERT_WITH_CODE((0 == tmp_result),
1670                         "Failed to enable SMC CAC!", result = tmp_result);
1671
1672         tmp_result = smu7_enable_power_containment(hwmgr);
1673         PP_ASSERT_WITH_CODE((0 == tmp_result),
1674                         "Failed to enable power containment!", result = tmp_result);
1675
1676         tmp_result = smu7_power_control_set_level(hwmgr);
1677         PP_ASSERT_WITH_CODE((0 == tmp_result),
1678                         "Failed to power control set level!", result = tmp_result);
1679
1680         tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1681         PP_ASSERT_WITH_CODE((0 == tmp_result),
1682                         "Failed to enable thermal auto throttle!", result = tmp_result);
1683
1684         tmp_result = smu7_pcie_performance_request(hwmgr);
1685         PP_ASSERT_WITH_CODE((0 == tmp_result),
1686                         "pcie performance request failed!", result = tmp_result);
1687
1688         smu7_populate_umdpstate_clocks(hwmgr);
1689
1690         return 0;
1691 }
1692
1693 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1694 {
1695         if (!hwmgr->avfs_supported)
1696                 return 0;
1697
1698         if (enable) {
1699                 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1700                                 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1701                         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1702                                         hwmgr, PPSMC_MSG_EnableAvfs, NULL),
1703                                         "Failed to enable AVFS!",
1704                                         return -EINVAL);
1705                 }
1706         } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1707                         CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1708                 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1709                                 hwmgr, PPSMC_MSG_DisableAvfs, NULL),
1710                                 "Failed to disable AVFS!",
1711                                 return -EINVAL);
1712         }
1713
1714         return 0;
1715 }
1716
1717 static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1718 {
1719         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1720
1721         if (!hwmgr->avfs_supported)
1722                 return 0;
1723
1724         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1725                 smu7_avfs_control(hwmgr, false);
1726         } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1727                 smu7_avfs_control(hwmgr, false);
1728                 smu7_avfs_control(hwmgr, true);
1729         } else {
1730                 smu7_avfs_control(hwmgr, true);
1731         }
1732
1733         return 0;
1734 }
1735
1736 static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1737 {
1738         int tmp_result, result = 0;
1739
1740         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1741                         PHM_PlatformCaps_ThermalController))
1742                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1743                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1744
1745         tmp_result = smu7_disable_power_containment(hwmgr);
1746         PP_ASSERT_WITH_CODE((tmp_result == 0),
1747                         "Failed to disable power containment!", result = tmp_result);
1748
1749         tmp_result = smu7_disable_smc_cac(hwmgr);
1750         PP_ASSERT_WITH_CODE((tmp_result == 0),
1751                         "Failed to disable SMC CAC!", result = tmp_result);
1752
1753         tmp_result = smu7_disable_didt_config(hwmgr);
1754         PP_ASSERT_WITH_CODE((tmp_result == 0),
1755                         "Failed to disable DIDT!", result = tmp_result);
1756
1757         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1758                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1759         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1760                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1761
1762         tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1763         PP_ASSERT_WITH_CODE((tmp_result == 0),
1764                         "Failed to disable thermal auto throttle!", result = tmp_result);
1765
1766         tmp_result = smu7_avfs_control(hwmgr, false);
1767         PP_ASSERT_WITH_CODE((tmp_result == 0),
1768                         "Failed to disable AVFS!", result = tmp_result);
1769
1770         tmp_result = smu7_stop_dpm(hwmgr);
1771         PP_ASSERT_WITH_CODE((tmp_result == 0),
1772                         "Failed to stop DPM!", result = tmp_result);
1773
1774         tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1775         PP_ASSERT_WITH_CODE((tmp_result == 0),
1776                         "Failed to disable deep sleep master switch!", result = tmp_result);
1777
1778         tmp_result = smu7_disable_ulv(hwmgr);
1779         PP_ASSERT_WITH_CODE((tmp_result == 0),
1780                         "Failed to disable ULV!", result = tmp_result);
1781
1782         tmp_result = smu7_clear_voting_clients(hwmgr);
1783         PP_ASSERT_WITH_CODE((tmp_result == 0),
1784                         "Failed to clear voting clients!", result = tmp_result);
1785
1786         tmp_result = smu7_reset_to_default(hwmgr);
1787         PP_ASSERT_WITH_CODE((tmp_result == 0),
1788                         "Failed to reset to default!", result = tmp_result);
1789
1790         tmp_result = smum_stop_smc(hwmgr);
1791         PP_ASSERT_WITH_CODE((tmp_result == 0),
1792                         "Failed to stop smc!", result = tmp_result);
1793
1794         tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1795         PP_ASSERT_WITH_CODE((tmp_result == 0),
1796                         "Failed to force to switch arbf0!", result = tmp_result);
1797
1798         return result;
1799 }
1800
1801 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1802 {
1803         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1804         struct phm_ppt_v1_information *table_info =
1805                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1806         struct amdgpu_device *adev = hwmgr->adev;
1807         uint8_t tmp1, tmp2;
1808         uint16_t tmp3 = 0;
1809
1810         data->dll_default_on = false;
1811         data->mclk_dpm0_activity_target = 0xa;
1812         data->vddc_vddgfx_delta = 300;
1813         data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1814         data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1815         data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1816         data->voting_rights_clients[1] = SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1817         data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1818         data->voting_rights_clients[3] = SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1819         data->voting_rights_clients[4] = SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1820         data->voting_rights_clients[5] = SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1821         data->voting_rights_clients[6] = SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1822         data->voting_rights_clients[7] = SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1823
1824         data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1825         data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1826         data->pcie_dpm_key_disabled =
1827                 !amdgpu_device_pcie_dynamic_switching_supported() ||
1828                 !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
1829         /* need to set voltage control types before EVV patching */
1830         data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1831         data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1832         data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1833         data->enable_tdc_limit_feature = true;
1834         data->enable_pkg_pwr_tracking_feature = true;
1835         data->force_pcie_gen = PP_PCIEGenInvalid;
1836         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1837         data->current_profile_setting.bupdate_sclk = 1;
1838         data->current_profile_setting.sclk_up_hyst = 0;
1839         data->current_profile_setting.sclk_down_hyst = 100;
1840         data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1841         data->current_profile_setting.bupdate_mclk = 1;
1842         if (hwmgr->chip_id >= CHIP_POLARIS10) {
1843                 if (adev->gmc.vram_width == 256) {
1844                         data->current_profile_setting.mclk_up_hyst = 10;
1845                         data->current_profile_setting.mclk_down_hyst = 60;
1846                         data->current_profile_setting.mclk_activity = 25;
1847                 } else if (adev->gmc.vram_width == 128) {
1848                         data->current_profile_setting.mclk_up_hyst = 5;
1849                         data->current_profile_setting.mclk_down_hyst = 16;
1850                         data->current_profile_setting.mclk_activity = 20;
1851                 } else if (adev->gmc.vram_width == 64) {
1852                         data->current_profile_setting.mclk_up_hyst = 3;
1853                         data->current_profile_setting.mclk_down_hyst = 16;
1854                         data->current_profile_setting.mclk_activity = 20;
1855                 }
1856         } else {
1857                 data->current_profile_setting.mclk_up_hyst = 0;
1858                 data->current_profile_setting.mclk_down_hyst = 100;
1859                 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1860         }
1861         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1862         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1863         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1864
1865         if (hwmgr->chip_id  == CHIP_HAWAII) {
1866                 data->thermal_temp_setting.temperature_low = 94500;
1867                 data->thermal_temp_setting.temperature_high = 95000;
1868                 data->thermal_temp_setting.temperature_shutdown = 104000;
1869         } else {
1870                 data->thermal_temp_setting.temperature_low = 99500;
1871                 data->thermal_temp_setting.temperature_high = 100000;
1872                 data->thermal_temp_setting.temperature_shutdown = 104000;
1873         }
1874
1875         data->fast_watermark_threshold = 100;
1876         if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1877                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1878                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1879         else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1880                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1881                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1882
1883         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1884                         PHM_PlatformCaps_ControlVDDGFX)) {
1885                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1886                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1887                         data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1888                 }
1889         }
1890
1891         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1892                         PHM_PlatformCaps_EnableMVDDControl)) {
1893                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1894                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1895                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1896                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1897                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1898                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1899         }
1900
1901         if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1902                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1903                         PHM_PlatformCaps_ControlVDDGFX);
1904
1905         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1906                         PHM_PlatformCaps_ControlVDDCI)) {
1907                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1908                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1909                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1910                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1911                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1912                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1913         }
1914
1915         if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1916                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1917                                 PHM_PlatformCaps_EnableMVDDControl);
1918
1919         if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1920                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1921                                 PHM_PlatformCaps_ControlVDDCI);
1922
1923         data->vddc_phase_shed_control = 1;
1924         if ((hwmgr->chip_id == CHIP_POLARIS12) ||
1925             ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1926             ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
1927             ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
1928             ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
1929                 if (data->voltage_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1930                         atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1931                                                         &tmp3);
1932                         tmp3 = (tmp3 >> 5) & 0x3;
1933                         data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1934                 }
1935         } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1936                 data->vddc_phase_shed_control = 1;
1937         }
1938
1939         if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1940                 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1941                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1942                                         PHM_PlatformCaps_ClockStretcher);
1943
1944         data->pcie_gen_performance.max = PP_PCIEGen1;
1945         data->pcie_gen_performance.min = PP_PCIEGen3;
1946         data->pcie_gen_power_saving.max = PP_PCIEGen1;
1947         data->pcie_gen_power_saving.min = PP_PCIEGen3;
1948         data->pcie_lane_performance.max = 0;
1949         data->pcie_lane_performance.min = 16;
1950         data->pcie_lane_power_saving.max = 0;
1951         data->pcie_lane_power_saving.min = 16;
1952
1953
1954         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1955                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1956                               PHM_PlatformCaps_UVDPowerGating);
1957         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1958                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1959                               PHM_PlatformCaps_VCEPowerGating);
1960
1961         data->disable_edc_leakage_controller = true;
1962         if (((adev->asic_type == CHIP_POLARIS10) && hwmgr->is_kicker) ||
1963             ((adev->asic_type == CHIP_POLARIS11) && hwmgr->is_kicker) ||
1964             (adev->asic_type == CHIP_POLARIS12) ||
1965             (adev->asic_type == CHIP_VEGAM))
1966                 data->disable_edc_leakage_controller = false;
1967
1968         if (!atomctrl_is_asic_internal_ss_supported(hwmgr)) {
1969                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1970                         PHM_PlatformCaps_MemorySpreadSpectrumSupport);
1971                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1972                         PHM_PlatformCaps_EngineSpreadSpectrumSupport);
1973         }
1974
1975         if ((adev->pdev->device == 0x699F) &&
1976             (adev->pdev->revision == 0xCF)) {
1977                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1978                                 PHM_PlatformCaps_PowerContainment);
1979                 data->enable_tdc_limit_feature = false;
1980                 data->enable_pkg_pwr_tracking_feature = false;
1981                 data->disable_edc_leakage_controller = true;
1982                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1983                                         PHM_PlatformCaps_ClockStretcher);
1984         }
1985 }
1986
1987 static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)
1988 {
1989         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1990         struct amdgpu_device *adev = hwmgr->adev;
1991         uint32_t asicrev1, evv_revision, max = 0, min = 0;
1992
1993         atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB, STRAP_EVV_REVISION_MSB,
1994                         &evv_revision);
1995
1996         atomctrl_read_efuse(hwmgr, 568, 579, &asicrev1);
1997
1998         if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1999             ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) {
2000                 min = 1200;
2001                 max = 2500;
2002         } else if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
2003                    ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
2004                 min = 900;
2005                 max = 2100;
2006         } else if (hwmgr->chip_id == CHIP_POLARIS10) {
2007                 if (adev->pdev->subsystem_vendor == 0x106B) {
2008                         min = 1000;
2009                         max = 2300;
2010                 } else {
2011                         if (evv_revision == 0) {
2012                                 min = 1000;
2013                                 max = 2300;
2014                         } else if (evv_revision == 1) {
2015                                 if (asicrev1 == 326) {
2016                                         min = 1200;
2017                                         max = 2500;
2018                                         /* TODO: PATCH RO in VBIOS */
2019                                 } else {
2020                                         min = 1200;
2021                                         max = 2000;
2022                                 }
2023                         } else if (evv_revision == 2) {
2024                                 min = 1200;
2025                                 max = 2500;
2026                         }
2027                 }
2028         } else {
2029                 min = 1100;
2030                 max = 2100;
2031         }
2032
2033         data->ro_range_minimum = min;
2034         data->ro_range_maximum = max;
2035
2036         /* TODO: PATCH RO in VBIOS here */
2037
2038         return 0;
2039 }
2040
2041 /**
2042  * smu7_get_evv_voltages - Get Leakage VDDC based on leakage ID.
2043  *
2044  * @hwmgr:  the address of the powerplay hardware manager.
2045  * Return:   always 0
2046  */
2047 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
2048 {
2049         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2050         uint16_t vv_id;
2051         uint16_t vddc = 0;
2052         uint16_t vddgfx = 0;
2053         uint16_t i, j;
2054         uint32_t sclk = 0;
2055         struct phm_ppt_v1_information *table_info =
2056                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2057         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
2058
2059         if (hwmgr->chip_id == CHIP_POLARIS10 ||
2060             hwmgr->chip_id == CHIP_POLARIS11 ||
2061             hwmgr->chip_id == CHIP_POLARIS12)
2062                 smu7_calculate_ro_range(hwmgr);
2063
2064         for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2065                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2066
2067                 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2068                         if ((hwmgr->pp_table_version == PP_TABLE_V1)
2069                             && !phm_get_sclk_for_voltage_evv(hwmgr,
2070                                                 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
2071                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2072                                                         PHM_PlatformCaps_ClockStretcher)) {
2073                                         sclk_table = table_info->vdd_dep_on_sclk;
2074
2075                                         for (j = 1; j < sclk_table->count; j++) {
2076                                                 if (sclk_table->entries[j].clk == sclk &&
2077                                                                 sclk_table->entries[j].cks_enable == 0) {
2078                                                         sclk += 5000;
2079                                                         break;
2080                                                 }
2081                                         }
2082                                 }
2083                                 if (0 == atomctrl_get_voltage_evv_on_sclk
2084                                     (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
2085                                      vv_id, &vddgfx)) {
2086                                         /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
2087                                         PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
2088
2089                                         /* the voltage should not be zero nor equal to leakage ID */
2090                                         if (vddgfx != 0 && vddgfx != vv_id) {
2091                                                 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
2092                                                 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
2093                                                 data->vddcgfx_leakage.count++;
2094                                         }
2095                                 } else {
2096                                         pr_info("Error retrieving EVV voltage value!\n");
2097                                 }
2098                         }
2099                 } else {
2100                         if ((hwmgr->pp_table_version == PP_TABLE_V0)
2101                                 || !phm_get_sclk_for_voltage_evv(hwmgr,
2102                                         table_info->vddc_lookup_table, vv_id, &sclk)) {
2103                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2104                                                 PHM_PlatformCaps_ClockStretcher)) {
2105                                         if (table_info == NULL)
2106                                                 return -EINVAL;
2107                                         sclk_table = table_info->vdd_dep_on_sclk;
2108
2109                                         for (j = 1; j < sclk_table->count; j++) {
2110                                                 if (sclk_table->entries[j].clk == sclk &&
2111                                                                 sclk_table->entries[j].cks_enable == 0) {
2112                                                         sclk += 5000;
2113                                                         break;
2114                                                 }
2115                                         }
2116                                 }
2117
2118                                 if (phm_get_voltage_evv_on_sclk(hwmgr,
2119                                                         VOLTAGE_TYPE_VDDC,
2120                                                         sclk, vv_id, &vddc) == 0) {
2121                                         if (vddc >= 2000 || vddc == 0)
2122                                                 return -EINVAL;
2123                                 } else {
2124                                         pr_debug("failed to retrieving EVV voltage!\n");
2125                                         continue;
2126                                 }
2127
2128                                 /* the voltage should not be zero nor equal to leakage ID */
2129                                 if (vddc != 0 && vddc != vv_id) {
2130                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
2131                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2132                                         data->vddc_leakage.count++;
2133                                 }
2134                         }
2135                 }
2136         }
2137
2138         return 0;
2139 }
2140
2141 /**
2142  * smu7_patch_ppt_v1_with_vdd_leakage - Change virtual leakage voltage to actual value.
2143  *
2144  * @hwmgr:  the address of the powerplay hardware manager.
2145  * @voltage: pointer to changing voltage
2146  * @leakage_table: pointer to leakage table
2147  */
2148 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2149                 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
2150 {
2151         uint32_t index;
2152
2153         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2154         for (index = 0; index < leakage_table->count; index++) {
2155                 /* if this voltage matches a leakage voltage ID */
2156                 /* patch with actual leakage voltage */
2157                 if (leakage_table->leakage_id[index] == *voltage) {
2158                         *voltage = leakage_table->actual_voltage[index];
2159                         break;
2160                 }
2161         }
2162
2163         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2164                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
2165 }
2166
2167 /**
2168  * smu7_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages.
2169  *
2170  * @hwmgr:  the address of the powerplay hardware manager.
2171  * @lookup_table: pointer to voltage lookup table
2172  * @leakage_table: pointer to leakage table
2173  * Return:     always 0
2174  */
2175 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2176                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2177                 struct smu7_leakage_voltage *leakage_table)
2178 {
2179         uint32_t i;
2180
2181         for (i = 0; i < lookup_table->count; i++)
2182                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2183                                 &lookup_table->entries[i].us_vdd, leakage_table);
2184
2185         return 0;
2186 }
2187
2188 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
2189                 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
2190                 uint16_t *vddc)
2191 {
2192         struct phm_ppt_v1_information *table_info =
2193                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2194         smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2195         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2196                         table_info->max_clock_voltage_on_dc.vddc;
2197         return 0;
2198 }
2199
2200 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
2201                 struct pp_hwmgr *hwmgr)
2202 {
2203         uint8_t entry_id;
2204         uint8_t voltage_id;
2205         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2206         struct phm_ppt_v1_information *table_info =
2207                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2208
2209         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2210                         table_info->vdd_dep_on_sclk;
2211         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2212                         table_info->vdd_dep_on_mclk;
2213         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2214                         table_info->mm_dep_table;
2215
2216         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2217                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2218                         voltage_id = sclk_table->entries[entry_id].vddInd;
2219                         sclk_table->entries[entry_id].vddgfx =
2220                                 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
2221                 }
2222         } else {
2223                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2224                         voltage_id = sclk_table->entries[entry_id].vddInd;
2225                         sclk_table->entries[entry_id].vddc =
2226                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2227                 }
2228         }
2229
2230         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
2231                 voltage_id = mclk_table->entries[entry_id].vddInd;
2232                 mclk_table->entries[entry_id].vddc =
2233                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2234         }
2235
2236         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
2237                 voltage_id = mm_table->entries[entry_id].vddcInd;
2238                 mm_table->entries[entry_id].vddc =
2239                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2240         }
2241
2242         return 0;
2243
2244 }
2245
2246 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
2247                         phm_ppt_v1_voltage_lookup_table *look_up_table,
2248                         phm_ppt_v1_voltage_lookup_record *record)
2249 {
2250         uint32_t i;
2251
2252         PP_ASSERT_WITH_CODE((NULL != look_up_table),
2253                 "Lookup Table empty.", return -EINVAL);
2254         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
2255                 "Lookup Table empty.", return -EINVAL);
2256
2257         i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
2258         PP_ASSERT_WITH_CODE((i >= look_up_table->count),
2259                 "Lookup Table is full.", return -EINVAL);
2260
2261         /* This is to avoid entering duplicate calculated records. */
2262         for (i = 0; i < look_up_table->count; i++) {
2263                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
2264                         if (look_up_table->entries[i].us_calculated == 1)
2265                                 return 0;
2266                         break;
2267                 }
2268         }
2269
2270         look_up_table->entries[i].us_calculated = 1;
2271         look_up_table->entries[i].us_vdd = record->us_vdd;
2272         look_up_table->entries[i].us_cac_low = record->us_cac_low;
2273         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
2274         look_up_table->entries[i].us_cac_high = record->us_cac_high;
2275         /* Only increment the count when we're appending, not replacing duplicate entry. */
2276         if (i == look_up_table->count)
2277                 look_up_table->count++;
2278
2279         return 0;
2280 }
2281
2282
2283 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2284 {
2285         uint8_t entry_id;
2286         struct phm_ppt_v1_voltage_lookup_record v_record;
2287         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2288         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2289
2290         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
2291         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
2292
2293         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2294                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2295                         if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
2296                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
2297                                         sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
2298                         else
2299                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
2300                                         sclk_table->entries[entry_id].vdd_offset;
2301
2302                         sclk_table->entries[entry_id].vddc =
2303                                 v_record.us_cac_low = v_record.us_cac_mid =
2304                                 v_record.us_cac_high = v_record.us_vdd;
2305
2306                         phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
2307                 }
2308
2309                 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
2310                         if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
2311                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
2312                                         mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
2313                         else
2314                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
2315                                         mclk_table->entries[entry_id].vdd_offset;
2316
2317                         mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
2318                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
2319                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
2320                 }
2321         }
2322         return 0;
2323 }
2324
2325 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2326 {
2327         uint8_t entry_id;
2328         struct phm_ppt_v1_voltage_lookup_record v_record;
2329         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2330         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2331         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
2332
2333         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2334                 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
2335                         if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
2336                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
2337                                         mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
2338                         else
2339                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
2340                                         mm_table->entries[entry_id].vddgfx_offset;
2341
2342                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
2343                         mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
2344                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
2345                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
2346                 }
2347         }
2348         return 0;
2349 }
2350
2351 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
2352                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2353 {
2354         uint32_t table_size, i, j;
2355         table_size = lookup_table->count;
2356
2357         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2358                 "Lookup table is empty", return -EINVAL);
2359
2360         /* Sorting voltages */
2361         for (i = 0; i < table_size - 1; i++) {
2362                 for (j = i + 1; j > 0; j--) {
2363                         if (lookup_table->entries[j].us_vdd <
2364                                         lookup_table->entries[j - 1].us_vdd) {
2365                                 swap(lookup_table->entries[j - 1],
2366                                      lookup_table->entries[j]);
2367                         }
2368                 }
2369         }
2370
2371         return 0;
2372 }
2373
2374 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2375 {
2376         int result = 0;
2377         int tmp_result;
2378         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2379         struct phm_ppt_v1_information *table_info =
2380                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2381
2382         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2383                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2384                         table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
2385                 if (tmp_result != 0)
2386                         result = tmp_result;
2387
2388                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2389                         &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
2390         } else {
2391
2392                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2393                                 table_info->vddc_lookup_table, &(data->vddc_leakage));
2394                 if (tmp_result)
2395                         result = tmp_result;
2396
2397                 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2398                                 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2399                 if (tmp_result)
2400                         result = tmp_result;
2401         }
2402
2403         tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2404         if (tmp_result)
2405                 result = tmp_result;
2406
2407         tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2408         if (tmp_result)
2409                 result = tmp_result;
2410
2411         tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2412         if (tmp_result)
2413                 result = tmp_result;
2414
2415         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
2416         if (tmp_result)
2417                 result = tmp_result;
2418
2419         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2420         if (tmp_result)
2421                 result = tmp_result;
2422
2423         return result;
2424 }
2425
2426 static int smu7_find_highest_vddc(struct pp_hwmgr *hwmgr)
2427 {
2428         struct phm_ppt_v1_information *table_info =
2429                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2430         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2431                                                 table_info->vdd_dep_on_sclk;
2432         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
2433                                                 table_info->vddc_lookup_table;
2434         uint16_t highest_voltage;
2435         uint32_t i;
2436
2437         highest_voltage = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2438
2439         for (i = 0; i < lookup_table->count; i++) {
2440                 if (lookup_table->entries[i].us_vdd < ATOM_VIRTUAL_VOLTAGE_ID0 &&
2441                     lookup_table->entries[i].us_vdd > highest_voltage)
2442                         highest_voltage = lookup_table->entries[i].us_vdd;
2443         }
2444
2445         return highest_voltage;
2446 }
2447
2448 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2449 {
2450         struct phm_ppt_v1_information *table_info =
2451                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2452
2453         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2454                                                 table_info->vdd_dep_on_sclk;
2455         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2456                                                 table_info->vdd_dep_on_mclk;
2457
2458         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2459                 "VDD dependency on SCLK table is missing.",
2460                 return -EINVAL);
2461         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2462                 "VDD dependency on SCLK table has to have is missing.",
2463                 return -EINVAL);
2464
2465         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2466                 "VDD dependency on MCLK table is missing",
2467                 return -EINVAL);
2468         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2469                 "VDD dependency on MCLK table has to have is missing.",
2470                 return -EINVAL);
2471
2472         table_info->max_clock_voltage_on_ac.sclk =
2473                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2474         table_info->max_clock_voltage_on_ac.mclk =
2475                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2476         if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM)
2477                 table_info->max_clock_voltage_on_ac.vddc =
2478                         smu7_find_highest_vddc(hwmgr);
2479         else
2480                 table_info->max_clock_voltage_on_ac.vddc =
2481                         allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2482         table_info->max_clock_voltage_on_ac.vddci =
2483                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2484
2485         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2486         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2487         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2488         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2489
2490         return 0;
2491 }
2492
2493 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2494 {
2495         struct phm_ppt_v1_information *table_info =
2496                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
2497         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2498         struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2499         uint32_t i;
2500         uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2501         struct amdgpu_device *adev = hwmgr->adev;
2502
2503         if (table_info != NULL) {
2504                 dep_mclk_table = table_info->vdd_dep_on_mclk;
2505                 lookup_table = table_info->vddc_lookup_table;
2506         } else
2507                 return 0;
2508
2509         hw_revision = adev->pdev->revision;
2510         sub_sys_id = adev->pdev->subsystem_device;
2511         sub_vendor_id = adev->pdev->subsystem_vendor;
2512
2513         if (adev->pdev->device == 0x67DF && hw_revision == 0xC7 &&
2514             ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2515              (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2516              (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2517
2518                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
2519                                               CGS_IND_REG__SMC,
2520                                               PWR_CKS_CNTL,
2521                                               CKS_STRETCH_AMOUNT,
2522                                               0x3);
2523
2524                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2525                         return 0;
2526
2527                 for (i = 0; i < lookup_table->count; i++) {
2528                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2529                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2530                                 return 0;
2531                         }
2532                 }
2533         }
2534         return 0;
2535 }
2536
2537 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2538 {
2539         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2540         uint32_t temp_reg;
2541         struct phm_ppt_v1_information *table_info =
2542                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2543
2544
2545         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2546                 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2547                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2548                 case 0:
2549                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2550                         break;
2551                 case 1:
2552                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2553                         break;
2554                 case 2:
2555                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2556                         break;
2557                 case 3:
2558                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2559                         break;
2560                 case 4:
2561                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2562                         break;
2563                 default:
2564                         break;
2565                 }
2566                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2567         }
2568
2569         if (table_info == NULL)
2570                 return 0;
2571
2572         if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2573                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2574                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2575                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2576
2577                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2578                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2579
2580                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2581
2582                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2583
2584                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2585                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2586
2587                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2588
2589                 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2590                                                                 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2591
2592                 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2593                 table_info->cac_dtp_table->usOperatingTempStep = 1;
2594                 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2595
2596                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2597                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2598
2599                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2600                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2601
2602                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2603                                table_info->cac_dtp_table->usOperatingTempMinLimit;
2604
2605                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2606                                table_info->cac_dtp_table->usOperatingTempMaxLimit;
2607
2608                 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2609                                table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2610
2611                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2612                                table_info->cac_dtp_table->usOperatingTempStep;
2613
2614                 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2615                                table_info->cac_dtp_table->usTargetOperatingTemp;
2616                 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2617                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2618                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
2619         }
2620
2621         return 0;
2622 }
2623
2624 /**
2625  * smu7_patch_ppt_v0_with_vdd_leakage - Change virtual leakage voltage to actual value.
2626  *
2627  * @hwmgr:  the address of the powerplay hardware manager.
2628  * @voltage: pointer to changing voltage
2629  * @leakage_table: pointer to leakage table
2630  */
2631 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2632                 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2633 {
2634         uint32_t index;
2635
2636         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2637         for (index = 0; index < leakage_table->count; index++) {
2638                 /* if this voltage matches a leakage voltage ID */
2639                 /* patch with actual leakage voltage */
2640                 if (leakage_table->leakage_id[index] == *voltage) {
2641                         *voltage = leakage_table->actual_voltage[index];
2642                         break;
2643                 }
2644         }
2645
2646         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2647                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
2648 }
2649
2650
2651 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2652                               struct phm_clock_voltage_dependency_table *tab)
2653 {
2654         uint16_t i;
2655         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2656
2657         if (tab)
2658                 for (i = 0; i < tab->count; i++)
2659                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2660                                                 &data->vddc_leakage);
2661
2662         return 0;
2663 }
2664
2665 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2666                                struct phm_clock_voltage_dependency_table *tab)
2667 {
2668         uint16_t i;
2669         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2670
2671         if (tab)
2672                 for (i = 0; i < tab->count; i++)
2673                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2674                                                         &data->vddci_leakage);
2675
2676         return 0;
2677 }
2678
2679 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2680                                   struct phm_vce_clock_voltage_dependency_table *tab)
2681 {
2682         uint16_t i;
2683         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2684
2685         if (tab)
2686                 for (i = 0; i < tab->count; i++)
2687                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2688                                                         &data->vddc_leakage);
2689
2690         return 0;
2691 }
2692
2693
2694 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2695                                   struct phm_uvd_clock_voltage_dependency_table *tab)
2696 {
2697         uint16_t i;
2698         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2699
2700         if (tab)
2701                 for (i = 0; i < tab->count; i++)
2702                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2703                                                         &data->vddc_leakage);
2704
2705         return 0;
2706 }
2707
2708 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2709                                          struct phm_phase_shedding_limits_table *tab)
2710 {
2711         uint16_t i;
2712         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2713
2714         if (tab)
2715                 for (i = 0; i < tab->count; i++)
2716                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2717                                                         &data->vddc_leakage);
2718
2719         return 0;
2720 }
2721
2722 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2723                                    struct phm_samu_clock_voltage_dependency_table *tab)
2724 {
2725         uint16_t i;
2726         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2727
2728         if (tab)
2729                 for (i = 0; i < tab->count; i++)
2730                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2731                                                         &data->vddc_leakage);
2732
2733         return 0;
2734 }
2735
2736 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2737                                   struct phm_acp_clock_voltage_dependency_table *tab)
2738 {
2739         uint16_t i;
2740         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2741
2742         if (tab)
2743                 for (i = 0; i < tab->count; i++)
2744                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2745                                         &data->vddc_leakage);
2746
2747         return 0;
2748 }
2749
2750 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2751                                   struct phm_clock_and_voltage_limits *tab)
2752 {
2753         uint32_t vddc, vddci;
2754         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2755
2756         if (tab) {
2757                 vddc = tab->vddc;
2758                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2759                                                    &data->vddc_leakage);
2760                 tab->vddc = vddc;
2761                 vddci = tab->vddci;
2762                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2763                                                    &data->vddci_leakage);
2764                 tab->vddci = vddci;
2765         }
2766
2767         return 0;
2768 }
2769
2770 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2771 {
2772         uint32_t i;
2773         uint32_t vddc;
2774         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2775
2776         if (tab) {
2777                 for (i = 0; i < tab->count; i++) {
2778                         vddc = (uint32_t)(tab->entries[i].Vddc);
2779                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2780                         tab->entries[i].Vddc = (uint16_t)vddc;
2781                 }
2782         }
2783
2784         return 0;
2785 }
2786
2787 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2788 {
2789         int tmp;
2790
2791         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2792         if (tmp)
2793                 return -EINVAL;
2794
2795         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2796         if (tmp)
2797                 return -EINVAL;
2798
2799         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2800         if (tmp)
2801                 return -EINVAL;
2802
2803         tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2804         if (tmp)
2805                 return -EINVAL;
2806
2807         tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2808         if (tmp)
2809                 return -EINVAL;
2810
2811         tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2812         if (tmp)
2813                 return -EINVAL;
2814
2815         tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2816         if (tmp)
2817                 return -EINVAL;
2818
2819         tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2820         if (tmp)
2821                 return -EINVAL;
2822
2823         tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2824         if (tmp)
2825                 return -EINVAL;
2826
2827         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2828         if (tmp)
2829                 return -EINVAL;
2830
2831         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2832         if (tmp)
2833                 return -EINVAL;
2834
2835         tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2836         if (tmp)
2837                 return -EINVAL;
2838
2839         return 0;
2840 }
2841
2842
2843 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2844 {
2845         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2846
2847         struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2848         struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2849         struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2850
2851         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2852                 "VDDC dependency on SCLK table is missing. This table is mandatory",
2853                 return -EINVAL);
2854         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2855                 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2856                 return -EINVAL);
2857
2858         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2859                 "VDDC dependency on MCLK table is missing. This table is mandatory",
2860                 return -EINVAL);
2861         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2862                 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2863                 return -EINVAL);
2864
2865         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2866         data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2867
2868         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2869                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2870         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2871                 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2872         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2873                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2874
2875         if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2876                 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2877                 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2878         }
2879
2880         if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2881                 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2882
2883         return 0;
2884 }
2885
2886 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2887 {
2888         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2889         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2890         kfree(hwmgr->backend);
2891         hwmgr->backend = NULL;
2892
2893         return 0;
2894 }
2895
2896 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2897 {
2898         uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2899         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2900         int i;
2901
2902         if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2903                 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2904                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2905                         if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2906                                                                 virtual_voltage_id,
2907                                                                 efuse_voltage_id) == 0) {
2908                                 if (vddc != 0 && vddc != virtual_voltage_id) {
2909                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2910                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2911                                         data->vddc_leakage.count++;
2912                                 }
2913                                 if (vddci != 0 && vddci != virtual_voltage_id) {
2914                                         data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2915                                         data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2916                                         data->vddci_leakage.count++;
2917                                 }
2918                         }
2919                 }
2920         }
2921         return 0;
2922 }
2923
2924 #define LEAKAGE_ID_MSB                  463
2925 #define LEAKAGE_ID_LSB                  454
2926
2927 static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr)
2928 {
2929         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2930         uint32_t efuse;
2931         uint16_t offset;
2932         int ret = 0;
2933
2934         if (data->disable_edc_leakage_controller)
2935                 return 0;
2936
2937         ret = atomctrl_get_edc_hilo_leakage_offset_table(hwmgr,
2938                                                          &data->edc_hilo_leakage_offset_from_vbios);
2939         if (ret)
2940                 return ret;
2941
2942         if (data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset &&
2943             data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) {
2944                 atomctrl_read_efuse(hwmgr, LEAKAGE_ID_LSB, LEAKAGE_ID_MSB, &efuse);
2945                 if (efuse < data->edc_hilo_leakage_offset_from_vbios.usHiLoLeakageThreshold)
2946                         offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset;
2947                 else
2948                         offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset;
2949
2950                 ret = atomctrl_get_edc_leakage_table(hwmgr,
2951                                                      &data->edc_leakage_table,
2952                                                      offset);
2953                 if (ret)
2954                         return ret;
2955         }
2956
2957         return ret;
2958 }
2959
2960 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2961 {
2962         struct smu7_hwmgr *data;
2963         int result = 0;
2964
2965         data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2966         if (data == NULL)
2967                 return -ENOMEM;
2968
2969         hwmgr->backend = data;
2970         smu7_patch_voltage_workaround(hwmgr);
2971         smu7_init_dpm_defaults(hwmgr);
2972
2973         /* Get leakage voltage based on leakage ID. */
2974         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2975                         PHM_PlatformCaps_EVV)) {
2976                 result = smu7_get_evv_voltages(hwmgr);
2977                 if (result) {
2978                         pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
2979                         return -EINVAL;
2980                 }
2981         } else {
2982                 smu7_get_elb_voltages(hwmgr);
2983         }
2984
2985         if (hwmgr->pp_table_version == PP_TABLE_V1) {
2986                 smu7_complete_dependency_tables(hwmgr);
2987                 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2988         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2989                 smu7_patch_dependency_tables_with_leakage(hwmgr);
2990                 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2991         }
2992
2993         /* Initalize Dynamic State Adjustment Rule Settings */
2994         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2995
2996         if (0 == result) {
2997                 struct amdgpu_device *adev = hwmgr->adev;
2998
2999                 data->is_tlu_enabled = false;
3000
3001                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3002                                                         SMU7_MAX_HARDWARE_POWERLEVELS;
3003                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3004                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3005
3006                 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
3007                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3008                         data->pcie_spc_cap = 20;
3009                 else
3010                         data->pcie_spc_cap = 16;
3011                 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
3012
3013                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3014 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3015                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3016                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3017                 smu7_thermal_parameter_init(hwmgr);
3018         } else {
3019                 /* Ignore return value in here, we are cleaning up a mess. */
3020                 smu7_hwmgr_backend_fini(hwmgr);
3021         }
3022
3023         result = smu7_update_edc_leakage_table(hwmgr);
3024         if (result)
3025                 return result;
3026
3027         return 0;
3028 }
3029
3030 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
3031 {
3032         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3033         uint32_t level, tmp;
3034
3035         if (!data->pcie_dpm_key_disabled) {
3036                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3037                         level = 0;
3038                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3039                         while (tmp >>= 1)
3040                                 level++;
3041
3042                         if (level)
3043                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3044                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level,
3045                                                 NULL);
3046                 }
3047         }
3048
3049         if (!data->sclk_dpm_key_disabled) {
3050                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3051                         level = 0;
3052                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3053                         while (tmp >>= 1)
3054                                 level++;
3055
3056                         if (level)
3057                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3058                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3059                                                 (1 << level),
3060                                                 NULL);
3061                 }
3062         }
3063
3064         if (!data->mclk_dpm_key_disabled) {
3065                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3066                         level = 0;
3067                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3068                         while (tmp >>= 1)
3069                                 level++;
3070
3071                         if (level)
3072                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3073                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3074                                                 (1 << level),
3075                                                 NULL);
3076                 }
3077         }
3078
3079         return 0;
3080 }
3081
3082 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3083 {
3084         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3085
3086         if (hwmgr->pp_table_version == PP_TABLE_V1)
3087                 phm_apply_dal_min_voltage_request(hwmgr);
3088 /* TO DO  for v0 iceland and Ci*/
3089
3090         if (!data->sclk_dpm_key_disabled) {
3091                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3092                         smum_send_msg_to_smc_with_parameter(hwmgr,
3093                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3094                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask,
3095                                         NULL);
3096         }
3097
3098         if (!data->mclk_dpm_key_disabled) {
3099                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3100                         smum_send_msg_to_smc_with_parameter(hwmgr,
3101                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3102                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask,
3103                                         NULL);
3104         }
3105
3106         return 0;
3107 }
3108
3109 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3110 {
3111         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3112
3113         if (!smum_is_dpm_running(hwmgr))
3114                 return -EINVAL;
3115
3116         if (!data->pcie_dpm_key_disabled) {
3117                 smum_send_msg_to_smc(hwmgr,
3118                                 PPSMC_MSG_PCIeDPM_UnForceLevel,
3119                                 NULL);
3120         }
3121
3122         return smu7_upload_dpm_level_enable_mask(hwmgr);
3123 }
3124
3125 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3126 {
3127         struct smu7_hwmgr *data =
3128                         (struct smu7_hwmgr *)(hwmgr->backend);
3129         uint32_t level;
3130
3131         if (!data->sclk_dpm_key_disabled)
3132                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3133                         level = phm_get_lowest_enabled_level(hwmgr,
3134                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3135                         smum_send_msg_to_smc_with_parameter(hwmgr,
3136                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3137                                                             (1 << level),
3138                                                             NULL);
3139
3140         }
3141
3142         if (!data->mclk_dpm_key_disabled) {
3143                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3144                         level = phm_get_lowest_enabled_level(hwmgr,
3145                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3146                         smum_send_msg_to_smc_with_parameter(hwmgr,
3147                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3148                                                             (1 << level),
3149                                                             NULL);
3150                 }
3151         }
3152
3153         if (!data->pcie_dpm_key_disabled) {
3154                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3155                         level = phm_get_lowest_enabled_level(hwmgr,
3156                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3157                         smum_send_msg_to_smc_with_parameter(hwmgr,
3158                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3159                                                             (level),
3160                                                             NULL);
3161                 }
3162         }
3163
3164         return 0;
3165 }
3166
3167 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
3168                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
3169 {
3170         uint32_t percentage;
3171         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3172         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3173         int32_t tmp_mclk;
3174         int32_t tmp_sclk;
3175         int32_t count;
3176
3177         if (golden_dpm_table->mclk_table.count < 1)
3178                 return -EINVAL;
3179
3180         percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
3181                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
3182
3183         if (golden_dpm_table->mclk_table.count == 1) {
3184                 percentage = 70;
3185                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
3186                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
3187         } else {
3188                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
3189                 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
3190         }
3191
3192         tmp_sclk = tmp_mclk * percentage / 100;
3193
3194         if (hwmgr->pp_table_version == PP_TABLE_V0) {
3195                 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
3196                         count >= 0; count--) {
3197                         if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
3198                                 *sclk_mask = count;
3199                                 break;
3200                         }
3201                 }
3202                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
3203                         *sclk_mask = 0;
3204
3205                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3206                         *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
3207         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3208                 struct phm_ppt_v1_information *table_info =
3209                                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3210
3211                 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
3212                         if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
3213                                 *sclk_mask = count;
3214                                 break;
3215                         }
3216                 }
3217                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
3218                         *sclk_mask = 0;
3219
3220                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3221                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
3222         }
3223
3224         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
3225                 *mclk_mask = 0;
3226         else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3227                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
3228
3229         *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
3230
3231         return 0;
3232 }
3233
3234 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
3235                                 enum amd_dpm_forced_level level)
3236 {
3237         int ret = 0;
3238         uint32_t sclk_mask = 0;
3239         uint32_t mclk_mask = 0;
3240         uint32_t pcie_mask = 0;
3241
3242         switch (level) {
3243         case AMD_DPM_FORCED_LEVEL_HIGH:
3244                 ret = smu7_force_dpm_highest(hwmgr);
3245                 break;
3246         case AMD_DPM_FORCED_LEVEL_LOW:
3247                 ret = smu7_force_dpm_lowest(hwmgr);
3248                 break;
3249         case AMD_DPM_FORCED_LEVEL_AUTO:
3250                 ret = smu7_unforce_dpm_levels(hwmgr);
3251                 break;
3252         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
3253         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
3254         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
3255         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
3256                 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
3257                 if (ret)
3258                         return ret;
3259                 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
3260                 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
3261                 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
3262                 break;
3263         case AMD_DPM_FORCED_LEVEL_MANUAL:
3264         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
3265         default:
3266                 break;
3267         }
3268
3269         if (!ret) {
3270                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3271                         smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
3272                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3273                         smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
3274         }
3275         return ret;
3276 }
3277
3278 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
3279 {
3280         return sizeof(struct smu7_power_state);
3281 }
3282
3283 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
3284                                  uint32_t vblank_time_us)
3285 {
3286         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3287         uint32_t switch_limit_us;
3288
3289         switch (hwmgr->chip_id) {
3290         case CHIP_POLARIS10:
3291         case CHIP_POLARIS11:
3292         case CHIP_POLARIS12:
3293                 if (hwmgr->is_kicker || (hwmgr->chip_id == CHIP_POLARIS12))
3294                         switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
3295                 else
3296                         switch_limit_us = data->is_memory_gddr5 ? 200 : 150;
3297                 break;
3298         case CHIP_VEGAM:
3299                 switch_limit_us = 30;
3300                 break;
3301         default:
3302                 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
3303                 break;
3304         }
3305
3306         if (vblank_time_us < switch_limit_us)
3307                 return true;
3308         else
3309                 return false;
3310 }
3311
3312 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3313                                 struct pp_power_state *request_ps,
3314                         const struct pp_power_state *current_ps)
3315 {
3316         struct amdgpu_device *adev = hwmgr->adev;
3317         struct smu7_power_state *smu7_ps =
3318                                 cast_phw_smu7_power_state(&request_ps->hardware);
3319         uint32_t sclk;
3320         uint32_t mclk;
3321         struct PP_Clocks minimum_clocks = {0};
3322         bool disable_mclk_switching;
3323         bool disable_mclk_switching_for_frame_lock;
3324         bool disable_mclk_switching_for_display;
3325         const struct phm_clock_and_voltage_limits *max_limits;
3326         uint32_t i;
3327         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3328         struct phm_ppt_v1_information *table_info =
3329                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3330         int32_t count;
3331         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3332         uint32_t latency;
3333         bool latency_allowed = false;
3334
3335         data->battery_state = (PP_StateUILabel_Battery ==
3336                         request_ps->classification.ui_label);
3337         data->mclk_ignore_signal = false;
3338
3339         max_limits = adev->pm.ac_power ?
3340                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3341                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3342
3343         /* Cap clock DPM tables at DC MAX if it is in DC. */
3344         if (!adev->pm.ac_power) {
3345                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3346                         if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
3347                                 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
3348                         if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
3349                                 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
3350                 }
3351         }
3352
3353         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3354         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3355
3356         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3357                         PHM_PlatformCaps_StablePState)) {
3358                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3359                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3360
3361                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3362                                 count >= 0; count--) {
3363                         if (stable_pstate_sclk >=
3364                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3365                                 stable_pstate_sclk =
3366                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3367                                 break;
3368                         }
3369                 }
3370
3371                 if (count < 0)
3372                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3373
3374                 stable_pstate_mclk = max_limits->mclk;
3375
3376                 minimum_clocks.engineClock = stable_pstate_sclk;
3377                 minimum_clocks.memoryClock = stable_pstate_mclk;
3378         }
3379
3380         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3381                                     hwmgr->platform_descriptor.platformCaps,
3382                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3383
3384         disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) &&
3385                                                 !hwmgr->display_config->multi_monitor_in_sync) ||
3386                                                 (hwmgr->display_config->num_display &&
3387                                                 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));
3388
3389         disable_mclk_switching = disable_mclk_switching_for_frame_lock ||
3390                                          disable_mclk_switching_for_display;
3391
3392         if (hwmgr->display_config->num_display == 0) {
3393                 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM)
3394                         data->mclk_ignore_signal = true;
3395                 else
3396                         disable_mclk_switching = false;
3397         }
3398
3399         sclk = smu7_ps->performance_levels[0].engine_clock;
3400         mclk = smu7_ps->performance_levels[0].memory_clock;
3401
3402         if (disable_mclk_switching &&
3403             (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
3404             hwmgr->chip_id <= CHIP_VEGAM)))
3405                 mclk = smu7_ps->performance_levels
3406                 [smu7_ps->performance_level_count - 1].memory_clock;
3407
3408         if (sclk < minimum_clocks.engineClock)
3409                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3410                                 max_limits->sclk : minimum_clocks.engineClock;
3411
3412         if (mclk < minimum_clocks.memoryClock)
3413                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3414                                 max_limits->mclk : minimum_clocks.memoryClock;
3415
3416         smu7_ps->performance_levels[0].engine_clock = sclk;
3417         smu7_ps->performance_levels[0].memory_clock = mclk;
3418
3419         smu7_ps->performance_levels[1].engine_clock =
3420                 (smu7_ps->performance_levels[1].engine_clock >=
3421                                 smu7_ps->performance_levels[0].engine_clock) ?
3422                                                 smu7_ps->performance_levels[1].engine_clock :
3423                                                 smu7_ps->performance_levels[0].engine_clock;
3424
3425         if (disable_mclk_switching) {
3426                 if (mclk < smu7_ps->performance_levels[1].memory_clock)
3427                         mclk = smu7_ps->performance_levels[1].memory_clock;
3428
3429                 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) {
3430                         if (disable_mclk_switching_for_display) {
3431                                 /* Find the lowest MCLK frequency that is within
3432                                  * the tolerable latency defined in DAL
3433                                  */
3434                                 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3435                                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3436                                         if (data->mclk_latency_table.entries[i].latency <= latency) {
3437                                                 latency_allowed = true;
3438
3439                                                 if ((data->mclk_latency_table.entries[i].frequency >=
3440                                                                 smu7_ps->performance_levels[0].memory_clock) &&
3441                                                     (data->mclk_latency_table.entries[i].frequency <=
3442                                                                 smu7_ps->performance_levels[1].memory_clock)) {
3443                                                         mclk = data->mclk_latency_table.entries[i].frequency;
3444                                                         break;
3445                                                 }
3446                                         }
3447                                 }
3448                                 if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) {
3449                                         data->mclk_ignore_signal = true;
3450                                 } else {
3451                                         data->mclk_ignore_signal = false;
3452                                 }
3453                         }
3454
3455                         if (disable_mclk_switching_for_frame_lock)
3456                                 mclk = smu7_ps->performance_levels[1].memory_clock;
3457                 }
3458
3459                 smu7_ps->performance_levels[0].memory_clock = mclk;
3460
3461                 if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
3462                       hwmgr->chip_id <= CHIP_VEGAM))
3463                         smu7_ps->performance_levels[1].memory_clock = mclk;
3464         } else {
3465                 if (smu7_ps->performance_levels[1].memory_clock <
3466                                 smu7_ps->performance_levels[0].memory_clock)
3467                         smu7_ps->performance_levels[1].memory_clock =
3468                                         smu7_ps->performance_levels[0].memory_clock;
3469         }
3470
3471         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3472                         PHM_PlatformCaps_StablePState)) {
3473                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3474                         smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3475                         smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3476                         smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3477                         smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3478                 }
3479         }
3480         return 0;
3481 }
3482
3483
3484 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3485 {
3486         struct pp_power_state  *ps;
3487         struct smu7_power_state  *smu7_ps;
3488
3489         if (hwmgr == NULL)
3490                 return -EINVAL;
3491
3492         ps = hwmgr->request_ps;
3493
3494         if (ps == NULL)
3495                 return -EINVAL;
3496
3497         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3498
3499         if (low)
3500                 return smu7_ps->performance_levels[0].memory_clock;
3501         else
3502                 return smu7_ps->performance_levels
3503                                 [smu7_ps->performance_level_count-1].memory_clock;
3504 }
3505
3506 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3507 {
3508         struct pp_power_state  *ps;
3509         struct smu7_power_state  *smu7_ps;
3510
3511         if (hwmgr == NULL)
3512                 return -EINVAL;
3513
3514         ps = hwmgr->request_ps;
3515
3516         if (ps == NULL)
3517                 return -EINVAL;
3518
3519         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3520
3521         if (low)
3522                 return smu7_ps->performance_levels[0].engine_clock;
3523         else
3524                 return smu7_ps->performance_levels
3525                                 [smu7_ps->performance_level_count-1].engine_clock;
3526 }
3527
3528 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3529                                         struct pp_hw_power_state *hw_ps)
3530 {
3531         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3532         struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
3533         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3534         uint16_t size;
3535         uint8_t frev, crev;
3536         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3537
3538         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3539          * We assume here that fw_info is unchanged if this call fails.
3540          */
3541         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
3542                         &size, &frev, &crev);
3543         if (!fw_info)
3544                 /* During a test, there is no firmware info table. */
3545                 return 0;
3546
3547         /* Patch the state. */
3548         data->vbios_boot_state.sclk_bootup_value =
3549                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3550         data->vbios_boot_state.mclk_bootup_value =
3551                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3552         data->vbios_boot_state.mvdd_bootup_value =
3553                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3554         data->vbios_boot_state.vddc_bootup_value =
3555                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3556         data->vbios_boot_state.vddci_bootup_value =
3557                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3558         data->vbios_boot_state.pcie_gen_bootup_value =
3559                         smu7_get_current_pcie_speed(hwmgr);
3560
3561         data->vbios_boot_state.pcie_lane_bootup_value =
3562                         (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
3563
3564         /* set boot power state */
3565         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3566         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3567         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3568         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3569
3570         return 0;
3571 }
3572
3573 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
3574 {
3575         int result;
3576         unsigned long ret = 0;
3577
3578         if (hwmgr->pp_table_version == PP_TABLE_V0) {
3579                 result = pp_tables_get_num_of_entries(hwmgr, &ret);
3580                 return result ? 0 : ret;
3581         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3582                 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
3583                 return result;
3584         }
3585         return 0;
3586 }
3587
3588 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
3589                 void *state, struct pp_power_state *power_state,
3590                 void *pp_table, uint32_t classification_flag)
3591 {
3592         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3593         struct smu7_power_state  *smu7_power_state =
3594                         (struct smu7_power_state *)(&(power_state->hardware));
3595         struct smu7_performance_level *performance_level;
3596         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3597         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3598                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3599         PPTable_Generic_SubTable_Header *sclk_dep_table =
3600                         (PPTable_Generic_SubTable_Header *)
3601                         (((unsigned long)powerplay_table) +
3602                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3603
3604         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3605                         (ATOM_Tonga_MCLK_Dependency_Table *)
3606                         (((unsigned long)powerplay_table) +
3607                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3608
3609         /* The following fields are not initialized here: id orderedList allStatesList */
3610         power_state->classification.ui_label =
3611                         (le16_to_cpu(state_entry->usClassification) &
3612                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3613                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3614         power_state->classification.flags = classification_flag;
3615         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3616
3617         power_state->classification.temporary_state = false;
3618         power_state->classification.to_be_deleted = false;
3619
3620         power_state->validation.disallowOnDC =
3621                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3622                                         ATOM_Tonga_DISALLOW_ON_DC));
3623
3624         power_state->pcie.lanes = 0;
3625
3626         power_state->display.disableFrameModulation = false;
3627         power_state->display.limitRefreshrate = false;
3628         power_state->display.enableVariBright =
3629                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3630                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3631
3632         power_state->validation.supportedPowerLevels = 0;
3633         power_state->uvd_clocks.VCLK = 0;
3634         power_state->uvd_clocks.DCLK = 0;
3635         power_state->temperatures.min = 0;
3636         power_state->temperatures.max = 0;
3637
3638         performance_level = &(smu7_power_state->performance_levels
3639                         [smu7_power_state->performance_level_count++]);
3640
3641         PP_ASSERT_WITH_CODE(
3642                         (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3643                         "Performance levels exceeds SMC limit!",
3644                         return -EINVAL);
3645
3646         PP_ASSERT_WITH_CODE(
3647                         (smu7_power_state->performance_level_count <
3648                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3649                         "Performance levels exceeds Driver limit!",
3650                         return -EINVAL);
3651
3652         /* Performance levels are arranged from low to high. */
3653         performance_level->memory_clock = mclk_dep_table->entries
3654                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3655         if (sclk_dep_table->ucRevId == 0)
3656                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3657                         [state_entry->ucEngineClockIndexLow].ulSclk;
3658         else if (sclk_dep_table->ucRevId == 1)
3659                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3660                         [state_entry->ucEngineClockIndexLow].ulSclk;
3661         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3662                         state_entry->ucPCIEGenLow);
3663         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3664                         state_entry->ucPCIELaneLow);
3665
3666         performance_level = &(smu7_power_state->performance_levels
3667                         [smu7_power_state->performance_level_count++]);
3668         performance_level->memory_clock = mclk_dep_table->entries
3669                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3670
3671         if (sclk_dep_table->ucRevId == 0)
3672                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3673                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3674         else if (sclk_dep_table->ucRevId == 1)
3675                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3676                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3677
3678         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3679                         state_entry->ucPCIEGenHigh);
3680         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3681                         state_entry->ucPCIELaneHigh);
3682
3683         return 0;
3684 }
3685
3686 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
3687                 unsigned long entry_index, struct pp_power_state *state)
3688 {
3689         int result;
3690         struct smu7_power_state *ps;
3691         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3692         struct phm_ppt_v1_information *table_info =
3693                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3694         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3695                         table_info->vdd_dep_on_mclk;
3696
3697         state->hardware.magic = PHM_VIslands_Magic;
3698
3699         ps = (struct smu7_power_state *)(&state->hardware);
3700
3701         result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
3702                         smu7_get_pp_table_entry_callback_func_v1);
3703
3704         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3705          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3706          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3707          */
3708         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3709                 if (dep_mclk_table->entries[0].clk !=
3710                                 data->vbios_boot_state.mclk_bootup_value)
3711                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3712                                         "does not match VBIOS boot MCLK level");
3713                 if (dep_mclk_table->entries[0].vddci !=
3714                                 data->vbios_boot_state.vddci_bootup_value)
3715                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3716                                         "does not match VBIOS boot VDDCI level");
3717         }
3718
3719         /* set DC compatible flag if this state supports DC */
3720         if (!state->validation.disallowOnDC)
3721                 ps->dc_compatible = true;
3722
3723         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3724                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3725
3726         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3727         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3728
3729         if (!result) {
3730                 uint32_t i;
3731
3732                 switch (state->classification.ui_label) {
3733                 case PP_StateUILabel_Performance:
3734                         data->use_pcie_performance_levels = true;
3735                         for (i = 0; i < ps->performance_level_count; i++) {
3736                                 if (data->pcie_gen_performance.max <
3737                                                 ps->performance_levels[i].pcie_gen)
3738                                         data->pcie_gen_performance.max =
3739                                                         ps->performance_levels[i].pcie_gen;
3740
3741                                 if (data->pcie_gen_performance.min >
3742                                                 ps->performance_levels[i].pcie_gen)
3743                                         data->pcie_gen_performance.min =
3744                                                         ps->performance_levels[i].pcie_gen;
3745
3746                                 if (data->pcie_lane_performance.max <
3747                                                 ps->performance_levels[i].pcie_lane)
3748                                         data->pcie_lane_performance.max =
3749                                                         ps->performance_levels[i].pcie_lane;
3750                                 if (data->pcie_lane_performance.min >
3751                                                 ps->performance_levels[i].pcie_lane)
3752                                         data->pcie_lane_performance.min =
3753                                                         ps->performance_levels[i].pcie_lane;
3754                         }
3755                         break;
3756                 case PP_StateUILabel_Battery:
3757                         data->use_pcie_power_saving_levels = true;
3758
3759                         for (i = 0; i < ps->performance_level_count; i++) {
3760                                 if (data->pcie_gen_power_saving.max <
3761                                                 ps->performance_levels[i].pcie_gen)
3762                                         data->pcie_gen_power_saving.max =
3763                                                         ps->performance_levels[i].pcie_gen;
3764
3765                                 if (data->pcie_gen_power_saving.min >
3766                                                 ps->performance_levels[i].pcie_gen)
3767                                         data->pcie_gen_power_saving.min =
3768                                                         ps->performance_levels[i].pcie_gen;
3769
3770                                 if (data->pcie_lane_power_saving.max <
3771                                                 ps->performance_levels[i].pcie_lane)
3772                                         data->pcie_lane_power_saving.max =
3773                                                         ps->performance_levels[i].pcie_lane;
3774
3775                                 if (data->pcie_lane_power_saving.min >
3776                                                 ps->performance_levels[i].pcie_lane)
3777                                         data->pcie_lane_power_saving.min =
3778                                                         ps->performance_levels[i].pcie_lane;
3779                         }
3780                         break;
3781                 default:
3782                         break;
3783                 }
3784         }
3785         return 0;
3786 }
3787
3788 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3789                                         struct pp_hw_power_state *power_state,
3790                                         unsigned int index, const void *clock_info)
3791 {
3792         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3793         struct smu7_power_state  *ps = cast_phw_smu7_power_state(power_state);
3794         const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
3795         struct smu7_performance_level *performance_level;
3796         uint32_t engine_clock, memory_clock;
3797         uint16_t pcie_gen_from_bios;
3798
3799         engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
3800         memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
3801
3802         if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
3803                 data->highest_mclk = memory_clock;
3804
3805         PP_ASSERT_WITH_CODE(
3806                         (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3807                         "Performance levels exceeds SMC limit!",
3808                         return -EINVAL);
3809
3810         PP_ASSERT_WITH_CODE(
3811                         (ps->performance_level_count <
3812                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3813                         "Performance levels exceeds Driver limit, Skip!",
3814                         return 0);
3815
3816         performance_level = &(ps->performance_levels
3817                         [ps->performance_level_count++]);
3818
3819         /* Performance levels are arranged from low to high. */
3820         performance_level->memory_clock = memory_clock;
3821         performance_level->engine_clock = engine_clock;
3822
3823         pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
3824
3825         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
3826         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
3827
3828         return 0;
3829 }
3830
3831 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
3832                 unsigned long entry_index, struct pp_power_state *state)
3833 {
3834         int result;
3835         struct smu7_power_state *ps;
3836         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3837         struct phm_clock_voltage_dependency_table *dep_mclk_table =
3838                         hwmgr->dyn_state.vddci_dependency_on_mclk;
3839
3840         memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3841
3842         state->hardware.magic = PHM_VIslands_Magic;
3843
3844         ps = (struct smu7_power_state *)(&state->hardware);
3845
3846         result = pp_tables_get_entry(hwmgr, entry_index, state,
3847                         smu7_get_pp_table_entry_callback_func_v0);
3848
3849         /*
3850          * This is the earliest time we have all the dependency table
3851          * and the VBIOS boot state as
3852          * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3853          * state if there is only one VDDCI/MCLK level, check if it's
3854          * the same as VBIOS boot state
3855          */
3856         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3857                 if (dep_mclk_table->entries[0].clk !=
3858                                 data->vbios_boot_state.mclk_bootup_value)
3859                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3860                                         "does not match VBIOS boot MCLK level");
3861                 if (dep_mclk_table->entries[0].v !=
3862                                 data->vbios_boot_state.vddci_bootup_value)
3863                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3864                                         "does not match VBIOS boot VDDCI level");
3865         }
3866
3867         /* set DC compatible flag if this state supports DC */
3868         if (!state->validation.disallowOnDC)
3869                 ps->dc_compatible = true;
3870
3871         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3872                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3873
3874         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3875         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3876
3877         if (!result) {
3878                 uint32_t i;
3879
3880                 switch (state->classification.ui_label) {
3881                 case PP_StateUILabel_Performance:
3882                         data->use_pcie_performance_levels = true;
3883
3884                         for (i = 0; i < ps->performance_level_count; i++) {
3885                                 if (data->pcie_gen_performance.max <
3886                                                 ps->performance_levels[i].pcie_gen)
3887                                         data->pcie_gen_performance.max =
3888                                                         ps->performance_levels[i].pcie_gen;
3889
3890                                 if (data->pcie_gen_performance.min >
3891                                                 ps->performance_levels[i].pcie_gen)
3892                                         data->pcie_gen_performance.min =
3893                                                         ps->performance_levels[i].pcie_gen;
3894
3895                                 if (data->pcie_lane_performance.max <
3896                                                 ps->performance_levels[i].pcie_lane)
3897                                         data->pcie_lane_performance.max =
3898                                                         ps->performance_levels[i].pcie_lane;
3899
3900                                 if (data->pcie_lane_performance.min >
3901                                                 ps->performance_levels[i].pcie_lane)
3902                                         data->pcie_lane_performance.min =
3903                                                         ps->performance_levels[i].pcie_lane;
3904                         }
3905                         break;
3906                 case PP_StateUILabel_Battery:
3907                         data->use_pcie_power_saving_levels = true;
3908
3909                         for (i = 0; i < ps->performance_level_count; i++) {
3910                                 if (data->pcie_gen_power_saving.max <
3911                                                 ps->performance_levels[i].pcie_gen)
3912                                         data->pcie_gen_power_saving.max =
3913                                                         ps->performance_levels[i].pcie_gen;
3914
3915                                 if (data->pcie_gen_power_saving.min >
3916                                                 ps->performance_levels[i].pcie_gen)
3917                                         data->pcie_gen_power_saving.min =
3918                                                         ps->performance_levels[i].pcie_gen;
3919
3920                                 if (data->pcie_lane_power_saving.max <
3921                                                 ps->performance_levels[i].pcie_lane)
3922                                         data->pcie_lane_power_saving.max =
3923                                                         ps->performance_levels[i].pcie_lane;
3924
3925                                 if (data->pcie_lane_power_saving.min >
3926                                                 ps->performance_levels[i].pcie_lane)
3927                                         data->pcie_lane_power_saving.min =
3928                                                         ps->performance_levels[i].pcie_lane;
3929                         }
3930                         break;
3931                 default:
3932                         break;
3933                 }
3934         }
3935         return 0;
3936 }
3937
3938 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3939                 unsigned long entry_index, struct pp_power_state *state)
3940 {
3941         if (hwmgr->pp_table_version == PP_TABLE_V0)
3942                 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3943         else if (hwmgr->pp_table_version == PP_TABLE_V1)
3944                 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3945
3946         return 0;
3947 }
3948
3949 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
3950 {
3951         struct amdgpu_device *adev = hwmgr->adev;
3952         int i;
3953         u32 tmp = 0;
3954
3955         if (!query)
3956                 return -EINVAL;
3957
3958         /*
3959          * PPSMC_MSG_GetCurrPkgPwr is not supported on:
3960          *  - Hawaii
3961          *  - Bonaire
3962          *  - Fiji
3963          *  - Tonga
3964          */
3965         if ((adev->asic_type != CHIP_HAWAII) &&
3966             (adev->asic_type != CHIP_BONAIRE) &&
3967             (adev->asic_type != CHIP_FIJI) &&
3968             (adev->asic_type != CHIP_TONGA)) {
3969                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp);
3970                 *query = tmp;
3971
3972                 if (tmp != 0)
3973                         return 0;
3974         }
3975
3976         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL);
3977         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3978                                                         ixSMU_PM_STATUS_95, 0);
3979
3980         for (i = 0; i < 10; i++) {
3981                 msleep(500);
3982                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL);
3983                 tmp = cgs_read_ind_register(hwmgr->device,
3984                                                 CGS_IND_REG__SMC,
3985                                                 ixSMU_PM_STATUS_95);
3986                 if (tmp != 0)
3987                         break;
3988         }
3989         *query = tmp;
3990
3991         return 0;
3992 }
3993
3994 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3995                             void *value, int *size)
3996 {
3997         uint32_t sclk, mclk, activity_percent;
3998         uint32_t offset, val_vid;
3999         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4000
4001         /* size must be at least 4 bytes for all sensors */
4002         if (*size < 4)
4003                 return -EINVAL;
4004
4005         switch (idx) {
4006         case AMDGPU_PP_SENSOR_GFX_SCLK:
4007                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &sclk);
4008                 *((uint32_t *)value) = sclk;
4009                 *size = 4;
4010                 return 0;
4011         case AMDGPU_PP_SENSOR_GFX_MCLK:
4012                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &mclk);
4013                 *((uint32_t *)value) = mclk;
4014                 *size = 4;
4015                 return 0;
4016         case AMDGPU_PP_SENSOR_GPU_LOAD:
4017         case AMDGPU_PP_SENSOR_MEM_LOAD:
4018                 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
4019                                                                 SMU_SoftRegisters,
4020                                                                 (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ?
4021                                                                 AverageGraphicsActivity :
4022                                                                 AverageMemoryActivity);
4023
4024                 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4025                 activity_percent += 0x80;
4026                 activity_percent >>= 8;
4027                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
4028                 *size = 4;
4029                 return 0;
4030         case AMDGPU_PP_SENSOR_GPU_TEMP:
4031                 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
4032                 *size = 4;
4033                 return 0;
4034         case AMDGPU_PP_SENSOR_UVD_POWER:
4035                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
4036                 *size = 4;
4037                 return 0;
4038         case AMDGPU_PP_SENSOR_VCE_POWER:
4039                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
4040                 *size = 4;
4041                 return 0;
4042         case AMDGPU_PP_SENSOR_GPU_POWER:
4043                 return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
4044         case AMDGPU_PP_SENSOR_VDDGFX:
4045                 if ((data->vr_config & VRCONF_VDDGFX_MASK) ==
4046                     (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT))
4047                         val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4048                                         CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
4049                 else
4050                         val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4051                                         CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID);
4052
4053                 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);
4054                 return 0;
4055         default:
4056                 return -EOPNOTSUPP;
4057         }
4058 }
4059
4060 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4061 {
4062         const struct phm_set_power_state_input *states =
4063                         (const struct phm_set_power_state_input *)input;
4064         const struct smu7_power_state *smu7_ps =
4065                         cast_const_phw_smu7_power_state(states->pnew_state);
4066         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4067         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4068         uint32_t sclk = smu7_ps->performance_levels
4069                         [smu7_ps->performance_level_count - 1].engine_clock;
4070         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4071         uint32_t mclk = smu7_ps->performance_levels
4072                         [smu7_ps->performance_level_count - 1].memory_clock;
4073         struct PP_Clocks min_clocks = {0};
4074         uint32_t i;
4075
4076         for (i = 0; i < sclk_table->count; i++) {
4077                 if (sclk == sclk_table->dpm_levels[i].value)
4078                         break;
4079         }
4080
4081         if (i >= sclk_table->count) {
4082                 if (sclk > sclk_table->dpm_levels[i-1].value) {
4083                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4084                         sclk_table->dpm_levels[i-1].value = sclk;
4085                 }
4086         } else {
4087         /* TODO: Check SCLK in DAL's minimum clocks
4088          * in case DeepSleep divider update is required.
4089          */
4090                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4091                         (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
4092                                 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4093                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4094         }
4095
4096         for (i = 0; i < mclk_table->count; i++) {
4097                 if (mclk == mclk_table->dpm_levels[i].value)
4098                         break;
4099         }
4100
4101         if (i >= mclk_table->count) {
4102                 if (mclk > mclk_table->dpm_levels[i-1].value) {
4103                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4104                         mclk_table->dpm_levels[i-1].value = mclk;
4105                 }
4106         }
4107
4108         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4109                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4110
4111         return 0;
4112 }
4113
4114 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4115                 const struct smu7_power_state *smu7_ps)
4116 {
4117         uint32_t i;
4118         uint32_t sclk, max_sclk = 0;
4119         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4120         struct smu7_dpm_table *dpm_table = &data->dpm_table;
4121
4122         for (i = 0; i < smu7_ps->performance_level_count; i++) {
4123                 sclk = smu7_ps->performance_levels[i].engine_clock;
4124                 if (max_sclk < sclk)
4125                         max_sclk = sclk;
4126         }
4127
4128         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4129                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4130                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4131                                         dpm_table->pcie_speed_table.dpm_levels
4132                                         [dpm_table->pcie_speed_table.count - 1].value :
4133                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4134         }
4135
4136         return 0;
4137 }
4138
4139 static int smu7_request_link_speed_change_before_state_change(
4140                 struct pp_hwmgr *hwmgr, const void *input)
4141 {
4142         const struct phm_set_power_state_input *states =
4143                         (const struct phm_set_power_state_input *)input;
4144         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4145         const struct smu7_power_state *smu7_nps =
4146                         cast_const_phw_smu7_power_state(states->pnew_state);
4147         const struct smu7_power_state *polaris10_cps =
4148                         cast_const_phw_smu7_power_state(states->pcurrent_state);
4149
4150         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
4151         uint16_t current_link_speed;
4152
4153         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4154                 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
4155         else
4156                 current_link_speed = data->force_pcie_gen;
4157
4158         data->force_pcie_gen = PP_PCIEGenInvalid;
4159         data->pspp_notify_required = false;
4160
4161         if (target_link_speed > current_link_speed) {
4162                 switch (target_link_speed) {
4163 #ifdef CONFIG_ACPI
4164                 case PP_PCIEGen3:
4165                         if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
4166                                 break;
4167                         data->force_pcie_gen = PP_PCIEGen2;
4168                         if (current_link_speed == PP_PCIEGen2)
4169                                 break;
4170                         fallthrough;
4171                 case PP_PCIEGen2:
4172                         if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
4173                                 break;
4174                         fallthrough;
4175 #endif
4176                 default:
4177                         data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
4178                         break;
4179                 }
4180         } else {
4181                 if (target_link_speed < current_link_speed)
4182                         data->pspp_notify_required = true;
4183         }
4184
4185         return 0;
4186 }
4187
4188 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4189 {
4190         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4191
4192         if (0 == data->need_update_smu7_dpm_table)
4193                 return 0;
4194
4195         if ((0 == data->sclk_dpm_key_disabled) &&
4196                 (data->need_update_smu7_dpm_table &
4197                         (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
4198                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4199                                 "Trying to freeze SCLK DPM when DPM is disabled",
4200                                 );
4201                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4202                                 PPSMC_MSG_SCLKDPM_FreezeLevel,
4203                                 NULL),
4204                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4205                                 return -EINVAL);
4206         }
4207
4208         if ((0 == data->mclk_dpm_key_disabled) &&
4209                 !data->mclk_ignore_signal &&
4210                 (data->need_update_smu7_dpm_table &
4211                  DPMTABLE_OD_UPDATE_MCLK)) {
4212                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4213                                 "Trying to freeze MCLK DPM when DPM is disabled",
4214                                 );
4215                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4216                                 PPSMC_MSG_MCLKDPM_FreezeLevel,
4217                                 NULL),
4218                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4219                                 return -EINVAL);
4220         }
4221
4222         return 0;
4223 }
4224
4225 static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
4226                 struct pp_hwmgr *hwmgr, const void *input)
4227 {
4228         int result = 0;
4229         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4230         struct smu7_dpm_table *dpm_table = &data->dpm_table;
4231         uint32_t count;
4232         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4233         struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4234         struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4235
4236         if (0 == data->need_update_smu7_dpm_table)
4237                 return 0;
4238
4239         if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4240                 for (count = 0; count < dpm_table->sclk_table.count; count++) {
4241                         dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
4242                         dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
4243                 }
4244         }
4245
4246         if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4247                 for (count = 0; count < dpm_table->mclk_table.count; count++) {
4248                         dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
4249                         dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
4250                 }
4251         }
4252
4253         if (data->need_update_smu7_dpm_table &
4254                         (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4255                 result = smum_populate_all_graphic_levels(hwmgr);
4256                 PP_ASSERT_WITH_CODE((0 == result),
4257                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4258                                 return result);
4259         }
4260
4261         if (data->need_update_smu7_dpm_table &
4262                         (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4263                 /*populate MCLK dpm table to SMU7 */
4264                 result = smum_populate_all_memory_levels(hwmgr);
4265                 PP_ASSERT_WITH_CODE((0 == result),
4266                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4267                                 return result);
4268         }
4269
4270         return result;
4271 }
4272
4273 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4274                           struct smu7_single_dpm_table *dpm_table,
4275                         uint32_t low_limit, uint32_t high_limit)
4276 {
4277         uint32_t i;
4278
4279         /* force the trim if mclk_switching is disabled to prevent flicker */
4280         bool force_trim = (low_limit == high_limit);
4281         for (i = 0; i < dpm_table->count; i++) {
4282         /*skip the trim if od is enabled*/
4283                 if ((!hwmgr->od_enabled || force_trim)
4284                         && (dpm_table->dpm_levels[i].value < low_limit
4285                         || dpm_table->dpm_levels[i].value > high_limit))
4286                         dpm_table->dpm_levels[i].enabled = false;
4287                 else
4288                         dpm_table->dpm_levels[i].enabled = true;
4289         }
4290
4291         return 0;
4292 }
4293
4294 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
4295                 const struct smu7_power_state *smu7_ps)
4296 {
4297         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4298         uint32_t high_limit_count;
4299
4300         PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
4301                         "power state did not have any performance level",
4302                         return -EINVAL);
4303
4304         high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
4305
4306         smu7_trim_single_dpm_states(hwmgr,
4307                         &(data->dpm_table.sclk_table),
4308                         smu7_ps->performance_levels[0].engine_clock,
4309                         smu7_ps->performance_levels[high_limit_count].engine_clock);
4310
4311         smu7_trim_single_dpm_states(hwmgr,
4312                         &(data->dpm_table.mclk_table),
4313                         smu7_ps->performance_levels[0].memory_clock,
4314                         smu7_ps->performance_levels[high_limit_count].memory_clock);
4315
4316         return 0;
4317 }
4318
4319 static int smu7_generate_dpm_level_enable_mask(
4320                 struct pp_hwmgr *hwmgr, const void *input)
4321 {
4322         int result = 0;
4323         const struct phm_set_power_state_input *states =
4324                         (const struct phm_set_power_state_input *)input;
4325         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4326         const struct smu7_power_state *smu7_ps =
4327                         cast_const_phw_smu7_power_state(states->pnew_state);
4328
4329
4330         result = smu7_trim_dpm_states(hwmgr, smu7_ps);
4331         if (result)
4332                 return result;
4333
4334         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4335                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4336         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4337                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4338         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4339                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4340
4341         return 0;
4342 }
4343
4344 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4345 {
4346         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4347
4348         if (0 == data->need_update_smu7_dpm_table)
4349                 return 0;
4350
4351         if ((0 == data->sclk_dpm_key_disabled) &&
4352                 (data->need_update_smu7_dpm_table &
4353                 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
4354
4355                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4356                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4357                                 );
4358                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4359                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel,
4360                                 NULL),
4361                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4362                         return -EINVAL);
4363         }
4364
4365         if ((0 == data->mclk_dpm_key_disabled) &&
4366                 !data->mclk_ignore_signal &&
4367                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4368
4369                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4370                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4371                                 );
4372                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4373                                 PPSMC_MSG_MCLKDPM_UnfreezeLevel,
4374                                 NULL),
4375                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4376                     return -EINVAL);
4377         }
4378
4379         data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
4380
4381         return 0;
4382 }
4383
4384 static int smu7_notify_link_speed_change_after_state_change(
4385                 struct pp_hwmgr *hwmgr, const void *input)
4386 {
4387         const struct phm_set_power_state_input *states =
4388                         (const struct phm_set_power_state_input *)input;
4389         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4390         const struct smu7_power_state *smu7_ps =
4391                         cast_const_phw_smu7_power_state(states->pnew_state);
4392         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
4393         uint8_t  request;
4394
4395         if (data->pspp_notify_required) {
4396                 if (target_link_speed == PP_PCIEGen3)
4397                         request = PCIE_PERF_REQ_GEN3;
4398                 else if (target_link_speed == PP_PCIEGen2)
4399                         request = PCIE_PERF_REQ_GEN2;
4400                 else
4401                         request = PCIE_PERF_REQ_GEN1;
4402
4403                 if (request == PCIE_PERF_REQ_GEN1 &&
4404                                 smu7_get_current_pcie_speed(hwmgr) > 0)
4405                         return 0;
4406
4407 #ifdef CONFIG_ACPI
4408                 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
4409                         if (PP_PCIEGen2 == target_link_speed)
4410                                 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
4411                         else
4412                                 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
4413                 }
4414 #endif
4415         }
4416
4417         return 0;
4418 }
4419
4420 static int smu7_notify_no_display(struct pp_hwmgr *hwmgr)
4421 {
4422         return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL) == 0) ?  0 : -EINVAL;
4423 }
4424
4425 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr)
4426 {
4427         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4428
4429         if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
4430                 if (hwmgr->chip_id == CHIP_VEGAM)
4431                         smum_send_msg_to_smc_with_parameter(hwmgr,
4432                                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2,
4433                                         NULL);
4434                 else
4435                         smum_send_msg_to_smc_with_parameter(hwmgr,
4436                                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2,
4437                                         NULL);
4438                 data->last_sent_vbi_timeout = data->frame_time_x2;
4439         }
4440
4441         return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ?  0 : -EINVAL;
4442 }
4443
4444 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
4445 {
4446         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4447         int result = 0;
4448
4449         if (data->mclk_ignore_signal)
4450                 result = smu7_notify_no_display(hwmgr);
4451         else
4452                 result = smu7_notify_has_display(hwmgr);
4453
4454         return result;
4455 }
4456
4457 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4458 {
4459         int tmp_result, result = 0;
4460         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4461
4462         tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4463         PP_ASSERT_WITH_CODE((0 == tmp_result),
4464                         "Failed to find DPM states clocks in DPM table!",
4465                         result = tmp_result);
4466
4467         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4468                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4469                 tmp_result =
4470                         smu7_request_link_speed_change_before_state_change(hwmgr, input);
4471                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4472                                 "Failed to request link speed change before state change!",
4473                                 result = tmp_result);
4474         }
4475
4476         tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
4477         PP_ASSERT_WITH_CODE((0 == tmp_result),
4478                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4479
4480         tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4481         PP_ASSERT_WITH_CODE((0 == tmp_result),
4482                         "Failed to populate and upload SCLK MCLK DPM levels!",
4483                         result = tmp_result);
4484
4485         /*
4486          * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
4487          * That effectively disables AVFS feature.
4488          */
4489         if (hwmgr->hardcode_pp_table != NULL)
4490                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4491
4492         tmp_result = smu7_update_avfs(hwmgr);
4493         PP_ASSERT_WITH_CODE((0 == tmp_result),
4494                         "Failed to update avfs voltages!",
4495                         result = tmp_result);
4496
4497         tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
4498         PP_ASSERT_WITH_CODE((0 == tmp_result),
4499                         "Failed to generate DPM level enabled mask!",
4500                         result = tmp_result);
4501
4502         tmp_result = smum_update_sclk_threshold(hwmgr);
4503         PP_ASSERT_WITH_CODE((0 == tmp_result),
4504                         "Failed to update SCLK threshold!",
4505                         result = tmp_result);
4506
4507         tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
4508         PP_ASSERT_WITH_CODE((0 == tmp_result),
4509                         "Failed to unfreeze SCLK MCLK DPM!",
4510                         result = tmp_result);
4511
4512         tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
4513         PP_ASSERT_WITH_CODE((0 == tmp_result),
4514                         "Failed to upload DPM level enabled mask!",
4515                         result = tmp_result);
4516
4517         tmp_result = smu7_notify_smc_display(hwmgr);
4518         PP_ASSERT_WITH_CODE((0 == tmp_result),
4519                         "Failed to notify smc display settings!",
4520                         result = tmp_result);
4521
4522         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4523                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4524                 tmp_result =
4525                         smu7_notify_link_speed_change_after_state_change(hwmgr, input);
4526                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4527                                 "Failed to notify link speed change after state change!",
4528                                 result = tmp_result);
4529         }
4530         data->apply_optimized_settings = false;
4531         return result;
4532 }
4533
4534 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4535 {
4536         hwmgr->thermal_controller.
4537         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4538
4539         return smum_send_msg_to_smc_with_parameter(hwmgr,
4540                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm,
4541                         NULL);
4542 }
4543
4544 static int
4545 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4546 {
4547         return 0;
4548 }
4549
4550 /**
4551  * smu7_program_display_gap - Programs the display gap
4552  *
4553  * @hwmgr:  the address of the powerplay hardware manager.
4554  * Return:   always OK
4555  */
4556 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
4557 {
4558         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4559         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4560         uint32_t display_gap2;
4561         uint32_t pre_vbi_time_in_us;
4562         uint32_t frame_time_in_us;
4563         uint32_t ref_clock, refresh_rate;
4564
4565         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4566         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4567
4568         ref_clock =  amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
4569         refresh_rate = hwmgr->display_config->vrefresh;
4570
4571         if (0 == refresh_rate)
4572                 refresh_rate = 60;
4573
4574         frame_time_in_us = 1000000 / refresh_rate;
4575
4576         pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
4577
4578         data->frame_time_x2 = frame_time_in_us * 2 / 100;
4579
4580         if (data->frame_time_x2 < 280) {
4581                 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2);
4582                 data->frame_time_x2 = 280;
4583         }
4584
4585         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4586
4587         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4588
4589         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4590                         data->soft_regs_start + smum_get_offsetof(hwmgr,
4591                                                         SMU_SoftRegisters,
4592                                                         PreVBlankGap), 0x64);
4593
4594         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4595                         data->soft_regs_start + smum_get_offsetof(hwmgr,
4596                                                         SMU_SoftRegisters,
4597                                                         VBlankTimeout),
4598                                         (frame_time_in_us - pre_vbi_time_in_us));
4599
4600         return 0;
4601 }
4602
4603 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4604 {
4605         return smu7_program_display_gap(hwmgr);
4606 }
4607
4608 /**
4609  * smu7_set_max_fan_rpm_output - Set maximum target operating fan output RPM
4610  *
4611  * @hwmgr:  the address of the powerplay hardware manager.
4612  * @us_max_fan_rpm:  max operating fan RPM value.
4613  * Return:   The response that came from the SMC.
4614  */
4615 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4616 {
4617         hwmgr->thermal_controller.
4618         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4619
4620         return smum_send_msg_to_smc_with_parameter(hwmgr,
4621                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm,
4622                         NULL);
4623 }
4624
4625 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
4626         .process = phm_irq_process,
4627 };
4628
4629 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
4630 {
4631         struct amdgpu_irq_src *source =
4632                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
4633
4634         if (!source)
4635                 return -ENOMEM;
4636
4637         source->funcs = &smu7_irq_funcs;
4638
4639         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4640                         AMDGPU_IRQ_CLIENTID_LEGACY,
4641                         VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
4642                         source);
4643         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4644                         AMDGPU_IRQ_CLIENTID_LEGACY,
4645                         VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
4646                         source);
4647
4648         /* Register CTF(GPIO_19) interrupt */
4649         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4650                         AMDGPU_IRQ_CLIENTID_LEGACY,
4651                         VISLANDS30_IV_SRCID_GPIO_19,
4652                         source);
4653
4654         return 0;
4655 }
4656
4657 static bool
4658 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4659 {
4660         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4661         bool is_update_required = false;
4662
4663         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4664                 is_update_required = true;
4665
4666         if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
4667                 is_update_required = true;
4668
4669         if (hwmgr->chip_id >= CHIP_POLARIS10 &&
4670             hwmgr->chip_id <= CHIP_VEGAM &&
4671             data->last_sent_vbi_timeout != data->frame_time_x2)
4672                 is_update_required = true;
4673
4674         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4675                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4676                         (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
4677                         hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4678                         is_update_required = true;
4679         }
4680         return is_update_required;
4681 }
4682
4683 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
4684                                                            const struct smu7_performance_level *pl2)
4685 {
4686         return ((pl1->memory_clock == pl2->memory_clock) &&
4687                   (pl1->engine_clock == pl2->engine_clock) &&
4688                   (pl1->pcie_gen == pl2->pcie_gen) &&
4689                   (pl1->pcie_lane == pl2->pcie_lane));
4690 }
4691
4692 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
4693                 const struct pp_hw_power_state *pstate1,
4694                 const struct pp_hw_power_state *pstate2, bool *equal)
4695 {
4696         const struct smu7_power_state *psa;
4697         const struct smu7_power_state *psb;
4698         int i;
4699         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4700
4701         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4702                 return -EINVAL;
4703
4704         psa = cast_const_phw_smu7_power_state(pstate1);
4705         psb = cast_const_phw_smu7_power_state(pstate2);
4706         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4707         if (psa->performance_level_count != psb->performance_level_count) {
4708                 *equal = false;
4709                 return 0;
4710         }
4711
4712         for (i = 0; i < psa->performance_level_count; i++) {
4713                 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4714                         /* If we have found even one performance level pair that is different the states are different. */
4715                         *equal = false;
4716                         return 0;
4717                 }
4718         }
4719
4720         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4721         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4722         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4723         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4724         /* For OD call, set value based on flag */
4725         *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
4726                                                         DPMTABLE_OD_UPDATE_MCLK |
4727                                                         DPMTABLE_OD_UPDATE_VDDC));
4728
4729         return 0;
4730 }
4731
4732 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
4733 {
4734         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4735
4736         uint32_t tmp;
4737
4738         /* Read MC indirect register offset 0x9F bits [3:0] to see
4739          * if VBIOS has already loaded a full version of MC ucode
4740          * or not.
4741          */
4742
4743         smu7_get_mc_microcode_version(hwmgr);
4744
4745         data->need_long_memory_training = false;
4746
4747         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
4748                                                         ixMC_IO_DEBUG_UP_13);
4749         tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
4750
4751         if (tmp & (1 << 23)) {
4752                 data->mem_latency_high = MEM_LATENCY_HIGH;
4753                 data->mem_latency_low = MEM_LATENCY_LOW;
4754                 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4755                     (hwmgr->chip_id == CHIP_POLARIS11) ||
4756                     (hwmgr->chip_id == CHIP_POLARIS12))
4757                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL);
4758         } else {
4759                 data->mem_latency_high = 330;
4760                 data->mem_latency_low = 330;
4761                 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4762                     (hwmgr->chip_id == CHIP_POLARIS11) ||
4763                     (hwmgr->chip_id == CHIP_POLARIS12))
4764                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL);
4765         }
4766
4767         return 0;
4768 }
4769
4770 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
4771 {
4772         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4773
4774         data->clock_registers.vCG_SPLL_FUNC_CNTL         =
4775                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
4776         data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
4777                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
4778         data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
4779                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
4780         data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
4781                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
4782         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
4783                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
4784         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
4785                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
4786         data->clock_registers.vDLL_CNTL                  =
4787                 cgs_read_register(hwmgr->device, mmDLL_CNTL);
4788         data->clock_registers.vMCLK_PWRMGT_CNTL          =
4789                 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
4790         data->clock_registers.vMPLL_AD_FUNC_CNTL         =
4791                 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
4792         data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
4793                 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
4794         data->clock_registers.vMPLL_FUNC_CNTL            =
4795                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
4796         data->clock_registers.vMPLL_FUNC_CNTL_1          =
4797                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
4798         data->clock_registers.vMPLL_FUNC_CNTL_2          =
4799                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
4800         data->clock_registers.vMPLL_SS1                  =
4801                 cgs_read_register(hwmgr->device, mmMPLL_SS1);
4802         data->clock_registers.vMPLL_SS2                  =
4803                 cgs_read_register(hwmgr->device, mmMPLL_SS2);
4804         return 0;
4805
4806 }
4807
4808 /**
4809  * smu7_get_memory_type - Find out if memory is GDDR5.
4810  *
4811  * @hwmgr:  the address of the powerplay hardware manager.
4812  * Return:   always 0
4813  */
4814 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
4815 {
4816         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4817         struct amdgpu_device *adev = hwmgr->adev;
4818
4819         data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
4820
4821         return 0;
4822 }
4823
4824 /**
4825  * smu7_enable_acpi_power_management - Enables Dynamic Power Management by SMC
4826  *
4827  * @hwmgr:  the address of the powerplay hardware manager.
4828  * Return:   always 0
4829  */
4830 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4831 {
4832         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4833                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4834
4835         return 0;
4836 }
4837
4838 /**
4839  * smu7_init_power_gate_state - Initialize PowerGating States for different engines
4840  *
4841  * @hwmgr:  the address of the powerplay hardware manager.
4842  * Return:   always 0
4843  */
4844 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
4845 {
4846         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4847
4848         data->uvd_power_gated = false;
4849         data->vce_power_gated = false;
4850
4851         return 0;
4852 }
4853
4854 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4855 {
4856         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4857
4858         data->low_sclk_interrupt_threshold = 0;
4859         return 0;
4860 }
4861
4862 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
4863 {
4864         int tmp_result, result = 0;
4865
4866         smu7_check_mc_firmware(hwmgr);
4867
4868         tmp_result = smu7_read_clock_registers(hwmgr);
4869         PP_ASSERT_WITH_CODE((0 == tmp_result),
4870                         "Failed to read clock registers!", result = tmp_result);
4871
4872         tmp_result = smu7_get_memory_type(hwmgr);
4873         PP_ASSERT_WITH_CODE((0 == tmp_result),
4874                         "Failed to get memory type!", result = tmp_result);
4875
4876         tmp_result = smu7_enable_acpi_power_management(hwmgr);
4877         PP_ASSERT_WITH_CODE((0 == tmp_result),
4878                         "Failed to enable ACPI power management!", result = tmp_result);
4879
4880         tmp_result = smu7_init_power_gate_state(hwmgr);
4881         PP_ASSERT_WITH_CODE((0 == tmp_result),
4882                         "Failed to init power gate state!", result = tmp_result);
4883
4884         tmp_result = smu7_get_mc_microcode_version(hwmgr);
4885         PP_ASSERT_WITH_CODE((0 == tmp_result),
4886                         "Failed to get MC microcode version!", result = tmp_result);
4887
4888         tmp_result = smu7_init_sclk_threshold(hwmgr);
4889         PP_ASSERT_WITH_CODE((0 == tmp_result),
4890                         "Failed to init sclk threshold!", result = tmp_result);
4891
4892         return result;
4893 }
4894
4895 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4896                 enum pp_clock_type type, uint32_t mask)
4897 {
4898         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4899
4900         if (mask == 0)
4901                 return -EINVAL;
4902
4903         switch (type) {
4904         case PP_SCLK:
4905                 if (!data->sclk_dpm_key_disabled)
4906                         smum_send_msg_to_smc_with_parameter(hwmgr,
4907                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4908                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask,
4909                                         NULL);
4910                 break;
4911         case PP_MCLK:
4912                 if (!data->mclk_dpm_key_disabled)
4913                         smum_send_msg_to_smc_with_parameter(hwmgr,
4914                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4915                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask,
4916                                         NULL);
4917                 break;
4918         case PP_PCIE:
4919         {
4920                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4921
4922                 if (!data->pcie_dpm_key_disabled) {
4923                         if (fls(tmp) != ffs(tmp))
4924                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel,
4925                                                 NULL);
4926                         else
4927                                 smum_send_msg_to_smc_with_parameter(hwmgr,
4928                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4929                                         fls(tmp) - 1,
4930                                         NULL);
4931                 }
4932                 break;
4933         }
4934         default:
4935                 break;
4936         }
4937
4938         return 0;
4939 }
4940
4941 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4942                 enum pp_clock_type type, char *buf)
4943 {
4944         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4945         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4946         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4947         struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4948         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4949         struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4950         struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4951         int size = 0;
4952         uint32_t i, now, clock, pcie_speed;
4953
4954         switch (type) {
4955         case PP_SCLK:
4956                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock);
4957
4958                 for (i = 0; i < sclk_table->count; i++) {
4959                         if (clock > sclk_table->dpm_levels[i].value)
4960                                 continue;
4961                         break;
4962                 }
4963                 now = i;
4964
4965                 for (i = 0; i < sclk_table->count; i++)
4966                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4967                                         i, sclk_table->dpm_levels[i].value / 100,
4968                                         (i == now) ? "*" : "");
4969                 break;
4970         case PP_MCLK:
4971                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock);
4972
4973                 for (i = 0; i < mclk_table->count; i++) {
4974                         if (clock > mclk_table->dpm_levels[i].value)
4975                                 continue;
4976                         break;
4977                 }
4978                 now = i;
4979
4980                 for (i = 0; i < mclk_table->count; i++)
4981                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4982                                         i, mclk_table->dpm_levels[i].value / 100,
4983                                         (i == now) ? "*" : "");
4984                 break;
4985         case PP_PCIE:
4986                 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
4987                 for (i = 0; i < pcie_table->count; i++) {
4988                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4989                                 continue;
4990                         break;
4991                 }
4992                 now = i;
4993
4994                 for (i = 0; i < pcie_table->count; i++)
4995                         size += sprintf(buf + size, "%d: %s %s\n", i,
4996                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
4997                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
4998                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
4999                                         (i == now) ? "*" : "");
5000                 break;
5001         case OD_SCLK:
5002                 if (hwmgr->od_enabled) {
5003                         size += sprintf(buf + size, "%s:\n", "OD_SCLK");
5004                         for (i = 0; i < odn_sclk_table->num_of_pl; i++)
5005                                 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
5006                                         i, odn_sclk_table->entries[i].clock/100,
5007                                         odn_sclk_table->entries[i].vddc);
5008                 }
5009                 break;
5010         case OD_MCLK:
5011                 if (hwmgr->od_enabled) {
5012                         size += sprintf(buf + size, "%s:\n", "OD_MCLK");
5013                         for (i = 0; i < odn_mclk_table->num_of_pl; i++)
5014                                 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
5015                                         i, odn_mclk_table->entries[i].clock/100,
5016                                         odn_mclk_table->entries[i].vddc);
5017                 }
5018                 break;
5019         case OD_RANGE:
5020                 if (hwmgr->od_enabled) {
5021                         size += sprintf(buf + size, "%s:\n", "OD_RANGE");
5022                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
5023                                 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
5024                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5025                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
5026                                 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
5027                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5028                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
5029                                 data->odn_dpm_table.min_vddc,
5030                                 data->odn_dpm_table.max_vddc);
5031                 }
5032                 break;
5033         default:
5034                 break;
5035         }
5036         return size;
5037 }
5038
5039 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5040 {
5041         switch (mode) {
5042         case AMD_FAN_CTRL_NONE:
5043                 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
5044                 break;
5045         case AMD_FAN_CTRL_MANUAL:
5046                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5047                         PHM_PlatformCaps_MicrocodeFanControl))
5048                         smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
5049                 break;
5050         case AMD_FAN_CTRL_AUTO:
5051                 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
5052                         smu7_fan_ctrl_start_smc_fan_control(hwmgr);
5053                 break;
5054         default:
5055                 break;
5056         }
5057 }
5058
5059 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5060 {
5061         return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
5062 }
5063
5064 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
5065 {
5066         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5067         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5068         struct smu7_single_dpm_table *golden_sclk_table =
5069                         &(data->golden_dpm_table.sclk_table);
5070         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
5071         int golden_value = golden_sclk_table->dpm_levels
5072                         [golden_sclk_table->count - 1].value;
5073
5074         value -= golden_value;
5075         value = DIV_ROUND_UP(value * 100, golden_value);
5076
5077         return value;
5078 }
5079
5080 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5081 {
5082         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5083         struct smu7_single_dpm_table *golden_sclk_table =
5084                         &(data->golden_dpm_table.sclk_table);
5085         struct pp_power_state  *ps;
5086         struct smu7_power_state  *smu7_ps;
5087
5088         if (value > 20)
5089                 value = 20;
5090
5091         ps = hwmgr->request_ps;
5092
5093         if (ps == NULL)
5094                 return -EINVAL;
5095
5096         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
5097
5098         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
5099                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5100                         value / 100 +
5101                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5102
5103         return 0;
5104 }
5105
5106 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
5107 {
5108         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5109         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5110         struct smu7_single_dpm_table *golden_mclk_table =
5111                         &(data->golden_dpm_table.mclk_table);
5112         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
5113         int golden_value = golden_mclk_table->dpm_levels
5114                         [golden_mclk_table->count - 1].value;
5115
5116         value -= golden_value;
5117         value = DIV_ROUND_UP(value * 100, golden_value);
5118
5119         return value;
5120 }
5121
5122 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5123 {
5124         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5125         struct smu7_single_dpm_table *golden_mclk_table =
5126                         &(data->golden_dpm_table.mclk_table);
5127         struct pp_power_state  *ps;
5128         struct smu7_power_state  *smu7_ps;
5129
5130         if (value > 20)
5131                 value = 20;
5132
5133         ps = hwmgr->request_ps;
5134
5135         if (ps == NULL)
5136                 return -EINVAL;
5137
5138         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
5139
5140         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
5141                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5142                         value / 100 +
5143                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5144
5145         return 0;
5146 }
5147
5148
5149 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
5150 {
5151         struct phm_ppt_v1_information *table_info =
5152                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5153         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
5154         struct phm_clock_voltage_dependency_table *sclk_table;
5155         int i;
5156
5157         if (hwmgr->pp_table_version == PP_TABLE_V1) {
5158                 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
5159                         return -EINVAL;
5160                 dep_sclk_table = table_info->vdd_dep_on_sclk;
5161                 for (i = 0; i < dep_sclk_table->count; i++)
5162                         clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
5163                 clocks->count = dep_sclk_table->count;
5164         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
5165                 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
5166                 for (i = 0; i < sclk_table->count; i++)
5167                         clocks->clock[i] = sclk_table->entries[i].clk * 10;
5168                 clocks->count = sclk_table->count;
5169         }
5170
5171         return 0;
5172 }
5173
5174 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
5175 {
5176         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5177
5178         if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
5179                 return data->mem_latency_high;
5180         else if (clk >= MEM_FREQ_HIGH_LATENCY)
5181                 return data->mem_latency_low;
5182         else
5183                 return MEM_LATENCY_ERR;
5184 }
5185
5186 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
5187 {
5188         struct phm_ppt_v1_information *table_info =
5189                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5190         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
5191         int i;
5192         struct phm_clock_voltage_dependency_table *mclk_table;
5193
5194         if (hwmgr->pp_table_version == PP_TABLE_V1) {
5195                 if (table_info == NULL)
5196                         return -EINVAL;
5197                 dep_mclk_table = table_info->vdd_dep_on_mclk;
5198                 for (i = 0; i < dep_mclk_table->count; i++) {
5199                         clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
5200                         clocks->latency[i] = smu7_get_mem_latency(hwmgr,
5201                                                 dep_mclk_table->entries[i].clk);
5202                 }
5203                 clocks->count = dep_mclk_table->count;
5204         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
5205                 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
5206                 for (i = 0; i < mclk_table->count; i++)
5207                         clocks->clock[i] = mclk_table->entries[i].clk * 10;
5208                 clocks->count = mclk_table->count;
5209         }
5210         return 0;
5211 }
5212
5213 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
5214                                                 struct amd_pp_clocks *clocks)
5215 {
5216         switch (type) {
5217         case amd_pp_sys_clock:
5218                 smu7_get_sclks(hwmgr, clocks);
5219                 break;
5220         case amd_pp_mem_clock:
5221                 smu7_get_mclks(hwmgr, clocks);
5222                 break;
5223         default:
5224                 return -EINVAL;
5225         }
5226
5227         return 0;
5228 }
5229
5230 static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr,
5231                                        struct pp_clock_levels_with_latency *clocks)
5232 {
5233         struct phm_ppt_v1_information *table_info =
5234                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5235         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
5236                         table_info->vdd_dep_on_sclk;
5237         int i;
5238
5239         clocks->num_levels = 0;
5240         for (i = 0; i < dep_sclk_table->count; i++) {
5241                 if (dep_sclk_table->entries[i].clk) {
5242                         clocks->data[clocks->num_levels].clocks_in_khz =
5243                                 dep_sclk_table->entries[i].clk * 10;
5244                         clocks->num_levels++;
5245                 }
5246         }
5247
5248         return 0;
5249 }
5250
5251 static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr,
5252                                        struct pp_clock_levels_with_latency *clocks)
5253 {
5254         struct phm_ppt_v1_information *table_info =
5255                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5256         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5257                         table_info->vdd_dep_on_mclk;
5258         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5259         int i;
5260
5261         clocks->num_levels = 0;
5262         data->mclk_latency_table.count = 0;
5263         for (i = 0; i < dep_mclk_table->count; i++) {
5264                 if (dep_mclk_table->entries[i].clk) {
5265                         clocks->data[clocks->num_levels].clocks_in_khz =
5266                                         dep_mclk_table->entries[i].clk * 10;
5267                         data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency =
5268                                         dep_mclk_table->entries[i].clk;
5269                         clocks->data[clocks->num_levels].latency_in_us =
5270                                 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency =
5271                                         smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk);
5272                         clocks->num_levels++;
5273                         data->mclk_latency_table.count++;
5274                 }
5275         }
5276
5277         return 0;
5278 }
5279
5280 static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
5281                                                enum amd_pp_clock_type type,
5282                                                struct pp_clock_levels_with_latency *clocks)
5283 {
5284         if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
5285               hwmgr->chip_id <= CHIP_VEGAM))
5286                 return -EINVAL;
5287
5288         switch (type) {
5289         case amd_pp_sys_clock:
5290                 smu7_get_sclks_with_latency(hwmgr, clocks);
5291                 break;
5292         case amd_pp_mem_clock:
5293                 smu7_get_mclks_with_latency(hwmgr, clocks);
5294                 break;
5295         default:
5296                 return -EINVAL;
5297         }
5298
5299         return 0;
5300 }
5301
5302 static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
5303                                                  void *clock_range)
5304 {
5305         struct phm_ppt_v1_information *table_info =
5306                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5307         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5308                         table_info->vdd_dep_on_mclk;
5309         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
5310                         table_info->vdd_dep_on_sclk;
5311         struct polaris10_smumgr *smu_data =
5312                         (struct polaris10_smumgr *)(hwmgr->smu_backend);
5313         SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
5314         struct dm_pp_wm_sets_with_clock_ranges *watermarks =
5315                         (struct dm_pp_wm_sets_with_clock_ranges *)clock_range;
5316         uint32_t i, j, k;
5317         bool valid_entry;
5318
5319         if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
5320               hwmgr->chip_id <= CHIP_VEGAM))
5321                 return -EINVAL;
5322
5323         for (i = 0; i < dep_mclk_table->count; i++) {
5324                 for (j = 0; j < dep_sclk_table->count; j++) {
5325                         valid_entry = false;
5326                         for (k = 0; k < watermarks->num_wm_sets; k++) {
5327                                 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 &&
5328                                     dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 &&
5329                                     dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 &&
5330                                     dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) {
5331                                         valid_entry = true;
5332                                         table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id;
5333                                         break;
5334                                 }
5335                         }
5336                         PP_ASSERT_WITH_CODE(valid_entry,
5337                                         "Clock is not in range of specified clock range for watermark from DAL!  Using highest water mark set.",
5338                                         table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id);
5339                 }
5340         }
5341
5342         return smu7_copy_bytes_to_smc(hwmgr,
5343                                       smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, DisplayWatermark),
5344                                       (uint8_t *)table->DisplayWatermark,
5345                                       sizeof(uint8_t) * SMU74_MAX_LEVELS_MEMORY * SMU74_MAX_LEVELS_GRAPHICS,
5346                                       SMC_RAM_END);
5347 }
5348
5349 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
5350                                         uint32_t virtual_addr_low,
5351                                         uint32_t virtual_addr_hi,
5352                                         uint32_t mc_addr_low,
5353                                         uint32_t mc_addr_hi,
5354                                         uint32_t size)
5355 {
5356         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5357
5358         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5359                                         data->soft_regs_start +
5360                                         smum_get_offsetof(hwmgr,
5361                                         SMU_SoftRegisters, DRAM_LOG_ADDR_H),
5362                                         mc_addr_hi);
5363
5364         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5365                                         data->soft_regs_start +
5366                                         smum_get_offsetof(hwmgr,
5367                                         SMU_SoftRegisters, DRAM_LOG_ADDR_L),
5368                                         mc_addr_low);
5369
5370         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5371                                         data->soft_regs_start +
5372                                         smum_get_offsetof(hwmgr,
5373                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
5374                                         virtual_addr_hi);
5375
5376         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5377                                         data->soft_regs_start +
5378                                         smum_get_offsetof(hwmgr,
5379                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
5380                                         virtual_addr_low);
5381
5382         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5383                                         data->soft_regs_start +
5384                                         smum_get_offsetof(hwmgr,
5385                                         SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
5386                                         size);
5387         return 0;
5388 }
5389
5390 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
5391                                         struct amd_pp_simple_clock_info *clocks)
5392 {
5393         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5394         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5395         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5396
5397         if (clocks == NULL)
5398                 return -EINVAL;
5399
5400         clocks->memory_max_clock = mclk_table->count > 1 ?
5401                                 mclk_table->dpm_levels[mclk_table->count-1].value :
5402                                 mclk_table->dpm_levels[0].value;
5403         clocks->engine_max_clock = sclk_table->count > 1 ?
5404                                 sclk_table->dpm_levels[sclk_table->count-1].value :
5405                                 sclk_table->dpm_levels[0].value;
5406         return 0;
5407 }
5408
5409 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
5410                 struct PP_TemperatureRange *thermal_data)
5411 {
5412         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5413         struct phm_ppt_v1_information *table_info =
5414                         (struct phm_ppt_v1_information *)hwmgr->pptable;
5415
5416         memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
5417
5418         if (hwmgr->pp_table_version == PP_TABLE_V1)
5419                 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp *
5420                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5421         else if (hwmgr->pp_table_version == PP_TABLE_V0)
5422                 thermal_data->max = data->thermal_temp_setting.temperature_shutdown *
5423                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5424
5425         thermal_data->sw_ctf_threshold = thermal_data->max;
5426
5427         return 0;
5428 }
5429
5430 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
5431                                         enum PP_OD_DPM_TABLE_COMMAND type,
5432                                         uint32_t clk,
5433                                         uint32_t voltage)
5434 {
5435         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5436
5437         if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) {
5438                 pr_info("OD voltage is out of range [%d - %d] mV\n",
5439                                                 data->odn_dpm_table.min_vddc,
5440                                                 data->odn_dpm_table.max_vddc);
5441                 return false;
5442         }
5443
5444         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5445                 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk ||
5446                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5447                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5448                                 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
5449                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5450                         return false;
5451                 }
5452         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5453                 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk ||
5454                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5455                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5456                                 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
5457                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5458                         return false;
5459                 }
5460         } else {
5461                 return false;
5462         }
5463
5464         return true;
5465 }
5466
5467 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5468                                         enum PP_OD_DPM_TABLE_COMMAND type,
5469                                         long *input, uint32_t size)
5470 {
5471         uint32_t i;
5472         struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
5473         struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
5474         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5475
5476         uint32_t input_clk;
5477         uint32_t input_vol;
5478         uint32_t input_level;
5479
5480         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5481                                 return -EINVAL);
5482
5483         if (!hwmgr->od_enabled) {
5484                 pr_info("OverDrive feature not enabled\n");
5485                 return -EINVAL;
5486         }
5487
5488         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5489                 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
5490                 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
5491                 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
5492                                 "Failed to get ODN SCLK and Voltage tables",
5493                                 return -EINVAL);
5494         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5495                 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
5496                 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
5497
5498                 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
5499                         "Failed to get ODN MCLK and Voltage tables",
5500                         return -EINVAL);
5501         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5502                 smu7_odn_initial_default_setting(hwmgr);
5503                 return 0;
5504         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
5505                 smu7_check_dpm_table_updated(hwmgr);
5506                 return 0;
5507         } else {
5508                 return -EINVAL;
5509         }
5510
5511         for (i = 0; i < size; i += 3) {
5512                 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
5513                         pr_info("invalid clock voltage input \n");
5514                         return 0;
5515                 }
5516                 input_level = input[i];
5517                 input_clk = input[i+1] * 100;
5518                 input_vol = input[i+2];
5519
5520                 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5521                         podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
5522                         podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
5523                         podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
5524                         podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
5525                         podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol;
5526                 } else {
5527                         return -EINVAL;
5528                 }
5529         }
5530
5531         return 0;
5532 }
5533
5534 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
5535 {
5536         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5537         uint32_t i, size = 0;
5538         uint32_t len;
5539
5540         static const char *title[8] = {"NUM",
5541                         "MODE_NAME",
5542                         "SCLK_UP_HYST",
5543                         "SCLK_DOWN_HYST",
5544                         "SCLK_ACTIVE_LEVEL",
5545                         "MCLK_UP_HYST",
5546                         "MCLK_DOWN_HYST",
5547                         "MCLK_ACTIVE_LEVEL"};
5548
5549         if (!buf)
5550                 return -EINVAL;
5551
5552         phm_get_sysfs_buf(&buf, &size);
5553
5554         size += sysfs_emit_at(buf, size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
5555                         title[0], title[1], title[2], title[3],
5556                         title[4], title[5], title[6], title[7]);
5557
5558         len = ARRAY_SIZE(smu7_profiling);
5559
5560         for (i = 0; i < len; i++) {
5561                 if (i == hwmgr->power_profile_mode) {
5562                         size += sysfs_emit_at(buf, size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
5563                         i, amdgpu_pp_profile_name[i], "*",
5564                         data->current_profile_setting.sclk_up_hyst,
5565                         data->current_profile_setting.sclk_down_hyst,
5566                         data->current_profile_setting.sclk_activity,
5567                         data->current_profile_setting.mclk_up_hyst,
5568                         data->current_profile_setting.mclk_down_hyst,
5569                         data->current_profile_setting.mclk_activity);
5570                         continue;
5571                 }
5572                 if (smu7_profiling[i].bupdate_sclk)
5573                         size += sysfs_emit_at(buf, size, "%3d %16s: %8d %16d %16d ",
5574                         i, amdgpu_pp_profile_name[i], smu7_profiling[i].sclk_up_hyst,
5575                         smu7_profiling[i].sclk_down_hyst,
5576                         smu7_profiling[i].sclk_activity);
5577                 else
5578                         size += sysfs_emit_at(buf, size, "%3d %16s: %8s %16s %16s ",
5579                         i, amdgpu_pp_profile_name[i], "-", "-", "-");
5580
5581                 if (smu7_profiling[i].bupdate_mclk)
5582                         size += sysfs_emit_at(buf, size, "%16d %16d %16d\n",
5583                         smu7_profiling[i].mclk_up_hyst,
5584                         smu7_profiling[i].mclk_down_hyst,
5585                         smu7_profiling[i].mclk_activity);
5586                 else
5587                         size += sysfs_emit_at(buf, size, "%16s %16s %16s\n",
5588                         "-", "-", "-");
5589         }
5590
5591         return size;
5592 }
5593
5594 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
5595                                         enum PP_SMC_POWER_PROFILE requst)
5596 {
5597         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5598         uint32_t tmp, level;
5599
5600         if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
5601                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
5602                         level = 0;
5603                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
5604                         while (tmp >>= 1)
5605                                 level++;
5606                         if (level > 0)
5607                                 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
5608                 }
5609         } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
5610                 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
5611         }
5612 }
5613
5614 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5615 {
5616         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5617         struct profile_mode_setting tmp;
5618         enum PP_SMC_POWER_PROFILE mode;
5619
5620         if (input == NULL)
5621                 return -EINVAL;
5622
5623         mode = input[size];
5624         switch (mode) {
5625         case PP_SMC_POWER_PROFILE_CUSTOM:
5626                 if (size < 8 && size != 0)
5627                         return -EINVAL;
5628                 /* If only CUSTOM is passed in, use the saved values. Check
5629                  * that we actually have a CUSTOM profile by ensuring that
5630                  * the "use sclk" or the "use mclk" bits are set
5631                  */
5632                 tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM];
5633                 if (size == 0) {
5634                         if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0)
5635                                 return -EINVAL;
5636                 } else {
5637                         tmp.bupdate_sclk = input[0];
5638                         tmp.sclk_up_hyst = input[1];
5639                         tmp.sclk_down_hyst = input[2];
5640                         tmp.sclk_activity = input[3];
5641                         tmp.bupdate_mclk = input[4];
5642                         tmp.mclk_up_hyst = input[5];
5643                         tmp.mclk_down_hyst = input[6];
5644                         tmp.mclk_activity = input[7];
5645                         smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp;
5646                 }
5647                 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5648                         memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
5649                         hwmgr->power_profile_mode = mode;
5650                 }
5651                 break;
5652         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
5653         case PP_SMC_POWER_PROFILE_POWERSAVING:
5654         case PP_SMC_POWER_PROFILE_VIDEO:
5655         case PP_SMC_POWER_PROFILE_VR:
5656         case PP_SMC_POWER_PROFILE_COMPUTE:
5657                 if (mode == hwmgr->power_profile_mode)
5658                         return 0;
5659
5660                 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
5661                 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5662                         if (tmp.bupdate_sclk) {
5663                                 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
5664                                 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
5665                                 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
5666                                 data->current_profile_setting.sclk_activity = tmp.sclk_activity;
5667                         }
5668                         if (tmp.bupdate_mclk) {
5669                                 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
5670                                 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
5671                                 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
5672                                 data->current_profile_setting.mclk_activity = tmp.mclk_activity;
5673                         }
5674                         smu7_patch_compute_profile_mode(hwmgr, mode);
5675                         hwmgr->power_profile_mode = mode;
5676                 }
5677                 break;
5678         default:
5679                 return -EINVAL;
5680         }
5681
5682         return 0;
5683 }
5684
5685 static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5686                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
5687                                 PHM_PerformanceLevel *level)
5688 {
5689         const struct smu7_power_state *ps;
5690         uint32_t i;
5691
5692         if (level == NULL || hwmgr == NULL || state == NULL)
5693                 return -EINVAL;
5694
5695         ps = cast_const_phw_smu7_power_state(state);
5696
5697         i = index > ps->performance_level_count - 1 ?
5698                         ps->performance_level_count - 1 : index;
5699
5700         level->coreClock = ps->performance_levels[i].engine_clock;
5701         level->memory_clock = ps->performance_levels[i].memory_clock;
5702
5703         return 0;
5704 }
5705
5706 static int smu7_power_off_asic(struct pp_hwmgr *hwmgr)
5707 {
5708         int result;
5709
5710         result = smu7_disable_dpm_tasks(hwmgr);
5711         PP_ASSERT_WITH_CODE((0 == result),
5712                         "[disable_dpm_tasks] Failed to disable DPM!",
5713                         );
5714
5715         return result;
5716 }
5717
5718 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
5719         .backend_init = &smu7_hwmgr_backend_init,
5720         .backend_fini = &smu7_hwmgr_backend_fini,
5721         .asic_setup = &smu7_setup_asic_task,
5722         .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
5723         .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
5724         .force_dpm_level = &smu7_force_dpm_level,
5725         .power_state_set = smu7_set_power_state_tasks,
5726         .get_power_state_size = smu7_get_power_state_size,
5727         .get_mclk = smu7_dpm_get_mclk,
5728         .get_sclk = smu7_dpm_get_sclk,
5729         .patch_boot_state = smu7_dpm_patch_boot_state,
5730         .get_pp_table_entry = smu7_get_pp_table_entry,
5731         .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
5732         .powerdown_uvd = smu7_powerdown_uvd,
5733         .powergate_uvd = smu7_powergate_uvd,
5734         .powergate_vce = smu7_powergate_vce,
5735         .disable_clock_power_gating = smu7_disable_clock_power_gating,
5736         .update_clock_gatings = smu7_update_clock_gatings,
5737         .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
5738         .display_config_changed = smu7_display_configuration_changed_task,
5739         .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
5740         .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
5741         .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
5742         .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
5743         .get_fan_speed_pwm = smu7_fan_ctrl_get_fan_speed_pwm,
5744         .set_fan_speed_pwm = smu7_fan_ctrl_set_fan_speed_pwm,
5745         .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
5746         .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
5747         .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
5748         .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
5749         .register_irq_handlers = smu7_register_irq_handlers,
5750         .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
5751         .check_states_equal = smu7_check_states_equal,
5752         .set_fan_control_mode = smu7_set_fan_control_mode,
5753         .get_fan_control_mode = smu7_get_fan_control_mode,
5754         .force_clock_level = smu7_force_clock_level,
5755         .print_clock_levels = smu7_print_clock_levels,
5756         .powergate_gfx = smu7_powergate_gfx,
5757         .get_sclk_od = smu7_get_sclk_od,
5758         .set_sclk_od = smu7_set_sclk_od,
5759         .get_mclk_od = smu7_get_mclk_od,
5760         .set_mclk_od = smu7_set_mclk_od,
5761         .get_clock_by_type = smu7_get_clock_by_type,
5762         .get_clock_by_type_with_latency = smu7_get_clock_by_type_with_latency,
5763         .set_watermarks_for_clocks_ranges = smu7_set_watermarks_for_clocks_ranges,
5764         .read_sensor = smu7_read_sensor,
5765         .dynamic_state_management_disable = smu7_disable_dpm_tasks,
5766         .avfs_control = smu7_avfs_control,
5767         .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
5768         .start_thermal_controller = smu7_start_thermal_controller,
5769         .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
5770         .get_max_high_clocks = smu7_get_max_high_clocks,
5771         .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
5772         .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
5773         .set_power_limit = smu7_set_power_limit,
5774         .get_power_profile_mode = smu7_get_power_profile_mode,
5775         .set_power_profile_mode = smu7_set_power_profile_mode,
5776         .get_performance_level = smu7_get_performance_level,
5777         .get_asic_baco_capability = smu7_baco_get_capability,
5778         .get_asic_baco_state = smu7_baco_get_state,
5779         .set_asic_baco_state = smu7_baco_set_state,
5780         .power_off_asic = smu7_power_off_asic,
5781 };
5782
5783 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
5784                 uint32_t clock_insr)
5785 {
5786         uint8_t i;
5787         uint32_t temp;
5788         uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
5789
5790         PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
5791         for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
5792                 temp = clock >> i;
5793
5794                 if (temp >= min || i == 0)
5795                         break;
5796         }
5797         return i;
5798 }
5799
5800 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
5801 {
5802         hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
5803         if (hwmgr->pp_table_version == PP_TABLE_V0)
5804                 hwmgr->pptable_func = &pptable_funcs;
5805         else if (hwmgr->pp_table_version == PP_TABLE_V1)
5806                 hwmgr->pptable_func = &pptable_v1_0_funcs;
5807
5808         return 0;
5809 }