2 * Copyright 2022 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __MES_API_DEF_H__
25 #define __MES_API_DEF_H__
29 #define MES_API_VERSION 1
31 /* Driver submits one API(cmd) as a single Frame and this command size is same
32 * for all API to ease the debugging and parsing of ring buffer.
34 enum { API_FRAME_SIZE_IN_DWORDS = 64 };
36 /* To avoid command in scheduler context to be overwritten whenenver mutilple
37 * interrupts come in, this creates another queue.
39 enum { API_NUMBER_OF_COMMAND_MAX = 32 };
42 MES_API_TYPE_SCHEDULER = 1,
46 enum MES_SCH_API_OPCODE {
47 MES_SCH_API_SET_HW_RSRC = 0,
48 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
49 MES_SCH_API_ADD_QUEUE = 2,
50 MES_SCH_API_REMOVE_QUEUE = 3,
51 MES_SCH_API_PERFORM_YIELD = 4,
52 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
53 MES_SCH_API_SUSPEND = 6,
54 MES_SCH_API_RESUME = 7,
55 MES_SCH_API_RESET = 8,
56 MES_SCH_API_SET_LOG_BUFFER = 9,
57 MES_SCH_API_CHANGE_GANG_PRORITY = 10,
58 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
59 MES_SCH_API_PROGRAM_GDS = 12,
60 MES_SCH_API_SET_DEBUG_VMID = 13,
61 MES_SCH_API_MISC = 14,
62 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
63 MES_SCH_API_AMD_LOG = 16,
64 MES_SCH_API_MAX = 0xFF
67 union MES_API_HEADER {
69 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
71 uint32_t dwsize : 8; /* including header */
72 uint32_t reserved : 12;
78 enum MES_AMD_PRIORITY_LEVEL {
79 AMD_PRIORITY_LEVEL_LOW = 0,
80 AMD_PRIORITY_LEVEL_NORMAL = 1,
81 AMD_PRIORITY_LEVEL_MEDIUM = 2,
82 AMD_PRIORITY_LEVEL_HIGH = 3,
83 AMD_PRIORITY_LEVEL_REALTIME = 4,
84 AMD_PRIORITY_NUM_LEVELS
89 MES_QUEUE_TYPE_COMPUTE,
94 struct MES_API_STATUS {
95 uint64_t api_completion_fence_addr;
96 uint64_t api_completion_fence_value;
99 enum { MAX_COMPUTE_PIPES = 8 };
100 enum { MAX_GFX_PIPES = 2 };
101 enum { MAX_SDMA_PIPES = 2 };
103 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
104 enum { MAX_GFX_HQD_PER_PIPE = 8 };
105 enum { MAX_SDMA_HQD_PER_PIPE = 10 };
106 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 };
108 enum { MAX_QUEUES_IN_A_GANG = 8 };
116 enum { VMID_INVALID = 0xffff };
118 enum { MAX_VMID_GCHUB = 16 };
119 enum { MAX_VMID_MMHUB = 16 };
121 enum SET_DEBUG_VMID_OPERATIONS {
122 DEBUG_VMID_OP_PROGRAM = 0,
123 DEBUG_VMID_OP_ALLOCATE = 1,
124 DEBUG_VMID_OP_RELEASE = 2
127 enum MES_LOG_OPERATION {
128 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
129 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
130 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
131 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
132 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
133 MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
136 enum MES_LOG_CONTEXT_STATE {
137 MES_LOG_CONTEXT_STATE_IDLE = 0,
138 MES_LOG_CONTEXT_STATE_RUNNING = 1,
139 MES_LOG_CONTEXT_STATE_READY = 2,
140 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
141 MES_LOG_CONTEXT_STATE_INVALID = 0xF,
144 struct MES_LOG_CONTEXT_STATE_CHANGE {
146 enum MES_LOG_CONTEXT_STATE new_context_state;
149 struct MES_LOG_QUEUE_NEW_WORK {
154 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
156 uint64_t h_sync_object;
159 struct MES_LOG_QUEUE_NO_MORE_WORK {
164 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
166 uint64_t h_sync_object;
169 struct MES_LOG_ENTRY_HEADER {
170 uint32_t first_free_entry_index;
171 uint32_t wraparound_count;
172 uint64_t number_of_entries;
173 uint64_t reserved[2];
176 struct MES_LOG_ENTRY_DATA {
177 uint64_t gpu_time_stamp;
178 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
179 uint32_t reserved_operation_type_bits;
181 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
182 struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
183 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
184 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
185 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
190 struct MES_LOG_BUFFER {
191 struct MES_LOG_ENTRY_HEADER header;
192 struct MES_LOG_ENTRY_DATA entries[1];
195 enum MES_SWIP_TO_HWIP_DEF {
196 MES_MAX_HWIP_SEGMENT = 8,
199 union MESAPI_SET_HW_RESOURCES {
201 union MES_API_HEADER header;
202 uint32_t vmid_mask_mmhub;
203 uint32_t vmid_mask_gfxhub;
205 uint32_t paging_vmid;
206 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
207 uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
208 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
209 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
210 uint64_t g_sch_ctx_gpu_mc_ptr;
211 uint64_t query_status_fence_gpu_mc_ptr;
212 uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
213 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
214 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
215 struct MES_API_STATUS api_status;
218 uint32_t disable_reset : 1;
219 uint32_t use_different_vmid_compute : 1;
220 uint32_t disable_mes_log : 1;
221 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
222 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
223 uint32_t second_gfx_pipe_enabled : 1;
224 uint32_t enable_level_process_quantum_check : 1;
225 uint32_t reserved : 25;
227 uint32_t uint32_t_all;
229 uint32_t oversubscription_timer;
230 uint64_t doorbell_info;
233 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
236 union MESAPI__ADD_QUEUE {
238 union MES_API_HEADER header;
240 uint64_t page_table_base_addr;
241 uint64_t process_va_start;
242 uint64_t process_va_end;
243 uint64_t process_quantum;
244 uint64_t process_context_addr;
245 uint64_t gang_quantum;
246 uint64_t gang_context_addr;
247 uint32_t inprocess_gang_priority;
248 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
249 uint32_t doorbell_offset;
254 enum MES_QUEUE_TYPE queue_type;
260 uint64_t trap_handler_addr;
261 uint32_t vm_context_cntl;
265 uint32_t debug_vmid : 4;
266 uint32_t program_gds : 1;
267 uint32_t is_gang_suspended : 1;
268 uint32_t is_tmz_queue : 1;
269 uint32_t map_kiq_utility_queue : 1;
270 uint32_t is_kfd_process : 1;
271 uint32_t reserved : 22;
273 struct MES_API_STATUS api_status;
277 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
280 union MESAPI__REMOVE_QUEUE {
282 union MES_API_HEADER header;
283 uint32_t doorbell_offset;
284 uint64_t gang_context_addr;
287 uint32_t unmap_legacy_gfx_queue : 1;
288 uint32_t unmap_kiq_utility_queue : 1;
289 uint32_t preempt_legacy_gfx_queue : 1;
290 uint32_t unmap_legacy_queue : 1;
291 uint32_t reserved : 28;
293 struct MES_API_STATUS api_status;
301 enum MES_QUEUE_TYPE queue_type;
304 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
307 union MESAPI__SET_SCHEDULING_CONFIG {
309 union MES_API_HEADER header;
310 /* Grace period when preempting another priority band for this
311 * priority band. The value for idle priority band is ignored,
312 * as it never preempts other bands.
314 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
315 /* Default quantum for scheduling across processes within
318 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
319 /* Default grace period for processes that preempt each other
320 * within a priority band.
322 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
323 /* For normal level this field specifies the target GPU
324 * percentage in situations when it's starved by the high level.
325 * Valid values are between 0 and 50, with the default being 10.
327 uint32_t normal_yield_percent;
328 struct MES_API_STATUS api_status;
331 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
334 union MESAPI__PERFORM_YIELD {
336 union MES_API_HEADER header;
338 struct MES_API_STATUS api_status;
341 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
344 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
346 union MES_API_HEADER header;
347 uint32_t inprocess_gang_priority;
348 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
349 uint64_t gang_quantum;
350 uint64_t gang_context_addr;
351 struct MES_API_STATUS api_status;
354 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
357 union MESAPI__SUSPEND {
359 union MES_API_HEADER header;
360 /* false - suspend all gangs; true - specific gang */
362 uint32_t suspend_all_gangs : 1;
363 uint32_t reserved : 31;
365 /* gang_context_addr is valid only if suspend_all = false */
366 uint64_t gang_context_addr;
368 uint64_t suspend_fence_addr;
369 uint32_t suspend_fence_value;
371 struct MES_API_STATUS api_status;
374 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
377 union MESAPI__RESUME {
379 union MES_API_HEADER header;
380 /* false - resume all gangs; true - specified gang */
382 uint32_t resume_all_gangs : 1;
383 uint32_t reserved : 31;
385 /* valid only if resume_all_gangs = false */
386 uint64_t gang_context_addr;
388 struct MES_API_STATUS api_status;
391 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
394 union MESAPI__RESET {
396 union MES_API_HEADER header;
399 /* Only reset the queue given by doorbell_offset (not entire gang) */
400 uint32_t reset_queue_only : 1;
401 /* Hang detection first then reset any queues that are hung */
402 uint32_t hang_detect_then_reset : 1;
403 /* Only do hang detection (no reset) */
404 uint32_t hang_detect_only : 1;
405 /* Rest HP and LP kernel queues not managed by MES */
406 uint32_t reset_legacy_gfx : 1;
407 uint32_t reserved : 28;
410 uint64_t gang_context_addr;
412 /* valid only if reset_queue_only = true */
413 uint32_t doorbell_offset;
415 /* valid only if hang_detect_then_reset = true */
416 uint64_t doorbell_offset_addr;
417 enum MES_QUEUE_TYPE queue_type;
419 /* valid only if reset_legacy_gfx = true */
421 uint32_t queue_id_lp;
423 uint64_t mqd_mc_addr_lp;
424 uint32_t doorbell_offset_lp;
425 uint64_t wptr_addr_lp;
428 uint32_t queue_id_hp;
430 uint64_t mqd_mc_addr_hp;
431 uint32_t doorbell_offset_hp;
432 uint64_t wptr_addr_hp;
434 struct MES_API_STATUS api_status;
437 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
440 union MESAPI__SET_LOGGING_BUFFER {
442 union MES_API_HEADER header;
443 /* There are separate log buffers for each queue type */
444 enum MES_QUEUE_TYPE log_type;
445 /* Log buffer GPU Address */
446 uint64_t logging_buffer_addr;
447 /* number of entries in the log buffer */
448 uint32_t number_of_entries;
449 /* Entry index at which CPU interrupt needs to be signalled */
450 uint32_t interrupt_entry;
452 struct MES_API_STATUS api_status;
455 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
458 union MESAPI__QUERY_MES_STATUS {
460 union MES_API_HEADER header;
461 bool mes_healthy; /* 0 - not healthy, 1 - healthy */
462 struct MES_API_STATUS api_status;
465 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
468 union MESAPI__PROGRAM_GDS {
470 union MES_API_HEADER header;
471 uint64_t process_context_addr;
477 struct MES_API_STATUS api_status;
480 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
483 union MESAPI__SET_DEBUG_VMID {
485 union MES_API_HEADER header;
486 struct MES_API_STATUS api_status;
489 uint32_t use_gds : 1;
490 uint32_t operation : 2;
491 uint32_t reserved : 29;
497 uint64_t process_context_addr;
498 uint64_t page_table_base_addr;
499 uint64_t process_va_start;
500 uint64_t process_va_end;
507 /* output addr of the acquired vmid value */
508 uint64_t output_addr;
511 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
514 enum MESAPI_MISC_OPCODE {
515 MESAPI_MISC__WRITE_REG,
516 MESAPI_MISC__INV_GART,
517 MESAPI_MISC__QUERY_STATUS,
518 MESAPI_MISC__READ_REG,
519 MESAPI_MISC__WAIT_REG_MEM,
523 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
532 uint64_t buffer_addr;
536 WRM_OPERATION__WAIT_REG_MEM,
537 WRM_OPERATION__WR_WAIT_WR_REG,
541 struct WAIT_REG_MEM {
542 enum WRM_OPERATION op;
545 uint32_t reg_offset1;
546 uint32_t reg_offset2;
550 uint64_t inv_range_va_start;
551 uint64_t inv_range_size;
554 struct QUERY_STATUS {
560 union MES_API_HEADER header;
561 enum MESAPI_MISC_OPCODE opcode;
562 struct MES_API_STATUS api_status;
565 struct WRITE_REG write_reg;
566 struct INV_GART inv_gart;
567 struct QUERY_STATUS query_status;
568 struct READ_REG read_reg;
569 struct WAIT_REG_MEM wait_reg_mem;
570 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
574 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
577 union MESAPI__UPDATE_ROOT_PAGE_TABLE {
579 union MES_API_HEADER header;
580 uint64_t page_table_base_addr;
581 uint64_t process_context_addr;
582 struct MES_API_STATUS api_status;
585 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
588 union MESAPI_AMD_LOG {
590 union MES_API_HEADER header;
591 uint64_t p_buffer_memory;
592 uint64_t p_buffer_size_used;
593 struct MES_API_STATUS api_status;
596 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];