drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "../dmub_srv.h"
  27 #include "dmub_dcn20.h"
  28 #include "dmub_dcn21.h"
  29 #include "dmub_cmd.h"
  30 #include "dmub_dcn30.h"
  31 #include "dmub_dcn301.h"
  32 #include "dmub_dcn302.h"
  33 #include "dmub_dcn303.h"
  34 #include "dmub_dcn31.h"
  35 #include "dmub_dcn314.h"
  36 #include "dmub_dcn315.h"
  37 #include "dmub_dcn316.h"
  38 #include "dmub_dcn32.h"
  39 #include "os_types.h"
  40 /*
  41  * Note: the DMUB service is standalone. No additional headers should be
  42  * added below or above this line unless they reside within the DMUB
  43  * folder.
  44  */
  45
  46 /* Alignment for framebuffer memory. */
  47 #define DMUB_FB_ALIGNMENT (1024 * 1024)
  48
  49 /* Stack size. */
  50 #define DMUB_STACK_SIZE (128 * 1024)
  51
  52 /* Context size. */
  53 #define DMUB_CONTEXT_SIZE (512 * 1024)
  54
  55 /* Mailbox size : Ring buffers are required for both inbox and outbox */
  56 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
  57
  58 /* Default state size if meta is absent. */
  59 #define DMUB_FW_STATE_SIZE (64 * 1024)
  60
  61 /* Default tracebuffer size if meta is absent. */
  62 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
  63
  64
  65 /* Default scratch mem size. */
  66 #define DMUB_SCRATCH_MEM_SIZE (256)
  67
  68 /* Number of windows in use. */
  69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)
  70 /* Base addresses. */
  71
  72 #define DMUB_CW0_BASE (0x60000000)
  73 #define DMUB_CW1_BASE (0x61000000)
  74 #define DMUB_CW3_BASE (0x63000000)
  75 #define DMUB_CW4_BASE (0x64000000)
  76 #define DMUB_CW5_BASE (0x65000000)
  77 #define DMUB_CW6_BASE (0x66000000)
  78
  79 #define DMUB_REGION5_BASE (0xA0000000)
  80
  81 static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
  82 {
  83         return (val + factor - 1) / factor * factor;
  84 }
  85
  86 void dmub_flush_buffer_mem(const struct dmub_fb *fb)
  87 {
  88         const uint8_t *base = (const uint8_t *)fb->cpu_addr;
  89         uint8_t buf[64];
  90         uint32_t pos, end;
  91
  92         /**
  93          * Read 64-byte chunks since we don't want to store a
  94          * large temporary buffer for this purpose.
  95          */
  96         end = fb->size / sizeof(buf) * sizeof(buf);
  97
  98         for (pos = 0; pos < end; pos += sizeof(buf))
  99                 dmub_memcpy(buf, base + pos, sizeof(buf));
 100
 101         /* Read anything leftover into the buffer. */
 102         if (end < fb->size)
 103                 dmub_memcpy(buf, base + pos, fb->size - end);
 104 }
 105
 106 static const struct dmub_fw_meta_info *
 107 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)
 108 {
 109         const union dmub_fw_meta *meta;
 110
 111         if (!blob || !blob_size)
 112                 return NULL;
 113
 114         if (blob_size < sizeof(union dmub_fw_meta) + meta_offset)
 115                 return NULL;
 116
 117         meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset -
 118                                             sizeof(union dmub_fw_meta));
 119
 120         if (meta->info.magic_value != DMUB_FW_META_MAGIC)
 121                 return NULL;
 122
 123         return &meta->info;
 124 }
 125
 126 static const struct dmub_fw_meta_info *
 127 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params)
 128 {
 129         const struct dmub_fw_meta_info *info = NULL;
 130
 131         if (params->fw_bss_data && params->bss_data_size) {
 132                 /* Legacy metadata region. */
 133                 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data,
 134                                                        params->bss_data_size,
 135                                                        DMUB_FW_META_OFFSET);
 136         } else if (params->fw_inst_const && params->inst_const_size) {
 137                 /* Combined metadata region - can be aligned to 16-bytes. */
 138                 uint32_t i;
 139
 140                 for (i = 0; i < 16; ++i) {
 141                         info = dmub_get_fw_meta_info_from_blob(
 142                                 params->fw_inst_const, params->inst_const_size, i);
 143
 144                         if (info)
 145                                 break;
 146                 }
 147         }
 148
 149         return info;
 150 }
 151
 152 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 153 {
 154         struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
 155
 156         switch (asic) {
 157         case DMUB_ASIC_DCN20:
 158         case DMUB_ASIC_DCN21:
 159         case DMUB_ASIC_DCN30:
 160         case DMUB_ASIC_DCN301:
 161         case DMUB_ASIC_DCN302:
 162         case DMUB_ASIC_DCN303:
 163                 dmub->regs = &dmub_srv_dcn20_regs;
 164
 165                 funcs->reset = dmub_dcn20_reset;
 166                 funcs->reset_release = dmub_dcn20_reset_release;
 167                 funcs->backdoor_load = dmub_dcn20_backdoor_load;
 168                 funcs->setup_windows = dmub_dcn20_setup_windows;
 169                 funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
 170                 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
 171                 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
 172                 funcs->is_supported = dmub_dcn20_is_supported;
 173                 funcs->is_hw_init = dmub_dcn20_is_hw_init;
 174                 funcs->set_gpint = dmub_dcn20_set_gpint;
 175                 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
 176                 funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
 177                 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
 178                 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
 179                 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
 180                 funcs->get_current_time = dmub_dcn20_get_current_time;
 181
 182                 // Out mailbox register access functions for RN and above
 183                 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
 184                 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
 185                 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
 186
 187                 //outbox0 call stacks
 188                 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;
 189                 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
 190                 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
 191
 192                 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
 193
 194                 if (asic == DMUB_ASIC_DCN21) {
 195                         dmub->regs = &dmub_srv_dcn21_regs;
 196
 197                         funcs->is_phy_init = dmub_dcn21_is_phy_init;
 198                 }
 199                 if (asic == DMUB_ASIC_DCN30) {
 200                         dmub->regs = &dmub_srv_dcn30_regs;
 201
 202                         funcs->backdoor_load = dmub_dcn30_backdoor_load;
 203                         funcs->setup_windows = dmub_dcn30_setup_windows;
 204                 }
 205                 if (asic == DMUB_ASIC_DCN301) {
 206                         dmub->regs = &dmub_srv_dcn301_regs;
 207
 208                         funcs->backdoor_load = dmub_dcn30_backdoor_load;
 209                         funcs->setup_windows = dmub_dcn30_setup_windows;
 210                 }
 211                 if (asic == DMUB_ASIC_DCN302) {
 212                         dmub->regs = &dmub_srv_dcn302_regs;
 213
 214                         funcs->backdoor_load = dmub_dcn30_backdoor_load;
 215                         funcs->setup_windows = dmub_dcn30_setup_windows;
 216                 }
 217                 if (asic == DMUB_ASIC_DCN303) {
 218                         dmub->regs = &dmub_srv_dcn303_regs;
 219
 220                         funcs->backdoor_load = dmub_dcn30_backdoor_load;
 221                         funcs->setup_windows = dmub_dcn30_setup_windows;
 222                 }
 223                 break;
 224
 225         case DMUB_ASIC_DCN31:
 226         case DMUB_ASIC_DCN31B:
 227         case DMUB_ASIC_DCN314:
 228         case DMUB_ASIC_DCN315:
 229         case DMUB_ASIC_DCN316:
 230                 if (asic == DMUB_ASIC_DCN314) {
 231                         dmub->regs_dcn31 = &dmub_srv_dcn314_regs;
 232                 } else if (asic == DMUB_ASIC_DCN315) {
 233                         dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
 234                 } else if (asic == DMUB_ASIC_DCN316) {
 235                         dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
 236                 } else {
 237                         dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
 238                         funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported;
 239                 }
 240                 funcs->reset = dmub_dcn31_reset;
 241                 funcs->reset_release = dmub_dcn31_reset_release;
 242                 funcs->backdoor_load = dmub_dcn31_backdoor_load;
 243                 funcs->setup_windows = dmub_dcn31_setup_windows;
 244                 funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
 245                 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
 246                 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
 247                 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
 248                 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
 249                 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
 250                 funcs->is_supported = dmub_dcn31_is_supported;
 251                 funcs->is_hw_init = dmub_dcn31_is_hw_init;
 252                 funcs->set_gpint = dmub_dcn31_set_gpint;
 253                 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
 254                 funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
 255                 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
 256                 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
 257                 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
 258                 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
 259                 //outbox0 call stacks
 260                 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
 261                 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
 262                 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
 263
 264                 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
 265                 funcs->should_detect = dmub_dcn31_should_detect;
 266                 funcs->get_current_time = dmub_dcn31_get_current_time;
 267
 268                 break;
 269
 270         case DMUB_ASIC_DCN32:
 271         case DMUB_ASIC_DCN321:
 272                 dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
 273                 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
 274                 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
 275                 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
 276                 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
 277                 funcs->reset = dmub_dcn32_reset;
 278                 funcs->reset_release = dmub_dcn32_reset_release;
 279                 funcs->backdoor_load = dmub_dcn32_backdoor_load;
 280                 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
 281                 funcs->setup_windows = dmub_dcn32_setup_windows;
 282                 funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
 283                 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
 284                 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
 285                 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
 286                 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
 287                 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
 288                 funcs->is_supported = dmub_dcn32_is_supported;
 289                 funcs->is_hw_init = dmub_dcn32_is_hw_init;
 290                 funcs->set_gpint = dmub_dcn32_set_gpint;
 291                 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
 292                 funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
 293                 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
 294                 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
 295                 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
 296                 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
 297
 298                 /* outbox0 call stacks */
 299                 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
 300                 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
 301                 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
 302                 funcs->get_current_time = dmub_dcn32_get_current_time;
 303                 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
 304
 305                 break;
 306
 307         default:
 308                 return false;
 309         }
 310
 311         return true;
 312 }
 313
 314 enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
 315                                  const struct dmub_srv_create_params *params)
 316 {
 317         enum dmub_status status = DMUB_STATUS_OK;
 318
 319         dmub_memset(dmub, 0, sizeof(*dmub));
 320
 321         dmub->funcs = params->funcs;
 322         dmub->user_ctx = params->user_ctx;
 323         dmub->asic = params->asic;
 324         dmub->fw_version = params->fw_version;
 325         dmub->is_virtual = params->is_virtual;
 326
 327         /* Setup asic dependent hardware funcs. */
 328         if (!dmub_srv_hw_setup(dmub, params->asic)) {
 329                 status = DMUB_STATUS_INVALID;
 330                 goto cleanup;
 331         }
 332
 333         /* Override (some) hardware funcs based on user params. */
 334         if (params->hw_funcs) {
 335                 if (params->hw_funcs->emul_get_inbox1_rptr)
 336                         dmub->hw_funcs.emul_get_inbox1_rptr =
 337                                 params->hw_funcs->emul_get_inbox1_rptr;
 338
 339                 if (params->hw_funcs->emul_set_inbox1_wptr)
 340                         dmub->hw_funcs.emul_set_inbox1_wptr =
 341                                 params->hw_funcs->emul_set_inbox1_wptr;
 342
 343                 if (params->hw_funcs->is_supported)
 344                         dmub->hw_funcs.is_supported =
 345                                 params->hw_funcs->is_supported;
 346         }
 347
 348         /* Sanity checks for required hw func pointers. */
 349         if (!dmub->hw_funcs.get_inbox1_rptr ||
 350             !dmub->hw_funcs.set_inbox1_wptr) {
 351                 status = DMUB_STATUS_INVALID;
 352                 goto cleanup;
 353         }
 354
 355 cleanup:
 356         if (status == DMUB_STATUS_OK)
 357                 dmub->sw_init = true;
 358         else
 359                 dmub_srv_destroy(dmub);
 360
 361         return status;
 362 }
 363
 364 void dmub_srv_destroy(struct dmub_srv *dmub)
 365 {
 366         dmub_memset(dmub, 0, sizeof(*dmub));
 367 }
 368
 369 enum dmub_status
 370 dmub_srv_calc_region_info(struct dmub_srv *dmub,
 371                           const struct dmub_srv_region_params *params,
 372                           struct dmub_srv_region_info *out)
 373 {
 374         struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
 375         struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
 376         struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
 377         struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
 378         struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
 379         struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
 380         struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
 381         struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM];
 382         const struct dmub_fw_meta_info *fw_info;
 383         uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
 384         uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
 385         uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE;
 386
 387         if (!dmub->sw_init)
 388                 return DMUB_STATUS_INVALID;
 389
 390         memset(out, 0, sizeof(*out));
 391
 392         out->num_regions = DMUB_NUM_WINDOWS;
 393
 394         inst->base = 0x0;
 395         inst->top = inst->base + params->inst_const_size;
 396
 397         data->base = dmub_align(inst->top, 256);
 398         data->top = data->base + params->bss_data_size;
 399
 400         /*
 401          * All cache windows below should be aligned to the size
 402          * of the DMCUB cache line, 64 bytes.
 403          */
 404
 405         stack->base = dmub_align(data->top, 256);
 406         stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
 407
 408         bios->base = dmub_align(stack->top, 256);
 409         bios->top = bios->base + params->vbios_size;
 410
 411         mail->base = dmub_align(bios->top, 256);
 412         mail->top = mail->base + DMUB_MAILBOX_SIZE;
 413
 414         fw_info = dmub_get_fw_meta_info(params);
 415
 416         if (fw_info) {
 417                 fw_state_size = fw_info->fw_region_size;
 418                 trace_buffer_size = fw_info->trace_buffer_size;
 419
 420                 /**
 421                  * If DM didn't fill in a version, then fill it in based on
 422                  * the firmware meta now that we have it.
 423                  *
 424                  * TODO: Make it easier for driver to extract this out to
 425                  * pass during creation.
 426                  */
 427                 if (dmub->fw_version == 0)
 428                         dmub->fw_version = fw_info->fw_version;
 429         }
 430
 431         trace_buff->base = dmub_align(mail->top, 256);
 432         trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
 433
 434         fw_state->base = dmub_align(trace_buff->top, 256);
 435         fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
 436
 437         scratch_mem->base = dmub_align(fw_state->top, 256);
 438         scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64);
 439
 440         out->fb_size = dmub_align(scratch_mem->top, 4096);
 441
 442         return DMUB_STATUS_OK;
 443 }
 444
 445 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
 446                                        const struct dmub_srv_fb_params *params,
 447                                        struct dmub_srv_fb_info *out)
 448 {
 449         uint8_t *cpu_base;
 450         uint64_t gpu_base;
 451         uint32_t i;
 452
 453         if (!dmub->sw_init)
 454                 return DMUB_STATUS_INVALID;
 455
 456         memset(out, 0, sizeof(*out));
 457
 458         if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
 459                 return DMUB_STATUS_INVALID;
 460
 461         cpu_base = (uint8_t *)params->cpu_addr;
 462         gpu_base = params->gpu_addr;
 463
 464         for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
 465                 const struct dmub_region *reg =
 466                         &params->region_info->regions[i];
 467
 468                 out->fb[i].cpu_addr = cpu_base + reg->base;
 469                 out->fb[i].gpu_addr = gpu_base + reg->base;
 470                 out->fb[i].size = reg->top - reg->base;
 471         }
 472
 473         out->num_fb = DMUB_NUM_WINDOWS;
 474
 475         return DMUB_STATUS_OK;
 476 }
 477
 478 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
 479                                          bool *is_supported)
 480 {
 481         *is_supported = false;
 482
 483         if (!dmub->sw_init)
 484                 return DMUB_STATUS_INVALID;
 485
 486         if (dmub->hw_funcs.is_supported)
 487                 *is_supported = dmub->hw_funcs.is_supported(dmub);
 488
 489         return DMUB_STATUS_OK;
 490 }
 491
 492 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
 493 {
 494         *is_hw_init = false;
 495
 496         if (!dmub->sw_init)
 497                 return DMUB_STATUS_INVALID;
 498
 499         if (!dmub->hw_init)
 500                 return DMUB_STATUS_OK;
 501
 502         if (dmub->hw_funcs.is_hw_init)
 503                 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
 504
 505         return DMUB_STATUS_OK;
 506 }
 507
 508 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 509                                   const struct dmub_srv_hw_params *params)
 510 {
 511         struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
 512         struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
 513         struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
 514         struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
 515         struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
 516         struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
 517         struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
 518         struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
 519
 520         struct dmub_rb_init_params rb_params, outbox0_rb_params;
 521         struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
 522         struct dmub_region inbox1, outbox1, outbox0;
 523
 524         if (!dmub->sw_init)
 525                 return DMUB_STATUS_INVALID;
 526
 527         if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
 528                 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
 529                 ASSERT(0);
 530                 return DMUB_STATUS_INVALID;
 531         }
 532
 533         dmub->fb_base = params->fb_base;
 534         dmub->fb_offset = params->fb_offset;
 535         dmub->psp_version = params->psp_version;
 536
 537         if (dmub->hw_funcs.reset)
 538                 dmub->hw_funcs.reset(dmub);
 539
 540         /* reset the cache of the last wptr as well now that hw is reset */
 541         dmub->inbox1_last_wptr = 0;
 542
 543         cw0.offset.quad_part = inst_fb->gpu_addr;
 544         cw0.region.base = DMUB_CW0_BASE;
 545         cw0.region.top = cw0.region.base + inst_fb->size - 1;
 546
 547         cw1.offset.quad_part = stack_fb->gpu_addr;
 548         cw1.region.base = DMUB_CW1_BASE;
 549         cw1.region.top = cw1.region.base + stack_fb->size - 1;
 550
 551         if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
 552                 dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
 553
 554         if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
 555                 /**
 556                  * Read back all the instruction memory so we don't hang the
 557                  * DMCUB when backdoor loading if the write from x86 hasn't been
 558                  * flushed yet. This only occurs in backdoor loading.
 559                  */
 560                 dmub_flush_buffer_mem(inst_fb);
 561
 562                 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
 563                         dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
 564                 else
 565                         dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
 566         }
 567
 568         cw2.offset.quad_part = data_fb->gpu_addr;
 569         cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
 570         cw2.region.top = cw2.region.base + data_fb->size;
 571
 572         cw3.offset.quad_part = bios_fb->gpu_addr;
 573         cw3.region.base = DMUB_CW3_BASE;
 574         cw3.region.top = cw3.region.base + bios_fb->size;
 575
 576         cw4.offset.quad_part = mail_fb->gpu_addr;
 577         cw4.region.base = DMUB_CW4_BASE;
 578         cw4.region.top = cw4.region.base + mail_fb->size;
 579
 580         /**
 581          * Doubled the mailbox region to accomodate inbox and outbox.
 582          * Note: Currently, currently total mailbox size is 16KB. It is split
 583          * equally into 8KB between inbox and outbox. If this config is
 584          * changed, then uncached base address configuration of outbox1
 585          * has to be updated in funcs->setup_out_mailbox.
 586          */
 587         inbox1.base = cw4.region.base;
 588         inbox1.top = cw4.region.base + DMUB_RB_SIZE;
 589         outbox1.base = inbox1.top;
 590         outbox1.top = cw4.region.top;
 591
 592         cw5.offset.quad_part = tracebuff_fb->gpu_addr;
 593         cw5.region.base = DMUB_CW5_BASE;
 594         cw5.region.top = cw5.region.base + tracebuff_fb->size;
 595
 596         outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
 597         outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
 598
 599         cw6.offset.quad_part = fw_state_fb->gpu_addr;
 600         cw6.region.base = DMUB_CW6_BASE;
 601         cw6.region.top = cw6.region.base + fw_state_fb->size;
 602
 603         dmub->fw_state = fw_state_fb->cpu_addr;
 604
 605         dmub->scratch_mem_fb = *scratch_mem_fb;
 606
 607         if (dmub->hw_funcs.setup_windows)
 608                 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
 609
 610         if (dmub->hw_funcs.setup_outbox0)
 611                 dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
 612
 613         if (dmub->hw_funcs.setup_mailbox)
 614                 dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
 615         if (dmub->hw_funcs.setup_out_mailbox)
 616                 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
 617
 618         dmub_memset(&rb_params, 0, sizeof(rb_params));
 619         rb_params.ctx = dmub;
 620         rb_params.base_address = mail_fb->cpu_addr;
 621         rb_params.capacity = DMUB_RB_SIZE;
 622         dmub_rb_init(&dmub->inbox1_rb, &rb_params);
 623
 624         // Initialize outbox1 ring buffer
 625         rb_params.ctx = dmub;
 626         rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
 627         rb_params.capacity = DMUB_RB_SIZE;
 628         dmub_rb_init(&dmub->outbox1_rb, &rb_params);
 629
 630         dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
 631         outbox0_rb_params.ctx = dmub;
 632         outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
 633         outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
 634         dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
 635
 636         /* Report to DMUB what features are supported by current driver */
 637         if (dmub->hw_funcs.enable_dmub_boot_options)
 638                 dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
 639
 640         if (dmub->hw_funcs.skip_dmub_panel_power_sequence)
 641                 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
 642                         params->skip_panel_power_sequence);
 643
 644         if (dmub->hw_funcs.reset_release)
 645                 dmub->hw_funcs.reset_release(dmub);
 646
 647         dmub->hw_init = true;
 648
 649         return DMUB_STATUS_OK;
 650 }
 651
 652 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
 653 {
 654         if (!dmub->sw_init)
 655                 return DMUB_STATUS_INVALID;
 656
 657         if (dmub->hw_funcs.reset)
 658                 dmub->hw_funcs.reset(dmub);
 659
 660         /* mailboxes have been reset in hw, so reset the sw state as well */
 661         dmub->inbox1_last_wptr = 0;
 662         dmub->inbox1_rb.wrpt = 0;
 663         dmub->inbox1_rb.rptr = 0;
 664         dmub->outbox0_rb.wrpt = 0;
 665         dmub->outbox0_rb.rptr = 0;
 666         dmub->outbox1_rb.wrpt = 0;
 667         dmub->outbox1_rb.rptr = 0;
 668
 669         dmub->hw_init = false;
 670
 671         return DMUB_STATUS_OK;
 672 }
 673
 674 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
 675                                     const union dmub_rb_cmd *cmd)
 676 {
 677         if (!dmub->hw_init)
 678                 return DMUB_STATUS_INVALID;
 679
 680         if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
 681                 return DMUB_STATUS_OK;
 682
 683         return DMUB_STATUS_QUEUE_FULL;
 684 }
 685
 686 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
 687 {
 688         struct dmub_rb flush_rb;
 689
 690         if (!dmub->hw_init)
 691                 return DMUB_STATUS_INVALID;
 692
 693         /**
 694          * Read back all the queued commands to ensure that they've
 695          * been flushed to framebuffer memory. Otherwise DMCUB might
 696          * read back stale, fully invalid or partially invalid data.
 697          */
 698         flush_rb = dmub->inbox1_rb;
 699         flush_rb.rptr = dmub->inbox1_last_wptr;
 700         dmub_rb_flush_pending(&flush_rb);
 701
 702         dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
 703
 704         dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
 705
 706         return DMUB_STATUS_OK;
 707 }
 708
 709 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
 710                                              uint32_t timeout_us)
 711 {
 712         uint32_t i;
 713
 714         if (!dmub->hw_init)
 715                 return DMUB_STATUS_INVALID;
 716
 717         for (i = 0; i <= timeout_us; i += 100) {
 718                 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
 719
 720                 if (status.bits.dal_fw && status.bits.mailbox_rdy)
 721                         return DMUB_STATUS_OK;
 722
 723                 udelay(100);
 724         }
 725
 726         return DMUB_STATUS_TIMEOUT;
 727 }
 728
 729 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
 730                                             uint32_t timeout_us)
 731 {
 732         uint32_t i = 0;
 733
 734         if (!dmub->hw_init)
 735                 return DMUB_STATUS_INVALID;
 736
 737         if (!dmub->hw_funcs.is_phy_init)
 738                 return DMUB_STATUS_OK;
 739
 740         for (i = 0; i <= timeout_us; i += 10) {
 741                 if (dmub->hw_funcs.is_phy_init(dmub))
 742                         return DMUB_STATUS_OK;
 743
 744                 udelay(10);
 745         }
 746
 747         return DMUB_STATUS_TIMEOUT;
 748 }
 749
 750 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
 751                                         uint32_t timeout_us)
 752 {
 753         uint32_t i, rptr;
 754
 755         if (!dmub->hw_init)
 756                 return DMUB_STATUS_INVALID;
 757
 758         for (i = 0; i <= timeout_us; ++i) {
 759                 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
 760
 761                 if (rptr > dmub->inbox1_rb.capacity)
 762                         return DMUB_STATUS_HW_FAILURE;
 763
 764                 dmub->inbox1_rb.rptr = rptr;
 765
 766                 if (dmub_rb_empty(&dmub->inbox1_rb))
 767                         return DMUB_STATUS_OK;
 768
 769                 udelay(1);
 770         }
 771
 772         return DMUB_STATUS_TIMEOUT;
 773 }
 774
 775 enum dmub_status
 776 dmub_srv_send_gpint_command(struct dmub_srv *dmub,
 777                             enum dmub_gpint_command command_code,
 778                             uint16_t param, uint32_t timeout_us)
 779 {
 780         union dmub_gpint_data_register reg;
 781         uint32_t i;
 782
 783         if (!dmub->sw_init)
 784                 return DMUB_STATUS_INVALID;
 785
 786         if (!dmub->hw_funcs.set_gpint)
 787                 return DMUB_STATUS_INVALID;
 788
 789         if (!dmub->hw_funcs.is_gpint_acked)
 790                 return DMUB_STATUS_INVALID;
 791
 792         reg.bits.status = 1;
 793         reg.bits.command_code = command_code;
 794         reg.bits.param = param;
 795
 796         dmub->hw_funcs.set_gpint(dmub, reg);
 797
 798         for (i = 0; i < timeout_us; ++i) {
 799                 udelay(1);
 800
 801                 if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
 802                         return DMUB_STATUS_OK;
 803         }
 804
 805         return DMUB_STATUS_TIMEOUT;
 806 }
 807
 808 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
 809                                              uint32_t *response)
 810 {
 811         *response = 0;
 812
 813         if (!dmub->sw_init)
 814                 return DMUB_STATUS_INVALID;
 815
 816         if (!dmub->hw_funcs.get_gpint_response)
 817                 return DMUB_STATUS_INVALID;
 818
 819         *response = dmub->hw_funcs.get_gpint_response(dmub);
 820
 821         return DMUB_STATUS_OK;
 822 }
 823
 824 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
 825                                              uint32_t *dataout)
 826 {
 827         *dataout = 0;
 828
 829         if (!dmub->sw_init)
 830                 return DMUB_STATUS_INVALID;
 831
 832         if (!dmub->hw_funcs.get_gpint_dataout)
 833                 return DMUB_STATUS_INVALID;
 834
 835         *dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
 836
 837         return DMUB_STATUS_OK;
 838 }
 839
 840 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
 841                                              union dmub_fw_boot_status *status)
 842 {
 843         status->all = 0;
 844
 845         if (!dmub->sw_init)
 846                 return DMUB_STATUS_INVALID;
 847
 848         if (dmub->hw_funcs.get_fw_status)
 849                 *status = dmub->hw_funcs.get_fw_status(dmub);
 850
 851         return DMUB_STATUS_OK;
 852 }
 853
 854 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
 855                                               union dmub_rb_cmd *cmd)
 856 {
 857         enum dmub_status status = DMUB_STATUS_OK;
 858
 859         // Queue command
 860         status = dmub_srv_cmd_queue(dmub, cmd);
 861
 862         if (status != DMUB_STATUS_OK)
 863                 return status;
 864
 865         // Execute command
 866         status = dmub_srv_cmd_execute(dmub);
 867
 868         if (status != DMUB_STATUS_OK)
 869                 return status;
 870
 871         // Wait for DMUB to process command
 872         status = dmub_srv_wait_for_idle(dmub, 100000);
 873
 874         if (status != DMUB_STATUS_OK)
 875                 return status;
 876
 877         // Copy data back from ring buffer into command
 878         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd);
 879
 880         return status;
 881 }
 882
 883 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
 884                                  void *entry)
 885 {
 886         const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
 887         uint64_t *dst = (uint64_t *)entry;
 888         uint8_t i;
 889         uint8_t loop_count;
 890
 891         if (rb->rptr == rb->wrpt)
 892                 return false;
 893
 894         loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t);
 895         // copying data
 896         for (i = 0; i < loop_count; i++)
 897                 *dst++ = *src++;
 898
 899         rb->rptr += sizeof(struct dmcub_trace_buf_entry);
 900
 901         rb->rptr %= rb->capacity;
 902
 903         return true;
 904 }
 905
 906 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
 907 {
 908         dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub);
 909
 910         return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
 911 }
 912
 913 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
 914 {
 915         if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
 916                 return false;
 917         dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
 918         return true;
 919 }
 920
 921 bool dmub_srv_should_detect(struct dmub_srv *dmub)
 922 {
 923         if (!dmub->hw_init || !dmub->hw_funcs.should_detect)
 924                 return false;
 925
 926         return dmub->hw_funcs.should_detect(dmub);
 927 }
 928
 929 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
 930 {
 931         if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
 932                 return DMUB_STATUS_INVALID;
 933
 934         dmub->hw_funcs.clear_inbox0_ack_register(dmub);
 935         return DMUB_STATUS_OK;
 936 }
 937
 938 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)
 939 {
 940         uint32_t i = 0;
 941         uint32_t ack = 0;
 942
 943         if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register)
 944                 return DMUB_STATUS_INVALID;
 945
 946         for (i = 0; i <= timeout_us; i++) {
 947                 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
 948                 if (ack)
 949                         return DMUB_STATUS_OK;
 950         }
 951         return DMUB_STATUS_TIMEOUT;
 952 }
 953
 954 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
 955                 union dmub_inbox0_data_register data)
 956 {
 957         if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
 958                 return DMUB_STATUS_INVALID;
 959
 960         dmub->hw_funcs.send_inbox0_cmd(dmub, data);
 961         return DMUB_STATUS_OK;
 962 }