drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "../dmub_srv.h"
  27 #include "dmub_dcn20.h"
  28 #include "dmub_dcn21.h"
  29 #include "dmub_cmd.h"
  30 #include "dmub_dcn30.h"
  31 #include "dmub_dcn301.h"
  32 #include "dmub_dcn302.h"
  33 #include "dmub_dcn303.h"
  34 #include "dmub_dcn31.h"
  35 #include "dmub_dcn314.h"
  36 #include "dmub_dcn315.h"
  37 #include "dmub_dcn316.h"
  38 #include "dmub_dcn32.h"
  39 #include "os_types.h"
  40 /*
  41  * Note: the DMUB service is standalone. No additional headers should be
  42  * added below or above this line unless they reside within the DMUB
  43  * folder.
  44  */
  45
  46 /* Alignment for framebuffer memory. */
  47 #define DMUB_FB_ALIGNMENT (1024 * 1024)
  48
  49 /* Stack size. */
  50 #define DMUB_STACK_SIZE (128 * 1024)
  51
  52 /* Context size. */
  53 #define DMUB_CONTEXT_SIZE (512 * 1024)
  54
  55 /* Mailbox size : Ring buffers are required for both inbox and outbox */
  56 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
  57
  58 /* Default state size if meta is absent. */
  59 #define DMUB_FW_STATE_SIZE (64 * 1024)
  60
  61 /* Default tracebuffer size if meta is absent. */
  62 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
  63
  64
  65 /* Default scratch mem size. */
  66 #define DMUB_SCRATCH_MEM_SIZE (256)
  67
  68 /* Number of windows in use. */
  69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)
  70 /* Base addresses. */
  71
  72 #define DMUB_CW0_BASE (0x60000000)
  73 #define DMUB_CW1_BASE (0x61000000)
  74 #define DMUB_CW3_BASE (0x63000000)
  75 #define DMUB_CW4_BASE (0x64000000)
  76 #define DMUB_CW5_BASE (0x65000000)
  77 #define DMUB_CW6_BASE (0x66000000)
  78
  79 #define DMUB_REGION5_BASE (0xA0000000)
  80
  81 static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
  82 {
  83         return (val + factor - 1) / factor * factor;
  84 }
  85
  86 void dmub_flush_buffer_mem(const struct dmub_fb *fb)
  87 {
  88         const uint8_t *base = (const uint8_t *)fb->cpu_addr;
  89         uint8_t buf[64];
  90         uint32_t pos, end;
  91
  92         /**
  93          * Read 64-byte chunks since we don't want to store a
  94          * large temporary buffer for this purpose.
  95          */
  96         end = fb->size / sizeof(buf) * sizeof(buf);
  97
  98         for (pos = 0; pos < end; pos += sizeof(buf))
  99                 dmub_memcpy(buf, base + pos, sizeof(buf));
 100
 101         /* Read anything leftover into the buffer. */
 102         if (end < fb->size)
 103                 dmub_memcpy(buf, base + pos, fb->size - end);
 104 }
 105
 106 static const struct dmub_fw_meta_info *
 107 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)
 108 {
 109         const union dmub_fw_meta *meta;
 110
 111         if (!blob || !blob_size)
 112                 return NULL;
 113
 114         if (blob_size < sizeof(union dmub_fw_meta) + meta_offset)
 115                 return NULL;
 116
 117         meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset -
 118                                             sizeof(union dmub_fw_meta));
 119
 120         if (meta->info.magic_value != DMUB_FW_META_MAGIC)
 121                 return NULL;
 122
 123         return &meta->info;
 124 }
 125
 126 static const struct dmub_fw_meta_info *
 127 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params)
 128 {
 129         const struct dmub_fw_meta_info *info = NULL;
 130
 131         if (params->fw_bss_data && params->bss_data_size) {
 132                 /* Legacy metadata region. */
 133                 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data,
 134                                                        params->bss_data_size,
 135                                                        DMUB_FW_META_OFFSET);
 136         } else if (params->fw_inst_const && params->inst_const_size) {
 137                 /* Combined metadata region - can be aligned to 16-bytes. */
 138                 uint32_t i;
 139
 140                 for (i = 0; i < 16; ++i) {
 141                         info = dmub_get_fw_meta_info_from_blob(
 142                                 params->fw_inst_const, params->inst_const_size, i);
 143
 144                         if (info)
 145                                 break;
 146                 }
 147         }
 148
 149         return info;
 150 }
 151
 152 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 153 {
 154         struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
 155
 156         switch (asic) {
 157         case DMUB_ASIC_DCN20:
 158         case DMUB_ASIC_DCN21:
 159         case DMUB_ASIC_DCN30:
 160         case DMUB_ASIC_DCN301:
 161         case DMUB_ASIC_DCN302:
 162         case DMUB_ASIC_DCN303:
 163                 dmub->regs = &dmub_srv_dcn20_regs;
 164
 165                 funcs->reset = dmub_dcn20_reset;
 166                 funcs->reset_release = dmub_dcn20_reset_release;
 167                 funcs->backdoor_load = dmub_dcn20_backdoor_load;
 168                 funcs->setup_windows = dmub_dcn20_setup_windows;
 169                 funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
 170                 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
 171                 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
 172                 funcs->is_supported = dmub_dcn20_is_supported;
 173                 funcs->is_hw_init = dmub_dcn20_is_hw_init;
 174                 funcs->set_gpint = dmub_dcn20_set_gpint;
 175                 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
 176                 funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
 177                 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
 178                 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
 179                 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
 180                 funcs->get_current_time = dmub_dcn20_get_current_time;
 181
 182                 // Out mailbox register access functions for RN and above
 183                 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
 184                 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
 185                 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
 186
 187                 //outbox0 call stacks
 188                 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;
 189                 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
 190                 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
 191
 192                 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
 193
 194                 if (asic == DMUB_ASIC_DCN21) {
 195                         dmub->regs = &dmub_srv_dcn21_regs;
 196
 197                         funcs->is_phy_init = dmub_dcn21_is_phy_init;
 198                 }
 199                 if (asic == DMUB_ASIC_DCN30) {
 200                         dmub->regs = &dmub_srv_dcn30_regs;
 201
 202                         funcs->backdoor_load = dmub_dcn30_backdoor_load;
 203                         funcs->setup_windows = dmub_dcn30_setup_windows;
 204                 }
 205                 if (asic == DMUB_ASIC_DCN301) {
 206                         dmub->regs = &dmub_srv_dcn301_regs;
 207
 208                         funcs->backdoor_load = dmub_dcn30_backdoor_load;
 209                         funcs->setup_windows = dmub_dcn30_setup_windows;
 210                 }
 211                 if (asic == DMUB_ASIC_DCN302) {
 212                         dmub->regs = &dmub_srv_dcn302_regs;
 213
 214                         funcs->backdoor_load = dmub_dcn30_backdoor_load;
 215                         funcs->setup_windows = dmub_dcn30_setup_windows;
 216                 }
 217                 if (asic == DMUB_ASIC_DCN303) {
 218                         dmub->regs = &dmub_srv_dcn303_regs;
 219
 220                         funcs->backdoor_load = dmub_dcn30_backdoor_load;
 221                         funcs->setup_windows = dmub_dcn30_setup_windows;
 222                 }
 223                 break;
 224
 225         case DMUB_ASIC_DCN31:
 226         case DMUB_ASIC_DCN31B:
 227         case DMUB_ASIC_DCN314:
 228         case DMUB_ASIC_DCN315:
 229         case DMUB_ASIC_DCN316:
 230                 if (asic == DMUB_ASIC_DCN314) {
 231                         dmub->regs_dcn31 = &dmub_srv_dcn314_regs;
 232                         funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported;
 233                 } else if (asic == DMUB_ASIC_DCN315) {
 234                         dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
 235                 } else if (asic == DMUB_ASIC_DCN316) {
 236                         dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
 237                 } else {
 238                         dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
 239                         funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported;
 240                 }
 241                 funcs->reset = dmub_dcn31_reset;
 242                 funcs->reset_release = dmub_dcn31_reset_release;
 243                 funcs->backdoor_load = dmub_dcn31_backdoor_load;
 244                 funcs->setup_windows = dmub_dcn31_setup_windows;
 245                 funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
 246                 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
 247                 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
 248                 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
 249                 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
 250                 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
 251                 funcs->is_supported = dmub_dcn31_is_supported;
 252                 funcs->is_hw_init = dmub_dcn31_is_hw_init;
 253                 funcs->set_gpint = dmub_dcn31_set_gpint;
 254                 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
 255                 funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
 256                 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
 257                 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
 258                 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
 259                 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
 260                 //outbox0 call stacks
 261                 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
 262                 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
 263                 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
 264
 265                 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
 266                 funcs->should_detect = dmub_dcn31_should_detect;
 267                 funcs->get_current_time = dmub_dcn31_get_current_time;
 268
 269                 break;
 270
 271         case DMUB_ASIC_DCN32:
 272         case DMUB_ASIC_DCN321:
 273                 dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
 274                 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
 275                 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
 276                 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
 277                 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
 278                 funcs->reset = dmub_dcn32_reset;
 279                 funcs->reset_release = dmub_dcn32_reset_release;
 280                 funcs->backdoor_load = dmub_dcn32_backdoor_load;
 281                 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
 282                 funcs->setup_windows = dmub_dcn32_setup_windows;
 283                 funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
 284                 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
 285                 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
 286                 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
 287                 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
 288                 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
 289                 funcs->is_supported = dmub_dcn32_is_supported;
 290                 funcs->is_hw_init = dmub_dcn32_is_hw_init;
 291                 funcs->set_gpint = dmub_dcn32_set_gpint;
 292                 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
 293                 funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
 294                 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
 295                 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
 296                 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
 297                 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
 298
 299                 /* outbox0 call stacks */
 300                 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
 301                 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
 302                 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
 303                 funcs->get_current_time = dmub_dcn32_get_current_time;
 304                 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
 305
 306                 break;
 307
 308         default:
 309                 return false;
 310         }
 311
 312         return true;
 313 }
 314
 315 enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
 316                                  const struct dmub_srv_create_params *params)
 317 {
 318         enum dmub_status status = DMUB_STATUS_OK;
 319
 320         dmub_memset(dmub, 0, sizeof(*dmub));
 321
 322         dmub->funcs = params->funcs;
 323         dmub->user_ctx = params->user_ctx;
 324         dmub->asic = params->asic;
 325         dmub->fw_version = params->fw_version;
 326         dmub->is_virtual = params->is_virtual;
 327
 328         /* Setup asic dependent hardware funcs. */
 329         if (!dmub_srv_hw_setup(dmub, params->asic)) {
 330                 status = DMUB_STATUS_INVALID;
 331                 goto cleanup;
 332         }
 333
 334         /* Override (some) hardware funcs based on user params. */
 335         if (params->hw_funcs) {
 336                 if (params->hw_funcs->emul_get_inbox1_rptr)
 337                         dmub->hw_funcs.emul_get_inbox1_rptr =
 338                                 params->hw_funcs->emul_get_inbox1_rptr;
 339
 340                 if (params->hw_funcs->emul_set_inbox1_wptr)
 341                         dmub->hw_funcs.emul_set_inbox1_wptr =
 342                                 params->hw_funcs->emul_set_inbox1_wptr;
 343
 344                 if (params->hw_funcs->is_supported)
 345                         dmub->hw_funcs.is_supported =
 346                                 params->hw_funcs->is_supported;
 347         }
 348
 349         /* Sanity checks for required hw func pointers. */
 350         if (!dmub->hw_funcs.get_inbox1_rptr ||
 351             !dmub->hw_funcs.set_inbox1_wptr) {
 352                 status = DMUB_STATUS_INVALID;
 353                 goto cleanup;
 354         }
 355
 356 cleanup:
 357         if (status == DMUB_STATUS_OK)
 358                 dmub->sw_init = true;
 359         else
 360                 dmub_srv_destroy(dmub);
 361
 362         return status;
 363 }
 364
 365 void dmub_srv_destroy(struct dmub_srv *dmub)
 366 {
 367         dmub_memset(dmub, 0, sizeof(*dmub));
 368 }
 369
 370 enum dmub_status
 371 dmub_srv_calc_region_info(struct dmub_srv *dmub,
 372                           const struct dmub_srv_region_params *params,
 373                           struct dmub_srv_region_info *out)
 374 {
 375         struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
 376         struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
 377         struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
 378         struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
 379         struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
 380         struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
 381         struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
 382         struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM];
 383         const struct dmub_fw_meta_info *fw_info;
 384         uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
 385         uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
 386         uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE;
 387         uint32_t previous_top = 0;
 388         if (!dmub->sw_init)
 389                 return DMUB_STATUS_INVALID;
 390
 391         memset(out, 0, sizeof(*out));
 392
 393         out->num_regions = DMUB_NUM_WINDOWS;
 394
 395         inst->base = 0x0;
 396         inst->top = inst->base + params->inst_const_size;
 397
 398         data->base = dmub_align(inst->top, 256);
 399         data->top = data->base + params->bss_data_size;
 400
 401         /*
 402          * All cache windows below should be aligned to the size
 403          * of the DMCUB cache line, 64 bytes.
 404          */
 405
 406         stack->base = dmub_align(data->top, 256);
 407         stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
 408
 409         bios->base = dmub_align(stack->top, 256);
 410         bios->top = bios->base + params->vbios_size;
 411
 412         if (params->is_mailbox_in_inbox) {
 413                 mail->base = 0;
 414                 mail->top = mail->base + DMUB_MAILBOX_SIZE;
 415                 previous_top = bios->top;
 416         } else {
 417                 mail->base = dmub_align(bios->top, 256);
 418                 mail->top = mail->base + DMUB_MAILBOX_SIZE;
 419                 previous_top = mail->top;
 420         }
 421
 422         fw_info = dmub_get_fw_meta_info(params);
 423
 424         if (fw_info) {
 425                 fw_state_size = fw_info->fw_region_size;
 426                 trace_buffer_size = fw_info->trace_buffer_size;
 427
 428                 /**
 429                  * If DM didn't fill in a version, then fill it in based on
 430                  * the firmware meta now that we have it.
 431                  *
 432                  * TODO: Make it easier for driver to extract this out to
 433                  * pass during creation.
 434                  */
 435                 if (dmub->fw_version == 0)
 436                         dmub->fw_version = fw_info->fw_version;
 437         }
 438
 439         trace_buff->base = dmub_align(previous_top, 256);
 440         trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
 441
 442         fw_state->base = dmub_align(trace_buff->top, 256);
 443         fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
 444
 445         scratch_mem->base = dmub_align(fw_state->top, 256);
 446         scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64);
 447
 448         out->fb_size = dmub_align(scratch_mem->top, 4096);
 449
 450         if (params->is_mailbox_in_inbox)
 451                 out->inbox_size = dmub_align(mail->top, 4096);
 452
 453         return DMUB_STATUS_OK;
 454 }
 455
 456 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,
 457                                        const struct dmub_srv_memory_params *params,
 458                                        struct dmub_srv_fb_info *out)
 459 {
 460         uint8_t *cpu_base;
 461         uint64_t gpu_base;
 462         uint32_t i;
 463
 464         if (!dmub->sw_init)
 465                 return DMUB_STATUS_INVALID;
 466
 467         memset(out, 0, sizeof(*out));
 468
 469         if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
 470                 return DMUB_STATUS_INVALID;
 471
 472         cpu_base = (uint8_t *)params->cpu_fb_addr;
 473         gpu_base = params->gpu_fb_addr;
 474
 475         for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
 476                 const struct dmub_region *reg =
 477                         &params->region_info->regions[i];
 478
 479                 out->fb[i].cpu_addr = cpu_base + reg->base;
 480                 out->fb[i].gpu_addr = gpu_base + reg->base;
 481
 482                 if (i == DMUB_WINDOW_4_MAILBOX && params->cpu_inbox_addr != 0) {
 483                         out->fb[i].cpu_addr = (uint8_t *)params->cpu_inbox_addr + reg->base;
 484                         out->fb[i].gpu_addr = params->gpu_inbox_addr + reg->base;
 485                 }
 486
 487                 out->fb[i].size = reg->top - reg->base;
 488         }
 489
 490         out->num_fb = DMUB_NUM_WINDOWS;
 491
 492         return DMUB_STATUS_OK;
 493 }
 494
 495 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
 496                                          bool *is_supported)
 497 {
 498         *is_supported = false;
 499
 500         if (!dmub->sw_init)
 501                 return DMUB_STATUS_INVALID;
 502
 503         if (dmub->hw_funcs.is_supported)
 504                 *is_supported = dmub->hw_funcs.is_supported(dmub);
 505
 506         return DMUB_STATUS_OK;
 507 }
 508
 509 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
 510 {
 511         *is_hw_init = false;
 512
 513         if (!dmub->sw_init)
 514                 return DMUB_STATUS_INVALID;
 515
 516         if (!dmub->hw_init)
 517                 return DMUB_STATUS_OK;
 518
 519         if (dmub->hw_funcs.is_hw_init)
 520                 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
 521
 522         return DMUB_STATUS_OK;
 523 }
 524
 525 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 526                                   const struct dmub_srv_hw_params *params)
 527 {
 528         struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
 529         struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
 530         struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
 531         struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
 532         struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
 533         struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
 534         struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
 535         struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
 536
 537         struct dmub_rb_init_params rb_params, outbox0_rb_params;
 538         struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
 539         struct dmub_region inbox1, outbox1, outbox0;
 540
 541         if (!dmub->sw_init)
 542                 return DMUB_STATUS_INVALID;
 543
 544         if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
 545                 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
 546                 ASSERT(0);
 547                 return DMUB_STATUS_INVALID;
 548         }
 549
 550         dmub->fb_base = params->fb_base;
 551         dmub->fb_offset = params->fb_offset;
 552         dmub->psp_version = params->psp_version;
 553
 554         if (dmub->hw_funcs.reset)
 555                 dmub->hw_funcs.reset(dmub);
 556
 557         /* reset the cache of the last wptr as well now that hw is reset */
 558         dmub->inbox1_last_wptr = 0;
 559
 560         cw0.offset.quad_part = inst_fb->gpu_addr;
 561         cw0.region.base = DMUB_CW0_BASE;
 562         cw0.region.top = cw0.region.base + inst_fb->size - 1;
 563
 564         cw1.offset.quad_part = stack_fb->gpu_addr;
 565         cw1.region.base = DMUB_CW1_BASE;
 566         cw1.region.top = cw1.region.base + stack_fb->size - 1;
 567
 568         if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
 569                 dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
 570
 571         if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
 572                 /**
 573                  * Read back all the instruction memory so we don't hang the
 574                  * DMCUB when backdoor loading if the write from x86 hasn't been
 575                  * flushed yet. This only occurs in backdoor loading.
 576                  */
 577                 dmub_flush_buffer_mem(inst_fb);
 578
 579                 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
 580                         dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
 581                 else
 582                         dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
 583         }
 584
 585         cw2.offset.quad_part = data_fb->gpu_addr;
 586         cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
 587         cw2.region.top = cw2.region.base + data_fb->size;
 588
 589         cw3.offset.quad_part = bios_fb->gpu_addr;
 590         cw3.region.base = DMUB_CW3_BASE;
 591         cw3.region.top = cw3.region.base + bios_fb->size;
 592
 593         cw4.offset.quad_part = mail_fb->gpu_addr;
 594         cw4.region.base = DMUB_CW4_BASE;
 595         cw4.region.top = cw4.region.base + mail_fb->size;
 596
 597         /**
 598          * Doubled the mailbox region to accomodate inbox and outbox.
 599          * Note: Currently, currently total mailbox size is 16KB. It is split
 600          * equally into 8KB between inbox and outbox. If this config is
 601          * changed, then uncached base address configuration of outbox1
 602          * has to be updated in funcs->setup_out_mailbox.
 603          */
 604         inbox1.base = cw4.region.base;
 605         inbox1.top = cw4.region.base + DMUB_RB_SIZE;
 606         outbox1.base = inbox1.top;
 607         outbox1.top = cw4.region.top;
 608
 609         cw5.offset.quad_part = tracebuff_fb->gpu_addr;
 610         cw5.region.base = DMUB_CW5_BASE;
 611         cw5.region.top = cw5.region.base + tracebuff_fb->size;
 612
 613         outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
 614         outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
 615
 616         cw6.offset.quad_part = fw_state_fb->gpu_addr;
 617         cw6.region.base = DMUB_CW6_BASE;
 618         cw6.region.top = cw6.region.base + fw_state_fb->size;
 619
 620         dmub->fw_state = fw_state_fb->cpu_addr;
 621
 622         dmub->scratch_mem_fb = *scratch_mem_fb;
 623
 624         if (dmub->hw_funcs.setup_windows)
 625                 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
 626
 627         if (dmub->hw_funcs.setup_outbox0)
 628                 dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
 629
 630         if (dmub->hw_funcs.setup_mailbox)
 631                 dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
 632         if (dmub->hw_funcs.setup_out_mailbox)
 633                 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
 634
 635         dmub_memset(&rb_params, 0, sizeof(rb_params));
 636         rb_params.ctx = dmub;
 637         rb_params.base_address = mail_fb->cpu_addr;
 638         rb_params.capacity = DMUB_RB_SIZE;
 639         dmub_rb_init(&dmub->inbox1_rb, &rb_params);
 640
 641         // Initialize outbox1 ring buffer
 642         rb_params.ctx = dmub;
 643         rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
 644         rb_params.capacity = DMUB_RB_SIZE;
 645         dmub_rb_init(&dmub->outbox1_rb, &rb_params);
 646
 647         dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
 648         outbox0_rb_params.ctx = dmub;
 649         outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
 650         outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
 651         dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
 652
 653         /* Report to DMUB what features are supported by current driver */
 654         if (dmub->hw_funcs.enable_dmub_boot_options)
 655                 dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
 656
 657         if (dmub->hw_funcs.skip_dmub_panel_power_sequence)
 658                 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
 659                         params->skip_panel_power_sequence);
 660
 661         if (dmub->hw_funcs.reset_release)
 662                 dmub->hw_funcs.reset_release(dmub);
 663
 664         dmub->hw_init = true;
 665
 666         return DMUB_STATUS_OK;
 667 }
 668
 669 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
 670 {
 671         if (!dmub->sw_init)
 672                 return DMUB_STATUS_INVALID;
 673
 674         if (dmub->hw_funcs.reset)
 675                 dmub->hw_funcs.reset(dmub);
 676
 677         /* mailboxes have been reset in hw, so reset the sw state as well */
 678         dmub->inbox1_last_wptr = 0;
 679         dmub->inbox1_rb.wrpt = 0;
 680         dmub->inbox1_rb.rptr = 0;
 681         dmub->outbox0_rb.wrpt = 0;
 682         dmub->outbox0_rb.rptr = 0;
 683         dmub->outbox1_rb.wrpt = 0;
 684         dmub->outbox1_rb.rptr = 0;
 685
 686         dmub->hw_init = false;
 687
 688         return DMUB_STATUS_OK;
 689 }
 690
 691 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
 692                                     const union dmub_rb_cmd *cmd)
 693 {
 694         if (!dmub->hw_init)
 695                 return DMUB_STATUS_INVALID;
 696
 697         if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
 698                 return DMUB_STATUS_OK;
 699
 700         return DMUB_STATUS_QUEUE_FULL;
 701 }
 702
 703 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
 704 {
 705         struct dmub_rb flush_rb;
 706
 707         if (!dmub->hw_init)
 708                 return DMUB_STATUS_INVALID;
 709
 710         /**
 711          * Read back all the queued commands to ensure that they've
 712          * been flushed to framebuffer memory. Otherwise DMCUB might
 713          * read back stale, fully invalid or partially invalid data.
 714          */
 715         flush_rb = dmub->inbox1_rb;
 716         flush_rb.rptr = dmub->inbox1_last_wptr;
 717         dmub_rb_flush_pending(&flush_rb);
 718
 719         dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
 720
 721         dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
 722
 723         return DMUB_STATUS_OK;
 724 }
 725
 726 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
 727                                              uint32_t timeout_us)
 728 {
 729         uint32_t i;
 730
 731         if (!dmub->hw_init)
 732                 return DMUB_STATUS_INVALID;
 733
 734         for (i = 0; i <= timeout_us; i += 100) {
 735                 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
 736
 737                 if (status.bits.dal_fw && status.bits.mailbox_rdy)
 738                         return DMUB_STATUS_OK;
 739
 740                 udelay(100);
 741         }
 742
 743         return DMUB_STATUS_TIMEOUT;
 744 }
 745
 746 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
 747                                             uint32_t timeout_us)
 748 {
 749         uint32_t i = 0;
 750
 751         if (!dmub->hw_init)
 752                 return DMUB_STATUS_INVALID;
 753
 754         if (!dmub->hw_funcs.is_phy_init)
 755                 return DMUB_STATUS_OK;
 756
 757         for (i = 0; i <= timeout_us; i += 10) {
 758                 if (dmub->hw_funcs.is_phy_init(dmub))
 759                         return DMUB_STATUS_OK;
 760
 761                 udelay(10);
 762         }
 763
 764         return DMUB_STATUS_TIMEOUT;
 765 }
 766
 767 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
 768                                         uint32_t timeout_us)
 769 {
 770         uint32_t i, rptr;
 771
 772         if (!dmub->hw_init)
 773                 return DMUB_STATUS_INVALID;
 774
 775         for (i = 0; i <= timeout_us; ++i) {
 776                 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
 777
 778                 if (rptr > dmub->inbox1_rb.capacity)
 779                         return DMUB_STATUS_HW_FAILURE;
 780
 781                 dmub->inbox1_rb.rptr = rptr;
 782
 783                 if (dmub_rb_empty(&dmub->inbox1_rb))
 784                         return DMUB_STATUS_OK;
 785
 786                 udelay(1);
 787         }
 788
 789         return DMUB_STATUS_TIMEOUT;
 790 }
 791
 792 enum dmub_status
 793 dmub_srv_send_gpint_command(struct dmub_srv *dmub,
 794                             enum dmub_gpint_command command_code,
 795                             uint16_t param, uint32_t timeout_us)
 796 {
 797         union dmub_gpint_data_register reg;
 798         uint32_t i;
 799
 800         if (!dmub->sw_init)
 801                 return DMUB_STATUS_INVALID;
 802
 803         if (!dmub->hw_funcs.set_gpint)
 804                 return DMUB_STATUS_INVALID;
 805
 806         if (!dmub->hw_funcs.is_gpint_acked)
 807                 return DMUB_STATUS_INVALID;
 808
 809         reg.bits.status = 1;
 810         reg.bits.command_code = command_code;
 811         reg.bits.param = param;
 812
 813         dmub->hw_funcs.set_gpint(dmub, reg);
 814
 815         for (i = 0; i < timeout_us; ++i) {
 816                 udelay(1);
 817
 818                 if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
 819                         return DMUB_STATUS_OK;
 820         }
 821
 822         return DMUB_STATUS_TIMEOUT;
 823 }
 824
 825 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
 826                                              uint32_t *response)
 827 {
 828         *response = 0;
 829
 830         if (!dmub->sw_init)
 831                 return DMUB_STATUS_INVALID;
 832
 833         if (!dmub->hw_funcs.get_gpint_response)
 834                 return DMUB_STATUS_INVALID;
 835
 836         *response = dmub->hw_funcs.get_gpint_response(dmub);
 837
 838         return DMUB_STATUS_OK;
 839 }
 840
 841 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
 842                                              uint32_t *dataout)
 843 {
 844         *dataout = 0;
 845
 846         if (!dmub->sw_init)
 847                 return DMUB_STATUS_INVALID;
 848
 849         if (!dmub->hw_funcs.get_gpint_dataout)
 850                 return DMUB_STATUS_INVALID;
 851
 852         *dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
 853
 854         return DMUB_STATUS_OK;
 855 }
 856
 857 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
 858                                              union dmub_fw_boot_status *status)
 859 {
 860         status->all = 0;
 861
 862         if (!dmub->sw_init)
 863                 return DMUB_STATUS_INVALID;
 864
 865         if (dmub->hw_funcs.get_fw_status)
 866                 *status = dmub->hw_funcs.get_fw_status(dmub);
 867
 868         return DMUB_STATUS_OK;
 869 }
 870
 871 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
 872                                               union dmub_rb_cmd *cmd)
 873 {
 874         enum dmub_status status = DMUB_STATUS_OK;
 875
 876         // Queue command
 877         status = dmub_srv_cmd_queue(dmub, cmd);
 878
 879         if (status != DMUB_STATUS_OK)
 880                 return status;
 881
 882         // Execute command
 883         status = dmub_srv_cmd_execute(dmub);
 884
 885         if (status != DMUB_STATUS_OK)
 886                 return status;
 887
 888         // Wait for DMUB to process command
 889         status = dmub_srv_wait_for_idle(dmub, 100000);
 890
 891         if (status != DMUB_STATUS_OK)
 892                 return status;
 893
 894         // Copy data back from ring buffer into command
 895         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd);
 896
 897         return status;
 898 }
 899
 900 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
 901                                  void *entry)
 902 {
 903         const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
 904         uint64_t *dst = (uint64_t *)entry;
 905         uint8_t i;
 906         uint8_t loop_count;
 907
 908         if (rb->rptr == rb->wrpt)
 909                 return false;
 910
 911         loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t);
 912         // copying data
 913         for (i = 0; i < loop_count; i++)
 914                 *dst++ = *src++;
 915
 916         rb->rptr += sizeof(struct dmcub_trace_buf_entry);
 917
 918         rb->rptr %= rb->capacity;
 919
 920         return true;
 921 }
 922
 923 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
 924 {
 925         dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub);
 926
 927         return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
 928 }
 929
 930 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
 931 {
 932         if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
 933                 return false;
 934         dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
 935         return true;
 936 }
 937
 938 bool dmub_srv_should_detect(struct dmub_srv *dmub)
 939 {
 940         if (!dmub->hw_init || !dmub->hw_funcs.should_detect)
 941                 return false;
 942
 943         return dmub->hw_funcs.should_detect(dmub);
 944 }
 945
 946 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
 947 {
 948         if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
 949                 return DMUB_STATUS_INVALID;
 950
 951         dmub->hw_funcs.clear_inbox0_ack_register(dmub);
 952         return DMUB_STATUS_OK;
 953 }
 954
 955 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)
 956 {
 957         uint32_t i = 0;
 958         uint32_t ack = 0;
 959
 960         if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register)
 961                 return DMUB_STATUS_INVALID;
 962
 963         for (i = 0; i <= timeout_us; i++) {
 964                 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
 965                 if (ack)
 966                         return DMUB_STATUS_OK;
 967                 udelay(1);
 968         }
 969         return DMUB_STATUS_TIMEOUT;
 970 }
 971
 972 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
 973                 union dmub_inbox0_data_register data)
 974 {
 975         if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
 976                 return DMUB_STATUS_INVALID;
 977
 978         dmub->hw_funcs.send_inbox0_cmd(dmub, data);
 979         return DMUB_STATUS_OK;
 980 }