2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
33 #if defined(_TEST_HARNESS)
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
43 #include "atomfirmware.h"
45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
47 //<DMUB_TYPES>==================================================================
48 /* Basic type definitions. */
50 #define __forceinline inline
53 * Flag from driver to indicate that ABM should be disabled gradually
54 * by slowly reversing all backlight programming and pixel compensation.
56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
59 * Flag from driver to indicate that ABM should be disabled immediately
60 * and undo all backlight programming and pixel compensation.
62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
65 * Flag from driver to indicate that ABM should be disabled immediately
66 * and keep the current backlight programming and pixel compensation.
68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
71 * Flag from driver to set the current ABM pipe index or ABM operating level.
73 #define SET_ABM_PIPE_NORMAL 1
76 * Number of ambient light levels in ABM algorithm.
78 #define NUM_AMBI_LEVEL 5
81 * Number of operating/aggression levels in ABM algorithm.
83 #define NUM_AGGR_LEVEL 4
86 * Number of segments in the gamma curve.
88 #define NUM_POWER_FN_SEGS 8
91 * Number of segments in the backlight curve.
93 #define NUM_BL_CURVE_SEGS 16
95 /* Maximum number of SubVP streams */
96 #define DMUB_MAX_SUBVP_STREAMS 2
98 /* Define max FPO streams as 4 for now. Current implementation today
99 * only supports 1, but could be more in the future. Reduce array
100 * size to ensure the command size remains less than 64 bytes if
103 #define DMUB_MAX_FPO_STREAMS 4
105 /* Maximum number of streams on any ASIC. */
106 #define DMUB_MAX_STREAMS 6
108 /* Maximum number of planes on any ASIC. */
109 #define DMUB_MAX_PLANES 6
111 /* Trace buffer offset for entry */
112 #define TRACE_BUFFER_ENTRY_OFFSET 16
115 * Maximum number of dirty rects supported by FW.
117 #define DMUB_MAX_DIRTY_RECTS 3
121 * PSR control version legacy
123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
125 * PSR control version with multi edp support
127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
131 * ABM control version legacy
133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
136 * ABM control version with multi edp support
138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
141 * Physical framebuffer address location, 64-bit.
143 #ifndef PHYSICAL_ADDRESS_LOC
144 #define PHYSICAL_ADDRESS_LOC union large_integer
148 * OS/FW agnostic memcpy
151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
155 * OS/FW agnostic memset
158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
161 #if defined(__cplusplus)
166 * OS/FW agnostic udelay
169 #define dmub_udelay(microseconds) udelay(microseconds)
172 #pragma pack(push, 1)
173 #define ABM_NUM_OF_ACE_SEGMENTS 5
178 * @abm_enabled: Indicates if ABM is enabled.
180 unsigned int abm_enabled : 1;
183 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
185 unsigned int disable_abm_requested : 1;
188 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled
191 unsigned int disable_abm_immediately : 1;
194 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
195 * to be disabled immediately and keep gain.
197 unsigned int disable_abm_immediate_keep_gain : 1;
200 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
202 unsigned int fractional_pwm : 1;
205 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
206 * of user backlight level.
208 unsigned int abm_gradual_bl_change : 1;
214 struct abm_save_restore {
216 * @flags: Misc. ABM flags.
218 union abm_flags flags;
221 * @pause: true: pause ABM and get state
222 * false: unpause ABM after setting state
227 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
229 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
232 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
234 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
237 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
239 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
243 * @knee_threshold: Current x-position of ACE knee (u0.16).
245 uint32_t knee_threshold;
247 * @current_gain: Current backlight reduction (u16.16).
249 uint32_t current_gain;
251 * @curr_bl_level: Current actual backlight level converging to target backlight level.
253 uint16_t curr_bl_level;
256 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
258 uint16_t curr_user_bl_level;
263 * union dmub_addr - DMUB physical/virtual 64-bit address.
267 uint32_t low_part; /**< Lower 32 bits */
268 uint32_t high_part; /**< Upper 32 bits */
269 } u; /*<< Low/high bit access */
270 uint64_t quad_part; /*<< 64 bit address */
275 * Dirty rect definition.
279 * Dirty rect x offset.
284 * Dirty rect y offset.
300 * Flags that can be set by driver to change some PSR behaviour.
302 union dmub_psr_debug_flags {
308 * Enable visual confirm in FW.
310 uint32_t visual_confirm : 1;
313 * Force all selective updates to bw full frame updates.
315 uint32_t force_full_frame_update : 1;
318 * Use HW Lock Mgr object to do HW locking in FW.
320 uint32_t use_hw_lock_mgr : 1;
323 * Use TPS3 signal when restore main link.
325 uint32_t force_wakeup_by_tps3 : 1;
328 * Back to back flip, therefore cannot power down PHY
330 uint32_t back_to_back_flip : 1;
335 * Union for debug flags.
341 * Flags that can be set by driver to change some Replay behaviour.
343 union replay_debug_flags {
346 * Enable visual confirm in FW.
348 uint32_t visual_confirm : 1;
351 * @skip_crc: Set if need to skip CRC.
353 uint32_t skip_crc : 1;
356 * @force_link_power_on: Force disable ALPM control
358 uint32_t force_link_power_on : 1;
361 * @force_phy_power_on: Force phy power on
363 uint32_t force_phy_power_on : 1;
366 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
368 uint32_t timing_resync_disabled : 1;
371 * @skip_crtc_disabled: CRTC disable skipped
373 uint32_t skip_crtc_disabled : 1;
376 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
378 uint32_t force_defer_one_frame_update : 1;
380 * @disable_delay_alpm_on: Force disable delay alpm on
382 uint32_t disable_delay_alpm_on : 1;
384 * @disable_desync_error_check: Force disable desync error check
386 uint32_t disable_desync_error_check : 1;
388 * @disable_desync_error_check: Force disable desync error check
390 uint32_t disable_dmub_save_restore : 1;
392 uint32_t reserved : 22;
398 union replay_hw_flags {
401 * @allow_alpm_fw_standby_mode: To indicate whether the
402 * ALPM FW standby mode is allowed
404 uint32_t allow_alpm_fw_standby_mode : 1;
407 * @dsc_enable_status: DSC enable status in driver
409 uint32_t dsc_enable_status : 1;
412 * @fec_enable_status: receive fec enable/disable status from driver
414 uint32_t fec_enable_status : 1;
417 * @smu_optimizations_en: SMU power optimization.
418 * Only when active display is Replay capable and display enters Replay.
419 * Trigger interrupt to SMU to powerup/down.
421 uint32_t smu_optimizations_en : 1;
424 * @otg_powered_down: Flag to keep track of OTG power state.
426 uint32_t otg_powered_down : 1;
429 * @phy_power_state: Indicates current phy power state
431 uint32_t phy_power_state : 1;
434 * @link_power_state: Indicates current link power state
436 uint32_t link_power_state : 1;
438 * Use TPS3 signal when restore main link.
440 uint32_t force_wakeup_by_tps3 : 1;
447 * DMUB visual confirm color
449 struct dmub_feature_caps {
451 * Max PSR version supported by FW.
454 uint8_t fw_assisted_mclk_switch;
456 uint8_t subvp_psr_support;
460 struct dmub_visual_confirm_color {
462 * Maximum 10 bits color value
470 #if defined(__cplusplus)
474 //==============================================================================
475 //</DMUB_TYPES>=================================================================
476 //==============================================================================
477 //< DMUB_META>==================================================================
478 //==============================================================================
479 #pragma pack(push, 1)
481 /* Magic value for identifying dmub_fw_meta_info */
482 #define DMUB_FW_META_MAGIC 0x444D5542
484 /* Offset from the end of the file to the dmub_fw_meta_info */
485 #define DMUB_FW_META_OFFSET 0x24
488 * struct dmub_fw_meta_info - metadata associated with fw binary
490 * NOTE: This should be considered a stable API. Fields should
491 * not be repurposed or reordered. New fields should be
492 * added instead to extend the structure.
494 * @magic_value: magic value identifying DMUB firmware meta info
495 * @fw_region_size: size of the firmware state region
496 * @trace_buffer_size: size of the tracebuffer region
497 * @fw_version: the firmware version information
498 * @dal_fw: 1 if the firmware is DAL
500 struct dmub_fw_meta_info {
501 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
502 uint32_t fw_region_size; /**< size of the firmware state region */
503 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
504 uint32_t fw_version; /**< the firmware version information */
505 uint8_t dal_fw; /**< 1 if the firmware is DAL */
506 uint8_t reserved[3]; /**< padding bits */
510 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
513 struct dmub_fw_meta_info info; /**< metadata info */
514 uint8_t reserved[64]; /**< padding bits */
519 //==============================================================================
520 //< DMUB Trace Buffer>================================================================
521 //==============================================================================
523 * dmub_trace_code_t - firmware trace code, 32-bits
525 typedef uint32_t dmub_trace_code_t;
528 * struct dmcub_trace_buf_entry - Firmware trace entry
530 struct dmcub_trace_buf_entry {
531 dmub_trace_code_t trace_code; /**< trace code for the event */
532 uint32_t tick_count; /**< the tick count at time of trace */
533 uint32_t param0; /**< trace defined parameter 0 */
534 uint32_t param1; /**< trace defined parameter 1 */
537 //==============================================================================
538 //< DMUB_STATUS>================================================================
539 //==============================================================================
542 * DMCUB scratch registers can be used to determine firmware status.
543 * Current scratch register usage is as follows:
545 * SCRATCH0: FW Boot Status register
546 * SCRATCH5: LVTMA Status Register
547 * SCRATCH15: FW Boot Options register
551 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
553 union dmub_fw_boot_status {
555 uint32_t dal_fw : 1; /**< 1 if DAL FW */
556 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
557 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
558 uint32_t restore_required : 1; /**< 1 if driver should call restore */
559 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
560 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
561 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
562 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
563 } bits; /**< status bits */
564 uint32_t all; /**< 32-bit access to status bits */
568 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
570 enum dmub_fw_boot_status_bit {
571 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
572 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
573 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
574 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
575 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
576 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
577 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
578 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
581 /* Register bit definition for SCRATCH5 */
582 union dmub_lvtma_status {
586 uint32_t reserved : 30;
591 enum dmub_lvtma_status_bit {
592 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
593 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
596 enum dmub_ips_disable_type {
597 DMUB_IPS_DISABLE_IPS1 = 1,
598 DMUB_IPS_DISABLE_IPS2 = 2,
599 DMUB_IPS_DISABLE_IPS2_Z10 = 3,
603 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
605 union dmub_fw_boot_options {
607 uint32_t pemu_env : 1; /**< 1 if PEMU */
608 uint32_t fpga_env : 1; /**< 1 if FPGA */
609 uint32_t optimized_init : 1; /**< 1 if optimized init */
610 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
611 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
612 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
613 uint32_t z10_disable: 1; /**< 1 to disable z10 */
614 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
615 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
616 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
617 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */
618 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
619 uint32_t power_optimization: 1;
620 uint32_t diag_env: 1; /* 1 if diagnostic environment */
621 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
622 uint32_t usb4_cm_version: 1; /**< 1 CM support */
623 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
624 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */
625 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
626 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
627 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
628 uint32_t ips_disable: 2; /* options to disable ips support*/
629 uint32_t reserved : 10; /**< reserved */
630 } bits; /**< boot bits */
631 uint32_t all; /**< 32-bit access to bits */
634 enum dmub_fw_boot_options_bit {
635 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
636 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
637 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
640 //==============================================================================
641 //</DMUB_STATUS>================================================================
642 //==============================================================================
643 //< DMUB_VBIOS>=================================================================
644 //==============================================================================
647 * enum dmub_cmd_vbios_type - VBIOS commands.
649 * Command IDs should be treated as stable ABI.
650 * Do not reuse or modify IDs.
652 enum dmub_cmd_vbios_type {
654 * Configures the DIG encoder.
656 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
660 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
662 * Sets the pixel clock/symbol clock.
664 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
666 * Enables or disables power gating.
668 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
670 * Controls embedded panels.
672 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
674 * Query DP alt status on a transmitter.
676 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
678 * Controls domain power gating
680 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
683 //==============================================================================
684 //</DMUB_VBIOS>=================================================================
685 //==============================================================================
686 //< DMUB_GPINT>=================================================================
687 //==============================================================================
690 * The shifts and masks below may alternatively be used to format and read
691 * the command register bits.
694 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
695 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
697 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
698 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
700 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
701 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
708 * Return response for DMUB_GPINT__STOP_FW command.
710 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
713 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
715 union dmub_gpint_data_register {
717 uint32_t param : 16; /**< 16-bit parameter */
718 uint32_t command_code : 12; /**< GPINT command */
719 uint32_t status : 4; /**< Command status bit */
720 } bits; /**< GPINT bit access */
721 uint32_t all; /**< GPINT 32-bit access */
725 * enum dmub_gpint_command - GPINT command to DMCUB FW
727 * Command IDs should be treated as stable ABI.
728 * Do not reuse or modify IDs.
730 enum dmub_gpint_command {
732 * Invalid command, ignored.
734 DMUB_GPINT__INVALID_COMMAND = 0,
736 * DESC: Queries the firmware version.
737 * RETURN: Firmware version.
739 DMUB_GPINT__GET_FW_VERSION = 1,
741 * DESC: Halts the firmware.
742 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
744 DMUB_GPINT__STOP_FW = 2,
746 * DESC: Get PSR state from FW.
747 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
749 DMUB_GPINT__GET_PSR_STATE = 7,
751 * DESC: Notifies DMCUB of the currently active streams.
752 * ARGS: Stream mask, 1 bit per active stream index.
754 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
756 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
757 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
758 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
759 * RETURN: PSR residency in milli-percent.
761 DMUB_GPINT__PSR_RESIDENCY = 9,
764 * DESC: Get REPLAY state from FW.
765 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
767 DMUB_GPINT__GET_REPLAY_STATE = 13,
770 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
771 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
772 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
773 * RETURN: REPLAY residency in milli-percent.
775 DMUB_GPINT__REPLAY_RESIDENCY = 14,
779 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
781 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
783 * DESC: Updates the trace buffer lower 32-bit mask.
785 * RETURN: Lower 32-bit mask.
787 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
789 * DESC: Updates the trace buffer lower 32-bit mask.
791 * RETURN: Lower 32-bit mask.
793 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
795 * DESC: Updates the trace buffer mask bi0~bit15.
797 * RETURN: Lower 32-bit mask.
799 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
803 * INBOX0 generic command definition
805 union dmub_inbox0_cmd_common {
807 uint32_t command_code: 8; /**< INBOX0 command code */
808 uint32_t param: 24; /**< 24-bit parameter */
814 * INBOX0 hw_lock command definition
816 union dmub_inbox0_cmd_lock_hw {
818 uint32_t command_code: 8;
820 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
821 uint32_t hw_lock_client: 2;
823 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
824 uint32_t otg_inst: 3;
825 uint32_t opp_inst: 3;
826 uint32_t dig_inst: 3;
828 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
829 uint32_t lock_pipe: 1;
830 uint32_t lock_cursor: 1;
831 uint32_t lock_dig: 1;
832 uint32_t triple_buffer_lock: 1;
834 uint32_t lock: 1; /**< Lock */
835 uint32_t should_release: 1; /**< Release */
836 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
841 union dmub_inbox0_data_register {
842 union dmub_inbox0_cmd_common inbox0_cmd_common;
843 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
846 enum dmub_inbox0_command {
848 * DESC: Invalid command, ignored.
850 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
852 * DESC: Notification to acquire/release HW lock
855 DMUB_INBOX0_CMD__HW_LOCK = 1,
857 //==============================================================================
858 //</DMUB_GPINT>=================================================================
859 //==============================================================================
860 //< DMUB_CMD>===================================================================
861 //==============================================================================
864 * Size in bytes of each DMUB command.
866 #define DMUB_RB_CMD_SIZE 64
869 * Maximum number of items in the DMUB ringbuffer.
871 #define DMUB_RB_MAX_ENTRY 128
874 * Ringbuffer size in bytes.
876 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
879 * REG_SET mask for reg offload.
881 #define REG_SET_MASK 0xFFFF
884 * enum dmub_cmd_type - DMUB inbox command.
886 * Command IDs should be treated as stable ABI.
887 * Do not reuse or modify IDs.
895 * Read modify write register sequence offload.
897 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
899 * Field update register sequence offload.
901 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
903 * Burst write sequence offload.
905 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
907 * Reg wait sequence offload.
909 DMUB_CMD__REG_REG_WAIT = 4,
911 * Workaround to avoid HUBP underflow during NV12 playback.
913 DMUB_CMD__PLAT_54186_WA = 5,
915 * Command type used to query FW feature caps.
917 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
919 * Command type used to get visual confirm color.
921 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
923 * Command type used for all PSR commands.
927 * Command type used for all MALL commands.
931 * Command type used for all ABM commands.
935 * Command type used to update dirty rects in FW.
937 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
939 * Command type used to update cursor info in FW.
941 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
943 * Command type used for HW locking in FW.
945 DMUB_CMD__HW_LOCK = 69,
947 * Command type used to access DP AUX.
949 DMUB_CMD__DP_AUX_ACCESS = 70,
951 * Command type used for OUTBOX1 notification enable
953 DMUB_CMD__OUTBOX1_ENABLE = 71,
956 * Command type used for all idle optimization commands.
958 DMUB_CMD__IDLE_OPT = 72,
960 * Command type used for all clock manager commands.
962 DMUB_CMD__CLK_MGR = 73,
964 * Command type used for all panel control commands.
966 DMUB_CMD__PANEL_CNTL = 74,
968 * Command type used for <TODO:description>
970 DMUB_CMD__CAB_FOR_SS = 75,
972 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
975 * Command type used for interfacing with DPIA.
979 * Command type used for EDID CEA parsing
981 DMUB_CMD__EDID_CEA = 79,
983 * Command type used for getting usbc cable ID
985 DMUB_CMD_GET_USBC_CABLE_ID = 81,
987 * Command type used to query HPD state.
989 DMUB_CMD__QUERY_HPD_STATE = 82,
991 * Command type used for all VBIOS interface commands.
995 * Command type used for all REPLAY commands.
997 DMUB_CMD__REPLAY = 83,
1000 * Command type used for all SECURE_DISPLAY commands.
1002 DMUB_CMD__SECURE_DISPLAY = 85,
1005 * Command type used to set DPIA HPD interrupt state
1007 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1009 DMUB_CMD__VBIOS = 128,
1013 * enum dmub_out_cmd_type - DMUB outbox commands.
1015 enum dmub_out_cmd_type {
1017 * Invalid outbox command, ignored.
1019 DMUB_OUT_CMD__NULL = 0,
1021 * Command type used for DP AUX Reply data notification
1023 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1025 * Command type used for DP HPD event notification
1027 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1029 * Command type used for SET_CONFIG Reply notification
1031 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1033 * Command type used for USB4 DPIA notification
1035 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1038 /* DMUB_CMD__DPIA command sub-types. */
1039 enum dmub_cmd_dpia_type {
1040 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1041 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
1042 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1045 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1046 enum dmub_cmd_dpia_notification_type {
1047 DPIA_NOTIFY__BW_ALLOCATION = 0,
1050 #pragma pack(push, 1)
1053 * struct dmub_cmd_header - Common command header fields.
1055 struct dmub_cmd_header {
1056 unsigned int type : 8; /**< command type */
1057 unsigned int sub_type : 8; /**< command sub type */
1058 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1059 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1060 unsigned int reserved0 : 6; /**< reserved bits */
1061 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1062 unsigned int reserved1 : 2; /**< reserved bits */
1066 * struct dmub_cmd_read_modify_write_sequence - Read modify write
1068 * 60 payload bytes can hold up to 5 sets of read modify writes,
1069 * each take 3 dwords.
1071 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1073 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
1074 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1076 struct dmub_cmd_read_modify_write_sequence {
1077 uint32_t addr; /**< register address */
1078 uint32_t modify_mask; /**< modify mask */
1079 uint32_t modify_value; /**< modify value */
1083 * Maximum number of ops in read modify write sequence.
1085 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1088 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1090 struct dmub_rb_cmd_read_modify_write {
1091 struct dmub_cmd_header header; /**< command header */
1093 * Read modify write sequence.
1095 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
1099 * Update a register with specified masks and values sequeunce
1101 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
1103 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
1107 * 1. auto-increment register where additional read would update pointer and produce wrong result
1108 * 2. toggle a bit without read in the middle
1111 struct dmub_cmd_reg_field_update_sequence {
1112 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
1113 uint32_t modify_value; /**< value to update with */
1117 * Maximum number of ops in field update sequence.
1119 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
1122 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
1124 struct dmub_rb_cmd_reg_field_update_sequence {
1125 struct dmub_cmd_header header; /**< command header */
1126 uint32_t addr; /**< register address */
1128 * Field update sequence.
1130 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
1135 * Maximum number of burst write values.
1137 #define DMUB_BURST_WRITE_VALUES__MAX 14
1140 * struct dmub_rb_cmd_burst_write - Burst write
1142 * support use case such as writing out LUTs.
1144 * 60 payload bytes can hold up to 14 values to write to given address
1146 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
1148 struct dmub_rb_cmd_burst_write {
1149 struct dmub_cmd_header header; /**< command header */
1150 uint32_t addr; /**< register start address */
1152 * Burst write register values.
1154 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
1158 * struct dmub_rb_cmd_common - Common command header
1160 struct dmub_rb_cmd_common {
1161 struct dmub_cmd_header header; /**< command header */
1163 * Padding to RB_CMD_SIZE
1165 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
1169 * struct dmub_cmd_reg_wait_data - Register wait data
1171 struct dmub_cmd_reg_wait_data {
1172 uint32_t addr; /**< Register address */
1173 uint32_t mask; /**< Mask for register bits */
1174 uint32_t condition_field_value; /**< Value to wait for */
1175 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
1179 * struct dmub_rb_cmd_reg_wait - Register wait command
1181 struct dmub_rb_cmd_reg_wait {
1182 struct dmub_cmd_header header; /**< Command header */
1183 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
1187 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
1189 * Reprograms surface parameters to avoid underflow.
1191 struct dmub_cmd_PLAT_54186_wa {
1192 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
1193 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
1194 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
1195 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
1196 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
1198 uint8_t hubp_inst : 4; /**< HUBP instance */
1199 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
1200 uint8_t immediate :1; /**< Immediate flip */
1201 uint8_t vmid : 4; /**< VMID */
1202 uint8_t grph_stereo : 1; /**< 1 if stereo */
1203 uint32_t reserved : 21; /**< Reserved */
1204 } flip_params; /**< Pageflip parameters */
1205 uint32_t reserved[9]; /**< Reserved bits */
1209 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
1211 struct dmub_rb_cmd_PLAT_54186_wa {
1212 struct dmub_cmd_header header; /**< Command header */
1213 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
1217 * struct dmub_rb_cmd_mall - MALL command data.
1219 struct dmub_rb_cmd_mall {
1220 struct dmub_cmd_header header; /**< Common command header */
1221 union dmub_addr cursor_copy_src; /**< Cursor copy address */
1222 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
1223 uint32_t tmr_delay; /**< Timer delay */
1224 uint32_t tmr_scale; /**< Timer scale */
1225 uint16_t cursor_width; /**< Cursor width in pixels */
1226 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
1227 uint16_t cursor_height; /**< Cursor height in pixels */
1228 uint8_t cursor_bpp; /**< Cursor bits per pixel */
1229 uint8_t debug_bits; /**< Debug bits */
1231 uint8_t reserved1; /**< Reserved bits */
1232 uint8_t reserved2; /**< Reserved bits */
1236 * enum dmub_cmd_cab_type - CAB command data.
1238 enum dmub_cmd_cab_type {
1240 * No idle optimizations (i.e. no CAB)
1242 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
1244 * No DCN requests for memory
1246 DMUB_CMD__CAB_NO_DCN_REQ = 1,
1248 * Fit surfaces in CAB (i.e. CAB enable)
1250 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
1254 * struct dmub_rb_cmd_cab - CAB command data.
1256 struct dmub_rb_cmd_cab_for_ss {
1257 struct dmub_cmd_header header;
1258 uint8_t cab_alloc_ways; /* total number of ways */
1259 uint8_t debug_bits; /* debug bits */
1263 * Enum for indicating which MCLK switch mode per pipe
1265 enum mclk_switch_mode {
1272 /* Per pipe struct which stores the MCLK switch mode
1273 * data to be sent to DMUB.
1274 * Named "v2" for now -- once FPO and SUBVP are fully merged
1275 * the type name can be updated
1277 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
1280 uint32_t pix_clk_100hz;
1281 uint16_t main_vblank_start;
1282 uint16_t main_vblank_end;
1283 uint16_t mall_region_lines;
1284 uint16_t prefetch_lines;
1285 uint16_t prefetch_to_mall_start_lines;
1286 uint16_t processing_delay_lines;
1287 uint16_t htotal; // required to calculate line time for multi-display cases
1289 uint8_t main_pipe_index;
1290 uint8_t phantom_pipe_index;
1291 /* Since the microschedule is calculated in terms of OTG lines,
1292 * include any scaling factors to make sure when we get accurate
1293 * conversion when programming MALL_START_LINE (which is in terms
1294 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1295 * is 1/2 (numerator = 1, denominator = 2).
1297 uint8_t scale_factor_numerator;
1298 uint8_t scale_factor_denominator;
1300 uint8_t main_split_pipe_index;
1301 uint8_t phantom_split_pipe_index;
1305 uint32_t pix_clk_100hz;
1306 uint16_t vblank_start;
1307 uint16_t vblank_end;
1308 uint16_t vstartup_start;
1311 uint8_t vblank_pipe_index;
1315 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
1316 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
1317 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
1318 uint8_t use_ramping; // Use ramping or not
1319 uint8_t drr_vblank_start_margin;
1320 } drr_info; // DRR considered as part of SubVP + VBLANK case
1324 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
1325 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1326 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1328 uint8_t mode; // enum mclk_switch_mode
1332 * Config data for Sub-VP and FPO
1333 * Named "v2" for now -- once FPO and SUBVP are fully merged
1334 * the type name can be updated
1336 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1337 uint16_t watermark_a_cache;
1338 uint8_t vertical_int_margin_us;
1339 uint8_t pstate_allow_width_us;
1340 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1344 * DMUB rb command definition for Sub-VP and FPO
1345 * Named "v2" for now -- once FPO and SUBVP are fully merged
1346 * the type name can be updated
1348 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1349 struct dmub_cmd_header header;
1350 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1354 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1356 enum dmub_cmd_idle_opt_type {
1358 * DCN hardware restore.
1360 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1363 * DCN hardware save.
1365 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
1368 * DCN hardware notify idle.
1370 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2
1374 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1376 struct dmub_rb_cmd_idle_opt_dcn_restore {
1377 struct dmub_cmd_header header; /**< header */
1381 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1383 struct dmub_dcn_notify_idle_cntl_data {
1384 uint8_t driver_idle;
1389 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1391 struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
1392 struct dmub_cmd_header header; /**< header */
1393 struct dmub_dcn_notify_idle_cntl_data cntl_data;
1397 * struct dmub_clocks - Clock update notification.
1399 struct dmub_clocks {
1400 uint32_t dispclk_khz; /**< dispclk kHz */
1401 uint32_t dppclk_khz; /**< dppclk kHz */
1402 uint32_t dcfclk_khz; /**< dcfclk kHz */
1403 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1407 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1409 enum dmub_cmd_clk_mgr_type {
1411 * Notify DMCUB of clock update.
1413 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1417 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1419 struct dmub_rb_cmd_clk_mgr_notify_clocks {
1420 struct dmub_cmd_header header; /**< header */
1421 struct dmub_clocks clocks; /**< clock data */
1425 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1427 struct dmub_cmd_digx_encoder_control_data {
1428 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
1432 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1434 struct dmub_rb_cmd_digx_encoder_control {
1435 struct dmub_cmd_header header; /**< header */
1436 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
1440 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1442 struct dmub_cmd_set_pixel_clock_data {
1443 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
1447 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1449 struct dmub_rb_cmd_set_pixel_clock {
1450 struct dmub_cmd_header header; /**< header */
1451 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
1455 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
1457 struct dmub_cmd_enable_disp_power_gating_data {
1458 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
1462 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
1464 struct dmub_rb_cmd_enable_disp_power_gating {
1465 struct dmub_cmd_header header; /**< header */
1466 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
1470 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
1472 struct dmub_dig_transmitter_control_data_v1_7 {
1473 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
1474 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
1476 uint8_t digmode; /**< enum atom_encode_mode_def */
1477 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
1479 uint8_t lanenum; /**< Number of lanes */
1481 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
1483 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
1484 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
1485 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
1486 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
1487 uint8_t reserved1; /**< For future use */
1488 uint8_t reserved2[3]; /**< For future use */
1489 uint32_t reserved3[11]; /**< For future use */
1493 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
1495 union dmub_cmd_dig1_transmitter_control_data {
1496 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
1497 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
1501 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
1503 struct dmub_rb_cmd_dig1_transmitter_control {
1504 struct dmub_cmd_header header; /**< header */
1505 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
1509 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
1511 struct dmub_rb_cmd_domain_control_data {
1512 uint8_t inst : 6; /**< DOMAIN instance to control */
1513 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
1514 uint8_t reserved[3]; /**< Reserved for future use */
1518 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
1520 struct dmub_rb_cmd_domain_control {
1521 struct dmub_cmd_header header; /**< header */
1522 struct dmub_rb_cmd_domain_control_data data; /**< payload */
1526 * DPIA tunnel command parameters.
1528 struct dmub_cmd_dig_dpia_control_data {
1529 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
1530 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
1532 uint8_t digmode; /** enum atom_encode_mode_def */
1533 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
1535 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
1536 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
1537 uint8_t hpdsel; /** =0: HPD is not assigned */
1538 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
1539 uint8_t dpia_id; /** Index of DPIA */
1540 uint8_t fec_rdy : 1;
1541 uint8_t reserved : 7;
1546 * DMUB command for DPIA tunnel control.
1548 struct dmub_rb_cmd_dig1_dpia_control {
1549 struct dmub_cmd_header header;
1550 struct dmub_cmd_dig_dpia_control_data dpia_control;
1554 * SET_CONFIG Command Payload
1556 struct set_config_cmd_payload {
1557 uint8_t msg_type; /* set config message type */
1558 uint8_t msg_data; /* set config message data */
1562 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
1564 struct dmub_cmd_set_config_control_data {
1565 struct set_config_cmd_payload cmd_pkt;
1566 uint8_t instance; /* DPIA instance */
1567 uint8_t immed_status; /* Immediate status returned in case of error */
1571 * DMUB command structure for SET_CONFIG command.
1573 struct dmub_rb_cmd_set_config_access {
1574 struct dmub_cmd_header header; /* header */
1575 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
1579 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
1581 struct dmub_cmd_mst_alloc_slots_control_data {
1582 uint8_t mst_alloc_slots; /* mst slots to be allotted */
1583 uint8_t instance; /* DPIA instance */
1584 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
1585 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
1589 * DMUB command structure for SET_ command.
1591 struct dmub_rb_cmd_set_mst_alloc_slots {
1592 struct dmub_cmd_header header; /* header */
1593 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
1597 * DMUB command structure for DPIA HPD int enable control.
1599 struct dmub_rb_cmd_dpia_hpd_int_enable {
1600 struct dmub_cmd_header header; /* header */
1601 uint32_t enable; /* dpia hpd interrupt enable */
1605 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1607 struct dmub_rb_cmd_dpphy_init {
1608 struct dmub_cmd_header header; /**< header */
1609 uint8_t reserved[60]; /**< reserved bits */
1613 * enum dp_aux_request_action - DP AUX request command listing.
1615 * 4 AUX request command bits are shifted to high nibble.
1617 enum dp_aux_request_action {
1618 /** I2C-over-AUX write request */
1619 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
1620 /** I2C-over-AUX read request */
1621 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
1622 /** I2C-over-AUX write status request */
1623 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
1624 /** I2C-over-AUX write request with MOT=1 */
1625 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
1626 /** I2C-over-AUX read request with MOT=1 */
1627 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
1628 /** I2C-over-AUX write status request with MOT=1 */
1629 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
1630 /** Native AUX write request */
1631 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
1632 /** Native AUX read request */
1633 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1637 * enum aux_return_code_type - DP AUX process return code listing.
1639 enum aux_return_code_type {
1640 /** AUX process succeeded */
1641 AUX_RET_SUCCESS = 0,
1642 /** AUX process failed with unknown reason */
1643 AUX_RET_ERROR_UNKNOWN,
1644 /** AUX process completed with invalid reply */
1645 AUX_RET_ERROR_INVALID_REPLY,
1646 /** AUX process timed out */
1647 AUX_RET_ERROR_TIMEOUT,
1648 /** HPD was low during AUX process */
1649 AUX_RET_ERROR_HPD_DISCON,
1650 /** Failed to acquire AUX engine */
1651 AUX_RET_ERROR_ENGINE_ACQUIRE,
1652 /** AUX request not supported */
1653 AUX_RET_ERROR_INVALID_OPERATION,
1654 /** AUX process not available */
1655 AUX_RET_ERROR_PROTOCOL_ERROR,
1659 * enum aux_channel_type - DP AUX channel type listing.
1661 enum aux_channel_type {
1662 /** AUX thru Legacy DP AUX */
1663 AUX_CHANNEL_LEGACY_DDC,
1664 /** AUX thru DPIA DP tunneling */
1669 * struct aux_transaction_parameters - DP AUX request transaction data
1671 struct aux_transaction_parameters {
1672 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1673 uint8_t action; /**< enum dp_aux_request_action */
1674 uint8_t length; /**< DP AUX request data length */
1675 uint8_t reserved; /**< For future use */
1676 uint32_t address; /**< DP AUX address */
1677 uint8_t data[16]; /**< DP AUX write data */
1681 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1683 struct dmub_cmd_dp_aux_control_data {
1684 uint8_t instance; /**< AUX instance or DPIA instance */
1685 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1686 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1687 uint8_t reserved0; /**< For future use */
1688 uint16_t timeout; /**< timeout time in us */
1689 uint16_t reserved1; /**< For future use */
1690 enum aux_channel_type type; /**< enum aux_channel_type */
1691 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1695 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1697 struct dmub_rb_cmd_dp_aux_access {
1701 struct dmub_cmd_header header;
1703 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1705 struct dmub_cmd_dp_aux_control_data aux_control;
1709 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1711 struct dmub_rb_cmd_outbox1_enable {
1715 struct dmub_cmd_header header;
1717 * enable: 0x0 -> disable outbox1 notification (default value)
1718 * 0x1 -> enable outbox1 notification
1723 /* DP AUX Reply command - OutBox Cmd */
1725 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1727 struct aux_reply_data {
1733 * Aux reply data length (max: 16 bytes)
1747 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1749 struct aux_reply_control_data {
1751 * Reserved for future use
1759 * Aux transaction result: definition in enum aux_return_code_type
1769 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1771 struct dmub_rb_cmd_dp_aux_reply {
1775 struct dmub_cmd_header header;
1777 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1779 struct aux_reply_control_data control;
1781 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1783 struct aux_reply_data reply_data;
1786 /* DP HPD Notify command - OutBox Cmd */
1796 * DP HPD short pulse
1804 enum dp_hpd_status {
1810 * DP_HPD status high
1816 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1818 struct dp_hpd_data {
1828 * HPD status: only for type: DP_HPD to indicate status
1838 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1840 struct dmub_rb_cmd_dp_hpd_notify {
1844 struct dmub_cmd_header header;
1846 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1848 struct dp_hpd_data hpd_data;
1852 * Definition of a SET_CONFIG reply from DPOA.
1854 enum set_config_status {
1855 SET_CONFIG_PENDING = 0,
1856 SET_CONFIG_ACK_RECEIVED,
1857 SET_CONFIG_RX_TIMEOUT,
1858 SET_CONFIG_UNKNOWN_ERROR,
1862 * Definition of a set_config reply
1864 struct set_config_reply_control_data {
1865 uint8_t instance; /* DPIA Instance */
1866 uint8_t status; /* Set Config reply */
1867 uint16_t pad; /* Alignment */
1871 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
1873 struct dmub_rb_cmd_dp_set_config_reply {
1874 struct dmub_cmd_header header;
1875 struct set_config_reply_control_data set_config_reply_control;
1879 * Definition of a DPIA notification header
1881 struct dpia_notification_header {
1882 uint8_t instance; /**< DPIA Instance */
1883 uint8_t reserved[3];
1884 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
1888 * Definition of the common data struct of DPIA notification
1890 struct dpia_notification_common {
1891 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
1892 - sizeof(struct dpia_notification_header)];
1896 * Definition of a DPIA notification data
1898 struct dpia_bw_allocation_notify_data {
1901 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
1902 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
1903 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
1904 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
1905 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
1906 uint16_t reserved: 11; /**< Reserved */
1912 uint8_t cm_id; /**< CM ID */
1913 uint8_t group_id; /**< Group ID */
1914 uint8_t granularity; /**< BW Allocation Granularity */
1915 uint8_t estimated_bw; /**< Estimated_BW */
1916 uint8_t allocated_bw; /**< Allocated_BW */
1921 * union dpia_notify_data_type - DPIA Notification in Outbox command
1923 union dpia_notification_data {
1925 * DPIA Notification for common data struct
1927 struct dpia_notification_common common_data;
1930 * DPIA Notification for DP BW Allocation support
1932 struct dpia_bw_allocation_notify_data dpia_bw_alloc;
1936 * Definition of a DPIA notification payload
1938 struct dpia_notification_payload {
1939 struct dpia_notification_header header;
1940 union dpia_notification_data data; /**< DPIA notification payload data */
1944 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
1946 struct dmub_rb_cmd_dpia_notification {
1947 struct dmub_cmd_header header; /**< DPIA notification header */
1948 struct dpia_notification_payload payload; /**< DPIA notification payload */
1952 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1954 struct dmub_cmd_hpd_state_query_data {
1955 uint8_t instance; /**< HPD instance or DPIA instance */
1956 uint8_t result; /**< For returning HPD state */
1957 uint16_t pad; /** < Alignment */
1958 enum aux_channel_type ch_type; /**< enum aux_channel_type */
1959 enum aux_return_code_type status; /**< for returning the status of command */
1963 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
1965 struct dmub_rb_cmd_query_hpd_state {
1969 struct dmub_cmd_header header;
1971 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1973 struct dmub_cmd_hpd_state_query_data data;
1977 * Command IDs should be treated as stable ABI.
1978 * Do not reuse or modify IDs.
1982 * PSR command sub-types.
1984 enum dmub_cmd_psr_type {
1986 * Set PSR version support.
1988 DMUB_CMD__PSR_SET_VERSION = 0,
1990 * Copy driver-calculated parameters to PSR state.
1992 DMUB_CMD__PSR_COPY_SETTINGS = 1,
1996 DMUB_CMD__PSR_ENABLE = 2,
2001 DMUB_CMD__PSR_DISABLE = 3,
2005 * PSR level is a 16-bit value dicated by driver that
2006 * will enable/disable different functionality.
2008 DMUB_CMD__PSR_SET_LEVEL = 4,
2011 * Forces PSR enabled until an explicit PSR disable call.
2013 DMUB_CMD__PSR_FORCE_STATIC = 5,
2015 * Set vtotal in psr active for FreeSync PSR.
2017 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
2019 * Set PSR power option
2021 DMUB_CMD__SET_PSR_POWER_OPT = 7,
2024 enum dmub_cmd_fams_type {
2025 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
2026 DMUB_CMD__FAMS_DRR_UPDATE = 1,
2027 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
2029 * For SubVP set manual trigger in FW because it
2030 * triggers DRR_UPDATE_PENDING which SubVP relies
2031 * on (for any SubVP cases that use a DRR display)
2033 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
2047 PSR_VERSION_SU_1 = 1,
2049 * PSR not supported.
2051 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
2055 * enum dmub_cmd_mall_type - MALL commands
2057 enum dmub_cmd_mall_type {
2059 * Allows display refresh from MALL.
2061 DMUB_CMD__MALL_ACTION_ALLOW = 0,
2063 * Disallows display refresh from MALL.
2065 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
2067 * Cursor copy for MALL.
2069 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
2071 * Controls DF requests.
2073 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
2077 * PHY Link rate for DP.
2079 enum phy_link_rate {
2083 PHY_RATE_UNKNOWN = 0,
2085 * Rate_1 (RBR) - 1.62 Gbps/Lane
2089 * Rate_2 - 2.16 Gbps/Lane
2093 * Rate_3 - 2.43 Gbps/Lane
2097 * Rate_4 (HBR) - 2.70 Gbps/Lane
2101 * Rate_5 (RBR2)- 3.24 Gbps/Lane
2105 * Rate_6 - 4.32 Gbps/Lane
2109 * Rate_7 (HBR2)- 5.40 Gbps/Lane
2113 * Rate_8 (HBR3)- 8.10 Gbps/Lane
2117 * UHBR10 - 10.0 Gbps/Lane
2121 * UHBR13.5 - 13.5 Gbps/Lane
2125 * UHBR10 - 20.0 Gbps/Lane
2131 * enum dmub_phy_fsm_state - PHY FSM states.
2132 * PHY FSM state to transit to during PSR enable/disable.
2134 enum dmub_phy_fsm_state {
2135 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
2137 DMUB_PHY_FSM_RESET_RELEASED,
2138 DMUB_PHY_FSM_SRAM_LOAD_DONE,
2139 DMUB_PHY_FSM_INITIALIZED,
2140 DMUB_PHY_FSM_CALIBRATED,
2141 DMUB_PHY_FSM_CALIBRATED_LP,
2142 DMUB_PHY_FSM_CALIBRATED_PG,
2143 DMUB_PHY_FSM_POWER_DOWN,
2144 DMUB_PHY_FSM_PLL_EN,
2146 DMUB_PHY_FSM_FAST_LP,
2147 DMUB_PHY_FSM_P2_PLL_OFF_CPM,
2148 DMUB_PHY_FSM_P2_PLL_OFF_PG,
2149 DMUB_PHY_FSM_P2_PLL_OFF,
2150 DMUB_PHY_FSM_P2_PLL_ON,
2154 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2156 struct dmub_cmd_psr_copy_settings_data {
2158 * Flags that can be set by driver to change some PSR behaviour.
2160 union dmub_psr_debug_flags debug;
2162 * 16-bit value dicated by driver that will enable/disable different functionality.
2171 * Not used in dmub fw,
2172 * dmub fw will get active opp by reading odm registers.
2177 * Not used in dmub fw,
2178 * dmub fw will get active opp by reading odm registers.
2186 * DIG FE HW instance.
2190 * DIG BE HW instance.
2194 * DP PHY HW instance.
2202 * Determines if SMU optimzations are enabled/disabled.
2204 uint8_t smu_optimizations_en;
2209 uint8_t frame_delay;
2211 * If RFB setup time is greater than the total VBLANK time,
2212 * it is not possible for the sink to capture the video frame
2213 * in the same frame the SDP is sent. In this case,
2214 * the frame capture indication bit should be set and an extra
2215 * static frame should be transmitted to the sink.
2217 uint8_t frame_cap_ind;
2219 * Granularity of Y offset supported by sink.
2221 uint8_t su_y_granularity;
2223 * Indicates whether sink should start capturing
2224 * immediately following active scan line,
2225 * or starting with the 2nd active scan line.
2227 uint8_t line_capture_indication;
2229 * Multi-display optimizations are implemented on certain ASICs.
2231 uint8_t multi_disp_optimizations_en;
2233 * The last possible line SDP may be transmitted without violating
2234 * the RFB setup time or entering the active video frame.
2236 uint16_t init_sdp_deadline;
2238 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
2240 uint8_t rate_control_caps ;
2242 * Force PSRSU always doing full frame update
2244 uint8_t force_ffu_mode;
2246 * Length of each horizontal line in us.
2248 uint32_t line_time_in_us;
2250 * FEC enable status in driver
2252 uint8_t fec_enable_status;
2254 * FEC re-enable delay when PSR exit.
2255 * unit is 100us, range form 0~255(0xFF).
2257 uint8_t fec_enable_delay_in100us;
2259 * PSR control version.
2261 uint8_t cmd_version;
2264 * Panel instance to identify which psr_state to use
2265 * Currently the support is only for 0 or 1
2269 * DSC enable status in driver
2271 uint8_t dsc_enable_status;
2273 * Use FSM state for PSR power up/down
2275 uint8_t use_phy_fsm;
2277 * frame delay for frame re-lock
2279 uint8_t relock_delay_frame_cnt;
2281 * Explicit padding to 2 byte boundary.
2287 uint16_t dsc_slice_height;
2289 * Explicit padding to 4 byte boundary.
2295 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2297 struct dmub_rb_cmd_psr_copy_settings {
2301 struct dmub_cmd_header header;
2303 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2305 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
2309 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
2311 struct dmub_cmd_psr_set_level_data {
2313 * 16-bit value dicated by driver that will enable/disable different functionality.
2317 * PSR control version.
2319 uint8_t cmd_version;
2322 * Panel instance to identify which psr_state to use
2323 * Currently the support is only for 0 or 1
2329 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2331 struct dmub_rb_cmd_psr_set_level {
2335 struct dmub_cmd_header header;
2337 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2339 struct dmub_cmd_psr_set_level_data psr_set_level_data;
2342 struct dmub_rb_cmd_psr_enable_data {
2344 * PSR control version.
2346 uint8_t cmd_version;
2349 * Panel instance to identify which psr_state to use
2350 * Currently the support is only for 0 or 1
2354 * Phy state to enter.
2355 * Values to use are defined in dmub_phy_fsm_state
2357 uint8_t phy_fsm_state;
2359 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2360 * Set this using enum phy_link_rate.
2361 * This does not support HDMI/DP2 for now.
2367 * Definition of a DMUB_CMD__PSR_ENABLE command.
2368 * PSR enable/disable is controlled using the sub_type.
2370 struct dmub_rb_cmd_psr_enable {
2374 struct dmub_cmd_header header;
2376 struct dmub_rb_cmd_psr_enable_data data;
2380 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2382 struct dmub_cmd_psr_set_version_data {
2384 * PSR version that FW should implement.
2386 enum psr_version version;
2388 * PSR control version.
2390 uint8_t cmd_version;
2393 * Panel instance to identify which psr_state to use
2394 * Currently the support is only for 0 or 1
2398 * Explicit padding to 4 byte boundary.
2404 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2406 struct dmub_rb_cmd_psr_set_version {
2410 struct dmub_cmd_header header;
2412 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2414 struct dmub_cmd_psr_set_version_data psr_set_version_data;
2417 struct dmub_cmd_psr_force_static_data {
2419 * PSR control version.
2421 uint8_t cmd_version;
2424 * Panel instance to identify which psr_state to use
2425 * Currently the support is only for 0 or 1
2429 * Explicit padding to 4 byte boundary.
2435 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2437 struct dmub_rb_cmd_psr_force_static {
2441 struct dmub_cmd_header header;
2443 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
2445 struct dmub_cmd_psr_force_static_data psr_force_static_data;
2449 * PSR SU debug flags.
2451 union dmub_psr_su_debug_flags {
2453 * PSR SU debug flags.
2457 * Update dirty rect in SW only.
2459 uint8_t update_dirty_rect_only : 1;
2461 * Reset the cursor/plane state before processing the call.
2463 uint8_t reset_state : 1;
2467 * Union for debug flags.
2473 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2474 * This triggers a selective update for PSR SU.
2476 struct dmub_cmd_update_dirty_rect_data {
2478 * Dirty rects from OS.
2480 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
2482 * PSR SU debug flags.
2484 union dmub_psr_su_debug_flags debug_flags;
2490 * Number of dirty rects.
2492 uint8_t dirty_rect_count;
2494 * PSR control version.
2496 uint8_t cmd_version;
2499 * Panel instance to identify which psr_state to use
2500 * Currently the support is only for 0 or 1
2506 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
2508 struct dmub_rb_cmd_update_dirty_rect {
2512 struct dmub_cmd_header header;
2514 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2516 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
2520 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2522 union dmub_reg_cursor_control_cfg {
2524 uint32_t cur_enable: 1;
2526 uint32_t cur_2x_magnify: 1;
2532 uint32_t line_per_chunk: 5;
2537 struct dmub_cursor_position_cache_hubp {
2538 union dmub_reg_cursor_control_cfg cur_ctl;
2539 union dmub_reg_position_cfg {
2541 uint32_t cur_x_pos: 16;
2542 uint32_t cur_y_pos: 16;
2546 union dmub_reg_hot_spot_cfg {
2553 union dmub_reg_dst_offset_cfg {
2555 uint32_t dst_x_offset: 13;
2556 uint32_t reserved: 19;
2562 union dmub_reg_cur0_control_cfg {
2564 uint32_t cur0_enable: 1;
2565 uint32_t expansion_mode: 1;
2567 uint32_t cur0_rom_en: 1;
2569 uint32_t reserved: 25;
2573 struct dmub_cursor_position_cache_dpp {
2574 union dmub_reg_cur0_control_cfg cur0_ctl;
2576 struct dmub_cursor_position_cfg {
2577 struct dmub_cursor_position_cache_hubp pHubp;
2578 struct dmub_cursor_position_cache_dpp pDpp;
2581 * Padding is required. To be 4 Bytes Aligned.
2586 struct dmub_cursor_attribute_cache_hubp {
2587 uint32_t SURFACE_ADDR_HIGH;
2588 uint32_t SURFACE_ADDR;
2589 union dmub_reg_cursor_control_cfg cur_ctl;
2590 union dmub_reg_cursor_size_cfg {
2593 uint32_t height: 16;
2597 union dmub_reg_cursor_settings_cfg {
2599 uint32_t dst_y_offset: 8;
2600 uint32_t chunk_hdl_adjust: 2;
2601 uint32_t reserved: 22;
2606 struct dmub_cursor_attribute_cache_dpp {
2607 union dmub_reg_cur0_control_cfg cur0_ctl;
2609 struct dmub_cursor_attributes_cfg {
2610 struct dmub_cursor_attribute_cache_hubp aHubp;
2611 struct dmub_cursor_attribute_cache_dpp aDpp;
2614 struct dmub_cmd_update_cursor_payload0 {
2616 * Cursor dirty rects.
2618 struct dmub_rect cursor_rect;
2620 * PSR SU debug flags.
2622 union dmub_psr_su_debug_flags debug_flags;
2624 * Cursor enable/disable.
2632 * PSR control version.
2634 uint8_t cmd_version;
2637 * Panel instance to identify which psr_state to use
2638 * Currently the support is only for 0 or 1
2642 * Cursor Position Register.
2643 * Registers contains Hubp & Dpp modules
2645 struct dmub_cursor_position_cfg position_cfg;
2648 struct dmub_cmd_update_cursor_payload1 {
2649 struct dmub_cursor_attributes_cfg attribute_cfg;
2652 union dmub_cmd_update_cursor_info_data {
2653 struct dmub_cmd_update_cursor_payload0 payload0;
2654 struct dmub_cmd_update_cursor_payload1 payload1;
2657 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
2659 struct dmub_rb_cmd_update_cursor_info {
2663 struct dmub_cmd_header header;
2665 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2667 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
2671 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2673 struct dmub_cmd_psr_set_vtotal_data {
2675 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
2677 uint16_t psr_vtotal_idle;
2679 * PSR control version.
2681 uint8_t cmd_version;
2684 * Panel instance to identify which psr_state to use
2685 * Currently the support is only for 0 or 1
2689 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
2691 uint16_t psr_vtotal_su;
2693 * Explicit padding to 4 byte boundary.
2699 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2701 struct dmub_rb_cmd_psr_set_vtotal {
2705 struct dmub_cmd_header header;
2707 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2709 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
2713 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
2715 struct dmub_cmd_psr_set_power_opt_data {
2717 * PSR control version.
2719 uint8_t cmd_version;
2722 * Panel instance to identify which psr_state to use
2723 * Currently the support is only for 0 or 1
2727 * Explicit padding to 4 byte boundary.
2736 #define REPLAY_RESIDENCY_MODE_SHIFT (0)
2737 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
2739 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2740 # define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
2741 # define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2743 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2744 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2745 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2748 REPLAY_STATE_0 = 0x0,
2749 REPLAY_STATE_1 = 0x10,
2750 REPLAY_STATE_1A = 0x11,
2751 REPLAY_STATE_2 = 0x20,
2752 REPLAY_STATE_3 = 0x30,
2753 REPLAY_STATE_3INIT = 0x31,
2754 REPLAY_STATE_4 = 0x40,
2755 REPLAY_STATE_4A = 0x41,
2756 REPLAY_STATE_4B = 0x42,
2757 REPLAY_STATE_4C = 0x43,
2758 REPLAY_STATE_4D = 0x44,
2759 REPLAY_STATE_4B_LOCKED = 0x4A,
2760 REPLAY_STATE_4C_UNLOCKED = 0x4B,
2761 REPLAY_STATE_5 = 0x50,
2762 REPLAY_STATE_5A = 0x51,
2763 REPLAY_STATE_5B = 0x52,
2764 REPLAY_STATE_5A_LOCKED = 0x5A,
2765 REPLAY_STATE_5B_UNLOCKED = 0x5B,
2766 REPLAY_STATE_6 = 0x60,
2767 REPLAY_STATE_6A = 0x61,
2768 REPLAY_STATE_6B = 0x62,
2769 REPLAY_STATE_INVALID = 0xFF,
2773 * Replay command sub-types.
2775 enum dmub_cmd_replay_type {
2777 * Copy driver-calculated parameters to REPLAY state.
2779 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
2783 DMUB_CMD__REPLAY_ENABLE = 1,
2785 * Set Replay power option.
2787 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
2789 * Set coasting vtotal.
2791 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
2795 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2797 struct dmub_cmd_replay_copy_settings_data {
2799 * Flags that can be set by driver to change some replay behaviour.
2801 union replay_debug_flags debug;
2804 * @flags: Flags used to determine feature functionality.
2806 union replay_hw_flags flags;
2817 * DIG FE HW instance.
2821 * DIG BE HW instance.
2830 * Panel isntance to identify which psr_state to use
2831 * Currently the support is only for 0 or 1
2835 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
2836 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
2838 uint8_t pixel_deviation_per_line;
2840 * @max_deviation_line: The max number of deviation line that can keep the timing
2841 * synchronized between the Source and Sink during Replay normal sleep mode.
2843 uint8_t max_deviation_line;
2845 * Length of each horizontal line in ns.
2847 uint32_t line_time_in_ns;
2853 * Determines if SMU optimzations are enabled/disabled.
2855 uint8_t smu_optimizations_en;
2857 * Determines if timing sync are enabled/disabled.
2859 uint8_t replay_timing_sync_supported;
2861 * Use FSM state for Replay power up/down
2863 uint8_t use_phy_fsm;
2867 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2869 struct dmub_rb_cmd_replay_copy_settings {
2873 struct dmub_cmd_header header;
2875 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2877 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
2881 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
2883 enum replay_enable {
2895 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
2897 struct dmub_rb_cmd_replay_enable_data {
2899 * Replay enable or disable.
2904 * Panel isntance to identify which replay_state to use
2905 * Currently the support is only for 0 or 1
2909 * Phy state to enter.
2910 * Values to use are defined in dmub_phy_fsm_state
2912 uint8_t phy_fsm_state;
2914 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2915 * Set this using enum phy_link_rate.
2916 * This does not support HDMI/DP2 for now.
2922 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
2923 * Replay enable/disable is controlled using action in data.
2925 struct dmub_rb_cmd_replay_enable {
2929 struct dmub_cmd_header header;
2931 struct dmub_rb_cmd_replay_enable_data data;
2935 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2937 struct dmub_cmd_replay_set_power_opt_data {
2940 * Panel isntance to identify which replay_state to use
2941 * Currently the support is only for 0 or 1
2945 * Explicit padding to 4 byte boundary.
2949 * REPLAY power option
2955 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2957 struct dmub_rb_cmd_replay_set_power_opt {
2961 struct dmub_cmd_header header;
2963 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2965 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
2969 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2971 struct dmub_cmd_replay_set_coasting_vtotal_data {
2973 * 16-bit value dicated by driver that indicates the coasting vtotal.
2975 uint16_t coasting_vtotal;
2977 * REPLAY control version.
2979 uint8_t cmd_version;
2982 * Panel isntance to identify which replay_state to use
2983 * Currently the support is only for 0 or 1
2989 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2991 struct dmub_rb_cmd_replay_set_coasting_vtotal {
2995 struct dmub_cmd_header header;
2997 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2999 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3003 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3005 struct dmub_rb_cmd_psr_set_power_opt {
3009 struct dmub_cmd_header header;
3011 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3013 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
3017 * Set of HW components that can be locked.
3019 * Note: If updating with more HW components, fields
3020 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3022 union dmub_hw_lock_flags {
3024 * Set of HW components that can be locked.
3028 * Lock/unlock OTG master update lock.
3030 uint8_t lock_pipe : 1;
3032 * Lock/unlock cursor.
3034 uint8_t lock_cursor : 1;
3036 * Lock/unlock global update lock.
3038 uint8_t lock_dig : 1;
3040 * Triple buffer lock requires additional hw programming to usual OTG master lock.
3042 uint8_t triple_buffer_lock : 1;
3046 * Union for HW Lock flags.
3052 * Instances of HW to be locked.
3054 * Note: If updating with more HW components, fields
3055 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3057 struct dmub_hw_lock_inst_flags {
3059 * OTG HW instance for OTG master update lock.
3063 * OPP instance for cursor lock.
3067 * OTG HW instance for global update lock.
3068 * TODO: Remove, and re-use otg_inst.
3072 * Explicit pad to 4 byte boundary.
3078 * Clients that can acquire the HW Lock Manager.
3080 * Note: If updating with more clients, fields in
3081 * dmub_inbox0_cmd_lock_hw must be updated to match.
3083 enum hw_lock_client {
3085 * Driver is the client of HW Lock Manager.
3087 HW_LOCK_CLIENT_DRIVER = 0,
3089 * PSR SU is the client of HW Lock Manager.
3091 HW_LOCK_CLIENT_PSR_SU = 1,
3093 * Replay is the client of HW Lock Manager.
3095 HW_LOCK_CLIENT_REPLAY = 4,
3099 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
3103 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3105 struct dmub_cmd_lock_hw_data {
3107 * Specifies the client accessing HW Lock Manager.
3109 enum hw_lock_client client;
3111 * HW instances to be locked.
3113 struct dmub_hw_lock_inst_flags inst_flags;
3115 * Which components to be locked.
3117 union dmub_hw_lock_flags hw_locks;
3119 * Specifies lock/unlock.
3123 * HW can be unlocked separately from releasing the HW Lock Mgr.
3124 * This flag is set if the client wishes to release the object.
3126 uint8_t should_release;
3128 * Explicit padding to 4 byte boundary.
3134 * Definition of a DMUB_CMD__HW_LOCK command.
3135 * Command is used by driver and FW.
3137 struct dmub_rb_cmd_lock_hw {
3141 struct dmub_cmd_header header;
3143 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3145 struct dmub_cmd_lock_hw_data lock_hw_data;
3149 * ABM command sub-types.
3151 enum dmub_cmd_abm_type {
3153 * Initialize parameters for ABM algorithm.
3154 * Data is passed through an indirect buffer.
3156 DMUB_CMD__ABM_INIT_CONFIG = 0,
3158 * Set OTG and panel HW instance.
3160 DMUB_CMD__ABM_SET_PIPE = 1,
3162 * Set user requested backklight level.
3164 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
3166 * Set ABM operating/aggression level.
3168 DMUB_CMD__ABM_SET_LEVEL = 3,
3170 * Set ambient light level.
3172 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
3174 * Enable/disable fractional duty cycle for backlight PWM.
3176 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
3179 * unregister vertical interrupt after steady state is reached
3181 DMUB_CMD__ABM_PAUSE = 6,
3184 * Save and Restore ABM state. On save we save parameters, and
3185 * on restore we update state with passed in data.
3187 DMUB_CMD__ABM_SAVE_RESTORE = 7,
3191 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
3193 * - Padded explicitly to 32-bit boundary.
3194 * - Must ensure this structure matches the one on driver-side,
3195 * otherwise it won't be aligned.
3197 struct abm_config_table {
3199 * Gamma curve thresholds, used for crgb conversion.
3201 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
3203 * Gamma curve offsets, used for crgb conversion.
3205 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
3207 * Gamma curve slopes, used for crgb conversion.
3209 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
3211 * Custom backlight curve thresholds.
3213 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
3215 * Custom backlight curve offsets.
3217 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
3219 * Ambient light thresholds.
3221 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
3223 * Minimum programmable backlight.
3225 uint16_t min_abm_backlight; // 122B
3227 * Minimum reduction values.
3229 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
3231 * Maximum reduction values.
3233 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
3235 * Bright positive gain.
3237 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
3239 * Dark negative gain.
3241 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
3245 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
3249 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
3253 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
3257 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
3261 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
3265 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
3267 * Explicit padding to 4 byte boundary.
3269 uint8_t pad3[3]; // 229B
3271 * Backlight ramp reduction.
3273 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
3275 * Backlight ramp start.
3277 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
3281 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
3283 struct dmub_cmd_abm_set_pipe_data {
3290 * Panel Control HW instance.
3295 * Controls how ABM will interpret a set pipe or set level command.
3297 uint8_t set_pipe_option;
3303 uint8_t ramping_boundary;
3307 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
3309 struct dmub_rb_cmd_abm_set_pipe {
3313 struct dmub_cmd_header header;
3316 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
3318 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
3322 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
3324 struct dmub_cmd_abm_set_backlight_data {
3326 * Number of frames to ramp to backlight user level.
3328 uint32_t frame_ramp;
3331 * Requested backlight level from user.
3333 uint32_t backlight_user_level;
3336 * ABM control version.
3341 * Panel Control HW instance mask.
3342 * Bit 0 is Panel Control HW instance 0.
3343 * Bit 1 is Panel Control HW instance 1.
3348 * Explicit padding to 4 byte boundary.
3354 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
3356 struct dmub_rb_cmd_abm_set_backlight {
3360 struct dmub_cmd_header header;
3363 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
3365 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
3369 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
3371 struct dmub_cmd_abm_set_level_data {
3373 * Set current ABM operating/aggression level.
3378 * ABM control version.
3383 * Panel Control HW instance mask.
3384 * Bit 0 is Panel Control HW instance 0.
3385 * Bit 1 is Panel Control HW instance 1.
3390 * Explicit padding to 4 byte boundary.
3396 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
3398 struct dmub_rb_cmd_abm_set_level {
3402 struct dmub_cmd_header header;
3405 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
3407 struct dmub_cmd_abm_set_level_data abm_set_level_data;
3411 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3413 struct dmub_cmd_abm_set_ambient_level_data {
3415 * Ambient light sensor reading from OS.
3417 uint32_t ambient_lux;
3420 * ABM control version.
3425 * Panel Control HW instance mask.
3426 * Bit 0 is Panel Control HW instance 0.
3427 * Bit 1 is Panel Control HW instance 1.
3432 * Explicit padding to 4 byte boundary.
3438 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3440 struct dmub_rb_cmd_abm_set_ambient_level {
3444 struct dmub_cmd_header header;
3447 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3449 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
3453 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
3455 struct dmub_cmd_abm_set_pwm_frac_data {
3457 * Enable/disable fractional duty cycle for backlight PWM.
3458 * TODO: Convert to uint8_t.
3460 uint32_t fractional_pwm;
3463 * ABM control version.
3468 * Panel Control HW instance mask.
3469 * Bit 0 is Panel Control HW instance 0.
3470 * Bit 1 is Panel Control HW instance 1.
3475 * Explicit padding to 4 byte boundary.
3481 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
3483 struct dmub_rb_cmd_abm_set_pwm_frac {
3487 struct dmub_cmd_header header;
3490 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
3492 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
3496 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3498 struct dmub_cmd_abm_init_config_data {
3500 * Location of indirect buffer used to pass init data to ABM.
3502 union dmub_addr src;
3505 * Indirect buffer length.
3511 * ABM control version.
3516 * Panel Control HW instance mask.
3517 * Bit 0 is Panel Control HW instance 0.
3518 * Bit 1 is Panel Control HW instance 1.
3523 * Explicit padding to 4 byte boundary.
3529 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
3531 struct dmub_rb_cmd_abm_init_config {
3535 struct dmub_cmd_header header;
3538 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3540 struct dmub_cmd_abm_init_config_data abm_init_config_data;
3544 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3547 struct dmub_cmd_abm_pause_data {
3550 * Panel Control HW instance mask.
3551 * Bit 0 is Panel Control HW instance 0.
3552 * Bit 1 is Panel Control HW instance 1.
3562 * Enable or disable ABM pause
3567 * Explicit padding to 4 byte boundary.
3574 * Definition of a DMUB_CMD__ABM_PAUSE command.
3576 struct dmub_rb_cmd_abm_pause {
3580 struct dmub_cmd_header header;
3583 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3585 struct dmub_cmd_abm_pause_data abm_pause_data;
3589 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
3591 struct dmub_rb_cmd_abm_save_restore {
3595 struct dmub_cmd_header header;
3603 * Enable or disable ABM pause
3608 * Explicit padding to 4 byte boundary.
3613 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3615 struct dmub_cmd_abm_init_config_data abm_init_config_data;
3619 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
3621 struct dmub_cmd_query_feature_caps_data {
3623 * DMUB feature capabilities.
3624 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
3626 struct dmub_feature_caps feature_caps;
3630 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
3632 struct dmub_rb_cmd_query_feature_caps {
3636 struct dmub_cmd_header header;
3638 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
3640 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
3644 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3646 struct dmub_cmd_visual_confirm_color_data {
3648 * DMUB feature capabilities.
3649 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
3651 struct dmub_visual_confirm_color visual_confirm_color;
3655 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3657 struct dmub_rb_cmd_get_visual_confirm_color {
3661 struct dmub_cmd_header header;
3663 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3665 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
3668 struct dmub_optc_state {
3669 uint32_t v_total_max;
3670 uint32_t v_total_min;
3674 struct dmub_rb_cmd_drr_update {
3675 struct dmub_cmd_header header;
3676 struct dmub_optc_state dmub_optc_state_req;
3679 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
3680 uint32_t pix_clk_100hz;
3681 uint8_t max_ramp_step;
3683 uint8_t min_refresh_in_hz;
3685 uint8_t pipe_index[4];
3688 struct dmub_cmd_fw_assisted_mclk_switch_config {
3689 uint8_t fams_enabled;
3690 uint8_t visual_confirm_enabled;
3691 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
3692 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
3695 struct dmub_rb_cmd_fw_assisted_mclk_switch {
3696 struct dmub_cmd_header header;
3697 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
3701 * enum dmub_cmd_panel_cntl_type - Panel control command.
3703 enum dmub_cmd_panel_cntl_type {
3705 * Initializes embedded panel hardware blocks.
3707 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
3709 * Queries backlight info for the embedded panel.
3711 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
3715 * struct dmub_cmd_panel_cntl_data - Panel control data.
3717 struct dmub_cmd_panel_cntl_data {
3718 uint32_t inst; /**< panel instance */
3719 uint32_t current_backlight; /* in/out */
3720 uint32_t bl_pwm_cntl; /* in/out */
3721 uint32_t bl_pwm_period_cntl; /* in/out */
3722 uint32_t bl_pwm_ref_div1; /* in/out */
3723 uint8_t is_backlight_on : 1; /* in/out */
3724 uint8_t is_powered_on : 1; /* in/out */
3726 uint32_t bl_pwm_ref_div2; /* in/out */
3727 uint8_t reserved[4];
3731 * struct dmub_rb_cmd_panel_cntl - Panel control command.
3733 struct dmub_rb_cmd_panel_cntl {
3734 struct dmub_cmd_header header; /**< header */
3735 struct dmub_cmd_panel_cntl_data data; /**< payload */
3739 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3741 struct dmub_cmd_lvtma_control_data {
3742 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
3743 uint8_t bypass_panel_control_wait;
3744 uint8_t reserved_0[2]; /**< For future use */
3745 uint8_t panel_inst; /**< LVTMA control instance */
3746 uint8_t reserved_1[3]; /**< For future use */
3750 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3752 struct dmub_rb_cmd_lvtma_control {
3756 struct dmub_cmd_header header;
3758 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3760 struct dmub_cmd_lvtma_control_data data;
3764 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3766 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
3767 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
3768 uint8_t is_usb; /**< is phy is usb */
3769 uint8_t is_dp_alt_disable; /**< is dp alt disable */
3770 uint8_t is_dp4; /**< is dp in 4 lane */
3774 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3776 struct dmub_rb_cmd_transmitter_query_dp_alt {
3777 struct dmub_cmd_header header; /**< header */
3778 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
3782 * Maximum number of bytes a chunk sent to DMUB for parsing
3784 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
3787 * Represent a chunk of CEA blocks sent to DMUB for parsing
3789 struct dmub_cmd_send_edid_cea {
3790 uint16_t offset; /**< offset into the CEA block */
3791 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
3792 uint16_t cea_total_length; /**< total length of the CEA block */
3793 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
3794 uint8_t pad[3]; /**< padding and for future expansion */
3798 * Result of VSDB parsing from CEA block
3800 struct dmub_cmd_edid_cea_amd_vsdb {
3801 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
3802 uint8_t freesync_supported; /**< 1 if Freesync is supported */
3803 uint16_t amd_vsdb_version; /**< AMD VSDB version */
3804 uint16_t min_frame_rate; /**< Maximum frame rate */
3805 uint16_t max_frame_rate; /**< Minimum frame rate */
3809 * Result of sending a CEA chunk
3811 struct dmub_cmd_edid_cea_ack {
3812 uint16_t offset; /**< offset of the chunk into the CEA block */
3813 uint8_t success; /**< 1 if this sending of chunk succeeded */
3814 uint8_t pad; /**< padding and for future expansion */
3818 * Specify whether the result is an ACK/NACK or the parsing has finished
3820 enum dmub_cmd_edid_cea_reply_type {
3821 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
3822 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
3826 * Definition of a DMUB_CMD__EDID_CEA command.
3828 struct dmub_rb_cmd_edid_cea {
3829 struct dmub_cmd_header header; /**< Command header */
3830 union dmub_cmd_edid_cea_data {
3831 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
3832 struct dmub_cmd_edid_cea_output { /**< output with results */
3833 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
3835 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
3836 struct dmub_cmd_edid_cea_ack ack;
3838 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
3839 } data; /**< Command data */
3844 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
3846 struct dmub_cmd_cable_id_input {
3847 uint8_t phy_inst; /**< phy inst for cable id data */
3851 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
3853 struct dmub_cmd_cable_id_output {
3854 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
3855 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
3856 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
3857 uint8_t RESERVED :2; /**< reserved means not defined */
3861 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
3863 struct dmub_rb_cmd_get_usbc_cable_id {
3864 struct dmub_cmd_header header; /**< Command header */
3866 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
3868 union dmub_cmd_cable_id_data {
3869 struct dmub_cmd_cable_id_input input; /**< Input */
3870 struct dmub_cmd_cable_id_output output; /**< Output */
3871 uint8_t output_raw; /**< Raw data output */
3876 * Command type of a DMUB_CMD__SECURE_DISPLAY command
3878 enum dmub_cmd_secure_display_type {
3879 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
3880 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
3881 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY
3885 * Definition of a DMUB_CMD__SECURE_DISPLAY command
3887 struct dmub_rb_cmd_secure_display {
3888 struct dmub_cmd_header header;
3890 * Data passed from driver to dmub firmware.
3892 struct dmub_cmd_roi_info {
3903 * union dmub_rb_cmd - DMUB inbox command.
3907 * Elements shared with all commands.
3909 struct dmub_rb_cmd_common cmd_common;
3911 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
3913 struct dmub_rb_cmd_read_modify_write read_modify_write;
3915 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
3917 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
3919 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
3921 struct dmub_rb_cmd_burst_write burst_write;
3923 * Definition of a DMUB_CMD__REG_REG_WAIT command.
3925 struct dmub_rb_cmd_reg_wait reg_wait;
3927 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
3929 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
3931 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
3933 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
3935 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
3937 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
3939 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
3941 struct dmub_rb_cmd_dpphy_init dpphy_init;
3943 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
3945 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
3947 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
3949 struct dmub_rb_cmd_domain_control domain_control;
3951 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
3953 struct dmub_rb_cmd_psr_set_version psr_set_version;
3955 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
3957 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
3959 * Definition of a DMUB_CMD__PSR_ENABLE command.
3961 struct dmub_rb_cmd_psr_enable psr_enable;
3963 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3965 struct dmub_rb_cmd_psr_set_level psr_set_level;
3967 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3969 struct dmub_rb_cmd_psr_force_static psr_force_static;
3971 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
3973 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
3975 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
3977 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
3979 * Definition of a DMUB_CMD__HW_LOCK command.
3980 * Command is used by driver and FW.
3982 struct dmub_rb_cmd_lock_hw lock_hw;
3984 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3986 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
3988 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3990 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
3992 * Definition of a DMUB_CMD__PLAT_54186_WA command.
3994 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
3996 * Definition of a DMUB_CMD__MALL command.
3998 struct dmub_rb_cmd_mall mall;
4000 * Definition of a DMUB_CMD__CAB command.
4002 struct dmub_rb_cmd_cab_for_ss cab;
4004 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
4007 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
4009 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
4012 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
4014 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
4017 * Definition of DMUB_CMD__PANEL_CNTL commands.
4019 struct dmub_rb_cmd_panel_cntl panel_cntl;
4021 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
4023 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
4026 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
4028 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
4031 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
4033 struct dmub_rb_cmd_abm_set_level abm_set_level;
4036 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4038 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
4041 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
4043 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
4046 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
4048 struct dmub_rb_cmd_abm_init_config abm_init_config;
4051 * Definition of a DMUB_CMD__ABM_PAUSE command.
4053 struct dmub_rb_cmd_abm_pause abm_pause;
4056 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
4058 struct dmub_rb_cmd_abm_save_restore abm_save_restore;
4061 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
4063 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
4066 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
4068 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
4071 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
4073 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
4076 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4078 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
4079 struct dmub_rb_cmd_drr_update drr_update;
4080 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
4083 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4085 struct dmub_rb_cmd_lvtma_control lvtma_control;
4087 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4089 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
4091 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
4093 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
4095 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
4097 struct dmub_rb_cmd_set_config_access set_config_access;
4099 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
4101 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
4103 * Definition of a DMUB_CMD__EDID_CEA command.
4105 struct dmub_rb_cmd_edid_cea edid_cea;
4107 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
4109 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
4112 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
4114 struct dmub_rb_cmd_query_hpd_state query_hpd;
4116 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
4118 struct dmub_rb_cmd_secure_display secure_display;
4121 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
4123 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
4125 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
4127 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
4129 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4131 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
4133 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
4135 struct dmub_rb_cmd_replay_enable replay_enable;
4137 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4139 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
4141 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4143 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
4147 * union dmub_rb_out_cmd - Outbox command
4149 union dmub_rb_out_cmd {
4151 * Parameters common to every command.
4153 struct dmub_rb_cmd_common cmd_common;
4155 * AUX reply command.
4157 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
4159 * HPD notify command.
4161 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
4163 * SET_CONFIG reply command.
4165 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
4167 * DPIA notification command.
4169 struct dmub_rb_cmd_dpia_notification dpia_notification;
4174 //==============================================================================
4175 //</DMUB_CMD>===================================================================
4176 //==============================================================================
4177 //< DMUB_RB>====================================================================
4178 //==============================================================================
4180 #if defined(__cplusplus)
4185 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
4187 struct dmub_rb_init_params {
4188 void *ctx; /**< Caller provided context pointer */
4189 void *base_address; /**< CPU base address for ring's data */
4190 uint32_t capacity; /**< Ringbuffer capacity in bytes */
4191 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
4192 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
4196 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
4199 void *base_address; /**< CPU address for the ring's data */
4200 uint32_t rptr; /**< Read pointer for consumer in bytes */
4201 uint32_t wrpt; /**< Write pointer for producer in bytes */
4202 uint32_t capacity; /**< Ringbuffer capacity in bytes */
4204 void *ctx; /**< Caller provided context pointer */
4205 void *dmub; /**< Pointer to the DMUB interface */
4209 * @brief Checks if the ringbuffer is empty.
4211 * @param rb DMUB Ringbuffer
4212 * @return true if empty
4213 * @return false otherwise
4215 static inline bool dmub_rb_empty(struct dmub_rb *rb)
4217 return (rb->wrpt == rb->rptr);
4221 * @brief Checks if the ringbuffer is full
4223 * @param rb DMUB Ringbuffer
4224 * @return true if full
4225 * @return false otherwise
4227 static inline bool dmub_rb_full(struct dmub_rb *rb)
4229 uint32_t data_count;
4231 if (rb->wrpt >= rb->rptr)
4232 data_count = rb->wrpt - rb->rptr;
4234 data_count = rb->capacity - (rb->rptr - rb->wrpt);
4236 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
4240 * @brief Pushes a command into the ringbuffer
4242 * @param rb DMUB ringbuffer
4243 * @param cmd The command to push
4244 * @return true if the ringbuffer was not full
4245 * @return false otherwise
4247 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
4248 const union dmub_rb_cmd *cmd)
4250 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
4251 const uint64_t *src = (const uint64_t *)cmd;
4254 if (dmub_rb_full(rb))
4258 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4261 rb->wrpt += DMUB_RB_CMD_SIZE;
4263 if (rb->wrpt >= rb->capacity)
4264 rb->wrpt %= rb->capacity;
4270 * @brief Pushes a command into the DMUB outbox ringbuffer
4272 * @param rb DMUB outbox ringbuffer
4273 * @param cmd Outbox command
4274 * @return true if not full
4275 * @return false otherwise
4277 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
4278 const union dmub_rb_out_cmd *cmd)
4280 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
4281 const uint8_t *src = (const uint8_t *)cmd;
4283 if (dmub_rb_full(rb))
4286 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
4288 rb->wrpt += DMUB_RB_CMD_SIZE;
4290 if (rb->wrpt >= rb->capacity)
4291 rb->wrpt %= rb->capacity;
4297 * @brief Returns the next unprocessed command in the ringbuffer.
4299 * @param rb DMUB ringbuffer
4300 * @param cmd The command to return
4301 * @return true if not empty
4302 * @return false otherwise
4304 static inline bool dmub_rb_front(struct dmub_rb *rb,
4305 union dmub_rb_cmd **cmd)
4307 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
4309 if (dmub_rb_empty(rb))
4312 *cmd = (union dmub_rb_cmd *)rb_cmd;
4318 * @brief Determines the next ringbuffer offset.
4320 * @param rb DMUB inbox ringbuffer
4321 * @param num_cmds Number of commands
4322 * @param next_rptr The next offset in the ringbuffer
4324 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
4326 uint32_t *next_rptr)
4328 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
4330 if (*next_rptr >= rb->capacity)
4331 *next_rptr %= rb->capacity;
4335 * @brief Returns a pointer to a command in the inbox.
4337 * @param rb DMUB inbox ringbuffer
4338 * @param cmd The inbox command to return
4339 * @param rptr The ringbuffer offset
4340 * @return true if not empty
4341 * @return false otherwise
4343 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
4344 union dmub_rb_cmd **cmd,
4347 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
4349 if (dmub_rb_empty(rb))
4352 *cmd = (union dmub_rb_cmd *)rb_cmd;
4358 * @brief Returns the next unprocessed command in the outbox.
4360 * @param rb DMUB outbox ringbuffer
4361 * @param cmd The outbox command to return
4362 * @return true if not empty
4363 * @return false otherwise
4365 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
4366 union dmub_rb_out_cmd *cmd)
4368 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
4369 uint64_t *dst = (uint64_t *)cmd;
4372 if (dmub_rb_empty(rb))
4376 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4383 * @brief Removes the front entry in the ringbuffer.
4385 * @param rb DMUB ringbuffer
4386 * @return true if the command was removed
4387 * @return false if there were no commands
4389 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
4391 if (dmub_rb_empty(rb))
4394 rb->rptr += DMUB_RB_CMD_SIZE;
4396 if (rb->rptr >= rb->capacity)
4397 rb->rptr %= rb->capacity;
4403 * @brief Flushes commands in the ringbuffer to framebuffer memory.
4405 * Avoids a race condition where DMCUB accesses memory while
4406 * there are still writes in flight to framebuffer.
4408 * @param rb DMUB ringbuffer
4410 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
4412 uint32_t rptr = rb->rptr;
4413 uint32_t wptr = rb->wrpt;
4415 while (rptr != wptr) {
4416 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
4419 /* Don't remove this.
4420 * The contents need to actually be read from the ring buffer
4421 * for this function to be effective.
4423 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4424 (void)READ_ONCE(*data++);
4426 rptr += DMUB_RB_CMD_SIZE;
4427 if (rptr >= rb->capacity)
4428 rptr %= rb->capacity;
4433 * @brief Initializes a DMCUB ringbuffer
4435 * @param rb DMUB ringbuffer
4436 * @param init_params initial configuration for the ringbuffer
4438 static inline void dmub_rb_init(struct dmub_rb *rb,
4439 struct dmub_rb_init_params *init_params)
4441 rb->base_address = init_params->base_address;
4442 rb->capacity = init_params->capacity;
4443 rb->rptr = init_params->read_ptr;
4444 rb->wrpt = init_params->write_ptr;
4448 * @brief Copies output data from in/out commands into the given command.
4450 * @param rb DMUB ringbuffer
4451 * @param cmd Command to copy data into
4453 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
4454 union dmub_rb_cmd *cmd)
4456 // Copy rb entry back into command
4457 uint8_t *rd_ptr = (rb->rptr == 0) ?
4458 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
4459 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
4461 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
4464 #if defined(__cplusplus)
4468 //==============================================================================
4469 //</DMUB_RB>====================================================================
4470 //==============================================================================
4472 #endif /* _DMUB_CMD_H_ */