2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
26 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
28 #include "core_types.h"
29 #include "core_status.h"
30 #include "dal_asic_id.h"
31 #include "dm_pp_smu.h"
33 #define MEMORY_TYPE_MULTIPLIER_CZ 4
34 #define MEMORY_TYPE_HBM 2
37 #define IS_PIPE_SYNCD_VALID(pipe) ((((pipe)->pipe_idx_syncd) & 0x80)?1:0)
38 #define GET_PIPE_SYNCD_FROM_PIPE(pipe) ((pipe)->pipe_idx_syncd & 0x7F)
39 #define SET_PIPE_SYNCD_TO_PIPE(pipe, pipe_syncd) ((pipe)->pipe_idx_syncd = (0x80 | pipe_syncd))
41 enum dce_version resource_parse_asic_id(
42 struct hw_asic_id asic_id);
44 struct resource_caps {
45 int num_timing_generator;
49 int num_stream_encoder;
55 unsigned int num_dig_link_enc; // Total number of DIGs (digital encoders) in DIO (Display Input/Output).
56 unsigned int num_usb4_dpia; // Total number of USB4 DPIA (DisplayPort Input Adapters).
57 int num_hpo_dp_stream_encoder;
58 int num_hpo_dp_link_encoder;
62 struct resource_straps {
63 uint32_t hdmi_disable;
64 uint32_t dc_pinstraps_audio;
65 uint32_t audio_stream_number;
68 struct resource_create_funcs {
69 void (*read_dce_straps)(
70 struct dc_context *ctx, struct resource_straps *straps);
72 struct audio *(*create_audio)(
73 struct dc_context *ctx, unsigned int inst);
75 struct stream_encoder *(*create_stream_encoder)(
76 enum engine_id eng_id, struct dc_context *ctx);
78 struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)(
79 enum engine_id eng_id, struct dc_context *ctx);
81 struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)(
83 struct dc_context *ctx);
85 struct dce_hwseq *(*create_hwseq)(
86 struct dc_context *ctx);
89 bool resource_construct(
90 unsigned int num_virtual_links,
92 struct resource_pool *pool,
93 const struct resource_create_funcs *create_funcs);
95 struct resource_pool *dc_create_resource_pool(struct dc *dc,
96 const struct dc_init_data *init_data,
97 enum dce_version dc_version);
99 void dc_destroy_resource_pool(struct dc *dc);
101 enum dc_status resource_map_pool_resources(
103 struct dc_state *context,
104 struct dc_stream_state *stream);
106 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
108 enum dc_status resource_build_scaling_params_for_context(
110 struct dc_state *context);
112 void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
114 void resource_unreference_clock_source(
115 struct resource_context *res_ctx,
116 const struct resource_pool *pool,
117 struct clock_source *clock_source);
119 void resource_reference_clock_source(
120 struct resource_context *res_ctx,
121 const struct resource_pool *pool,
122 struct clock_source *clock_source);
124 int resource_get_clock_source_reference(
125 struct resource_context *res_ctx,
126 const struct resource_pool *pool,
127 struct clock_source *clock_source);
129 bool resource_are_streams_timing_synchronizable(
130 struct dc_stream_state *stream1,
131 struct dc_stream_state *stream2);
133 bool resource_are_vblanks_synchronizable(
134 struct dc_stream_state *stream1,
135 struct dc_stream_state *stream2);
137 struct clock_source *resource_find_used_clk_src_for_sharing(
138 struct resource_context *res_ctx,
139 struct pipe_ctx *pipe_ctx);
141 struct clock_source *dc_resource_find_first_free_pll(
142 struct resource_context *res_ctx,
143 const struct resource_pool *pool);
145 bool resource_attach_surfaces_to_context(
146 struct dc_plane_state *const *plane_state,
148 struct dc_stream_state *dc_stream,
149 struct dc_state *context,
150 const struct resource_pool *pool);
152 #define FREE_PIPE_INDEX_NOT_FOUND -1
155 * pipe types are identified based on MUXes in DCN front end that are capable
156 * of taking input from one DCN pipeline to another DCN pipeline. The name is
157 * in a form of XXXX_YYYY, where XXXX is the DCN front end hardware block the
158 * pipeline ends with and YYYY is the rendering role that the pipe is in.
160 * For instance OTG_MASTER is a pipe ending with OTG hardware block in its
161 * pipeline and it is in a role of a master pipe for timing generation.
163 * For quick reference a diagram of each pipe type's areas of responsibility
164 * for outputting timings on the screen is shown below:
166 * Timing Active for Stream 0
167 * __________________________________________________
168 * |OTG master 0 (OPP head 0)|OPP head 2 (DPP pipe 2) |
171 * | ______________|____ |
172 * | |DPP pipe 1 |DPP | |
177 * | |______________|____| |
180 * | ODM slice 0 | ODM slice 1 |
181 * |_________________________|________________________|
183 * Timing Active for Stream 1
184 * __________________________________________________
185 * |OTG master 4 (OPP head 4) |
191 * | Blank Pixel Data |
192 * | (generated by DPG4) |
198 * |__________________________________________________|
200 * Inter-pipe Relation
201 * __________________________________________________
202 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
203 * | | plane 0 | slice 0 | |
204 * | 0 | -------------MPC---------ODM----------- |
205 * | | plane 1 | | | | |
206 * | 1 | ------------- | | | |
207 * | | plane 0 | slice 1 | | |
208 * | 2 | -------------MPC--------- | |
209 * | | plane 1 | | | |
210 * | 3 | ------------- | | |
212 * | 4 | | ----------------------- |
215 * |________|_______________|___________|_____________|
218 /* free pipe - free pipe is an uninitialized pipe without a stream
219 * associated with it. It is a free DCN pipe resource. It can be
220 * acquired as any type of pipe.
224 /* OTG master pipe - the master pipe of its OPP head pipes with a
225 * functional OTG. It merges all its OPP head pipes pixel data in ODM
226 * block and output to backend DIG. OTG master pipe is responsible for
227 * generating entire crtc timing to backend DIG. An OTG master pipe may
228 * or may not have a plane. If it has a plane it blends it as the left
229 * most MPC slice of the top most layer. If it doesn't have a plane it
230 * can output pixel data from its OPP head pipes' test pattern
231 * generators (DPG) such as solid black pixel data to blank the screen.
235 /* OPP head pipe - the head pipe of an MPC blending tree with a
236 * functional OPP outputting to an OTG. OPP head pipe is responsible for
237 * processing output pixels in its own ODM slice. It may or may not have
238 * a plane. If it has a plane it blends it as the top most layer within
239 * its own ODM slice. If it doesn't have a plane it can output pixel
240 * data from its DPG such as solid black pixel data to blank the pixel
241 * data in its own ODM slice. OTG master pipe is also an OPP head pipe
242 * but with more responsibility.
246 /* DPP pipe - the pipe with a functional DPP outputting to an OPP head
247 * pipe's MPC. DPP pipe is responsible for processing pixel data from
248 * its own MPC slice of a plane. It must be connected to an OPP head
249 * pipe and it must have a plane associated with it.
255 * Determine if the input pipe ctx is of a pipe type.
256 * return - true if pipe ctx is of the input type.
258 bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type);
261 * Determine if the input pipe ctx is used for rendering a plane with MPCC
262 * combine. MPCC combine is a hardware feature to combine multiple DPP pipes
263 * into a single plane. It is typically used for bypassing pipe bandwidth
264 * limitation for rendering a very large plane or saving power by reducing UCLK
267 * For instance in the Inter-pipe Relation diagram shown below, both PIPE 0 and
268 * 1 are for MPCC combine for plane 0
270 * Inter-pipe Relation
271 * __________________________________________________
272 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
274 * | 0 | -------------MPC----------------------- |
275 * | | plane 0 | | | |
276 * | 1 | ------------- | | |
277 * |________|_______________|___________|_____________|
279 * return - true if pipe ctx is used for mpcc combine.
281 bool resource_is_for_mpcc_combine(const struct pipe_ctx *pipe_ctx);
284 * Look for a free pipe in new resource context that is used as a secondary DPP
285 * pipe in MPC blending tree associated with input OPP head pipe.
287 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise
288 * pipe idx of the free pipe
290 int resource_find_free_pipe_used_in_cur_mpc_blending_tree(
291 const struct resource_context *cur_res_ctx,
292 struct resource_context *new_res_ctx,
293 const struct pipe_ctx *cur_opp_head);
296 * Look for a free pipe in new resource context that is not used in current
299 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise
300 * pipe idx of the free pipe
302 int recource_find_free_pipe_not_used_in_cur_res_ctx(
303 const struct resource_context *cur_res_ctx,
304 struct resource_context *new_res_ctx,
305 const struct resource_pool *pool);
308 * Look for a free pipe in new resource context that is used as a secondary DPP
309 * pipe in any MPCC combine in current resource context.
310 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise
311 * pipe idx of the free pipe
313 int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
314 const struct resource_context *cur_res_ctx,
315 struct resource_context *new_res_ctx,
316 const struct resource_pool *pool);
319 * Look for any free pipe in new resource context.
320 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise
321 * pipe idx of the free pipe
323 int resource_find_any_free_pipe(struct resource_context *new_res_ctx,
324 const struct resource_pool *pool);
327 * Legacy find free secondary pipe logic deprecated for newer DCNs as it doesn't
328 * find the most optimal free pipe to prevent from time consuming hardware state
331 struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
332 struct resource_context *res_ctx,
333 const struct resource_pool *pool,
334 const struct pipe_ctx *primary_pipe);
337 * Get number of MPC "cuts" of the plane associated with the pipe. MPC slice
338 * count is equal to MPC splits + 1. For example if a plane is cut 3 times, it
339 * will have 4 pieces of slice.
340 * return - 0 if pipe is not used for a plane with MPCC combine. otherwise
341 * the number of MPC "cuts" for the plane.
343 int resource_get_num_mpc_splits(const struct pipe_ctx *pipe);
346 * Get number of ODM "cuts" of the timing associated with the pipe. ODM slice
347 * count is equal to ODM splits + 1. For example if a timing is cut 3 times, it
348 * will have 4 pieces of slice.
349 * return - 0 if pipe is not used for ODM combine. otherwise
350 * the number of ODM "cuts" for the timing.
352 int resource_get_num_odm_splits(const struct pipe_ctx *pipe);
355 * Get the OTG master pipe in resource context associated with the stream.
356 * return - NULL if not found. Otherwise the OTG master pipe associated with the
359 struct pipe_ctx *resource_get_otg_master_for_stream(
360 struct resource_context *res_ctx,
361 struct dc_stream_state *stream);
364 * Get the OTG master pipe for the input pipe context.
365 * return - the OTG master pipe for the input pipe
368 struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx);
371 * Get the OPP head pipe for the input pipe context.
372 * return - the OPP head pipe for the input pipe
375 struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx);
378 bool resource_validate_attach_surfaces(
379 const struct dc_validation_set set[],
381 const struct dc_state *old_context,
382 struct dc_state *context,
383 const struct resource_pool *pool);
385 enum dc_status resource_map_clock_resources(
387 struct dc_state *context,
388 struct dc_stream_state *stream);
390 enum dc_status resource_map_phy_clock_resources(
392 struct dc_state *context,
393 struct dc_stream_state *stream);
395 bool pipe_need_reprogram(
396 struct pipe_ctx *pipe_ctx_old,
397 struct pipe_ctx *pipe_ctx);
399 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
400 struct bit_depth_reduction_params *fmt_bit_depth);
402 void update_audio_usage(
403 struct resource_context *res_ctx,
404 const struct resource_pool *pool,
408 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
410 void get_audio_check(struct audio_info *aud_modes,
411 struct audio_check *aud_chk);
413 bool get_temp_dp_link_res(struct dc_link *link,
414 struct link_resource *link_res,
415 struct dc_link_settings *link_settings);
417 #if defined(CONFIG_DRM_AMD_DC_FP)
418 struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
419 const struct resource_context *res_ctx,
420 const struct resource_pool *pool,
421 const struct dc_link *link);
424 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
425 struct dc_state *context);
427 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
428 struct dc_state *context,
429 uint8_t disabled_master_pipe_idx);
431 void reset_sync_context_for_pipe(const struct dc *dc,
432 struct dc_state *context,
435 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter);
437 const struct link_hwss *get_link_hwss(const struct dc_link *link,
438 const struct link_resource *link_res);
440 bool is_h_timing_divisible_by_2(struct dc_stream_state *stream);
442 bool dc_resource_acquire_secondary_pipe_for_mpc_odm(
444 struct dc_state *state,
445 struct pipe_ctx *pri_pipe,
446 struct pipe_ctx *sec_pipe,
449 /* A test harness interface that modifies dp encoder resources in the given dc
450 * state and bypasses the need to revalidate. The interface assumes that the
451 * test harness interface is called with pre-validated link config stored in the
452 * pipe_ctx and updates dp encoder resources according to the link config.
454 enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,
455 struct dc_state *context,
456 struct pipe_ctx *pipe_ctx);
457 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */