drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_HW_SEQUENCER_H__
  27 #define __DC_HW_SEQUENCER_H__
  28 #include "dc_types.h"
  29 #include "clock_source.h"
  30 #include "inc/hw/timing_generator.h"
  31 #include "inc/hw/opp.h"
  32 #include "inc/hw/link_encoder.h"
  33 #include "core_status.h"
  34
  35 enum pipe_gating_control {
  36         PIPE_GATING_CONTROL_DISABLE = 0,
  37         PIPE_GATING_CONTROL_ENABLE,
  38         PIPE_GATING_CONTROL_INIT
  39 };
  40
  41 enum vline_select {
  42         VLINE0,
  43         VLINE1
  44 };
  45
  46 struct dce_hwseq_wa {
  47         bool blnd_crtc_trigger;
  48         bool DEGVIDCN10_253;
  49         bool false_optc_underflow;
  50         bool DEGVIDCN10_254;
  51 };
  52
  53 struct hwseq_wa_state {
  54         bool DEGVIDCN10_253_applied;
  55 };
  56
  57 struct dce_hwseq {
  58         struct dc_context *ctx;
  59         const struct dce_hwseq_registers *regs;
  60         const struct dce_hwseq_shift *shifts;
  61         const struct dce_hwseq_mask *masks;
  62         struct dce_hwseq_wa wa;
  63         struct hwseq_wa_state wa_state;
  64 };
  65
  66 struct pipe_ctx;
  67 struct dc_state;
  68 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  69 struct dc_stream_status;
  70 struct dc_writeback_info;
  71 #endif
  72 struct dchub_init_data;
  73 struct dc_static_screen_events;
  74 struct resource_pool;
  75 struct resource_context;
  76 struct stream_resource;
  77 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
  78 struct dc_phy_addr_space_config;
  79 struct dc_virtual_addr_space_config;
  80 #endif
  81 struct hubp;
  82 struct dpp;
  83
  84 struct hw_sequencer_funcs {
  85
  86         void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  87
  88         void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  89
  90         void (*init_hw)(struct dc *dc);
  91
  92         void (*init_pipes)(struct dc *dc, struct dc_state *context);
  93
  94         enum dc_status (*apply_ctx_to_hw)(
  95                         struct dc *dc, struct dc_state *context);
  96
  97         void (*reset_hw_ctx_wrap)(
  98                         struct dc *dc, struct dc_state *context);
  99
 100         void (*apply_ctx_for_surface)(
 101                         struct dc *dc,
 102                         const struct dc_stream_state *stream,
 103                         int num_planes,
 104                         struct dc_state *context);
 105
 106         void (*program_gamut_remap)(
 107                         struct pipe_ctx *pipe_ctx);
 108
 109         void (*program_output_csc)(struct dc *dc,
 110                         struct pipe_ctx *pipe_ctx,
 111                         enum dc_color_space colorspace,
 112                         uint16_t *matrix,
 113                         int opp_id);
 114
 115 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 116         void (*program_triplebuffer)(
 117                 const struct dc *dc,
 118                 struct pipe_ctx *pipe_ctx,
 119                 bool enableTripleBuffer);
 120         void (*set_flip_control_gsl)(
 121                 struct pipe_ctx *pipe_ctx,
 122                 bool flip_immediate);
 123 #endif
 124
 125         void (*update_plane_addr)(
 126                 const struct dc *dc,
 127                 struct pipe_ctx *pipe_ctx);
 128
 129         void (*plane_atomic_disconnect)(
 130                 struct dc *dc,
 131                 struct pipe_ctx *pipe_ctx);
 132
 133         void (*update_dchub)(
 134                 struct dce_hwseq *hws,
 135                 struct dchub_init_data *dh_data);
 136
 137 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 138         int (*init_sys_ctx)(
 139                         struct dce_hwseq *hws,
 140                         struct dc *dc,
 141                         struct dc_phy_addr_space_config *pa_config);
 142         void (*init_vm_ctx)(
 143                         struct dce_hwseq *hws,
 144                         struct dc *dc,
 145                         struct dc_virtual_addr_space_config *va_config,
 146                         int vmid);
 147 #endif
 148         void (*update_mpcc)(
 149                 struct dc *dc,
 150                 struct pipe_ctx *pipe_ctx);
 151
 152         void (*update_pending_status)(
 153                         struct pipe_ctx *pipe_ctx);
 154
 155         bool (*set_input_transfer_func)(
 156                                 struct pipe_ctx *pipe_ctx,
 157                                 const struct dc_plane_state *plane_state);
 158
 159         bool (*set_output_transfer_func)(
 160                                 struct pipe_ctx *pipe_ctx,
 161                                 const struct dc_stream_state *stream);
 162
 163         void (*power_down)(struct dc *dc);
 164
 165         void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
 166
 167         void (*enable_timing_synchronization)(
 168                         struct dc *dc,
 169                         int group_index,
 170                         int group_size,
 171                         struct pipe_ctx *grouped_pipes[]);
 172
 173         void (*enable_per_frame_crtc_position_reset)(
 174                         struct dc *dc,
 175                         int group_size,
 176                         struct pipe_ctx *grouped_pipes[]);
 177
 178         void (*enable_display_pipe_clock_gating)(
 179                                         struct dc_context *ctx,
 180                                         bool clock_gating);
 181
 182         bool (*enable_display_power_gating)(
 183                                         struct dc *dc,
 184                                         uint8_t controller_id,
 185                                         struct dc_bios *dcb,
 186                                         enum pipe_gating_control power_gating);
 187
 188         void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 189
 190         void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
 191
 192         void (*send_immediate_sdp_message)(
 193                                 struct pipe_ctx *pipe_ctx,
 194                                 const uint8_t *custom_sdp_message,
 195                                 unsigned int sdp_message_size);
 196
 197         void (*enable_stream)(struct pipe_ctx *pipe_ctx);
 198
 199         void (*disable_stream)(struct pipe_ctx *pipe_ctx,
 200                         int option);
 201
 202         void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
 203                         struct dc_link_settings *link_settings);
 204
 205         void (*blank_stream)(struct pipe_ctx *pipe_ctx);
 206
 207         void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
 208
 209         void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx, int option);
 210
 211         void (*pipe_control_lock)(
 212                                 struct dc *dc,
 213                                 struct pipe_ctx *pipe,
 214                                 bool lock);
 215
 216         void (*pipe_control_lock_global)(
 217                                 struct dc *dc,
 218                                 struct pipe_ctx *pipe,
 219                                 bool lock);
 220         void (*blank_pixel_data)(
 221                         struct dc *dc,
 222                         struct pipe_ctx *pipe_ctx,
 223                         bool blank);
 224
 225         void (*prepare_bandwidth)(
 226                         struct dc *dc,
 227                         struct dc_state *context);
 228         void (*optimize_bandwidth)(
 229                         struct dc *dc,
 230                         struct dc_state *context);
 231
 232 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 233         bool (*update_bandwidth)(
 234                         struct dc *dc,
 235                         struct dc_state *context);
 236         void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
 237         bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
 238 #endif
 239
 240         void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
 241                         int vmin, int vmax);
 242
 243         void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
 244                         struct crtc_position *position);
 245
 246         void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
 247                         int num_pipes, const struct dc_static_screen_events *events);
 248
 249         enum dc_status (*enable_stream_timing)(
 250                         struct pipe_ctx *pipe_ctx,
 251                         struct dc_state *context,
 252                         struct dc *dc);
 253
 254         void (*setup_stereo)(
 255                         struct pipe_ctx *pipe_ctx,
 256                         struct dc *dc);
 257
 258         void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
 259
 260         void (*log_hw_state)(struct dc *dc,
 261                 struct dc_log_buffer_ctx *log_ctx);
 262         void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);
 263         void (*clear_status_bits)(struct dc *dc, unsigned int mask);
 264
 265         void (*wait_for_mpcc_disconnect)(struct dc *dc,
 266                         struct resource_pool *res_pool,
 267                         struct pipe_ctx *pipe_ctx);
 268
 269         void (*edp_power_control)(
 270                         struct dc_link *link,
 271                         bool enable);
 272         void (*edp_backlight_control)(
 273                         struct dc_link *link,
 274                         bool enable);
 275         void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
 276
 277         void (*set_cursor_position)(struct pipe_ctx *pipe);
 278         void (*set_cursor_attribute)(struct pipe_ctx *pipe);
 279         void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
 280
 281         void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
 282         void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
 283         bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 284
 285         void (*init_blank)(struct dc *dc, struct timing_generator *tg);
 286         void (*disable_vga)(struct dce_hwseq *hws);
 287         void (*bios_golden_init)(struct dc *dc);
 288         void (*plane_atomic_power_down)(struct dc *dc,
 289                         struct dpp *dpp,
 290                         struct hubp *hubp);
 291
 292         void (*plane_atomic_disable)(
 293                         struct dc *dc, struct pipe_ctx *pipe_ctx);
 294
 295         void (*enable_power_gating_plane)(
 296                 struct dce_hwseq *hws,
 297                 bool enable);
 298
 299         void (*dpp_pg_control)(
 300                         struct dce_hwseq *hws,
 301                         unsigned int dpp_inst,
 302                         bool power_on);
 303
 304         void (*hubp_pg_control)(
 305                         struct dce_hwseq *hws,
 306                         unsigned int hubp_inst,
 307                         bool power_on);
 308
 309         void (*dsc_pg_control)(
 310                         struct dce_hwseq *hws,
 311                         unsigned int dsc_inst,
 312                         bool power_on);
 313
 314
 315 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 316         void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
 317         void (*program_all_writeback_pipes_in_tree)(
 318                         struct dc *dc,
 319                         const struct dc_stream_state *stream,
 320                         struct dc_state *context);
 321         void (*update_writeback)(struct dc *dc,
 322                         const struct dc_stream_status *stream_status,
 323                         struct dc_writeback_info *wb_info);
 324         void (*enable_writeback)(struct dc *dc,
 325                         const struct dc_stream_status *stream_status,
 326                         struct dc_writeback_info *wb_info);
 327         void (*disable_writeback)(struct dc *dc,
 328                         unsigned int dwb_pipe_inst);
 329 #endif
 330         enum dc_status (*set_clock)(struct dc *dc,
 331                         enum dc_clock_type clock_type,
 332                         uint32_t clk_khz,
 333                         uint32_t stepping);
 334
 335         void (*get_clock)(struct dc *dc,
 336                         enum dc_clock_type clock_type,
 337                         struct dc_clock_config *clock_cfg);
 338
 339 };
 340
 341 void color_space_to_black_color(
 342         const struct dc *dc,
 343         enum dc_color_space colorspace,
 344         struct tg_color *black_color);
 345
 346 bool hwss_wait_for_blank_complete(
 347                 struct timing_generator *tg);
 348
 349 const uint16_t *find_color_matrix(
 350                 enum dc_color_space color_space,
 351                 uint32_t *array_size);
 352
 353 #endif /* __DC_HW_SEQUENCER_H__ */