1 /* Copyright © 2022 Advanced Micro Devices, Inc. All rights reserved. */
3 #ifndef __DAL_CURSOR_CACHE_H__
4 #define __DAL_CURSOR_CACHE_H__
6 union reg_cursor_control_cfg {
8 uint32_t cur_enable: 1;
10 uint32_t cur_2x_magnify: 1;
16 uint32_t line_per_chunk: 5;
21 struct cursor_position_cache_hubp {
22 union reg_cursor_control_cfg cur_ctl;
23 union reg_position_cfg {
30 union reg_hot_spot_cfg {
37 union reg_dst_offset_cfg {
39 uint32_t dst_x_offset: 13;
40 uint32_t reserved: 19;
46 struct cursor_attribute_cache_hubp {
47 uint32_t SURFACE_ADDR_HIGH;
48 uint32_t SURFACE_ADDR;
49 union reg_cursor_control_cfg cur_ctl;
50 union reg_cursor_size_cfg {
57 union reg_cursor_settings_cfg {
59 uint32_t dst_y_offset: 8;
60 uint32_t chunk_hdl_adjust: 2;
61 uint32_t reserved: 22;
74 union reg_cur0_control_cfg {
76 uint32_t cur0_enable: 1;
77 uint32_t expansion_mode: 1;
79 uint32_t cur0_rom_en: 1;
81 uint32_t reserved: 25;
85 struct cursor_position_cache_dpp {
86 union reg_cur0_control_cfg cur0_ctl;
89 struct cursor_attribute_cache_dpp {
90 union reg_cur0_control_cfg cur0_ctl;
93 struct cursor_attributes_cfg {
94 struct cursor_attribute_cache_hubp aHubp;
95 struct cursor_attribute_cache_dpp aDpp;