drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corp
   4  *
   5  * Author:
   6  * Manasi Navare <manasi.d.navare@intel.com>
   7  */
   8
   9 /* DC versions of linux includes */
  10 #include <include/drm_dsc_dc.h>
  11
  12 #define EXPORT_SYMBOL(symbol)   /* nothing */
  13 #define BUILD_BUG_ON(cond)      /* nothing */
  14 #define DIV_ROUND_UP(a, b)      (((b) + (a) - 1) / (b))
  15 #define ERANGE                  -1
  16 #define DRM_DEBUG_KMS(msg)      /* nothing */
  17 #define cpu_to_be16(__x) little_to_big(__x)
  18 #define MAX(x, y)               ((x) > (y) ? (x) : (y))
  19
  20 static unsigned short little_to_big(int data)
  21 {
  22         /* Swap lower and upper byte. DMCU uses big endian format. */
  23         return (0xff & (data >> 8)) + ((data & 0xff) << 8);
  24 }
  25
  26 /*
  27  * Everything below this comment was copied directly from drm_dsc.c.
  28  * Only the functions needed in DC are included.
  29  * Please keep this file synced with upstream.
  30  */
  31
  32 /**
  33  * DOC: dsc helpers
  34  *
  35  * These functions contain some common logic and helpers to deal with VESA
  36  * Display Stream Compression standard required for DSC on Display Port/eDP or
  37  * MIPI display interfaces.
  38  */
  39
  40 /**
  41  * drm_dsc_pps_payload_pack() - Populates the DSC PPS
  42  *
  43  * @pps_payload:
  44  * Bitwise struct for DSC Picture Parameter Set. This is defined
  45  * by &struct drm_dsc_picture_parameter_set
  46  * @dsc_cfg:
  47  * DSC Configuration data filled by driver as defined by
  48  * &struct drm_dsc_config
  49  *
  50  * DSC source device sends a picture parameter set (PPS) containing the
  51  * information required by the sink to decode the compressed frame. Driver
  52  * populates the DSC PPS struct using the DSC configuration parameters in
  53  * the order expected by the DSC Display Sink device. For the DSC, the sink
  54  * device expects the PPS payload in big endian format for fields
  55  * that span more than 1 byte.
  56  */
  57 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
  58                                 const struct drm_dsc_config *dsc_cfg)
  59 {
  60         int i;
  61
  62         /* Protect against someone accidently changing struct size */
  63         BUILD_BUG_ON(sizeof(*pps_payload) !=
  64                      DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
  65
  66         memset(pps_payload, 0, sizeof(*pps_payload));
  67
  68         /* PPS 0 */
  69         pps_payload->dsc_version =
  70                 dsc_cfg->dsc_version_minor |
  71                 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
  72
  73         /* PPS 1, 2 is 0 */
  74
  75         /* PPS 3 */
  76         pps_payload->pps_3 =
  77                 dsc_cfg->line_buf_depth |
  78                 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
  79
  80         /* PPS 4 */
  81         pps_payload->pps_4 =
  82                 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
  83                  DSC_PPS_MSB_SHIFT) |
  84                 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
  85                 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
  86                 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
  87                 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
  88
  89         /* PPS 5 */
  90         pps_payload->bits_per_pixel_low =
  91                 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
  92
  93         /*
  94          * The DSC panel expects the PPS packet to have big endian format
  95          * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
  96          * to big endian format. If format is little endian, it will swap
  97          * bytes to convert to Big endian else keep it unchanged.
  98          */
  99
 100         /* PPS 6, 7 */
 101         pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
 102
 103         /* PPS 8, 9 */
 104         pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
 105
 106         /* PPS 10, 11 */
 107         pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
 108
 109         /* PPS 12, 13 */
 110         pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
 111
 112         /* PPS 14, 15 */
 113         pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
 114
 115         /* PPS 16 */
 116         pps_payload->initial_xmit_delay_high =
 117                 ((dsc_cfg->initial_xmit_delay &
 118                   DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
 119                  DSC_PPS_MSB_SHIFT);
 120
 121         /* PPS 17 */
 122         pps_payload->initial_xmit_delay_low =
 123                 (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
 124
 125         /* PPS 18, 19 */
 126         pps_payload->initial_dec_delay =
 127                 cpu_to_be16(dsc_cfg->initial_dec_delay);
 128
 129         /* PPS 20 is 0 */
 130
 131         /* PPS 21 */
 132         pps_payload->initial_scale_value =
 133                 dsc_cfg->initial_scale_value;
 134
 135         /* PPS 22, 23 */
 136         pps_payload->scale_increment_interval =
 137                 cpu_to_be16(dsc_cfg->scale_increment_interval);
 138
 139         /* PPS 24 */
 140         pps_payload->scale_decrement_interval_high =
 141                 ((dsc_cfg->scale_decrement_interval &
 142                   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
 143                  DSC_PPS_MSB_SHIFT);
 144
 145         /* PPS 25 */
 146         pps_payload->scale_decrement_interval_low =
 147                 (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
 148
 149         /* PPS 26[7:0], PPS 27[7:5] RESERVED */
 150
 151         /* PPS 27 */
 152         pps_payload->first_line_bpg_offset =
 153                 dsc_cfg->first_line_bpg_offset;
 154
 155         /* PPS 28, 29 */
 156         pps_payload->nfl_bpg_offset =
 157                 cpu_to_be16(dsc_cfg->nfl_bpg_offset);
 158
 159         /* PPS 30, 31 */
 160         pps_payload->slice_bpg_offset =
 161                 cpu_to_be16(dsc_cfg->slice_bpg_offset);
 162
 163         /* PPS 32, 33 */
 164         pps_payload->initial_offset =
 165                 cpu_to_be16(dsc_cfg->initial_offset);
 166
 167         /* PPS 34, 35 */
 168         pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
 169
 170         /* PPS 36 */
 171         pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
 172
 173         /* PPS 37 */
 174         pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
 175
 176         /* PPS 38, 39 */
 177         pps_payload->rc_model_size =
 178                 cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
 179
 180         /* PPS 40 */
 181         pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
 182
 183         /* PPS 41 */
 184         pps_payload->rc_quant_incr_limit0 =
 185                 dsc_cfg->rc_quant_incr_limit0;
 186
 187         /* PPS 42 */
 188         pps_payload->rc_quant_incr_limit1 =
 189                 dsc_cfg->rc_quant_incr_limit1;
 190
 191         /* PPS 43 */
 192         pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
 193                 DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
 194
 195         /* PPS 44 - 57 */
 196         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
 197                 pps_payload->rc_buf_thresh[i] =
 198                         dsc_cfg->rc_buf_thresh[i];
 199
 200         /* PPS 58 - 87 */
 201         /*
 202          * For DSC sink programming the RC Range parameter fields
 203          * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
 204          */
 205         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 206                 pps_payload->rc_range_parameters[i] =
 207                         ((dsc_cfg->rc_range_params[i].range_min_qp <<
 208                           DSC_PPS_RC_RANGE_MINQP_SHIFT) |
 209                          (dsc_cfg->rc_range_params[i].range_max_qp <<
 210                           DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
 211                          (dsc_cfg->rc_range_params[i].range_bpg_offset));
 212                 pps_payload->rc_range_parameters[i] =
 213                         cpu_to_be16(pps_payload->rc_range_parameters[i]);
 214         }
 215
 216         /* PPS 88 */
 217         pps_payload->native_422_420 = dsc_cfg->native_422 |
 218                 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
 219
 220         /* PPS 89 */
 221         pps_payload->second_line_bpg_offset =
 222                 dsc_cfg->second_line_bpg_offset;
 223
 224         /* PPS 90, 91 */
 225         pps_payload->nsl_bpg_offset =
 226                 cpu_to_be16(dsc_cfg->nsl_bpg_offset);
 227
 228         /* PPS 92, 93 */
 229         pps_payload->second_line_offset_adj =
 230                 cpu_to_be16(dsc_cfg->second_line_offset_adj);
 231
 232         /* PPS 94 - 127 are O */
 233 }
 234 EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
 235
 236 static int compute_offset(struct drm_dsc_config *vdsc_cfg, int pixels_per_group,
 237                                 int groups_per_line, int grpcnt)
 238 {
 239         int offset = 0;
 240         int grpcnt_id = DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay, pixels_per_group);
 241
 242         if (grpcnt <= grpcnt_id)
 243                 offset = DIV_ROUND_UP(grpcnt * pixels_per_group * vdsc_cfg->bits_per_pixel, 16);
 244         else
 245                 offset = DIV_ROUND_UP(grpcnt_id * pixels_per_group * vdsc_cfg->bits_per_pixel, 16)
 246                         - (((grpcnt - grpcnt_id) * vdsc_cfg->slice_bpg_offset) >> 11);
 247
 248         if (grpcnt <= groups_per_line)
 249                 offset += grpcnt * vdsc_cfg->first_line_bpg_offset;
 250         else
 251                 offset += groups_per_line * vdsc_cfg->first_line_bpg_offset
 252                         - (((grpcnt - groups_per_line) * vdsc_cfg->nfl_bpg_offset) >> 11);
 253
 254         if (vdsc_cfg->native_420) {
 255                 if (grpcnt <= groups_per_line)
 256                         offset -= (grpcnt * vdsc_cfg->nsl_bpg_offset) >> 11;
 257                 else if (grpcnt <= 2 * groups_per_line)
 258                         offset += (grpcnt - groups_per_line) * vdsc_cfg->second_line_bpg_offset
 259                                 - ((groups_per_line * vdsc_cfg->nsl_bpg_offset) >> 11);
 260                 else
 261                         offset += (grpcnt - groups_per_line) * vdsc_cfg->second_line_bpg_offset
 262                                 - (((grpcnt - groups_per_line) * vdsc_cfg->nsl_bpg_offset) >> 11);
 263         }
 264
 265         return offset;
 266 }
 267
 268 /**
 269  * drm_dsc_compute_rc_parameters() - Write rate control
 270  * parameters to the dsc configuration defined in
 271  * &struct drm_dsc_config in accordance with the DSC 1.2
 272  * specification. Some configuration fields must be present
 273  * beforehand.
 274  *
 275  * @vdsc_cfg:
 276  * DSC Configuration data partially filled by driver
 277  */
 278 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
 279 {
 280         unsigned long groups_per_line = 0;
 281         unsigned long groups_total = 0;
 282         unsigned long num_extra_mux_bits = 0;
 283         unsigned long slice_bits = 0;
 284         unsigned long hrd_delay = 0;
 285         unsigned long final_scale = 0;
 286         unsigned long rbs_min = 0;
 287         unsigned long max_offset = 0;
 288
 289         if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
 290                 /* Number of groups used to code each line of a slice */
 291                 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
 292                                                DSC_RC_PIXELS_PER_GROUP);
 293
 294                 /* chunksize in Bytes */
 295                 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
 296                                                           vdsc_cfg->bits_per_pixel,
 297                                                           (8 * 16));
 298         } else {
 299                 /* Number of groups used to code each line of a slice */
 300                 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
 301                                                DSC_RC_PIXELS_PER_GROUP);
 302
 303                 /* chunksize in Bytes */
 304                 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
 305                                                           vdsc_cfg->bits_per_pixel,
 306                                                           (8 * 16));
 307         }
 308
 309         if (vdsc_cfg->convert_rgb)
 310                 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
 311                                           (4 * vdsc_cfg->bits_per_component + 4)
 312                                           - 2);
 313         else if (vdsc_cfg->native_422)
 314                 num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
 315                         (4 * vdsc_cfg->bits_per_component + 4) +
 316                         3 * (4 * vdsc_cfg->bits_per_component) - 2;
 317         else
 318                 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
 319                         (4 * vdsc_cfg->bits_per_component + 4) +
 320                         2 * (4 * vdsc_cfg->bits_per_component) - 2;
 321         /* Number of bits in one Slice */
 322         slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
 323
 324         while ((num_extra_mux_bits > 0) &&
 325                ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
 326                 num_extra_mux_bits--;
 327
 328         if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
 329                 vdsc_cfg->initial_scale_value = groups_per_line + 8;
 330
 331         /* scale_decrement_interval calculation according to DSC spec 1.11 */
 332         if (vdsc_cfg->initial_scale_value > 8)
 333                 vdsc_cfg->scale_decrement_interval = groups_per_line /
 334                         (vdsc_cfg->initial_scale_value - 8);
 335         else
 336                 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
 337
 338         vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
 339                 (vdsc_cfg->initial_xmit_delay *
 340                  vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
 341
 342         if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
 343                 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
 344                 return -ERANGE;
 345         }
 346
 347         final_scale = (vdsc_cfg->rc_model_size * 8) /
 348                 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
 349         if (vdsc_cfg->slice_height > 1)
 350                 /*
 351                  * NflBpgOffset is 16 bit value with 11 fractional bits
 352                  * hence we multiply by 2^11 for preserving the
 353                  * fractional part
 354                  */
 355                 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
 356                                                         (vdsc_cfg->slice_height - 1));
 357         else
 358                 vdsc_cfg->nfl_bpg_offset = 0;
 359
 360         /* 2^16 - 1 */
 361         if (vdsc_cfg->nfl_bpg_offset > 65535) {
 362                 DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
 363                 return -ERANGE;
 364         }
 365
 366         if (vdsc_cfg->slice_height > 2)
 367                 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->second_line_bpg_offset << 11),
 368                                                         (vdsc_cfg->slice_height - 1));
 369         else
 370                 vdsc_cfg->nsl_bpg_offset = 0;
 371
 372         if (vdsc_cfg->nsl_bpg_offset > 65535) {
 373                 DRM_DEBUG_KMS("NslBpgOffset is too large for this slice height\n");
 374                 return -ERANGE;
 375         }
 376
 377         /* Number of groups used to code the entire slice */
 378         groups_total = groups_per_line * vdsc_cfg->slice_height;
 379
 380         /* slice_bpg_offset is 16 bit value with 11 fractional bits */
 381         vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
 382                                                     vdsc_cfg->initial_offset +
 383                                                     num_extra_mux_bits) << 11),
 384                                                   groups_total);
 385
 386         if (final_scale > 9) {
 387                 /*
 388                  * ScaleIncrementInterval =
 389                  * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
 390                  * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
 391                  * we need divide by 2^11 from pstDscCfg values
 392                  */
 393                 vdsc_cfg->scale_increment_interval =
 394                                 (vdsc_cfg->final_offset * (1 << 11)) /
 395                                 ((vdsc_cfg->nfl_bpg_offset +
 396                                 vdsc_cfg->nsl_bpg_offset +
 397                                 vdsc_cfg->slice_bpg_offset) *
 398                                 (final_scale - 9));
 399         } else {
 400                 /*
 401                  * If finalScaleValue is less than or equal to 9, a value of 0 should
 402                  * be used to disable the scale increment at the end of the slice
 403                  */
 404                 vdsc_cfg->scale_increment_interval = 0;
 405         }
 406
 407         if (vdsc_cfg->scale_increment_interval > 65535) {
 408                 DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
 409                 return -ERANGE;
 410         }
 411
 412         /*
 413          * DSC spec mentions that bits_per_pixel specifies the target
 414          * bits/pixel (bpp) rate that is used by the encoder,
 415          * in steps of 1/16 of a bit per pixel
 416          */
 417         if (vdsc_cfg->dsc_version_minor == 2 && (vdsc_cfg->native_420 || vdsc_cfg->native_422)) {
 418
 419                 max_offset = compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
 420                                         DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
 421                                                 DSC_RC_PIXELS_PER_GROUP));
 422
 423                 max_offset = MAX(max_offset,
 424                                 compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
 425                                         DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
 426                                                 groups_per_line)));
 427
 428                 max_offset = MAX(max_offset,
 429                                 compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
 430                                         DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
 431                                                 groups_per_line * 2)));
 432
 433                 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + max_offset;
 434         } else {
 435                 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
 436                         DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
 437                                      vdsc_cfg->bits_per_pixel, 16) +
 438                         groups_per_line * vdsc_cfg->first_line_bpg_offset;
 439         }
 440
 441         hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
 442         vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
 443         vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
 444
 445         return 0;
 446 }
 447 EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);