drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #ifndef __DML2_DISPLAY_MODE_VBA_H__
  28 #define __DML2_DISPLAY_MODE_VBA_H__
  29
  30 struct display_mode_lib;
  31
  32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
  33
  34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
  35
  36 dml_get_attr_decl(clk_dcf_deepsleep);
  37 dml_get_attr_decl(wm_urgent);
  38 dml_get_attr_decl(wm_memory_trip);
  39 dml_get_attr_decl(wm_writeback_urgent);
  40 dml_get_attr_decl(wm_stutter_exit);
  41 dml_get_attr_decl(wm_stutter_enter_exit);
  42 dml_get_attr_decl(wm_z8_stutter_exit);
  43 dml_get_attr_decl(wm_z8_stutter_enter_exit);
  44 dml_get_attr_decl(stutter_efficiency_z8);
  45 dml_get_attr_decl(stutter_num_bursts_z8);
  46 dml_get_attr_decl(wm_dram_clock_change);
  47 dml_get_attr_decl(wm_writeback_dram_clock_change);
  48 dml_get_attr_decl(stutter_efficiency_no_vblank);
  49 dml_get_attr_decl(stutter_efficiency);
  50 dml_get_attr_decl(stutter_period);
  51 dml_get_attr_decl(urgent_latency);
  52 dml_get_attr_decl(urgent_extra_latency);
  53 dml_get_attr_decl(nonurgent_latency);
  54 dml_get_attr_decl(dram_clock_change_latency);
  55 dml_get_attr_decl(dispclk_calculated);
  56 dml_get_attr_decl(total_data_read_bw);
  57 dml_get_attr_decl(return_bw);
  58 dml_get_attr_decl(tcalc);
  59 dml_get_attr_decl(fraction_of_urgent_bandwidth);
  60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
  61 dml_get_attr_decl(cstate_max_cap_mode);
  62 dml_get_attr_decl(comp_buffer_size_kbytes);
  63 dml_get_attr_decl(pixel_chunk_size_in_kbyte);
  64 dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
  65 dml_get_attr_decl(meta_chunk_size_in_kbyte);
  66 dml_get_attr_decl(min_pixel_chunk_size_in_byte);
  67 dml_get_attr_decl(min_meta_chunk_size_in_byte);
  68 dml_get_attr_decl(fclk_watermark);
  69 dml_get_attr_decl(usr_retraining_watermark);
  70
  71 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
  72
  73 dml_get_pipe_attr_decl(dsc_delay);
  74 dml_get_pipe_attr_decl(dppclk_calculated);
  75 dml_get_pipe_attr_decl(dscclk_calculated);
  76 dml_get_pipe_attr_decl(min_ttu_vblank);
  77 dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
  78 dml_get_pipe_attr_decl(vratio_prefetch_l);
  79 dml_get_pipe_attr_decl(vratio_prefetch_c);
  80 dml_get_pipe_attr_decl(dst_x_after_scaler);
  81 dml_get_pipe_attr_decl(dst_y_after_scaler);
  82 dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
  83 dml_get_pipe_attr_decl(dst_y_per_row_vblank);
  84 dml_get_pipe_attr_decl(dst_y_prefetch);
  85 dml_get_pipe_attr_decl(dst_y_per_vm_flip);
  86 dml_get_pipe_attr_decl(dst_y_per_row_flip);
  87 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
  88 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
  89 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
  90 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
  91 dml_get_pipe_attr_decl(dpte_row_height_linear_c);
  92 dml_get_pipe_attr_decl(swath_height_l);
  93 dml_get_pipe_attr_decl(swath_height_c);
  94 dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
  95 dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
  96 dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
  97 dml_get_pipe_attr_decl(vm_group_size_in_bytes);
  98 dml_get_pipe_attr_decl(det_buffer_size_kbytes);
  99 dml_get_pipe_attr_decl(dpte_row_height_linear_l);
 100 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
 101 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
 102 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
 103 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
 104 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
 105 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
 106 dml_get_pipe_attr_decl(pte_buffer_mode);
 107 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
 108 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
 109 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
 110 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
 111 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us);
 112 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us);
 113 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us);
 114 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us);
 115 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us);
 116 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us);
 117 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us);
 118 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us);
 119 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us);
 120 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us);
 121 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us);
 122 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us);
 123 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us);
 124 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us);
 125 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us);
 126 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us);
 127 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us);
 128 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us);
 129 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us);
 130 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us);
 131 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);
 132 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);
 133
 134 dml_get_pipe_attr_decl(vstartup);
 135 dml_get_pipe_attr_decl(vupdate_offset);
 136 dml_get_pipe_attr_decl(vupdate_width);
 137 dml_get_pipe_attr_decl(vready_offset);
 138 dml_get_pipe_attr_decl(vready_at_or_after_vsync);
 139 dml_get_pipe_attr_decl(min_dst_y_next_start);
 140 dml_get_pipe_attr_decl(vstartup_calculated);
 141 dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
 142
 143 double get_total_immediate_flip_bytes(
 144                 struct display_mode_lib *mode_lib,
 145                 const display_e2e_pipe_params_st *pipes,
 146                 unsigned int num_pipes);
 147 double get_total_immediate_flip_bw(
 148                 struct display_mode_lib *mode_lib,
 149                 const display_e2e_pipe_params_st *pipes,
 150                 unsigned int num_pipes);
 151 double get_total_prefetch_bw(
 152                 struct display_mode_lib *mode_lib,
 153                 const display_e2e_pipe_params_st *pipes,
 154                 unsigned int num_pipes);
 155 unsigned int dml_get_voltage_level(
 156                 struct display_mode_lib *mode_lib,
 157                 const display_e2e_pipe_params_st *pipes,
 158                 unsigned int num_pipes);
 159
 160 unsigned int get_total_surface_size_in_mall_bytes(
 161                 struct display_mode_lib *mode_lib,
 162                 const display_e2e_pipe_params_st *pipes,
 163                 unsigned int num_pipes);
 164 unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx);
 165
 166 bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
 167                 const display_e2e_pipe_params_st *pipes,
 168                 unsigned int num_pipes,
 169                 unsigned int pipe_idx);
 170 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
 171
 172 void Calculate256BBlockSizes(
 173                 enum source_format_class SourcePixelFormat,
 174                 enum dm_swizzle_mode SurfaceTiling,
 175                 unsigned int BytePerPixelY,
 176                 unsigned int BytePerPixelC,
 177                 unsigned int *BlockHeight256BytesY,
 178                 unsigned int *BlockHeight256BytesC,
 179                 unsigned int *BlockWidth256BytesY,
 180                 unsigned int *BlockWidth256BytesC);
 181
 182 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
 183         unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
 184         double dummy_single_array[2][DC__NUM_DPP__MAX];
 185         unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
 186         double dummy_double_array[2][DC__NUM_DPP__MAX];
 187         bool dummy_boolean_array[DC__NUM_DPP__MAX];
 188         bool dummy_boolean;
 189         bool dummy_boolean2;
 190         enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
 191         DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
 192         bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
 193         unsigned int ReorderBytes;
 194         unsigned int VMDataOnlyReturnBW;
 195         double HostVMInefficiencyFactor;
 196 };
 197
 198 struct dml32_ModeSupportAndSystemConfigurationFull {
 199         unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
 200         double dummy_double_array[2][DC__NUM_DPP__MAX];
 201         DmlPipe SurfParameters[DC__NUM_DPP__MAX];
 202         double dummy_single[5];
 203         double dummy_single2[5];
 204         SOCParametersList mSOCParameters;
 205         unsigned int MaximumSwathWidthSupportLuma;
 206         unsigned int MaximumSwathWidthSupportChroma;
 207         double DSTYAfterScaler[DC__NUM_DPP__MAX];
 208         double DSTXAfterScaler[DC__NUM_DPP__MAX];
 209         double MaxTotalVActiveRDBandwidth;
 210         bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
 211 };
 212
 213 struct dummy_vars {
 214         struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 215         DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
 216         struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
 217 };
 218
 219 struct vba_vars_st {
 220         ip_params_st ip;
 221         soc_bounding_box_st soc;
 222
 223         int maxMpcComb;
 224         bool UseMaximumVStartup;
 225
 226         double WritebackDISPCLK;
 227         double DPPCLKUsingSingleDPPLuma;
 228         double DPPCLKUsingSingleDPPChroma;
 229         double DISPCLKWithRamping;
 230         double DISPCLKWithoutRamping;
 231         double GlobalDPPCLK;
 232         double DISPCLKWithRampingRoundedToDFSGranularity;
 233         double DISPCLKWithoutRampingRoundedToDFSGranularity;
 234         double MaxDispclkRoundedToDFSGranularity;
 235         bool DCCEnabledAnyPlane;
 236         double ReturnBandwidthToDCN;
 237         unsigned int TotalActiveDPP;
 238         unsigned int TotalDCCActiveDPP;
 239         double UrgentRoundTripAndOutOfOrderLatency;
 240         double StutterPeriod;
 241         double FrameTimeForMinFullDETBufferingTime;
 242         double AverageReadBandwidth;
 243         double TotalRowReadBandwidth;
 244         double PartOfBurstThatFitsInROB;
 245         double StutterBurstTime;
 246         unsigned int NextPrefetchMode;
 247         double NextMaxVStartup;
 248         double VBlankTime;
 249         double SmallestVBlank;
 250         enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
 251         double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
 252         double EffectiveDETPlusLBLinesLuma;
 253         double EffectiveDETPlusLBLinesChroma;
 254         double UrgentLatencySupportUsLuma;
 255         double UrgentLatencySupportUsChroma;
 256         unsigned int DSCFormatFactor;
 257
 258         bool DummyPStateCheck;
 259         bool DRAMClockChangeSupportsVActive;
 260         bool PrefetchModeSupported;
 261         bool PrefetchAndImmediateFlipSupported;
 262         enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
 263         double XFCRemoteSurfaceFlipDelay;
 264         double TInitXFill;
 265         double TslvChk;
 266         double SrcActiveDrainRate;
 267         bool ImmediateFlipSupported;
 268         enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
 269
 270         bool PrefetchERROR;
 271
 272         unsigned int VStartupLines;
 273         unsigned int ActiveDPPs;
 274         unsigned int LBLatencyHidingSourceLinesY;
 275         unsigned int LBLatencyHidingSourceLinesC;
 276         double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
 277         double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
 278         double MinActiveDRAMClockChangeMargin;
 279         double InitFillLevel;
 280         double FinalFillMargin;
 281         double FinalFillLevel;
 282         double RemainingFillLevel;
 283         double TFinalxFill;
 284
 285         //
 286         // SOC Bounding Box Parameters
 287         //
 288         double SRExitTime;
 289         double SREnterPlusExitTime;
 290         double UrgentLatencyPixelDataOnly;
 291         double UrgentLatencyPixelMixedWithVMData;
 292         double UrgentLatencyVMDataOnly;
 293         double UrgentLatency; // max of the above three
 294         double USRRetrainingLatency;
 295         double SMNLatency;
 296         double FCLKChangeLatency;
 297         unsigned int MALLAllocatedForDCNFinal;
 298         double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
 299         double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
 300         double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
 301         double WritebackLatency;
 302         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
 303         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
 304         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
 305         double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
 306         double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
 307         double NumberOfChannels;
 308         double DRAMChannelWidth;
 309         double FabricDatapathToDCNDataReturn;
 310         double ReturnBusWidth;
 311         double Downspreading;
 312         double DISPCLKDPPCLKDSCCLKDownSpreading;
 313         double DISPCLKDPPCLKVCOSpeed;
 314         double RoundTripPingLatencyCycles;
 315         double UrgentOutOfOrderReturnPerChannel;
 316         double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
 317         double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
 318         double UrgentOutOfOrderReturnPerChannelVMDataOnly;
 319         unsigned int VMMPageSize;
 320         double DRAMClockChangeLatency;
 321         double XFCBusTransportTime;
 322         bool UseUrgentBurstBandwidth;
 323         double XFCXBUFLatencyTolerance;
 324
 325         //
 326         // IP Parameters
 327         //
 328         unsigned int ROBBufferSizeInKByte;
 329         unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
 330         double DETBufferSizeInTime;
 331         unsigned int DPPOutputBufferPixels;
 332         unsigned int OPPOutputBufferLines;
 333         unsigned int PixelChunkSizeInKByte;
 334         double ReturnBW;
 335         bool GPUVMEnable;
 336         bool HostVMEnable;
 337         unsigned int GPUVMMaxPageTableLevels;
 338         unsigned int HostVMMaxPageTableLevels;
 339         unsigned int HostVMCachedPageTableLevels;
 340         unsigned int OverrideGPUVMPageTableLevels;
 341         unsigned int OverrideHostVMPageTableLevels;
 342         unsigned int MetaChunkSize;
 343         unsigned int MinMetaChunkSizeBytes;
 344         unsigned int WritebackChunkSize;
 345         bool ODMCapability;
 346         unsigned int NumberOfDSC;
 347         unsigned int LineBufferSize;
 348         unsigned int MaxLineBufferLines;
 349         unsigned int WritebackInterfaceLumaBufferSize;
 350         unsigned int WritebackInterfaceChromaBufferSize;
 351         unsigned int WritebackChromaLineBufferWidth;
 352         enum writeback_config WritebackConfiguration;
 353         double MaxDCHUBToPSCLThroughput;
 354         double MaxPSCLToLBThroughput;
 355         unsigned int PTEBufferSizeInRequestsLuma;
 356         unsigned int PTEBufferSizeInRequestsChroma;
 357         double DISPCLKRampingMargin;
 358         unsigned int MaxInterDCNTileRepeaters;
 359         bool XFCSupported;
 360         double XFCSlvChunkSize;
 361         double XFCFillBWOverhead;
 362         double XFCFillConstant;
 363         double XFCTSlvVupdateOffset;
 364         double XFCTSlvVupdateWidth;
 365         double XFCTSlvVreadyOffset;
 366         double DPPCLKDelaySubtotal;
 367         double DPPCLKDelaySCL;
 368         double DPPCLKDelaySCLLBOnly;
 369         double DPPCLKDelayCNVCFormater;
 370         double DPPCLKDelayCNVCCursor;
 371         double DISPCLKDelaySubtotal;
 372         bool ProgressiveToInterlaceUnitInOPP;
 373         unsigned int CompressedBufferSegmentSizeInkByteFinal;
 374         unsigned int CompbufReservedSpace64B;
 375         unsigned int CompbufReservedSpaceZs;
 376         unsigned int LineBufferSizeFinal;
 377         unsigned int MaximumPixelsPerLinePerDSCUnit;
 378         unsigned int AlphaPixelChunkSizeInKByte;
 379         double MinPixelChunkSizeBytes;
 380         unsigned int DCCMetaBufferSizeBytes;
 381         // Pipe/Plane Parameters
 382         int VoltageLevel;
 383         double FabricClock;
 384         double DRAMSpeed;
 385         double DISPCLK;
 386         double SOCCLK;
 387         double DCFCLK;
 388         unsigned int MaxTotalDETInKByte;
 389         unsigned int MinCompressedBufferSizeInKByte;
 390         unsigned int NumberOfActiveSurfaces;
 391         bool ViewportStationary[DC__NUM_DPP__MAX];
 392         unsigned int RefreshRate[DC__NUM_DPP__MAX];
 393         double       OutputBPP[DC__NUM_DPP__MAX];
 394         unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
 395         bool SynchronizeTimingsFinal;
 396         bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
 397         bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
 398         unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
 399         unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
 400         enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
 401         bool DRRDisplay[DC__NUM_DPP__MAX];
 402         bool PteBufferMode[DC__NUM_DPP__MAX];
 403         enum dm_output_type OutputType[DC__NUM_DPP__MAX];
 404         enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
 405
 406         unsigned int NumberOfActivePlanes;
 407         unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
 408         unsigned int ViewportWidth[DC__NUM_DPP__MAX];
 409         unsigned int ViewportHeight[DC__NUM_DPP__MAX];
 410         unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
 411         unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
 412         unsigned int PitchY[DC__NUM_DPP__MAX];
 413         unsigned int PitchC[DC__NUM_DPP__MAX];
 414         double HRatio[DC__NUM_DPP__MAX];
 415         double VRatio[DC__NUM_DPP__MAX];
 416         unsigned int htaps[DC__NUM_DPP__MAX];
 417         unsigned int vtaps[DC__NUM_DPP__MAX];
 418         unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
 419         unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
 420         unsigned int HTotal[DC__NUM_DPP__MAX];
 421         unsigned int VTotal[DC__NUM_DPP__MAX];
 422         unsigned int VTotal_Max[DC__NUM_DPP__MAX];
 423         unsigned int VTotal_Min[DC__NUM_DPP__MAX];
 424         int DPPPerPlane[DC__NUM_DPP__MAX];
 425         double PixelClock[DC__NUM_DPP__MAX];
 426         double PixelClockBackEnd[DC__NUM_DPP__MAX];
 427         bool DCCEnable[DC__NUM_DPP__MAX];
 428         bool FECEnable[DC__NUM_DPP__MAX];
 429         unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
 430         unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
 431         enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
 432         enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
 433         bool WritebackEnable[DC__NUM_DPP__MAX];
 434         unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
 435         double WritebackDestinationWidth[DC__NUM_DPP__MAX];
 436         double WritebackDestinationHeight[DC__NUM_DPP__MAX];
 437         double WritebackSourceHeight[DC__NUM_DPP__MAX];
 438         enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
 439         unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
 440         unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
 441         unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
 442         unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
 443         double WritebackHRatio[DC__NUM_DPP__MAX];
 444         double WritebackVRatio[DC__NUM_DPP__MAX];
 445         unsigned int HActive[DC__NUM_DPP__MAX];
 446         unsigned int VActive[DC__NUM_DPP__MAX];
 447         bool Interlace[DC__NUM_DPP__MAX];
 448         enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
 449         unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
 450         bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
 451         int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
 452         unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
 453         double DCCRate[DC__NUM_DPP__MAX];
 454         double AverageDCCCompressionRate;
 455         enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
 456         double OutputBpp[DC__NUM_DPP__MAX];
 457         bool DSCEnabled[DC__NUM_DPP__MAX];
 458         unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
 459         enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
 460         enum output_encoder_class Output[DC__NUM_DPP__MAX];
 461         bool skip_dio_check[DC__NUM_DPP__MAX];
 462         unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
 463         bool SynchronizedVBlank;
 464         unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
 465         unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 466         unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 467         bool XFCEnabled[DC__NUM_DPP__MAX];
 468         bool ScalerEnabled[DC__NUM_DPP__MAX];
 469         unsigned int VBlankNom[DC__NUM_DPP__MAX];
 470
 471         // Intermediates/Informational
 472         bool ImmediateFlipSupport;
 473         unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
 474         unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
 475         unsigned int SwathHeightY[DC__NUM_DPP__MAX];
 476         unsigned int SwathHeightC[DC__NUM_DPP__MAX];
 477         unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
 478         double LastPixelOfLineExtraWatermark;
 479         double TotalDataReadBandwidth;
 480         unsigned int TotalActiveWriteback;
 481         unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
 482         unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
 483         double BandwidthAvailableForImmediateFlip;
 484         unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
 485         unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
 486         unsigned int MinPrefetchMode;
 487         unsigned int MaxPrefetchMode;
 488         bool AnyLinesForVMOrRowTooLarge;
 489         double MaxVStartup;
 490         bool IgnoreViewportPositioning;
 491         bool ErrorResult[DC__NUM_DPP__MAX];
 492         //
 493         // Calculated dml_ml->vba.Outputs
 494         //
 495         double DCFCLKDeepSleep;
 496         double UrgentWatermark;
 497         double UrgentExtraLatency;
 498         double WritebackUrgentWatermark;
 499         double StutterExitWatermark;
 500         double StutterEnterPlusExitWatermark;
 501         double DRAMClockChangeWatermark;
 502         double WritebackDRAMClockChangeWatermark;
 503         double StutterEfficiency;
 504         double StutterEfficiencyNotIncludingVBlank;
 505         double NonUrgentLatencyTolerance;
 506         double MinActiveDRAMClockChangeLatencySupported;
 507         double Z8StutterEfficiencyBestCase;
 508         unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
 509         double Z8StutterEfficiencyNotIncludingVBlankBestCase;
 510         double StutterPeriodBestCase;
 511         Watermarks      Watermark;
 512         bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
 513
 514         // These are the clocks calcuated by the library but they are not actually
 515         // used explicitly. They are fetched by tests and then possibly used. The
 516         // ultimate values to use are the ones specified by the parameters to DML
 517         double DISPCLK_calculated;
 518         double DPPCLK_calculated[DC__NUM_DPP__MAX];
 519
 520         bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
 521
 522         bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
 523         bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
 524         unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
 525         double VUpdateWidthPix[DC__NUM_DPP__MAX];
 526         double VReadyOffsetPix[DC__NUM_DPP__MAX];
 527
 528         unsigned int TotImmediateFlipBytes;
 529         double TCalc;
 530
 531         display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
 532         unsigned int cache_num_pipes;
 533         unsigned int pipe_plane[DC__NUM_DPP__MAX];
 534
 535         /* vba mode support */
 536         /*inputs*/
 537         bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
 538         double MaxHSCLRatio;
 539         double MaxVSCLRatio;
 540         unsigned int MaxNumWriteback;
 541         bool WritebackLumaAndChromaScalingSupported;
 542         bool Cursor64BppSupport;
 543         double DCFCLKPerState[DC__VOLTAGE_STATES];
 544         double DCFCLKState[DC__VOLTAGE_STATES][2];
 545         double FabricClockPerState[DC__VOLTAGE_STATES];
 546         double SOCCLKPerState[DC__VOLTAGE_STATES];
 547         double PHYCLKPerState[DC__VOLTAGE_STATES];
 548         double DTBCLKPerState[DC__VOLTAGE_STATES];
 549         double MaxDppclk[DC__VOLTAGE_STATES];
 550         double MaxDSCCLK[DC__VOLTAGE_STATES];
 551         double DRAMSpeedPerState[DC__VOLTAGE_STATES];
 552         double MaxDispclk[DC__VOLTAGE_STATES];
 553         int VoltageOverrideLevel;
 554         double PHYCLKD32PerState[DC__VOLTAGE_STATES];
 555
 556         /*outputs*/
 557         bool ScaleRatioAndTapsSupport;
 558         bool SourceFormatPixelAndScanSupport;
 559         double TotalBandwidthConsumedGBytePerSecond;
 560         bool DCCEnabledInAnyPlane;
 561         bool WritebackLatencySupport;
 562         bool WritebackModeSupport;
 563         bool Writeback10bpc420Supported;
 564         bool BandwidthSupport[DC__VOLTAGE_STATES];
 565         unsigned int TotalNumberOfActiveWriteback;
 566         double CriticalPoint;
 567         double ReturnBWToDCNPerState;
 568         bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 569         bool prefetch_vm_bw_valid;
 570         bool prefetch_row_bw_valid;
 571         bool NumberOfOTGSupport;
 572         bool NonsupportedDSCInputBPC;
 573         bool WritebackScaleRatioAndTapsSupport;
 574         bool CursorSupport;
 575         bool PitchSupport;
 576         enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
 577
 578         /* Mode Support Reason */
 579         bool P2IWith420;
 580         bool DSCOnlyIfNecessaryWithBPP;
 581         bool DSC422NativeNotSupported;
 582         bool LinkRateDoesNotMatchDPVersion;
 583         bool LinkRateForMultistreamNotIndicated;
 584         bool BPPForMultistreamNotIndicated;
 585         bool MultistreamWithHDMIOreDP;
 586         bool MSOOrODMSplitWithNonDPLink;
 587         bool NotEnoughLanesForMSO;
 588         bool ViewportExceedsSurface;
 589
 590         bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
 591         bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
 592         bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
 593         bool InvalidCombinationOfMALLUseForPState;
 594
 595         enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
 596         double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
 597         double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
 598         double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
 599         double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
 600         double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
 601         double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
 602         double MetaRowBytesThisState[DC__NUM_DPP__MAX];
 603         bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 604         bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 605         bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
 606         bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
 607
 608         unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 609         double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 610         unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
 611         unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
 612         unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
 613         unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
 614         bool ImmediateFlipRequiredFinal;
 615         bool DCCProgrammingAssumesScanDirectionUnknownFinal;
 616         bool EnoughWritebackUnits;
 617         bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
 618         bool NumberOfDP2p0Support;
 619         unsigned int MaxNumDP2p0Streams;
 620         unsigned int MaxNumDP2p0Outputs;
 621         enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 622         enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 623         double WritebackLineBufferLumaBufferSize;
 624         double WritebackLineBufferChromaBufferSize;
 625         double WritebackMinHSCLRatio;
 626         double WritebackMinVSCLRatio;
 627         double WritebackMaxHSCLRatio;
 628         double WritebackMaxVSCLRatio;
 629         double WritebackMaxHSCLTaps;
 630         double WritebackMaxVSCLTaps;
 631         unsigned int MaxNumDPP;
 632         unsigned int MaxNumOTG;
 633         double CursorBufferSize;
 634         double CursorChunkSize;
 635         unsigned int Mode;
 636         double OutputLinkDPLanes[DC__NUM_DPP__MAX];
 637         double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
 638         double ImmediateFlipBW[DC__NUM_DPP__MAX];
 639         double MaxMaxVStartup[DC__VOLTAGE_STATES][2];
 640
 641         double WritebackLumaVExtra;
 642         double WritebackChromaVExtra;
 643         double WritebackRequiredDISPCLK;
 644         double MaximumSwathWidthSupport;
 645         double MaximumSwathWidthInDETBuffer;
 646         double MaximumSwathWidthInLineBuffer;
 647         double MaxDispclkRoundedDownToDFSGranularity;
 648         double MaxDppclkRoundedDownToDFSGranularity;
 649         double PlaneRequiredDISPCLKWithoutODMCombine;
 650         double PlaneRequiredDISPCLKWithODMCombine;
 651         double PlaneRequiredDISPCLK;
 652         double TotalNumberOfActiveOTG;
 653         double FECOverhead;
 654         double EffectiveFECOverhead;
 655         double Outbpp;
 656         unsigned int OutbppDSC;
 657         double TotalDSCUnitsRequired;
 658         double bpp;
 659         unsigned int slices;
 660         double SwathWidthGranularityY;
 661         double RoundedUpMaxSwathSizeBytesY;
 662         double SwathWidthGranularityC;
 663         double RoundedUpMaxSwathSizeBytesC;
 664         double EffectiveDETLBLinesLuma;
 665         double EffectiveDETLBLinesChroma;
 666         double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];
 667         double PDEAndMetaPTEBytesPerFrameY;
 668         double PDEAndMetaPTEBytesPerFrameC;
 669         unsigned int MetaRowBytesY;
 670         unsigned int MetaRowBytesC;
 671         unsigned int DPTEBytesPerRowC;
 672         unsigned int DPTEBytesPerRowY;
 673         double ExtraLatency;
 674         double TimeCalc;
 675         double TWait;
 676         double MaximumReadBandwidthWithPrefetch;
 677         double MaximumReadBandwidthWithoutPrefetch;
 678         double total_dcn_read_bw_with_flip;
 679         double total_dcn_read_bw_with_flip_no_urgent_burst;
 680         double FractionOfUrgentBandwidth;
 681         double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
 682
 683         /* ms locals */
 684         double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
 685         unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 686         int NoOfDPPThisState[DC__NUM_DPP__MAX];
 687         enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 688         double SwathWidthYThisState[DC__NUM_DPP__MAX];
 689         unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 690         unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
 691         unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
 692         double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 693         double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 694         double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 695         double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 696         double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 697         double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
 698         bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 699         bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 700         bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
 701         bool PrefetchSupported[DC__VOLTAGE_STATES][2];
 702         bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
 703         double RequiredDISPCLK[DC__VOLTAGE_STATES][2];
 704         bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
 705         bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
 706         unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];
 707         unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];
 708         bool ModeSupport[DC__VOLTAGE_STATES][2];
 709         double ReturnBWPerState[DC__VOLTAGE_STATES][2];
 710         bool DIOSupport[DC__VOLTAGE_STATES];
 711         bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
 712         bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
 713         bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
 714         double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
 715         bool ROBSupport[DC__VOLTAGE_STATES][2];
 716         //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
 717         bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
 718         bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
 719         bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
 720         double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];
 721         double PrefetchBW[DC__NUM_DPP__MAX];
 722         double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 723         double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 724         double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 725         double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 726         double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 727         unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
 728         unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
 729         double PrefillY[DC__NUM_DPP__MAX];
 730         double PrefillC[DC__NUM_DPP__MAX];
 731         double LineTimesForPrefetch[DC__NUM_DPP__MAX];
 732         double LinesForMetaPTE[DC__NUM_DPP__MAX];
 733         double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
 734         double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
 735         double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
 736         double BytePerPixelInDETY[DC__NUM_DPP__MAX];
 737         double BytePerPixelInDETC[DC__NUM_DPP__MAX];
 738         bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 739         unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 740         double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 741         double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 742         double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 743         bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
 744         unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
 745         unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
 746         unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
 747         unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
 748         double MaxSwathHeightY[DC__NUM_DPP__MAX];
 749         double MaxSwathHeightC[DC__NUM_DPP__MAX];
 750         double MinSwathHeightY[DC__NUM_DPP__MAX];
 751         double MinSwathHeightC[DC__NUM_DPP__MAX];
 752         double ReadBandwidthLuma[DC__NUM_DPP__MAX];
 753         double ReadBandwidthChroma[DC__NUM_DPP__MAX];
 754         double ReadBandwidth[DC__NUM_DPP__MAX];
 755         double WriteBandwidth[DC__NUM_DPP__MAX];
 756         double PSCL_FACTOR[DC__NUM_DPP__MAX];
 757         double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
 758         double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 759         unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
 760         unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
 761         double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
 762         double AlignedYPitch[DC__NUM_DPP__MAX];
 763         double AlignedCPitch[DC__NUM_DPP__MAX];
 764         double MaximumSwathWidth[DC__NUM_DPP__MAX];
 765         double cursor_bw[DC__NUM_DPP__MAX];
 766         double cursor_bw_pre[DC__NUM_DPP__MAX];
 767         double Tno_bw[DC__NUM_DPP__MAX];
 768         double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
 769         double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
 770         double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
 771         double final_flip_bw[DC__NUM_DPP__MAX];
 772         bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
 773         double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 774         unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
 775         unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
 776         unsigned int dpte_row_height[DC__NUM_DPP__MAX];
 777         unsigned int meta_req_height[DC__NUM_DPP__MAX];
 778         unsigned int meta_req_width[DC__NUM_DPP__MAX];
 779         unsigned int meta_row_height[DC__NUM_DPP__MAX];
 780         unsigned int meta_row_width[DC__NUM_DPP__MAX];
 781         unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
 782         unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
 783         unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
 784         unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
 785         unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
 786         bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
 787         double meta_row_bw[DC__NUM_DPP__MAX];
 788         double dpte_row_bw[DC__NUM_DPP__MAX];
 789         double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];                     // WM
 790         double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];                     // WM
 791         double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
 792         double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
 793         enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];
 794         double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
 795         double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
 796         double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
 797         double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
 798         double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
 799         double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
 800
 801
 802         bool           MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 803         double         SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
 804         double         MaximumSwathWidthInLineBufferLuma;
 805         double         MaximumSwathWidthInLineBufferChroma;
 806         double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
 807         double         MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
 808         enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
 809         double         dummy1[DC__NUM_DPP__MAX];
 810         double         dummy2[DC__NUM_DPP__MAX];
 811         unsigned int   dummy3[DC__NUM_DPP__MAX];
 812         unsigned int   dummy4[DC__NUM_DPP__MAX];
 813         double         dummy5;
 814         double         dummy6;
 815         double         dummy7[DC__NUM_DPP__MAX];
 816         double         dummy8[DC__NUM_DPP__MAX];
 817         double         dummy13[DC__NUM_DPP__MAX];
 818         double         dummy_double_array[2][DC__NUM_DPP__MAX];
 819         unsigned int        dummyinteger3[DC__NUM_DPP__MAX];
 820         unsigned int        dummyinteger4[DC__NUM_DPP__MAX];
 821         unsigned int        dummyinteger5;
 822         unsigned int        dummyinteger6;
 823         unsigned int        dummyinteger7;
 824         unsigned int        dummyinteger8;
 825         unsigned int        dummyinteger9;
 826         unsigned int        dummyinteger10;
 827         unsigned int        dummyinteger11;
 828         unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
 829
 830         bool           dummysinglestring;
 831         bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 832         double         PlaneRequiredDISPCLKWithODMCombine2To1;
 833         double         PlaneRequiredDISPCLKWithODMCombine4To1;
 834         unsigned int   TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];
 835         bool           LinkDSCEnable;
 836         bool           ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
 837         enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
 838         double   SwathWidthCThisState[DC__NUM_DPP__MAX];
 839         bool           ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 840         double         AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
 841         double         AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
 842
 843         unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
 844         unsigned int NotEnoughUrgentLatencyHidingPre;
 845         int PTEBufferSizeInRequestsForLuma;
 846         int PTEBufferSizeInRequestsForChroma;
 847
 848         // Missing from VBA
 849         int dpte_group_bytes_chroma;
 850         unsigned int vm_group_bytes_chroma;
 851         double dst_x_after_scaler;
 852         double dst_y_after_scaler;
 853         unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
 854
 855         /* perf locals*/
 856         double PrefetchBandwidth[DC__NUM_DPP__MAX];
 857         double VInitPreFillY[DC__NUM_DPP__MAX];
 858         double VInitPreFillC[DC__NUM_DPP__MAX];
 859         unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
 860         unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
 861         unsigned int VStartup[DC__NUM_DPP__MAX];
 862         double DSTYAfterScaler[DC__NUM_DPP__MAX];
 863         double DSTXAfterScaler[DC__NUM_DPP__MAX];
 864         bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
 865         bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
 866         double VRatioPrefetchY[DC__NUM_DPP__MAX];
 867         double VRatioPrefetchC[DC__NUM_DPP__MAX];
 868         double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
 869         double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
 870         double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
 871         double MinTTUVBlank[DC__NUM_DPP__MAX];
 872         double BytePerPixelDETY[DC__NUM_DPP__MAX];
 873         double BytePerPixelDETC[DC__NUM_DPP__MAX];
 874         double SwathWidthY[DC__NUM_DPP__MAX];
 875         double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
 876         double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
 877         double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
 878         double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
 879         double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
 880         double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
 881         double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
 882         double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
 883         double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
 884         double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
 885         double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
 886         double MetaRowByte[DC__NUM_DPP__MAX];
 887         double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
 888         double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
 889         double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
 890         double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
 891         double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
 892         double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
 893         double DSCCLK_calculated[DC__NUM_DPP__MAX];
 894         unsigned int DSCDelay[DC__NUM_DPP__MAX];
 895         unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
 896         double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
 897         double DPPCLK[DC__NUM_DPP__MAX];
 898         unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
 899         unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
 900         unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
 901         double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
 902         unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
 903         unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
 904         unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
 905         unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
 906         double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
 907         double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
 908         double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
 909         double XFCTransferDelay[DC__NUM_DPP__MAX];
 910         double XFCPrechargeDelay[DC__NUM_DPP__MAX];
 911         double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
 912         double XFCPrefetchMargin[DC__NUM_DPP__MAX];
 913         unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
 914         unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
 915         double FullDETBufferingTimeY[DC__NUM_DPP__MAX];                     // WM
 916         double FullDETBufferingTimeC[DC__NUM_DPP__MAX];                     // WM
 917         double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
 918         double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
 919         double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
 920         double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
 921         double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
 922         double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
 923         unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
 924         unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
 925         unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
 926         unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
 927         unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
 928         unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
 929         unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
 930         unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
 931         double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
 932         double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
 933         double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
 934         double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
 935         double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
 936         double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
 937         double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
 938         double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
 939         double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
 940         double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
 941         unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
 942         unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
 943         unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
 944         unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
 945         double LinesToFinishSwathTransferStutterCriticalPlane;
 946         unsigned int BytePerPixelYCriticalPlane;
 947         double SwathWidthYCriticalPlane;
 948         double LinesInDETY[DC__NUM_DPP__MAX];
 949         double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
 950
 951         double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
 952         double SwathWidthC[DC__NUM_DPP__MAX];
 953         unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
 954         unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
 955         unsigned int dummyinteger1;
 956         unsigned int dummyinteger2;
 957         double FinalDRAMClockChangeLatency;
 958         double Tdmdl_vm[DC__NUM_DPP__MAX];
 959         double Tdmdl[DC__NUM_DPP__MAX];
 960         double TSetup[DC__NUM_DPP__MAX];
 961         unsigned int ThisVStartup;
 962         bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
 963         double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
 964         double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
 965         double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
 966         double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
 967         unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
 968         unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
 969         double VStartupMargin;
 970         bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
 971
 972         /* Missing from VBA */
 973         unsigned int MaximumMaxVStartupLines;
 974         double FabricAndDRAMBandwidth;
 975         double LinesInDETLuma;
 976         double LinesInDETChroma;
 977         unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
 978         unsigned int LinesInDETC[DC__NUM_DPP__MAX];
 979         unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
 980         double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 981         double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
 982         double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];
 983         bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
 984         unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 985         unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 986         double qual_row_bw[DC__NUM_DPP__MAX];
 987         double prefetch_row_bw[DC__NUM_DPP__MAX];
 988         double prefetch_vm_bw[DC__NUM_DPP__MAX];
 989
 990         double PTEGroupSize;
 991         unsigned int PDEProcessingBufIn64KBReqs;
 992
 993         double MaxTotalVActiveRDBandwidth;
 994         bool DoUrgentLatencyAdjustment;
 995         double UrgentLatencyAdjustmentFabricClockComponent;
 996         double UrgentLatencyAdjustmentFabricClockReference;
 997         double MinUrgentLatencySupportUs;
 998         double MinFullDETBufferingTime;
 999         double AverageReadBandwidthGBytePerSecond;
1000         bool   FirstMainPlane;
1001
1002         unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
1003         unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
1004         double HRatioChroma[DC__NUM_DPP__MAX];
1005         double VRatioChroma[DC__NUM_DPP__MAX];
1006         int WritebackSourceWidth[DC__NUM_DPP__MAX];
1007
1008         bool ModeIsSupported;
1009         bool ODMCombine4To1Supported;
1010
1011         unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
1012         unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
1013         unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
1014         unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
1015         unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
1016         unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
1017         bool DSCEnable[DC__NUM_DPP__MAX];
1018
1019         double DRAMClockChangeLatencyOverride;
1020
1021         double GPUVMMinPageSize;
1022         double HostVMMinPageSize;
1023
1024         bool   MPCCombineEnable[DC__NUM_DPP__MAX];
1025         unsigned int HostVMMaxNonCachedPageTableLevels;
1026         bool   DynamicMetadataVMEnabled;
1027         double       WritebackInterfaceBufferSize;
1028         double       WritebackLineBufferSize;
1029
1030         double DCCRateLuma[DC__NUM_DPP__MAX];
1031         double DCCRateChroma[DC__NUM_DPP__MAX];
1032
1033         double PHYCLKD18PerState[DC__VOLTAGE_STATES];
1034
1035         bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
1036         bool NumberOfHDMIFRLSupport;
1037         unsigned int MaxNumHDMIFRLOutputs;
1038         int    AudioSampleRate[DC__NUM_DPP__MAX];
1039         int    AudioSampleLayout[DC__NUM_DPP__MAX];
1040
1041         int PercentMarginOverMinimumRequiredDCFCLK;
1042         bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
1043         enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX];
1044         unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
1045         unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
1046         bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
1047         bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1048         int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
1049         int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
1050         double UrgLatency[DC__VOLTAGE_STATES];
1051         double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1052         double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1053         bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1054         bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1055         double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1056         double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1057         double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1058         double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1059         unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1060         unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1061         bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
1062         unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1063         unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1064         unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1065         unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1066         double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];
1067         double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];
1068         double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];
1069         double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];
1070         double WritebackDelayTime[DC__NUM_DPP__MAX];
1071         unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
1072         unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
1073         unsigned int dummyinteger17;
1074         unsigned int dummyinteger18;
1075         unsigned int dummyinteger19;
1076         unsigned int dummyinteger20;
1077         unsigned int dummyinteger21;
1078         unsigned int dummyinteger22;
1079         unsigned int dummyinteger23;
1080         unsigned int dummyinteger24;
1081         unsigned int dummyinteger25;
1082         unsigned int dummyinteger26;
1083         unsigned int dummyinteger27;
1084         unsigned int dummyinteger28;
1085         unsigned int dummyinteger29;
1086         bool dummystring[DC__NUM_DPP__MAX];
1087         double BPP;
1088         enum odm_combine_policy ODMCombinePolicy;
1089         bool UseMinimumRequiredDCFCLK;
1090         bool ClampMinDCFCLK;
1091         bool AllowDramClockChangeOneDisplayVactive;
1092
1093         double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
1094         double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
1095         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
1096         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
1097         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
1098         double SRExitZ8Time;
1099         double SREnterPlusExitZ8Time;
1100         double Z8StutterExitWatermark;
1101         double Z8StutterEnterPlusExitWatermark;
1102         double Z8StutterEfficiencyNotIncludingVBlank;
1103         double Z8StutterEfficiency;
1104         double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
1105         double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
1106         double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
1107         double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
1108         double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
1109         double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
1110         double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1111         double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1112         bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1113         bool LinkCapacitySupport[DC__NUM_DPP__MAX];
1114         bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1115         unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1116         unsigned int VFrontPorch[DC__NUM_DPP__MAX];
1117         int ConfigReturnBufferSizeInKByte;
1118         enum unbounded_requesting_policy UseUnboundedRequesting;
1119         int CompressedBufferSegmentSizeInkByte;
1120         int CompressedBufferSizeInkByte;
1121         int MetaFIFOSizeInKEntries;
1122         int ZeroSizeBufferEntries;
1123         int COMPBUF_RESERVED_SPACE_64B;
1124         int COMPBUF_RESERVED_SPACE_ZS;
1125         bool UnboundedRequestEnabled;
1126         bool DSC422NativeSupport;
1127         bool NoEnoughUrgentLatencyHiding;
1128         bool NoEnoughUrgentLatencyHidingPre;
1129         int NumberOfStutterBurstsPerFrame;
1130         int Z8NumberOfStutterBurstsPerFrame;
1131         unsigned int MaximumDSCBitsPerComponent;
1132         unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
1133         double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
1134         double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
1135         double SurfaceRequiredDISPCLKWithoutODMCombine;
1136         double SurfaceRequiredDISPCLK;
1137         double MinActiveFCLKChangeLatencySupported;
1138         int MinVoltageLevel;
1139         int MaxVoltageLevel;
1140         unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
1141         unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
1142         unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1143         unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
1144         unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
1145         bool ExceededMALLSize;
1146         bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
1147         unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
1148         unsigned int CompressedBufferSizeInkByteThisState;
1149         enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
1150         bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
1151         enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
1152         bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
1153         bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
1154         enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
1155         bool UnboundedRequestEnabledThisState;
1156         bool DRAMClockChangeRequirementFinal;
1157         bool FCLKChangeRequirementFinal;
1158         bool USRRetrainingRequiredFinal;
1159         unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
1160         unsigned int nomDETInKByte;
1161         enum mpc_combine_affinity  MPCCombineUse[DC__NUM_DPP__MAX];
1162         bool MPCCombineMethodIncompatible;
1163         unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
1164         bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
1165         enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
1166         unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
1167         bool OutputMultistreamEn[DC__NUM_DPP__MAX];
1168         bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
1169         double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
1170         double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
1171         bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1172         bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1173         bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
1174         bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
1175         bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
1176         unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
1177         unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
1178         unsigned int BlockHeightY[DC__NUM_DPP__MAX];
1179         unsigned int BlockHeightC[DC__NUM_DPP__MAX];
1180         unsigned int BlockWidthY[DC__NUM_DPP__MAX];
1181         unsigned int BlockWidthC[DC__NUM_DPP__MAX];
1182         unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
1183         bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
1184         struct dummy_vars dummy_vars;
1185 };
1186
1187 bool CalculateMinAndMaxPrefetchMode(
1188                 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
1189                 unsigned int *MinPrefetchMode,
1190                 unsigned int *MaxPrefetchMode);
1191
1192 double CalculateWriteBackDISPCLK(
1193                 enum source_format_class WritebackPixelFormat,
1194                 double PixelClock,
1195                 double WritebackHRatio,
1196                 double WritebackVRatio,
1197                 unsigned int WritebackLumaHTaps,
1198                 unsigned int WritebackLumaVTaps,
1199                 unsigned int WritebackChromaHTaps,
1200                 unsigned int WritebackChromaVTaps,
1201                 double WritebackDestinationWidth,
1202                 unsigned int HTotal,
1203                 unsigned int WritebackChromaLineBufferWidth);
1204
1205 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */