drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #ifndef __DML2_DISPLAY_MODE_VBA_H__
  28 #define __DML2_DISPLAY_MODE_VBA_H__
  29
  30 struct display_mode_lib;
  31
  32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
  33
  34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
  35
  36 dml_get_attr_decl(clk_dcf_deepsleep);
  37 dml_get_attr_decl(wm_urgent);
  38 dml_get_attr_decl(wm_memory_trip);
  39 dml_get_attr_decl(wm_writeback_urgent);
  40 dml_get_attr_decl(wm_stutter_exit);
  41 dml_get_attr_decl(wm_stutter_enter_exit);
  42 dml_get_attr_decl(wm_z8_stutter_exit);
  43 dml_get_attr_decl(wm_z8_stutter_enter_exit);
  44 dml_get_attr_decl(stutter_efficiency_z8);
  45 dml_get_attr_decl(stutter_num_bursts_z8);
  46 dml_get_attr_decl(wm_dram_clock_change);
  47 dml_get_attr_decl(wm_writeback_dram_clock_change);
  48 dml_get_attr_decl(stutter_efficiency_no_vblank);
  49 dml_get_attr_decl(stutter_efficiency);
  50 dml_get_attr_decl(stutter_period);
  51 dml_get_attr_decl(urgent_latency);
  52 dml_get_attr_decl(urgent_extra_latency);
  53 dml_get_attr_decl(nonurgent_latency);
  54 dml_get_attr_decl(dram_clock_change_latency);
  55 dml_get_attr_decl(dispclk_calculated);
  56 dml_get_attr_decl(total_data_read_bw);
  57 dml_get_attr_decl(return_bw);
  58 dml_get_attr_decl(tcalc);
  59 dml_get_attr_decl(fraction_of_urgent_bandwidth);
  60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
  61 dml_get_attr_decl(cstate_max_cap_mode);
  62 dml_get_attr_decl(comp_buffer_size_kbytes);
  63 dml_get_attr_decl(pixel_chunk_size_in_kbyte);
  64 dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
  65 dml_get_attr_decl(meta_chunk_size_in_kbyte);
  66 dml_get_attr_decl(min_pixel_chunk_size_in_byte);
  67 dml_get_attr_decl(min_meta_chunk_size_in_byte);
  68 dml_get_attr_decl(fclk_watermark);
  69 dml_get_attr_decl(usr_retraining_watermark);
  70
  71 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
  72
  73 dml_get_pipe_attr_decl(dsc_delay);
  74 dml_get_pipe_attr_decl(dppclk_calculated);
  75 dml_get_pipe_attr_decl(dscclk_calculated);
  76 dml_get_pipe_attr_decl(min_ttu_vblank);
  77 dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
  78 dml_get_pipe_attr_decl(vratio_prefetch_l);
  79 dml_get_pipe_attr_decl(vratio_prefetch_c);
  80 dml_get_pipe_attr_decl(dst_x_after_scaler);
  81 dml_get_pipe_attr_decl(dst_y_after_scaler);
  82 dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
  83 dml_get_pipe_attr_decl(dst_y_per_row_vblank);
  84 dml_get_pipe_attr_decl(dst_y_prefetch);
  85 dml_get_pipe_attr_decl(dst_y_per_vm_flip);
  86 dml_get_pipe_attr_decl(dst_y_per_row_flip);
  87 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
  88 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
  89 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
  90 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
  91 dml_get_pipe_attr_decl(dpte_row_height_linear_c);
  92 dml_get_pipe_attr_decl(swath_height_l);
  93 dml_get_pipe_attr_decl(swath_height_c);
  94 dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
  95 dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
  96 dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
  97 dml_get_pipe_attr_decl(vm_group_size_in_bytes);
  98 dml_get_pipe_attr_decl(det_buffer_size_kbytes);
  99 dml_get_pipe_attr_decl(dpte_row_height_linear_l);
 100 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
 101 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
 102 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
 103 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
 104 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
 105 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
 106 dml_get_pipe_attr_decl(pte_buffer_mode);
 107 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
 108 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
 109 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
 110 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
 111 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us);
 112 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us);
 113 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us);
 114 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us);
 115 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us);
 116 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us);
 117 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us);
 118 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us);
 119 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us);
 120 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us);
 121 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us);
 122 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us);
 123 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us);
 124 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us);
 125 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us);
 126 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us);
 127 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us);
 128 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us);
 129 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us);
 130 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us);
 131 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);
 132 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);
 133
 134 dml_get_pipe_attr_decl(vstartup);
 135 dml_get_pipe_attr_decl(vupdate_offset);
 136 dml_get_pipe_attr_decl(vupdate_width);
 137 dml_get_pipe_attr_decl(vready_offset);
 138 dml_get_pipe_attr_decl(vready_at_or_after_vsync);
 139 dml_get_pipe_attr_decl(min_dst_y_next_start);
 140 dml_get_pipe_attr_decl(vstartup_calculated);
 141 dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
 142
 143 double get_total_immediate_flip_bytes(
 144                 struct display_mode_lib *mode_lib,
 145                 const display_e2e_pipe_params_st *pipes,
 146                 unsigned int num_pipes);
 147 double get_total_immediate_flip_bw(
 148                 struct display_mode_lib *mode_lib,
 149                 const display_e2e_pipe_params_st *pipes,
 150                 unsigned int num_pipes);
 151 double get_total_prefetch_bw(
 152                 struct display_mode_lib *mode_lib,
 153                 const display_e2e_pipe_params_st *pipes,
 154                 unsigned int num_pipes);
 155 unsigned int dml_get_voltage_level(
 156                 struct display_mode_lib *mode_lib,
 157                 const display_e2e_pipe_params_st *pipes,
 158                 unsigned int num_pipes);
 159
 160 unsigned int get_total_surface_size_in_mall_bytes(
 161                 struct display_mode_lib *mode_lib,
 162                 const display_e2e_pipe_params_st *pipes,
 163                 unsigned int num_pipes);
 164 unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx);
 165
 166 bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
 167                 const display_e2e_pipe_params_st *pipes,
 168                 unsigned int num_pipes,
 169                 unsigned int pipe_idx);
 170 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
 171
 172 void Calculate256BBlockSizes(
 173                 enum source_format_class SourcePixelFormat,
 174                 enum dm_swizzle_mode SurfaceTiling,
 175                 unsigned int BytePerPixelY,
 176                 unsigned int BytePerPixelC,
 177                 unsigned int *BlockHeight256BytesY,
 178                 unsigned int *BlockHeight256BytesC,
 179                 unsigned int *BlockWidth256BytesY,
 180                 unsigned int *BlockWidth256BytesC);
 181
 182 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
 183         unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
 184         double dummy_single_array[2][DC__NUM_DPP__MAX];
 185         unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
 186         double dummy_double_array[2][DC__NUM_DPP__MAX];
 187         bool dummy_boolean_array[DC__NUM_DPP__MAX];
 188         bool dummy_boolean;
 189         bool dummy_boolean2;
 190         enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
 191         DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
 192         bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
 193         unsigned int ReorderBytes;
 194         unsigned int VMDataOnlyReturnBW;
 195         double HostVMInefficiencyFactor;
 196 };
 197
 198 struct dml32_ModeSupportAndSystemConfigurationFull {
 199         unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
 200         double dummy_double_array[2][DC__NUM_DPP__MAX];
 201         DmlPipe SurfParameters[DC__NUM_DPP__MAX];
 202         double dummy_single[5];
 203         double dummy_single2[5];
 204         SOCParametersList mSOCParameters;
 205         unsigned int MaximumSwathWidthSupportLuma;
 206         unsigned int MaximumSwathWidthSupportChroma;
 207         double DSTYAfterScaler[DC__NUM_DPP__MAX];
 208         double DSTXAfterScaler[DC__NUM_DPP__MAX];
 209         double MaxTotalVActiveRDBandwidth;
 210         bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
 211 };
 212
 213 struct dummy_vars {
 214         struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 215         DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
 216         struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
 217 };
 218
 219 struct vba_vars_st {
 220         ip_params_st ip;
 221         soc_bounding_box_st soc;
 222
 223         int maxMpcComb;
 224         bool UseMaximumVStartup;
 225
 226         double WritebackDISPCLK;
 227         double DPPCLKUsingSingleDPPLuma;
 228         double DPPCLKUsingSingleDPPChroma;
 229         double DISPCLKWithRamping;
 230         double DISPCLKWithoutRamping;
 231         double GlobalDPPCLK;
 232         double DISPCLKWithRampingRoundedToDFSGranularity;
 233         double DISPCLKWithoutRampingRoundedToDFSGranularity;
 234         double MaxDispclkRoundedToDFSGranularity;
 235         double MaxDppclkRoundedToDFSGranularity;
 236         bool DCCEnabledAnyPlane;
 237         double ReturnBandwidthToDCN;
 238         unsigned int TotalActiveDPP;
 239         unsigned int TotalDCCActiveDPP;
 240         double UrgentRoundTripAndOutOfOrderLatency;
 241         double StutterPeriod;
 242         double FrameTimeForMinFullDETBufferingTime;
 243         double AverageReadBandwidth;
 244         double TotalRowReadBandwidth;
 245         double PartOfBurstThatFitsInROB;
 246         double StutterBurstTime;
 247         unsigned int NextPrefetchMode;
 248         double NextMaxVStartup;
 249         double VBlankTime;
 250         double SmallestVBlank;
 251         enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
 252         double DCFCLKDeepSleepPerSurface[DC__NUM_DPP__MAX];
 253         double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
 254         double EffectiveDETPlusLBLinesLuma;
 255         double EffectiveDETPlusLBLinesChroma;
 256         double UrgentLatencySupportUsLuma;
 257         double UrgentLatencySupportUsChroma;
 258         unsigned int DSCFormatFactor;
 259
 260         bool DummyPStateCheck;
 261         bool DRAMClockChangeSupportsVActive;
 262         bool PrefetchModeSupported;
 263         bool PrefetchAndImmediateFlipSupported;
 264         enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
 265         double XFCRemoteSurfaceFlipDelay;
 266         double TInitXFill;
 267         double TslvChk;
 268         double SrcActiveDrainRate;
 269         bool ImmediateFlipSupported;
 270         enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
 271
 272         bool PrefetchERROR;
 273
 274         unsigned int VStartupLines;
 275         unsigned int ActiveDPPs;
 276         unsigned int LBLatencyHidingSourceLinesY;
 277         unsigned int LBLatencyHidingSourceLinesC;
 278         double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
 279         double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
 280         double MinActiveDRAMClockChangeMargin;
 281         double InitFillLevel;
 282         double FinalFillMargin;
 283         double FinalFillLevel;
 284         double RemainingFillLevel;
 285         double TFinalxFill;
 286
 287         //
 288         // SOC Bounding Box Parameters
 289         //
 290         double SRExitTime;
 291         double SREnterPlusExitTime;
 292         double UrgentLatencyPixelDataOnly;
 293         double UrgentLatencyPixelMixedWithVMData;
 294         double UrgentLatencyVMDataOnly;
 295         double UrgentLatency; // max of the above three
 296         double USRRetrainingLatency;
 297         double SMNLatency;
 298         double FCLKChangeLatency;
 299         unsigned int MALLAllocatedForDCNFinal;
 300         double DefaultGPUVMMinPageSizeKBytes; // Default for the project
 301         double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
 302         double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
 303         double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
 304         double WritebackLatency;
 305         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
 306         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
 307         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
 308         double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
 309         double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
 310         double NumberOfChannels;
 311         double DRAMChannelWidth;
 312         double FabricDatapathToDCNDataReturn;
 313         double ReturnBusWidth;
 314         double Downspreading;
 315         double DISPCLKDPPCLKDSCCLKDownSpreading;
 316         double DISPCLKDPPCLKVCOSpeed;
 317         double RoundTripPingLatencyCycles;
 318         double UrgentOutOfOrderReturnPerChannel;
 319         double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
 320         double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
 321         double UrgentOutOfOrderReturnPerChannelVMDataOnly;
 322         unsigned int VMMPageSize;
 323         double DRAMClockChangeLatency;
 324         double XFCBusTransportTime;
 325         bool UseUrgentBurstBandwidth;
 326         double XFCXBUFLatencyTolerance;
 327
 328         //
 329         // IP Parameters
 330         //
 331         unsigned int ROBBufferSizeInKByte;
 332         unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
 333         double DETBufferSizeInTime;
 334         unsigned int DPPOutputBufferPixels;
 335         unsigned int OPPOutputBufferLines;
 336         unsigned int PixelChunkSizeInKByte;
 337         double ReturnBW;
 338         bool GPUVMEnable;
 339         bool HostVMEnable;
 340         unsigned int GPUVMMaxPageTableLevels;
 341         unsigned int HostVMMaxPageTableLevels;
 342         unsigned int HostVMCachedPageTableLevels;
 343         unsigned int OverrideGPUVMPageTableLevels;
 344         unsigned int OverrideHostVMPageTableLevels;
 345         unsigned int MetaChunkSize;
 346         unsigned int MinMetaChunkSizeBytes;
 347         unsigned int WritebackChunkSize;
 348         bool ODMCapability;
 349         unsigned int NumberOfDSC;
 350         unsigned int LineBufferSize;
 351         unsigned int MaxLineBufferLines;
 352         unsigned int WritebackInterfaceLumaBufferSize;
 353         unsigned int WritebackInterfaceChromaBufferSize;
 354         unsigned int WritebackChromaLineBufferWidth;
 355         enum writeback_config WritebackConfiguration;
 356         double MaxDCHUBToPSCLThroughput;
 357         double MaxPSCLToLBThroughput;
 358         unsigned int PTEBufferSizeInRequestsLuma;
 359         unsigned int PTEBufferSizeInRequestsChroma;
 360         double DISPCLKRampingMargin;
 361         unsigned int MaxInterDCNTileRepeaters;
 362         bool XFCSupported;
 363         double XFCSlvChunkSize;
 364         double XFCFillBWOverhead;
 365         double XFCFillConstant;
 366         double XFCTSlvVupdateOffset;
 367         double XFCTSlvVupdateWidth;
 368         double XFCTSlvVreadyOffset;
 369         double DPPCLKDelaySubtotal;
 370         double DPPCLKDelaySCL;
 371         double DPPCLKDelaySCLLBOnly;
 372         double DPPCLKDelayCNVCFormater;
 373         double DPPCLKDelayCNVCCursor;
 374         double DISPCLKDelaySubtotal;
 375         bool ProgressiveToInterlaceUnitInOPP;
 376         unsigned int CompressedBufferSegmentSizeInkByteFinal;
 377         unsigned int CompbufReservedSpace64B;
 378         unsigned int CompbufReservedSpaceZs;
 379         unsigned int LineBufferSizeFinal;
 380         unsigned int MaximumPixelsPerLinePerDSCUnit;
 381         unsigned int AlphaPixelChunkSizeInKByte;
 382         double MinPixelChunkSizeBytes;
 383         unsigned int DCCMetaBufferSizeBytes;
 384         // Pipe/Plane Parameters
 385         int VoltageLevel;
 386         double FabricClock;
 387         double DRAMSpeed;
 388         double DISPCLK;
 389         double SOCCLK;
 390         double DCFCLK;
 391         unsigned int MaxTotalDETInKByte;
 392         unsigned int MinCompressedBufferSizeInKByte;
 393         unsigned int NumberOfActiveSurfaces;
 394         bool ViewportStationary[DC__NUM_DPP__MAX];
 395         unsigned int RefreshRate[DC__NUM_DPP__MAX];
 396         double       OutputBPP[DC__NUM_DPP__MAX];
 397         unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
 398         bool SynchronizeTimingsFinal;
 399         bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
 400         bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
 401         unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
 402         unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
 403         enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
 404         bool DRRDisplay[DC__NUM_DPP__MAX];
 405         bool PteBufferMode[DC__NUM_DPP__MAX];
 406         enum dm_output_type OutputType[DC__NUM_DPP__MAX];
 407         enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
 408
 409         unsigned int NumberOfActivePlanes;
 410         unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
 411         unsigned int ViewportWidth[DC__NUM_DPP__MAX];
 412         unsigned int ViewportHeight[DC__NUM_DPP__MAX];
 413         unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
 414         unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
 415         unsigned int PitchY[DC__NUM_DPP__MAX];
 416         unsigned int PitchC[DC__NUM_DPP__MAX];
 417         double HRatio[DC__NUM_DPP__MAX];
 418         double VRatio[DC__NUM_DPP__MAX];
 419         unsigned int htaps[DC__NUM_DPP__MAX];
 420         unsigned int vtaps[DC__NUM_DPP__MAX];
 421         unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
 422         unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
 423         unsigned int HTotal[DC__NUM_DPP__MAX];
 424         unsigned int VTotal[DC__NUM_DPP__MAX];
 425         unsigned int VTotal_Max[DC__NUM_DPP__MAX];
 426         unsigned int VTotal_Min[DC__NUM_DPP__MAX];
 427         int DPPPerPlane[DC__NUM_DPP__MAX];
 428         double PixelClock[DC__NUM_DPP__MAX];
 429         double PixelClockBackEnd[DC__NUM_DPP__MAX];
 430         bool DCCEnable[DC__NUM_DPP__MAX];
 431         bool FECEnable[DC__NUM_DPP__MAX];
 432         unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
 433         unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
 434         enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
 435         enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
 436         bool WritebackEnable[DC__NUM_DPP__MAX];
 437         unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
 438         double WritebackDestinationWidth[DC__NUM_DPP__MAX];
 439         double WritebackDestinationHeight[DC__NUM_DPP__MAX];
 440         double WritebackSourceHeight[DC__NUM_DPP__MAX];
 441         enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
 442         unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
 443         unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
 444         unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
 445         unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
 446         double WritebackHRatio[DC__NUM_DPP__MAX];
 447         double WritebackVRatio[DC__NUM_DPP__MAX];
 448         unsigned int HActive[DC__NUM_DPP__MAX];
 449         unsigned int VActive[DC__NUM_DPP__MAX];
 450         bool Interlace[DC__NUM_DPP__MAX];
 451         enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
 452         unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
 453         bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
 454         int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
 455         unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
 456         double DCCRate[DC__NUM_DPP__MAX];
 457         double AverageDCCCompressionRate;
 458         enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
 459         double OutputBpp[DC__NUM_DPP__MAX];
 460         bool DSCEnabled[DC__NUM_DPP__MAX];
 461         unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
 462         enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
 463         enum output_encoder_class Output[DC__NUM_DPP__MAX];
 464         bool skip_dio_check[DC__NUM_DPP__MAX];
 465         unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
 466         bool SynchronizedVBlank;
 467         unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
 468         unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 469         unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 470         bool XFCEnabled[DC__NUM_DPP__MAX];
 471         bool ScalerEnabled[DC__NUM_DPP__MAX];
 472         unsigned int VBlankNom[DC__NUM_DPP__MAX];
 473
 474         // Intermediates/Informational
 475         bool ImmediateFlipSupport;
 476         unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
 477         unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
 478         unsigned int SwathHeightY[DC__NUM_DPP__MAX];
 479         unsigned int SwathHeightC[DC__NUM_DPP__MAX];
 480         unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
 481         double LastPixelOfLineExtraWatermark;
 482         double TotalDataReadBandwidth;
 483         unsigned int TotalActiveWriteback;
 484         unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
 485         unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
 486         double BandwidthAvailableForImmediateFlip;
 487         unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
 488         unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
 489         unsigned int MinPrefetchMode;
 490         unsigned int MaxPrefetchMode;
 491         bool AnyLinesForVMOrRowTooLarge;
 492         double MaxVStartup;
 493         bool IgnoreViewportPositioning;
 494         bool ErrorResult[DC__NUM_DPP__MAX];
 495         //
 496         // Calculated dml_ml->vba.Outputs
 497         //
 498         double DCFCLKDeepSleep;
 499         double UrgentWatermark;
 500         double UrgentExtraLatency;
 501         double WritebackUrgentWatermark;
 502         double StutterExitWatermark;
 503         double StutterEnterPlusExitWatermark;
 504         double DRAMClockChangeWatermark;
 505         double WritebackDRAMClockChangeWatermark;
 506         double StutterEfficiency;
 507         double StutterEfficiencyNotIncludingVBlank;
 508         double NonUrgentLatencyTolerance;
 509         double MinActiveDRAMClockChangeLatencySupported;
 510         double Z8StutterEfficiencyBestCase;
 511         unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
 512         double Z8StutterEfficiencyNotIncludingVBlankBestCase;
 513         double StutterPeriodBestCase;
 514         Watermarks      Watermark;
 515         bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
 516
 517         // These are the clocks calcuated by the library but they are not actually
 518         // used explicitly. They are fetched by tests and then possibly used. The
 519         // ultimate values to use are the ones specified by the parameters to DML
 520         double DISPCLK_calculated;
 521         double DPPCLK_calculated[DC__NUM_DPP__MAX];
 522
 523         bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
 524
 525         bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
 526         bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
 527         unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
 528         double VUpdateWidthPix[DC__NUM_DPP__MAX];
 529         double VReadyOffsetPix[DC__NUM_DPP__MAX];
 530
 531         unsigned int TotImmediateFlipBytes;
 532         double TCalc;
 533
 534         display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
 535         unsigned int cache_num_pipes;
 536         unsigned int pipe_plane[DC__NUM_DPP__MAX];
 537
 538         /* vba mode support */
 539         /*inputs*/
 540         bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
 541         double MaxHSCLRatio;
 542         double MaxVSCLRatio;
 543         unsigned int MaxNumWriteback;
 544         bool WritebackLumaAndChromaScalingSupported;
 545         bool Cursor64BppSupport;
 546         double DCFCLKPerState[DC__VOLTAGE_STATES];
 547         double DCFCLKState[DC__VOLTAGE_STATES][2];
 548         double FabricClockPerState[DC__VOLTAGE_STATES];
 549         double SOCCLKPerState[DC__VOLTAGE_STATES];
 550         double PHYCLKPerState[DC__VOLTAGE_STATES];
 551         double DTBCLKPerState[DC__VOLTAGE_STATES];
 552         double MaxDppclk[DC__VOLTAGE_STATES];
 553         double MaxDSCCLK[DC__VOLTAGE_STATES];
 554         double DRAMSpeedPerState[DC__VOLTAGE_STATES];
 555         double MaxDispclk[DC__VOLTAGE_STATES];
 556         int VoltageOverrideLevel;
 557         double PHYCLKD32PerState[DC__VOLTAGE_STATES];
 558
 559         /*outputs*/
 560         bool ScaleRatioAndTapsSupport;
 561         bool SourceFormatPixelAndScanSupport;
 562         double TotalBandwidthConsumedGBytePerSecond;
 563         bool DCCEnabledInAnyPlane;
 564         bool WritebackLatencySupport;
 565         bool WritebackModeSupport;
 566         bool Writeback10bpc420Supported;
 567         bool BandwidthSupport[DC__VOLTAGE_STATES];
 568         unsigned int TotalNumberOfActiveWriteback;
 569         double CriticalPoint;
 570         double ReturnBWToDCNPerState;
 571         bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 572         bool prefetch_vm_bw_valid;
 573         bool prefetch_row_bw_valid;
 574         bool NumberOfOTGSupport;
 575         bool NonsupportedDSCInputBPC;
 576         bool WritebackScaleRatioAndTapsSupport;
 577         bool CursorSupport;
 578         bool PitchSupport;
 579         enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
 580
 581         /* Mode Support Reason */
 582         bool P2IWith420;
 583         bool DSCOnlyIfNecessaryWithBPP;
 584         bool DSC422NativeNotSupported;
 585         bool LinkRateDoesNotMatchDPVersion;
 586         bool LinkRateForMultistreamNotIndicated;
 587         bool BPPForMultistreamNotIndicated;
 588         bool MultistreamWithHDMIOreDP;
 589         bool MSOOrODMSplitWithNonDPLink;
 590         bool NotEnoughLanesForMSO;
 591         bool ViewportExceedsSurface;
 592
 593         bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
 594         bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
 595         bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
 596         bool InvalidCombinationOfMALLUseForPState;
 597
 598         enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
 599         double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
 600         double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
 601         double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
 602         double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
 603         double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
 604         double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
 605         double MetaRowBytesThisState[DC__NUM_DPP__MAX];
 606         bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 607         bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 608         bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
 609         bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
 610
 611         unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 612         double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 613         unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
 614         unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
 615         unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
 616         unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
 617         bool ImmediateFlipRequiredFinal;
 618         bool DCCProgrammingAssumesScanDirectionUnknownFinal;
 619         bool EnoughWritebackUnits;
 620         bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
 621         bool NumberOfDP2p0Support;
 622         unsigned int MaxNumDP2p0Streams;
 623         unsigned int MaxNumDP2p0Outputs;
 624         enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 625         enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 626         double WritebackLineBufferLumaBufferSize;
 627         double WritebackLineBufferChromaBufferSize;
 628         double WritebackMinHSCLRatio;
 629         double WritebackMinVSCLRatio;
 630         double WritebackMaxHSCLRatio;
 631         double WritebackMaxVSCLRatio;
 632         double WritebackMaxHSCLTaps;
 633         double WritebackMaxVSCLTaps;
 634         unsigned int MaxNumDPP;
 635         unsigned int MaxNumOTG;
 636         double CursorBufferSize;
 637         double CursorChunkSize;
 638         unsigned int Mode;
 639         double OutputLinkDPLanes[DC__NUM_DPP__MAX];
 640         double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
 641         double ImmediateFlipBW[DC__NUM_DPP__MAX];
 642         double MaxMaxVStartup[DC__VOLTAGE_STATES][2];
 643
 644         double WritebackLumaVExtra;
 645         double WritebackChromaVExtra;
 646         double WritebackRequiredDISPCLK;
 647         double MaximumSwathWidthSupport;
 648         double MaximumSwathWidthInDETBuffer;
 649         double MaximumSwathWidthInLineBuffer;
 650         double MaxDispclkRoundedDownToDFSGranularity;
 651         double MaxDppclkRoundedDownToDFSGranularity;
 652         double PlaneRequiredDISPCLKWithoutODMCombine;
 653         double PlaneRequiredDISPCLKWithODMCombine;
 654         double PlaneRequiredDISPCLK;
 655         double TotalNumberOfActiveOTG;
 656         double FECOverhead;
 657         double EffectiveFECOverhead;
 658         double Outbpp;
 659         unsigned int OutbppDSC;
 660         double TotalDSCUnitsRequired;
 661         double bpp;
 662         unsigned int slices;
 663         double SwathWidthGranularityY;
 664         double RoundedUpMaxSwathSizeBytesY;
 665         double SwathWidthGranularityC;
 666         double RoundedUpMaxSwathSizeBytesC;
 667         double EffectiveDETLBLinesLuma;
 668         double EffectiveDETLBLinesChroma;
 669         double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];
 670         double PDEAndMetaPTEBytesPerFrameY;
 671         double PDEAndMetaPTEBytesPerFrameC;
 672         unsigned int MetaRowBytesY;
 673         unsigned int MetaRowBytesC;
 674         unsigned int DPTEBytesPerRowC;
 675         unsigned int DPTEBytesPerRowY;
 676         double ExtraLatency;
 677         double TimeCalc;
 678         double TWait;
 679         double MaximumReadBandwidthWithPrefetch;
 680         double MaximumReadBandwidthWithoutPrefetch;
 681         double total_dcn_read_bw_with_flip;
 682         double total_dcn_read_bw_with_flip_no_urgent_burst;
 683         double FractionOfUrgentBandwidth;
 684         double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
 685
 686         /* ms locals */
 687         double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
 688         unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 689         int NoOfDPPThisState[DC__NUM_DPP__MAX];
 690         enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 691         double SwathWidthYThisState[DC__NUM_DPP__MAX];
 692         unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 693         unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
 694         unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
 695         double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 696         double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 697         double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 698         double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 699         double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 700         double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
 701         bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 702         bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 703         bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
 704         bool PrefetchSupported[DC__VOLTAGE_STATES][2];
 705         bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
 706         double RequiredDISPCLK[DC__VOLTAGE_STATES][2];
 707         bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
 708         bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
 709         unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];
 710         unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];
 711         bool ModeSupport[DC__VOLTAGE_STATES][2];
 712         double ReturnBWPerState[DC__VOLTAGE_STATES][2];
 713         bool DIOSupport[DC__VOLTAGE_STATES];
 714         bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
 715         bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
 716         bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
 717         double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
 718         bool ROBSupport[DC__VOLTAGE_STATES][2];
 719         //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
 720         bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
 721         bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
 722         bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
 723         double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];
 724         double PrefetchBW[DC__NUM_DPP__MAX];
 725         double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 726         double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 727         double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 728         double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 729         double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 730         unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
 731         unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
 732         double PrefillY[DC__NUM_DPP__MAX];
 733         double PrefillC[DC__NUM_DPP__MAX];
 734         double LineTimesForPrefetch[DC__NUM_DPP__MAX];
 735         double LinesForMetaPTE[DC__NUM_DPP__MAX];
 736         double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
 737         double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
 738         double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
 739         double BytePerPixelInDETY[DC__NUM_DPP__MAX];
 740         double BytePerPixelInDETC[DC__NUM_DPP__MAX];
 741         bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 742         unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 743         double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 744         double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 745         double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 746         bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
 747         unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
 748         unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
 749         unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
 750         unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
 751         double MaxSwathHeightY[DC__NUM_DPP__MAX];
 752         double MaxSwathHeightC[DC__NUM_DPP__MAX];
 753         double MinSwathHeightY[DC__NUM_DPP__MAX];
 754         double MinSwathHeightC[DC__NUM_DPP__MAX];
 755         double ReadBandwidthLuma[DC__NUM_DPP__MAX];
 756         double ReadBandwidthChroma[DC__NUM_DPP__MAX];
 757         double ReadBandwidth[DC__NUM_DPP__MAX];
 758         double WriteBandwidth[DC__NUM_DPP__MAX];
 759         double PSCL_FACTOR[DC__NUM_DPP__MAX];
 760         double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
 761         double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 762         unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
 763         unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
 764         double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
 765         double AlignedYPitch[DC__NUM_DPP__MAX];
 766         double AlignedCPitch[DC__NUM_DPP__MAX];
 767         double MaximumSwathWidth[DC__NUM_DPP__MAX];
 768         double cursor_bw[DC__NUM_DPP__MAX];
 769         double cursor_bw_pre[DC__NUM_DPP__MAX];
 770         double Tno_bw[DC__NUM_DPP__MAX];
 771         double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
 772         double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
 773         double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
 774         double final_flip_bw[DC__NUM_DPP__MAX];
 775         bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
 776         double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 777         unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
 778         unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
 779         unsigned int dpte_row_height[DC__NUM_DPP__MAX];
 780         unsigned int meta_req_height[DC__NUM_DPP__MAX];
 781         unsigned int meta_req_width[DC__NUM_DPP__MAX];
 782         unsigned int meta_row_height[DC__NUM_DPP__MAX];
 783         unsigned int meta_row_width[DC__NUM_DPP__MAX];
 784         unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
 785         unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
 786         unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
 787         unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
 788         unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
 789         bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
 790         double meta_row_bw[DC__NUM_DPP__MAX];
 791         double dpte_row_bw[DC__NUM_DPP__MAX];
 792         double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];                     // WM
 793         double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];                     // WM
 794         double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
 795         double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
 796         enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];
 797         double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
 798         double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
 799         double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
 800         double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
 801         double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
 802         double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
 803
 804
 805         bool           MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 806         double         SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
 807         double         MaximumSwathWidthInLineBufferLuma;
 808         double         MaximumSwathWidthInLineBufferChroma;
 809         double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
 810         double         MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
 811         enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
 812         double         dummy1[DC__NUM_DPP__MAX];
 813         double         dummy2[DC__NUM_DPP__MAX];
 814         unsigned int   dummy3[DC__NUM_DPP__MAX];
 815         unsigned int   dummy4[DC__NUM_DPP__MAX];
 816         double         dummy5;
 817         double         dummy6;
 818         double         dummy7[DC__NUM_DPP__MAX];
 819         double         dummy8[DC__NUM_DPP__MAX];
 820         double         dummy13[DC__NUM_DPP__MAX];
 821         double         dummy_double_array[2][DC__NUM_DPP__MAX];
 822         unsigned int        dummyinteger1ms[DC__NUM_DPP__MAX];
 823         double        dummyinteger2ms[DC__NUM_DPP__MAX];
 824         unsigned int        dummyinteger3[DC__NUM_DPP__MAX];
 825         unsigned int        dummyinteger4[DC__NUM_DPP__MAX];
 826         unsigned int        dummyinteger5;
 827         unsigned int        dummyinteger6;
 828         unsigned int        dummyinteger7;
 829         unsigned int        dummyinteger8;
 830         unsigned int        dummyinteger9;
 831         unsigned int        dummyinteger10;
 832         unsigned int        dummyinteger11;
 833         unsigned int        dummyinteger12;
 834         unsigned int        dummyinteger30;
 835         unsigned int        dummyinteger31;
 836         unsigned int        dummyinteger32;
 837         unsigned int        dummyintegerarr1[DC__NUM_DPP__MAX];
 838         unsigned int        dummyintegerarr2[DC__NUM_DPP__MAX];
 839         unsigned int        dummyintegerarr3[DC__NUM_DPP__MAX];
 840         unsigned int        dummyintegerarr4[DC__NUM_DPP__MAX];
 841         unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
 842         unsigned int        dummy_integer_array22[22][DC__NUM_DPP__MAX];
 843
 844         bool           dummysinglestring;
 845         bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 846         double         PlaneRequiredDISPCLKWithODMCombine2To1;
 847         double         PlaneRequiredDISPCLKWithODMCombine4To1;
 848         unsigned int   TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];
 849         bool           LinkDSCEnable;
 850         bool           ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
 851         enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
 852         double   SwathWidthCThisState[DC__NUM_DPP__MAX];
 853         bool           ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 854         double         AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
 855         double         AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
 856
 857         unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
 858         unsigned int NotEnoughUrgentLatencyHidingPre;
 859         int PTEBufferSizeInRequestsForLuma;
 860         int PTEBufferSizeInRequestsForChroma;
 861
 862         // Missing from VBA
 863         int dpte_group_bytes_chroma;
 864         unsigned int vm_group_bytes_chroma;
 865         double dst_x_after_scaler;
 866         double dst_y_after_scaler;
 867         unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
 868
 869         /* perf locals*/
 870         double PrefetchBandwidth[DC__NUM_DPP__MAX];
 871         double VInitPreFillY[DC__NUM_DPP__MAX];
 872         double VInitPreFillC[DC__NUM_DPP__MAX];
 873         unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
 874         unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
 875         unsigned int VStartup[DC__NUM_DPP__MAX];
 876         double DSTYAfterScaler[DC__NUM_DPP__MAX];
 877         double DSTXAfterScaler[DC__NUM_DPP__MAX];
 878         bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
 879         bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
 880         double VRatioPrefetchY[DC__NUM_DPP__MAX];
 881         double VRatioPrefetchC[DC__NUM_DPP__MAX];
 882         double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
 883         double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
 884         double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
 885         double MinTTUVBlank[DC__NUM_DPP__MAX];
 886         double BytePerPixelDETY[DC__NUM_DPP__MAX];
 887         double BytePerPixelDETC[DC__NUM_DPP__MAX];
 888         double SwathWidthY[DC__NUM_DPP__MAX];
 889         double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
 890         double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
 891         double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
 892         double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
 893         double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
 894         double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
 895         double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
 896         double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
 897         double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
 898         double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
 899         double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
 900         double MetaRowByte[DC__NUM_DPP__MAX];
 901         double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
 902         double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
 903         double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
 904         double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
 905         double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
 906         double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
 907         double DSCCLK_calculated[DC__NUM_DPP__MAX];
 908         unsigned int DSCDelay[DC__NUM_DPP__MAX];
 909         unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
 910         double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
 911         double DPPCLK[DC__NUM_DPP__MAX];
 912         unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
 913         unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
 914         unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
 915         double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
 916         unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
 917         unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
 918         unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
 919         unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
 920         double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
 921         double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
 922         double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
 923         double XFCTransferDelay[DC__NUM_DPP__MAX];
 924         double XFCPrechargeDelay[DC__NUM_DPP__MAX];
 925         double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
 926         double XFCPrefetchMargin[DC__NUM_DPP__MAX];
 927         unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
 928         unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
 929         double FullDETBufferingTimeY[DC__NUM_DPP__MAX];                     // WM
 930         double FullDETBufferingTimeC[DC__NUM_DPP__MAX];                     // WM
 931         double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
 932         double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
 933         double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
 934         double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
 935         double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
 936         double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
 937         unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
 938         unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
 939         unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
 940         unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
 941         unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
 942         unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
 943         unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
 944         unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
 945         double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
 946         double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
 947         double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
 948         double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
 949         double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
 950         double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
 951         double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
 952         double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
 953         double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
 954         double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
 955         unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
 956         unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
 957         unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
 958         unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
 959         double LinesToFinishSwathTransferStutterCriticalPlane;
 960         unsigned int BytePerPixelYCriticalPlane;
 961         double SwathWidthYCriticalPlane;
 962         double LinesInDETY[DC__NUM_DPP__MAX];
 963         double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
 964
 965         double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
 966         double SwathWidthC[DC__NUM_DPP__MAX];
 967         unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
 968         unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
 969         unsigned int dummyinteger1;
 970         unsigned int dummyinteger2;
 971         double FinalDRAMClockChangeLatency;
 972         double Tdmdl_vm[DC__NUM_DPP__MAX];
 973         double Tdmdl[DC__NUM_DPP__MAX];
 974         double TSetup[DC__NUM_DPP__MAX];
 975         unsigned int ThisVStartup;
 976         bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
 977         double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
 978         double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
 979         double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
 980         double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
 981         unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
 982         unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
 983         unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX];
 984         double VStartupMargin;
 985         bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
 986
 987         /* Missing from VBA */
 988         unsigned int MaximumMaxVStartupLines;
 989         double FabricAndDRAMBandwidth;
 990         double LinesInDETLuma;
 991         double LinesInDETChroma;
 992         unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
 993         unsigned int LinesInDETC[DC__NUM_DPP__MAX];
 994         unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
 995         double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 996         double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
 997         double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];
 998         bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
 999         unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1000         unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1001         double qual_row_bw[DC__NUM_DPP__MAX];
1002         double prefetch_row_bw[DC__NUM_DPP__MAX];
1003         double prefetch_vm_bw[DC__NUM_DPP__MAX];
1004
1005         double PTEGroupSize;
1006         unsigned int PDEProcessingBufIn64KBReqs;
1007
1008         double MaxTotalVActiveRDBandwidth;
1009         bool DoUrgentLatencyAdjustment;
1010         double UrgentLatencyAdjustmentFabricClockComponent;
1011         double UrgentLatencyAdjustmentFabricClockReference;
1012         double MinUrgentLatencySupportUs;
1013         double MinFullDETBufferingTime;
1014         double AverageReadBandwidthGBytePerSecond;
1015         bool   FirstMainPlane;
1016
1017         unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
1018         unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
1019         double HRatioChroma[DC__NUM_DPP__MAX];
1020         double VRatioChroma[DC__NUM_DPP__MAX];
1021         int WritebackSourceWidth[DC__NUM_DPP__MAX];
1022
1023         bool ModeIsSupported;
1024         bool ODMCombine4To1Supported;
1025
1026         unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
1027         unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
1028         unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
1029         unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
1030         unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
1031         unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
1032         bool DSCEnable[DC__NUM_DPP__MAX];
1033
1034         double DRAMClockChangeLatencyOverride;
1035
1036         double GPUVMMinPageSize;
1037         double HostVMMinPageSize;
1038
1039         bool   MPCCombineEnable[DC__NUM_DPP__MAX];
1040         unsigned int HostVMMaxNonCachedPageTableLevels;
1041         bool   DynamicMetadataVMEnabled;
1042         double       WritebackInterfaceBufferSize;
1043         double       WritebackLineBufferSize;
1044
1045         double DCCRateLuma[DC__NUM_DPP__MAX];
1046         double DCCRateChroma[DC__NUM_DPP__MAX];
1047
1048         double PHYCLKD18PerState[DC__VOLTAGE_STATES];
1049
1050         bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
1051         bool NumberOfHDMIFRLSupport;
1052         unsigned int MaxNumHDMIFRLOutputs;
1053         int    AudioSampleRate[DC__NUM_DPP__MAX];
1054         int    AudioSampleLayout[DC__NUM_DPP__MAX];
1055
1056         int PercentMarginOverMinimumRequiredDCFCLK;
1057         bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
1058         enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX];
1059         unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
1060         unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
1061         bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
1062         bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1063         int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
1064         int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
1065         double UrgLatency[DC__VOLTAGE_STATES];
1066         double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1067         double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1068         bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1069         bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1070         double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1071         double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1072         double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1073         double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1074         unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1075         unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1076         bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
1077         unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1078         unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1079         unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1080         unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1081         double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];
1082         double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];
1083         double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];
1084         double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];
1085         double WritebackDelayTime[DC__NUM_DPP__MAX];
1086         unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
1087         unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
1088         unsigned int dummyinteger15;
1089         unsigned int dummyinteger16;
1090         unsigned int dummyinteger17;
1091         unsigned int dummyinteger18;
1092         unsigned int dummyinteger19;
1093         unsigned int dummyinteger20;
1094         unsigned int dummyinteger21;
1095         unsigned int dummyinteger22;
1096         unsigned int dummyinteger23;
1097         unsigned int dummyinteger24;
1098         unsigned int dummyinteger25;
1099         unsigned int dummyinteger26;
1100         unsigned int dummyinteger27;
1101         unsigned int dummyinteger28;
1102         unsigned int dummyinteger29;
1103         bool dummystring[DC__NUM_DPP__MAX];
1104         double BPP;
1105         enum odm_combine_policy ODMCombinePolicy;
1106         bool UseMinimumRequiredDCFCLK;
1107         bool ClampMinDCFCLK;
1108         bool AllowDramClockChangeOneDisplayVactive;
1109
1110         double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
1111         double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
1112         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
1113         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
1114         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
1115         double SRExitZ8Time;
1116         double SREnterPlusExitZ8Time;
1117         double Z8StutterExitWatermark;
1118         double Z8StutterEnterPlusExitWatermark;
1119         double Z8StutterEfficiencyNotIncludingVBlank;
1120         double Z8StutterEfficiency;
1121         double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
1122         double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
1123         double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
1124         double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
1125         double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
1126         double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
1127         double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1128         double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1129         bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1130         bool LinkCapacitySupport[DC__NUM_DPP__MAX];
1131         bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1132         unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1133         unsigned int VFrontPorch[DC__NUM_DPP__MAX];
1134         int ConfigReturnBufferSizeInKByte;
1135         enum unbounded_requesting_policy UseUnboundedRequesting;
1136         int CompressedBufferSegmentSizeInkByte;
1137         int CompressedBufferSizeInkByte;
1138         int MetaFIFOSizeInKEntries;
1139         int ZeroSizeBufferEntries;
1140         int COMPBUF_RESERVED_SPACE_64B;
1141         int COMPBUF_RESERVED_SPACE_ZS;
1142         bool UnboundedRequestEnabled;
1143         bool DSC422NativeSupport;
1144         bool NoEnoughUrgentLatencyHiding;
1145         bool NoEnoughUrgentLatencyHidingPre;
1146         int NumberOfStutterBurstsPerFrame;
1147         int Z8NumberOfStutterBurstsPerFrame;
1148         unsigned int MaximumDSCBitsPerComponent;
1149         unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
1150         double UrgentLatencyWithUSRRetraining;
1151         double UrgLatencyWithUSRRetraining[DC__VOLTAGE_STATES];
1152         double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
1153         double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
1154         double SurfaceRequiredDISPCLKWithoutODMCombine;
1155         double SurfaceRequiredDISPCLK;
1156         double SurfaceRequiredDISPCLKWithODMCombine2To1;
1157         double SurfaceRequiredDISPCLKWithODMCombine4To1;
1158         double MinActiveFCLKChangeLatencySupported;
1159         double dummy14;
1160         double dummy15;
1161         int MinVoltageLevel;
1162         int MaxVoltageLevel;
1163         unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
1164         unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
1165         unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1166         unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
1167         unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
1168         bool ExceededMALLSize;
1169         bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
1170         unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
1171         unsigned int dummyinteger33;
1172         unsigned int CompressedBufferSizeInkByteThisState;
1173         enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
1174         Latencies myLatency;
1175         Latencies mLatency;
1176         Watermarks DummyWatermark;
1177         bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
1178         bool dummyBooleanvector1[DC__NUM_DPP__MAX];
1179         bool dummyBooleanvector2[DC__NUM_DPP__MAX];
1180         enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
1181         bool NotEnoughUrgentLatencyHiding_dml32[DC__VOLTAGE_STATES][2];
1182         bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
1183         bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
1184         enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
1185         bool UnboundedRequestEnabledThisState;
1186         bool DRAMClockChangeRequirementFinal;
1187         bool FCLKChangeRequirementFinal;
1188         bool USRRetrainingRequiredFinal;
1189         bool MALLUseFinal;
1190         bool ConfigurableDETSizeEnFinal;
1191         bool dummyboolean;
1192         unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
1193         unsigned int nomDETInKByte;
1194         enum mpc_combine_affinity  MPCCombineUse[DC__NUM_DPP__MAX];
1195         bool MPCCombineMethodIncompatible;
1196         unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
1197         bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
1198         enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
1199         unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
1200         bool OutputMultistreamEn[DC__NUM_DPP__MAX];
1201         bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
1202         double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
1203         double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
1204         bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1205         bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1206         bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
1207         bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
1208         bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
1209         unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
1210         unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
1211         unsigned int BlockHeightY[DC__NUM_DPP__MAX];
1212         unsigned int BlockHeightC[DC__NUM_DPP__MAX];
1213         unsigned int BlockWidthY[DC__NUM_DPP__MAX];
1214         unsigned int BlockWidthC[DC__NUM_DPP__MAX];
1215         unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
1216         bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
1217         struct dummy_vars dummy_vars;
1218 };
1219
1220 bool CalculateMinAndMaxPrefetchMode(
1221                 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
1222                 unsigned int *MinPrefetchMode,
1223                 unsigned int *MaxPrefetchMode);
1224
1225 double CalculateWriteBackDISPCLK(
1226                 enum source_format_class WritebackPixelFormat,
1227                 double PixelClock,
1228                 double WritebackHRatio,
1229                 double WritebackVRatio,
1230                 unsigned int WritebackLumaHTaps,
1231                 unsigned int WritebackLumaVTaps,
1232                 unsigned int WritebackChromaHTaps,
1233                 unsigned int WritebackChromaVTaps,
1234                 double WritebackDestinationWidth,
1235                 unsigned int HTotal,
1236                 unsigned int WritebackChromaLineBufferWidth);
1237
1238 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */