drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc_features.h"
  27 #include "display_mode_enums.h"
  28
  29 #ifndef __DISPLAY_MODE_STRUCTS_H__
  30 #define __DISPLAY_MODE_STRUCTS_H__
  31
  32 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
  33 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
  34 typedef struct _vcs_dpi_ip_params_st ip_params_st;
  35 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
  36 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
  37 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
  38 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
  39 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
  40 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
  41 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
  42 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
  43 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
  44 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
  45 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
  46 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
  47 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
  48 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
  49 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
  50 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
  51 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
  52 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
  53 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
  54 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
  55 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
  56
  57 struct _vcs_dpi_voltage_scaling_st {
  58         int state;
  59         double dscclk_mhz;
  60         double dcfclk_mhz;
  61         double socclk_mhz;
  62         double phyclk_d18_mhz;
  63         double dram_speed_mts;
  64         double fabricclk_mhz;
  65         double dispclk_mhz;
  66         double dram_bw_per_chan_gbps;
  67         double phyclk_mhz;
  68         double dppclk_mhz;
  69         double dtbclk_mhz;
  70 };
  71
  72 struct _vcs_dpi_soc_bounding_box_st {
  73         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
  74         unsigned int num_states;
  75         double sr_exit_time_us;
  76         double sr_enter_plus_exit_time_us;
  77         double sr_exit_z8_time_us;
  78         double sr_enter_plus_exit_z8_time_us;
  79         double urgent_latency_us;
  80         double urgent_latency_pixel_data_only_us;
  81         double urgent_latency_pixel_mixed_with_vm_data_us;
  82         double urgent_latency_vm_data_only_us;
  83         double writeback_latency_us;
  84         double ideal_dram_bw_after_urgent_percent;
  85         double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
  86         double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
  87         double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
  88         double pct_ideal_sdp_bw_after_urgent;
  89         double max_avg_sdp_bw_use_normal_percent;
  90         double max_avg_dram_bw_use_normal_percent;
  91         unsigned int max_request_size_bytes;
  92         double downspread_percent;
  93         double dram_page_open_time_ns;
  94         double dram_rw_turnaround_time_ns;
  95         double dram_return_buffer_per_channel_bytes;
  96         double dram_channel_width_bytes;
  97         double fabric_datapath_to_dcn_data_return_bytes;
  98         double dcn_downspread_percent;
  99         double dispclk_dppclk_vco_speed_mhz;
 100         double dfs_vco_period_ps;
 101         unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
 102         unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
 103         unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
 104         unsigned int round_trip_ping_latency_dcfclk_cycles;
 105         unsigned int urgent_out_of_order_return_per_channel_bytes;
 106         unsigned int channel_interleave_bytes;
 107         unsigned int num_banks;
 108         unsigned int num_chans;
 109         unsigned int vmm_page_size_bytes;
 110         unsigned int hostvm_min_page_size_bytes;
 111         unsigned int gpuvm_min_page_size_bytes;
 112         double dram_clock_change_latency_us;
 113         double dummy_pstate_latency_us;
 114         double writeback_dram_clock_change_latency_us;
 115         unsigned int return_bus_width_bytes;
 116         unsigned int voltage_override;
 117         double xfc_bus_transport_time_us;
 118         double xfc_xbuf_latency_tolerance_us;
 119         int use_urgent_burst_bw;
 120         double min_dcfclk;
 121         bool do_urgent_latency_adjustment;
 122         double urgent_latency_adjustment_fabric_clock_component_us;
 123         double urgent_latency_adjustment_fabric_clock_reference_mhz;
 124         bool disable_dram_clock_change_vactive_support;
 125         bool allow_dram_clock_one_display_vactive;
 126         enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank;
 127 };
 128
 129 struct _vcs_dpi_ip_params_st {
 130         bool use_min_dcfclk;
 131         bool clamp_min_dcfclk;
 132         bool gpuvm_enable;
 133         bool hostvm_enable;
 134         bool dsc422_native_support;
 135         unsigned int gpuvm_max_page_table_levels;
 136         unsigned int hostvm_max_page_table_levels;
 137         unsigned int hostvm_cached_page_table_levels;
 138         unsigned int pte_group_size_bytes;
 139         unsigned int max_inter_dcn_tile_repeaters;
 140         unsigned int num_dsc;
 141         unsigned int odm_capable;
 142         unsigned int rob_buffer_size_kbytes;
 143         unsigned int det_buffer_size_kbytes;
 144         unsigned int dpte_buffer_size_in_pte_reqs_luma;
 145         unsigned int dpte_buffer_size_in_pte_reqs_chroma;
 146         unsigned int pde_proc_buffer_size_64k_reqs;
 147         unsigned int dpp_output_buffer_pixels;
 148         unsigned int opp_output_buffer_lines;
 149         unsigned int pixel_chunk_size_kbytes;
 150         unsigned char pte_enable;
 151         unsigned int pte_chunk_size_kbytes;
 152         unsigned int meta_chunk_size_kbytes;
 153         unsigned int min_meta_chunk_size_bytes;
 154         unsigned int writeback_chunk_size_kbytes;
 155         unsigned int line_buffer_size_bits;
 156         unsigned int max_line_buffer_lines;
 157         unsigned int writeback_luma_buffer_size_kbytes;
 158         unsigned int writeback_chroma_buffer_size_kbytes;
 159         unsigned int writeback_chroma_line_buffer_width_pixels;
 160
 161         unsigned int writeback_interface_buffer_size_kbytes;
 162         unsigned int writeback_line_buffer_buffer_size;
 163
 164         unsigned int writeback_10bpc420_supported;
 165         double writeback_max_hscl_ratio;
 166         double writeback_max_vscl_ratio;
 167         double writeback_min_hscl_ratio;
 168         double writeback_min_vscl_ratio;
 169         unsigned int maximum_dsc_bits_per_component;
 170         unsigned int writeback_max_hscl_taps;
 171         unsigned int writeback_max_vscl_taps;
 172         unsigned int writeback_line_buffer_luma_buffer_size;
 173         unsigned int writeback_line_buffer_chroma_buffer_size;
 174
 175         unsigned int max_page_table_levels;
 176         unsigned int max_num_dpp;
 177         unsigned int max_num_otg;
 178         unsigned int cursor_chunk_size;
 179         unsigned int cursor_buffer_size;
 180         unsigned int max_num_wb;
 181         unsigned int max_dchub_pscl_bw_pix_per_clk;
 182         unsigned int max_pscl_lb_bw_pix_per_clk;
 183         unsigned int max_lb_vscl_bw_pix_per_clk;
 184         unsigned int max_vscl_hscl_bw_pix_per_clk;
 185         double max_hscl_ratio;
 186         double max_vscl_ratio;
 187         unsigned int hscl_mults;
 188         unsigned int vscl_mults;
 189         unsigned int max_hscl_taps;
 190         unsigned int max_vscl_taps;
 191         unsigned int xfc_supported;
 192         unsigned int ptoi_supported;
 193         unsigned int gfx7_compat_tiling_supported;
 194
 195         bool odm_combine_4to1_supported;
 196         bool dynamic_metadata_vm_enabled;
 197         unsigned int max_num_hdmi_frl_outputs;
 198
 199         unsigned int xfc_fill_constant_bytes;
 200         double dispclk_ramp_margin_percent;
 201         double xfc_fill_bw_overhead_percent;
 202         double underscan_factor;
 203         unsigned int min_vblank_lines;
 204         unsigned int dppclk_delay_subtotal;
 205         unsigned int dispclk_delay_subtotal;
 206         double dcfclk_cstate_latency;
 207         unsigned int dppclk_delay_scl;
 208         unsigned int dppclk_delay_scl_lb_only;
 209         unsigned int dppclk_delay_cnvc_formatter;
 210         unsigned int dppclk_delay_cnvc_cursor;
 211         unsigned int is_line_buffer_bpp_fixed;
 212         unsigned int line_buffer_fixed_bpp;
 213         unsigned int dcc_supported;
 214         unsigned int config_return_buffer_size_in_kbytes;
 215         unsigned int compressed_buffer_segment_size_in_kbytes;
 216         unsigned int meta_fifo_size_in_kentries;
 217         unsigned int zero_size_buffer_entries;
 218         unsigned int compbuf_reserved_space_64b;
 219         unsigned int compbuf_reserved_space_zs;
 220
 221         unsigned int IsLineBufferBppFixed;
 222         unsigned int LineBufferFixedBpp;
 223         unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 224         unsigned int bug_forcing_LC_req_same_size_fixed;
 225         unsigned int number_of_cursors;
 226 };
 227
 228 struct _vcs_dpi_display_xfc_params_st {
 229         double xfc_tslv_vready_offset_us;
 230         double xfc_tslv_vupdate_width_us;
 231         double xfc_tslv_vupdate_offset_us;
 232         int xfc_slv_chunk_size_bytes;
 233 };
 234
 235 struct _vcs_dpi_display_pipe_source_params_st {
 236         int source_format;
 237         double dcc_fraction_of_zs_req_luma;
 238         double dcc_fraction_of_zs_req_chroma;
 239         unsigned char dcc;
 240         unsigned int dcc_rate;
 241         unsigned int dcc_rate_chroma;
 242         unsigned char dcc_use_global;
 243         unsigned char vm;
 244         bool unbounded_req_mode;
 245         bool gpuvm;    // gpuvm enabled
 246         bool hostvm;    // hostvm enabled
 247         bool gpuvm_levels_force_en;
 248         unsigned int gpuvm_levels_force;
 249         bool hostvm_levels_force_en;
 250         unsigned int hostvm_levels_force;
 251         int source_scan;
 252         int sw_mode;
 253         int macro_tile_size;
 254         unsigned int surface_width_y;
 255         unsigned int surface_height_y;
 256         unsigned int surface_width_c;
 257         unsigned int surface_height_c;
 258         unsigned int viewport_width;
 259         unsigned int viewport_height;
 260         unsigned int viewport_y_y;
 261         unsigned int viewport_y_c;
 262         unsigned int viewport_width_c;
 263         unsigned int viewport_height_c;
 264         unsigned int viewport_width_max;
 265         unsigned int viewport_height_max;
 266         unsigned int data_pitch;
 267         unsigned int data_pitch_c;
 268         unsigned int meta_pitch;
 269         unsigned int meta_pitch_c;
 270         unsigned int cur0_src_width;
 271         int cur0_bpp;
 272         unsigned int cur1_src_width;
 273         int cur1_bpp;
 274         int num_cursors;
 275         unsigned char is_hsplit;
 276         unsigned char dynamic_metadata_enable;
 277         unsigned int dynamic_metadata_lines_before_active;
 278         unsigned int dynamic_metadata_xmit_bytes;
 279         unsigned int hsplit_grp;
 280         unsigned char xfc_enable;
 281         unsigned char xfc_slave;
 282         unsigned char immediate_flip;
 283         struct _vcs_dpi_display_xfc_params_st xfc_params;
 284         //for vstartuplines calculation freesync
 285         unsigned char v_total_min;
 286         unsigned char v_total_max;
 287 };
 288 struct writeback_st {
 289         int wb_src_height;
 290         int wb_src_width;
 291         int wb_dst_width;
 292         int wb_dst_height;
 293         int wb_pixel_format;
 294         int wb_htaps_luma;
 295         int wb_vtaps_luma;
 296         int wb_htaps_chroma;
 297         int wb_vtaps_chroma;
 298         double wb_hratio;
 299         double wb_vratio;
 300 };
 301
 302 struct _vcs_dpi_display_output_params_st {
 303         int dp_lanes;
 304         double output_bpp;
 305         unsigned int dsc_input_bpc;
 306         int dsc_enable;
 307         int wb_enable;
 308         int num_active_wb;
 309         int output_type;
 310         int is_virtual;
 311         int output_format;
 312         int dsc_slices;
 313         int max_audio_sample_rate;
 314         struct writeback_st wb;
 315 };
 316
 317 struct _vcs_dpi_scaler_ratio_depth_st {
 318         double hscl_ratio;
 319         double vscl_ratio;
 320         double hscl_ratio_c;
 321         double vscl_ratio_c;
 322         double vinit;
 323         double vinit_c;
 324         double vinit_bot;
 325         double vinit_bot_c;
 326         int lb_depth;
 327         int scl_enable;
 328 };
 329
 330 struct _vcs_dpi_scaler_taps_st {
 331         unsigned int htaps;
 332         unsigned int vtaps;
 333         unsigned int htaps_c;
 334         unsigned int vtaps_c;
 335 };
 336
 337 struct _vcs_dpi_display_pipe_dest_params_st {
 338         unsigned int recout_width;
 339         unsigned int recout_height;
 340         unsigned int full_recout_width;
 341         unsigned int full_recout_height;
 342         unsigned int hblank_start;
 343         unsigned int hblank_end;
 344         unsigned int vblank_start;
 345         unsigned int vblank_end;
 346         unsigned int htotal;
 347         unsigned int vtotal;
 348         unsigned int vfront_porch;
 349         unsigned int vactive;
 350         unsigned int hactive;
 351         unsigned int vstartup_start;
 352         unsigned int vupdate_offset;
 353         unsigned int vupdate_width;
 354         unsigned int vready_offset;
 355         unsigned char interlaced;
 356         double pixel_rate_mhz;
 357         unsigned char synchronized_vblank_all_planes;
 358         unsigned char otg_inst;
 359         unsigned int odm_combine;
 360         unsigned char use_maximum_vstartup;
 361         unsigned int vtotal_max;
 362         unsigned int vtotal_min;
 363 };
 364
 365 struct _vcs_dpi_display_pipe_params_st {
 366         display_pipe_source_params_st src;
 367         display_pipe_dest_params_st dest;
 368         scaler_ratio_depth_st scale_ratio_depth;
 369         scaler_taps_st scale_taps;
 370 };
 371
 372 struct _vcs_dpi_display_clocks_and_cfg_st {
 373         int voltage;
 374         double dppclk_mhz;
 375         double refclk_mhz;
 376         double dispclk_mhz;
 377         double dcfclk_mhz;
 378         double socclk_mhz;
 379 };
 380
 381 struct _vcs_dpi_display_e2e_pipe_params_st {
 382         display_pipe_params_st pipe;
 383         display_output_params_st dout;
 384         display_clocks_and_cfg_st clks_cfg;
 385 };
 386
 387 struct _vcs_dpi_display_data_rq_misc_params_st {
 388         unsigned int full_swath_bytes;
 389         unsigned int stored_swath_bytes;
 390         unsigned int blk256_height;
 391         unsigned int blk256_width;
 392         unsigned int req_height;
 393         unsigned int req_width;
 394 };
 395
 396 struct _vcs_dpi_display_data_rq_sizing_params_st {
 397         unsigned int chunk_bytes;
 398         unsigned int min_chunk_bytes;
 399         unsigned int meta_chunk_bytes;
 400         unsigned int min_meta_chunk_bytes;
 401         unsigned int mpte_group_bytes;
 402         unsigned int dpte_group_bytes;
 403 };
 404
 405 struct _vcs_dpi_display_data_rq_dlg_params_st {
 406         unsigned int swath_width_ub;
 407         unsigned int swath_height;
 408         unsigned int req_per_swath_ub;
 409         unsigned int meta_pte_bytes_per_frame_ub;
 410         unsigned int dpte_req_per_row_ub;
 411         unsigned int dpte_groups_per_row_ub;
 412         unsigned int dpte_row_height;
 413         unsigned int dpte_bytes_per_row_ub;
 414         unsigned int meta_chunks_per_row_ub;
 415         unsigned int meta_req_per_row_ub;
 416         unsigned int meta_row_height;
 417         unsigned int meta_bytes_per_row_ub;
 418 };
 419
 420 struct _vcs_dpi_display_rq_dlg_params_st {
 421         display_data_rq_dlg_params_st rq_l;
 422         display_data_rq_dlg_params_st rq_c;
 423 };
 424
 425 struct _vcs_dpi_display_rq_sizing_params_st {
 426         display_data_rq_sizing_params_st rq_l;
 427         display_data_rq_sizing_params_st rq_c;
 428 };
 429
 430 struct _vcs_dpi_display_rq_misc_params_st {
 431         display_data_rq_misc_params_st rq_l;
 432         display_data_rq_misc_params_st rq_c;
 433 };
 434
 435 struct _vcs_dpi_display_rq_params_st {
 436         unsigned char yuv420;
 437         unsigned char yuv420_10bpc;
 438         unsigned char rgbe_alpha;
 439         display_rq_misc_params_st misc;
 440         display_rq_sizing_params_st sizing;
 441         display_rq_dlg_params_st dlg;
 442 };
 443
 444 struct _vcs_dpi_display_dlg_regs_st {
 445         unsigned int refcyc_h_blank_end;
 446         unsigned int dlg_vblank_end;
 447         unsigned int min_dst_y_next_start;
 448         unsigned int refcyc_per_htotal;
 449         unsigned int refcyc_x_after_scaler;
 450         unsigned int dst_y_after_scaler;
 451         unsigned int dst_y_prefetch;
 452         unsigned int dst_y_per_vm_vblank;
 453         unsigned int dst_y_per_row_vblank;
 454         unsigned int dst_y_per_vm_flip;
 455         unsigned int dst_y_per_row_flip;
 456         unsigned int ref_freq_to_pix_freq;
 457         unsigned int vratio_prefetch;
 458         unsigned int vratio_prefetch_c;
 459         unsigned int refcyc_per_pte_group_vblank_l;
 460         unsigned int refcyc_per_pte_group_vblank_c;
 461         unsigned int refcyc_per_meta_chunk_vblank_l;
 462         unsigned int refcyc_per_meta_chunk_vblank_c;
 463         unsigned int refcyc_per_pte_group_flip_l;
 464         unsigned int refcyc_per_pte_group_flip_c;
 465         unsigned int refcyc_per_meta_chunk_flip_l;
 466         unsigned int refcyc_per_meta_chunk_flip_c;
 467         unsigned int dst_y_per_pte_row_nom_l;
 468         unsigned int dst_y_per_pte_row_nom_c;
 469         unsigned int refcyc_per_pte_group_nom_l;
 470         unsigned int refcyc_per_pte_group_nom_c;
 471         unsigned int dst_y_per_meta_row_nom_l;
 472         unsigned int dst_y_per_meta_row_nom_c;
 473         unsigned int refcyc_per_meta_chunk_nom_l;
 474         unsigned int refcyc_per_meta_chunk_nom_c;
 475         unsigned int refcyc_per_line_delivery_pre_l;
 476         unsigned int refcyc_per_line_delivery_pre_c;
 477         unsigned int refcyc_per_line_delivery_l;
 478         unsigned int refcyc_per_line_delivery_c;
 479         unsigned int chunk_hdl_adjust_cur0;
 480         unsigned int chunk_hdl_adjust_cur1;
 481         unsigned int vready_after_vcount0;
 482         unsigned int dst_y_offset_cur0;
 483         unsigned int dst_y_offset_cur1;
 484         unsigned int xfc_reg_transfer_delay;
 485         unsigned int xfc_reg_precharge_delay;
 486         unsigned int xfc_reg_remote_surface_flip_latency;
 487         unsigned int xfc_reg_prefetch_margin;
 488         unsigned int dst_y_delta_drq_limit;
 489         unsigned int refcyc_per_vm_group_vblank;
 490         unsigned int refcyc_per_vm_group_flip;
 491         unsigned int refcyc_per_vm_req_vblank;
 492         unsigned int refcyc_per_vm_req_flip;
 493         unsigned int refcyc_per_vm_dmdata;
 494         unsigned int dmdata_dl_delta;
 495 };
 496
 497 struct _vcs_dpi_display_ttu_regs_st {
 498         unsigned int qos_level_low_wm;
 499         unsigned int qos_level_high_wm;
 500         unsigned int min_ttu_vblank;
 501         unsigned int qos_level_flip;
 502         unsigned int refcyc_per_req_delivery_l;
 503         unsigned int refcyc_per_req_delivery_c;
 504         unsigned int refcyc_per_req_delivery_cur0;
 505         unsigned int refcyc_per_req_delivery_cur1;
 506         unsigned int refcyc_per_req_delivery_pre_l;
 507         unsigned int refcyc_per_req_delivery_pre_c;
 508         unsigned int refcyc_per_req_delivery_pre_cur0;
 509         unsigned int refcyc_per_req_delivery_pre_cur1;
 510         unsigned int qos_level_fixed_l;
 511         unsigned int qos_level_fixed_c;
 512         unsigned int qos_level_fixed_cur0;
 513         unsigned int qos_level_fixed_cur1;
 514         unsigned int qos_ramp_disable_l;
 515         unsigned int qos_ramp_disable_c;
 516         unsigned int qos_ramp_disable_cur0;
 517         unsigned int qos_ramp_disable_cur1;
 518 };
 519
 520 struct _vcs_dpi_display_data_rq_regs_st {
 521         unsigned int chunk_size;
 522         unsigned int min_chunk_size;
 523         unsigned int meta_chunk_size;
 524         unsigned int min_meta_chunk_size;
 525         unsigned int dpte_group_size;
 526         unsigned int mpte_group_size;
 527         unsigned int swath_height;
 528         unsigned int pte_row_height_linear;
 529 };
 530
 531 struct _vcs_dpi_display_rq_regs_st {
 532         display_data_rq_regs_st rq_regs_l;
 533         display_data_rq_regs_st rq_regs_c;
 534         unsigned int drq_expansion_mode;
 535         unsigned int prq_expansion_mode;
 536         unsigned int mrq_expansion_mode;
 537         unsigned int crq_expansion_mode;
 538         unsigned int plane1_base_address;
 539         unsigned int aperture_low_addr;   // bits [47:18]
 540         unsigned int aperture_high_addr;  // bits [47:18]
 541 };
 542
 543 struct _vcs_dpi_display_dlg_sys_params_st {
 544         double t_mclk_wm_us;
 545         double t_urg_wm_us;
 546         double t_sr_wm_us;
 547         double t_extra_us;
 548         double mem_trip_us;
 549         double t_srx_delay_us;
 550         double deepsleep_dcfclk_mhz;
 551         double total_flip_bw;
 552         unsigned int total_flip_bytes;
 553 };
 554
 555 struct _vcs_dpi_display_arb_params_st {
 556         int max_req_outstanding;
 557         int min_req_outstanding;
 558         int sat_level_us;
 559 };
 560
 561 #endif /*__DISPLAY_MODE_STRUCTS_H__*/