drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "clk_mgr.h"
  28 #include "resource.h"
  29 #include "dcn321_fpu.h"
  30 #include "dcn32/dcn32_resource.h"
  31 #include "dcn321/dcn321_resource.h"
  32
  33 #define DCN3_2_DEFAULT_DET_SIZE 256
  34
  35 struct _vcs_dpi_ip_params_st dcn3_21_ip = {
  36         .gpuvm_enable = 0,
  37         .gpuvm_max_page_table_levels = 4,
  38         .hostvm_enable = 0,
  39         .rob_buffer_size_kbytes = 128,
  40         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
  41         .config_return_buffer_size_in_kbytes = 1280,
  42         .compressed_buffer_segment_size_in_kbytes = 64,
  43         .meta_fifo_size_in_kentries = 22,
  44         .zero_size_buffer_entries = 512,
  45         .compbuf_reserved_space_64b = 256,
  46         .compbuf_reserved_space_zs = 64,
  47         .dpp_output_buffer_pixels = 2560,
  48         .opp_output_buffer_lines = 1,
  49         .pixel_chunk_size_kbytes = 8,
  50         .alpha_pixel_chunk_size_kbytes = 4,
  51         .min_pixel_chunk_size_bytes = 1024,
  52         .dcc_meta_buffer_size_bytes = 6272,
  53         .meta_chunk_size_kbytes = 2,
  54         .min_meta_chunk_size_bytes = 256,
  55         .writeback_chunk_size_kbytes = 8,
  56         .ptoi_supported = false,
  57         .num_dsc = 4,
  58         .maximum_dsc_bits_per_component = 12,
  59         .maximum_pixels_per_line_per_dsc_unit = 6016,
  60         .dsc422_native_support = true,
  61         .is_line_buffer_bpp_fixed = true,
  62         .line_buffer_fixed_bpp = 57,
  63         .line_buffer_size_bits = 1171920,
  64         .max_line_buffer_lines = 32,
  65         .writeback_interface_buffer_size_kbytes = 90,
  66         .max_num_dpp = 4,
  67         .max_num_otg = 4,
  68         .max_num_hdmi_frl_outputs = 1,
  69         .max_num_wb = 1,
  70         .max_dchub_pscl_bw_pix_per_clk = 4,
  71         .max_pscl_lb_bw_pix_per_clk = 2,
  72         .max_lb_vscl_bw_pix_per_clk = 4,
  73         .max_vscl_hscl_bw_pix_per_clk = 4,
  74         .max_hscl_ratio = 6,
  75         .max_vscl_ratio = 6,
  76         .max_hscl_taps = 8,
  77         .max_vscl_taps = 8,
  78         .dpte_buffer_size_in_pte_reqs_luma = 64,
  79         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  80         .dispclk_ramp_margin_percent = 1,
  81         .max_inter_dcn_tile_repeaters = 8,
  82         .cursor_buffer_size = 16,
  83         .cursor_chunk_size = 2,
  84         .writeback_line_buffer_buffer_size = 0,
  85         .writeback_min_hscl_ratio = 1,
  86         .writeback_min_vscl_ratio = 1,
  87         .writeback_max_hscl_ratio = 1,
  88         .writeback_max_vscl_ratio = 1,
  89         .writeback_max_hscl_taps = 1,
  90         .writeback_max_vscl_taps = 1,
  91         .dppclk_delay_subtotal = 47,
  92         .dppclk_delay_scl = 50,
  93         .dppclk_delay_scl_lb_only = 16,
  94         .dppclk_delay_cnvc_formatter = 28,
  95         .dppclk_delay_cnvc_cursor = 6,
  96         .dispclk_delay_subtotal = 125,
  97         .dynamic_metadata_vm_enabled = false,
  98         .odm_combine_4to1_supported = false,
  99         .dcc_supported = true,
 100         .max_num_dp2p0_outputs = 2,
 101         .max_num_dp2p0_streams = 4,
 102 };
 103
 104 struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
 105         .clock_limits = {
 106                 {
 107                         .state = 0,
 108                         .dcfclk_mhz = 1564.0,
 109                         .fabricclk_mhz = 400.0,
 110                         .dispclk_mhz = 2150.0,
 111                         .dppclk_mhz = 2150.0,
 112                         .phyclk_mhz = 810.0,
 113                         .phyclk_d18_mhz = 667.0,
 114                         .phyclk_d32_mhz = 625.0,
 115                         .socclk_mhz = 1200.0,
 116                         .dscclk_mhz = 716.667,
 117                         .dram_speed_mts = 1600.0,
 118                         .dtbclk_mhz = 1564.0,
 119                 },
 120         },
 121         .num_states = 1,
 122         .sr_exit_time_us = 12.36,
 123         .sr_enter_plus_exit_time_us = 16.72,
 124         .sr_exit_z8_time_us = 285.0,
 125         .sr_enter_plus_exit_z8_time_us = 320,
 126         .writeback_latency_us = 12.0,
 127         .round_trip_ping_latency_dcfclk_cycles = 263,
 128         .urgent_latency_pixel_data_only_us = 4.0,
 129         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 130         .urgent_latency_vm_data_only_us = 4.0,
 131         .fclk_change_latency_us = 20,
 132         .usr_retraining_latency_us = 2,
 133         .smn_latency_us = 2,
 134         .mall_allocated_for_dcn_mbytes = 64,
 135         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 136         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 137         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 138         .pct_ideal_sdp_bw_after_urgent = 100.0,
 139         .pct_ideal_fabric_bw_after_urgent = 67.0,
 140         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 141         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 142         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 143         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 144         .max_avg_sdp_bw_use_normal_percent = 80.0,
 145         .max_avg_fabric_bw_use_normal_percent = 60.0,
 146         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 147         .max_avg_dram_bw_use_normal_percent = 15.0,
 148         .num_chans = 8,
 149         .dram_channel_width_bytes = 2,
 150         .fabric_datapath_to_dcn_data_return_bytes = 64,
 151         .return_bus_width_bytes = 64,
 152         .downspread_percent = 0.38,
 153         .dcn_downspread_percent = 0.5,
 154         .dram_clock_change_latency_us = 400,
 155         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 156         .do_urgent_latency_adjustment = true,
 157         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 158         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 159 };
 160
 161 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
 162 {
 163         if (entry->dcfclk_mhz > 0) {
 164                 float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100);
 165
 166                 entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100));
 167                 entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans *
 168                                 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 169         } else if (entry->fabricclk_mhz > 0) {
 170                 float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100);
 171
 172                 entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100));
 173                 entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans *
 174                                 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 175         } else if (entry->dram_speed_mts > 0) {
 176                 float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans *
 177                                 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 178
 179                 entry->fabricclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100));
 180                 entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100));
 181         }
 182 }
 183
 184 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
 185 {
 186         float memory_bw_kbytes_sec;
 187         float fabric_bw_kbytes_sec;
 188         float sdp_bw_kbytes_sec;
 189         float limiting_bw_kbytes_sec;
 190
 191         memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans *
 192                         dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 193
 194         fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100);
 195
 196         sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100);
 197
 198         limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
 199
 200         if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
 201                 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
 202
 203         if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
 204                 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
 205
 206         return limiting_bw_kbytes_sec;
 207 }
 208
 209 void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
 210                                            unsigned int *num_entries,
 211                                            struct _vcs_dpi_voltage_scaling_st *entry)
 212 {
 213         int i = 0;
 214         int index = 0;
 215         float net_bw_of_new_state = 0;
 216
 217         dc_assert_fp_enabled();
 218
 219         get_optimal_ntuple(entry);
 220
 221         if (*num_entries == 0) {
 222                 table[0] = *entry;
 223                 (*num_entries)++;
 224         } else {
 225                 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry);
 226                 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) {
 227                         index++;
 228                         if (index >= *num_entries)
 229                                 break;
 230                 }
 231
 232                 for (i = *num_entries; i > index; i--)
 233                         table[i] = table[i - 1];
 234
 235                 table[index] = *entry;
 236                 (*num_entries)++;
 237         }
 238 }
 239
 240 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
 241                 unsigned int index)
 242 {
 243         int i;
 244
 245         if (*num_entries == 0)
 246                 return;
 247
 248         for (i = index; i < *num_entries - 1; i++) {
 249                 table[i] = table[i + 1];
 250         }
 251         memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
 252 }
 253
 254 static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
 255                 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
 256 {
 257         int i, j;
 258         struct _vcs_dpi_voltage_scaling_st entry = {0};
 259
 260         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
 261                         max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
 262
 263         unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
 264
 265         static const unsigned int num_dcfclk_stas = 5;
 266         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
 267
 268         unsigned int num_uclk_dpms = 0;
 269         unsigned int num_fclk_dpms = 0;
 270         unsigned int num_dcfclk_dpms = 0;
 271
 272         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
 273                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
 274                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
 275                 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
 276                         max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
 277                 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
 278                         max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
 279                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
 280                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
 281                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
 282                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
 283                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
 284                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
 285                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
 286                         max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
 287
 288                 if (bw_params->clk_table.entries[i].memclk_mhz > 0)
 289                         num_uclk_dpms++;
 290                 if (bw_params->clk_table.entries[i].fclk_mhz > 0)
 291                         num_fclk_dpms++;
 292                 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0)
 293                         num_dcfclk_dpms++;
 294         }
 295
 296         if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)
 297                 return -1;
 298
 299         if (max_dppclk_mhz == 0)
 300                 max_dppclk_mhz = max_dispclk_mhz;
 301
 302         if (max_fclk_mhz == 0)
 303                 max_fclk_mhz = max_dcfclk_mhz * dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / dcn3_21_soc.pct_ideal_fabric_bw_after_urgent;
 304
 305         if (max_phyclk_mhz == 0)
 306                 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
 307
 308         *num_entries = 0;
 309         entry.dispclk_mhz = max_dispclk_mhz;
 310         entry.dscclk_mhz = max_dispclk_mhz / 3;
 311         entry.dppclk_mhz = max_dppclk_mhz;
 312         entry.dtbclk_mhz = max_dtbclk_mhz;
 313         entry.phyclk_mhz = max_phyclk_mhz;
 314         entry.phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
 315         entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
 316
 317         // Insert all the DCFCLK STAs
 318         for (i = 0; i < num_dcfclk_stas; i++) {
 319                 entry.dcfclk_mhz = dcfclk_sta_targets[i];
 320                 entry.fabricclk_mhz = 0;
 321                 entry.dram_speed_mts = 0;
 322
 323                 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry);
 324         }
 325
 326         // Insert the max DCFCLK
 327         entry.dcfclk_mhz = max_dcfclk_mhz;
 328         entry.fabricclk_mhz = 0;
 329         entry.dram_speed_mts = 0;
 330
 331         dcn321_insert_entry_into_table_sorted(table, num_entries, &entry);
 332
 333         // Insert the UCLK DPMS
 334         for (i = 0; i < num_uclk_dpms; i++) {
 335                 entry.dcfclk_mhz = 0;
 336                 entry.fabricclk_mhz = 0;
 337                 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
 338
 339                 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry);
 340         }
 341
 342         // If FCLK is coarse grained, insert individual DPMs.
 343         if (num_fclk_dpms > 2) {
 344                 for (i = 0; i < num_fclk_dpms; i++) {
 345                         entry.dcfclk_mhz = 0;
 346                         entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
 347                         entry.dram_speed_mts = 0;
 348
 349                         dcn321_insert_entry_into_table_sorted(table, num_entries, &entry);
 350                 }
 351         }
 352         // If FCLK fine grained, only insert max
 353         else {
 354                 entry.dcfclk_mhz = 0;
 355                 entry.fabricclk_mhz = max_fclk_mhz;
 356                 entry.dram_speed_mts = 0;
 357
 358                 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry);
 359         }
 360
 361         // At this point, the table contains all "points of interest" based on
 362         // DPMs from PMFW, and STAs.  Table is sorted by BW, and all clock
 363         // ratios (by derate, are exact).
 364
 365         // Remove states that require higher clocks than are supported
 366         for (i = *num_entries - 1; i >= 0 ; i--) {
 367                 if (table[i].dcfclk_mhz > max_dcfclk_mhz ||
 368                                 table[i].fabricclk_mhz > max_fclk_mhz ||
 369                                 table[i].dram_speed_mts > max_uclk_mhz * 16)
 370                         remove_entry_from_table_at_index(table, num_entries, i);
 371         }
 372
 373         // At this point, the table only contains supported points of interest
 374         // it could be used as is, but some states may be redundant due to
 375         // coarse grained nature of some clocks, so we want to round up to
 376         // coarse grained DPMs and remove duplicates.
 377
 378         // Round up UCLKs
 379         for (i = *num_entries - 1; i >= 0 ; i--) {
 380                 for (j = 0; j < num_uclk_dpms; j++) {
 381                         if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
 382                                 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
 383                                 break;
 384                         }
 385                 }
 386         }
 387
 388         // If FCLK is coarse grained, round up to next DPMs
 389         if (num_fclk_dpms > 2) {
 390                 for (i = *num_entries - 1; i >= 0 ; i--) {
 391                         for (j = 0; j < num_fclk_dpms; j++) {
 392                                 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
 393                                         table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
 394                                         break;
 395                                 }
 396                         }
 397                 }
 398         }
 399         // Otherwise, round up to minimum.
 400         else {
 401                 for (i = *num_entries - 1; i >= 0 ; i--) {
 402                         if (table[i].fabricclk_mhz < min_fclk_mhz) {
 403                                 table[i].fabricclk_mhz = min_fclk_mhz;
 404                                 break;
 405                         }
 406                 }
 407         }
 408
 409         // Round DCFCLKs up to minimum
 410         for (i = *num_entries - 1; i >= 0 ; i--) {
 411                 if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
 412                         table[i].dcfclk_mhz = min_dcfclk_mhz;
 413                         break;
 414                 }
 415         }
 416
 417         // Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
 418         i = 0;
 419         while (i < *num_entries - 1) {
 420                 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
 421                                 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
 422                                 table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
 423                         remove_entry_from_table_at_index(table, num_entries, i + 1);
 424                 else
 425                         i++;
 426         }
 427
 428         // Fix up the state indicies
 429         for (i = *num_entries - 1; i >= 0 ; i--) {
 430                 table[i].state = i;
 431         }
 432
 433         return 0;
 434 }
 435
 436 static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
 437                 unsigned int *optimal_dcfclk,
 438                 unsigned int *optimal_fclk)
 439 {
 440         double bw_from_dram, bw_from_dram1, bw_from_dram2;
 441
 442         bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans *
 443                 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100);
 444         bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans *
 445                 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100);
 446
 447         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
 448
 449         if (optimal_fclk)
 450                 *optimal_fclk = bw_from_dram /
 451                 (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
 452
 453         if (optimal_dcfclk)
 454                 *optimal_dcfclk =  bw_from_dram /
 455                 (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
 456 }
 457
 458 /** dcn321_update_bw_bounding_box
 459  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
 460  * with actual values as per dGPU SKU:
 461  * -with passed few options from dc->config
 462  * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)
 463  * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
 464  * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU
 465  * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)
 466  * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different
 467  *  clocks (which might differ for certain dGPU SKU of the same ASIC)
 468  */
 469 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
 470 {
 471         dc_assert_fp_enabled();
 472         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 473                 /* Overrides from dc->config options */
 474                 dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
 475
 476                 /* Override from passed dc->bb_overrides if available*/
 477                 if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
 478                                 && dc->bb_overrides.sr_exit_time_ns) {
 479                         dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
 480                 }
 481
 482                 if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000)
 483                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
 484                                 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
 485                         dcn3_21_soc.sr_enter_plus_exit_time_us =
 486                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
 487                 }
 488
 489                 if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
 490                         && dc->bb_overrides.urgent_latency_ns) {
 491                         dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
 492                 }
 493
 494                 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000)
 495                                 != dc->bb_overrides.dram_clock_change_latency_ns
 496                                 && dc->bb_overrides.dram_clock_change_latency_ns) {
 497                         dcn3_21_soc.dram_clock_change_latency_us =
 498                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
 499                 }
 500
 501                 if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000)
 502                                 != dc->bb_overrides.dummy_clock_change_latency_ns
 503                                 && dc->bb_overrides.dummy_clock_change_latency_ns) {
 504                         dcn3_21_soc.dummy_pstate_latency_us =
 505                                 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
 506                 }
 507
 508                 /* Override from VBIOS if VBIOS bb_info available */
 509                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
 510                         struct bp_soc_bb_info bb_info = {0};
 511
 512                         if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
 513                                 if (bb_info.dram_clock_change_latency_100ns > 0)
 514                                         dcn3_21_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
 515
 516                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
 517                                 dcn3_21_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
 518
 519                         if (bb_info.dram_sr_exit_latency_100ns > 0)
 520                                 dcn3_21_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
 521                         }
 522                 }
 523
 524                 /* Override from VBIOS for num_chan */
 525                 if (dc->ctx->dc_bios->vram_info.num_chans)
 526                         dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
 527
 528                 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
 529                         dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
 530
 531         }
 532
 533         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
 534         dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 535         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 536
 537         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
 538         if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
 539                 if (dc->debug.use_legacy_soc_bb_mechanism) {
 540                         unsigned int i = 0, j = 0, num_states = 0;
 541
 542                         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
 543                         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
 544                         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
 545                         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
 546
 547                         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
 548                         unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
 549                         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
 550
 551                         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
 552                                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
 553                                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
 554                                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
 555                                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
 556                                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
 557                                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
 558                                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
 559                                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
 560                         }
 561                         if (!max_dcfclk_mhz)
 562                                 max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz;
 563                         if (!max_dispclk_mhz)
 564                                 max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz;
 565                         if (!max_dppclk_mhz)
 566                                 max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz;
 567                         if (!max_phyclk_mhz)
 568                                 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
 569
 570                         if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
 571                                 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
 572                                 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
 573                                 num_dcfclk_sta_targets++;
 574                         } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
 575                                 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
 576                                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
 577                                         if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
 578                                                 dcfclk_sta_targets[i] = max_dcfclk_mhz;
 579                                                 break;
 580                                         }
 581                                 }
 582                                 // Update size of array since we "removed" duplicates
 583                                 num_dcfclk_sta_targets = i + 1;
 584                         }
 585
 586                         num_uclk_states = bw_params->clk_table.num_entries;
 587
 588                         // Calculate optimal dcfclk for each uclk
 589                         for (i = 0; i < num_uclk_states; i++) {
 590                                 dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
 591                                                 &optimal_dcfclk_for_uclk[i], NULL);
 592                                 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
 593                                         optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
 594                                 }
 595                         }
 596
 597                         // Calculate optimal uclk for each dcfclk sta target
 598                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
 599                                 for (j = 0; j < num_uclk_states; j++) {
 600                                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
 601                                                 optimal_uclk_for_dcfclk_sta_targets[i] =
 602                                                                 bw_params->clk_table.entries[j].memclk_mhz * 16;
 603                                                 break;
 604                                         }
 605                                 }
 606                         }
 607
 608                         i = 0;
 609                         j = 0;
 610                         // create the final dcfclk and uclk table
 611                         while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
 612                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
 613                                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
 614                                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
 615                                 } else {
 616                                         if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
 617                                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
 618                                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
 619                                         } else {
 620                                                 j = num_uclk_states;
 621                                         }
 622                                 }
 623                         }
 624
 625                         while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
 626                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
 627                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
 628                         }
 629
 630                         while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
 631                                         optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
 632                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
 633                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
 634                         }
 635
 636                         dcn3_21_soc.num_states = num_states;
 637                         for (i = 0; i < dcn3_21_soc.num_states; i++) {
 638                                 dcn3_21_soc.clock_limits[i].state = i;
 639                                 dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
 640                                 dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
 641
 642                                 /* Fill all states with max values of all these clocks */
 643                                 dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
 644                                 dcn3_21_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
 645                                 dcn3_21_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
 646                                 dcn3_21_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
 647
 648                                 /* Populate from bw_params for DTBCLK, SOCCLK */
 649                                 if (i > 0) {
 650                                         if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
 651                                                 dcn3_21_soc.clock_limits[i].dtbclk_mhz  = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
 652                                         } else {
 653                                                 dcn3_21_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
 654                                         }
 655                                 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
 656                                         dcn3_21_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
 657                                 }
 658
 659                                 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
 660                                         dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz;
 661                                 else
 662                                         dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
 663
 664                                 if (!dram_speed_mts[i] && i > 0)
 665                                         dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts;
 666                                 else
 667                                         dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
 668
 669                                 /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
 670                                 /* PHYCLK_D18, PHYCLK_D32 */
 671                                 dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
 672                                 dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
 673                         }
 674                 } else {
 675                         build_synthetic_soc_states(bw_params, dcn3_21_soc.clock_limits, &dcn3_21_soc.num_states);
 676                 }
 677
 678                 /* Re-init DML with updated bb */
 679                 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
 680                 if (dc->current_state)
 681                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
 682         }
 683 }
 684