drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include "dcn32_fpu.h"
  27 #include "dcn32/dcn32_resource.h"
  28 #include "dcn20/dcn20_resource.h"
  29 #include "display_mode_vba_util_32.h"
  30 #include "dml/dcn32/display_mode_vba_32.h"
  31 // We need this includes for WATERMARKS_* defines
  32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
  33 #include "dcn30/dcn30_resource.h"
  34 #include "link.h"
  35
  36 #define DC_LOGGER_INIT(logger)
  37
  38 static const struct subvp_high_refresh_list subvp_high_refresh_list = {
  39                         .min_refresh = 120,
  40                         .max_refresh = 165,
  41                         .res = {
  42                                 {.width = 3840, .height = 2160, },
  43                                 {.width = 3440, .height = 1440, },
  44                                 {.width = 2560, .height = 1440, }},
  45 };
  46
  47 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
  48         .gpuvm_enable = 0,
  49         .gpuvm_max_page_table_levels = 4,
  50         .hostvm_enable = 0,
  51         .rob_buffer_size_kbytes = 128,
  52         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
  53         .config_return_buffer_size_in_kbytes = 1280,
  54         .compressed_buffer_segment_size_in_kbytes = 64,
  55         .meta_fifo_size_in_kentries = 22,
  56         .zero_size_buffer_entries = 512,
  57         .compbuf_reserved_space_64b = 256,
  58         .compbuf_reserved_space_zs = 64,
  59         .dpp_output_buffer_pixels = 2560,
  60         .opp_output_buffer_lines = 1,
  61         .pixel_chunk_size_kbytes = 8,
  62         .alpha_pixel_chunk_size_kbytes = 4,
  63         .min_pixel_chunk_size_bytes = 1024,
  64         .dcc_meta_buffer_size_bytes = 6272,
  65         .meta_chunk_size_kbytes = 2,
  66         .min_meta_chunk_size_bytes = 256,
  67         .writeback_chunk_size_kbytes = 8,
  68         .ptoi_supported = false,
  69         .num_dsc = 4,
  70         .maximum_dsc_bits_per_component = 12,
  71         .maximum_pixels_per_line_per_dsc_unit = 6016,
  72         .dsc422_native_support = true,
  73         .is_line_buffer_bpp_fixed = true,
  74         .line_buffer_fixed_bpp = 57,
  75         .line_buffer_size_bits = 1171920,
  76         .max_line_buffer_lines = 32,
  77         .writeback_interface_buffer_size_kbytes = 90,
  78         .max_num_dpp = 4,
  79         .max_num_otg = 4,
  80         .max_num_hdmi_frl_outputs = 1,
  81         .max_num_wb = 1,
  82         .max_dchub_pscl_bw_pix_per_clk = 4,
  83         .max_pscl_lb_bw_pix_per_clk = 2,
  84         .max_lb_vscl_bw_pix_per_clk = 4,
  85         .max_vscl_hscl_bw_pix_per_clk = 4,
  86         .max_hscl_ratio = 6,
  87         .max_vscl_ratio = 6,
  88         .max_hscl_taps = 8,
  89         .max_vscl_taps = 8,
  90         .dpte_buffer_size_in_pte_reqs_luma = 64,
  91         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  92         .dispclk_ramp_margin_percent = 1,
  93         .max_inter_dcn_tile_repeaters = 8,
  94         .cursor_buffer_size = 16,
  95         .cursor_chunk_size = 2,
  96         .writeback_line_buffer_buffer_size = 0,
  97         .writeback_min_hscl_ratio = 1,
  98         .writeback_min_vscl_ratio = 1,
  99         .writeback_max_hscl_ratio = 1,
 100         .writeback_max_vscl_ratio = 1,
 101         .writeback_max_hscl_taps = 1,
 102         .writeback_max_vscl_taps = 1,
 103         .dppclk_delay_subtotal = 47,
 104         .dppclk_delay_scl = 50,
 105         .dppclk_delay_scl_lb_only = 16,
 106         .dppclk_delay_cnvc_formatter = 28,
 107         .dppclk_delay_cnvc_cursor = 6,
 108         .dispclk_delay_subtotal = 125,
 109         .dynamic_metadata_vm_enabled = false,
 110         .odm_combine_4to1_supported = false,
 111         .dcc_supported = true,
 112         .max_num_dp2p0_outputs = 2,
 113         .max_num_dp2p0_streams = 4,
 114 };
 115
 116 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
 117         .clock_limits = {
 118                 {
 119                         .state = 0,
 120                         .dcfclk_mhz = 1564.0,
 121                         .fabricclk_mhz = 2500.0,
 122                         .dispclk_mhz = 2150.0,
 123                         .dppclk_mhz = 2150.0,
 124                         .phyclk_mhz = 810.0,
 125                         .phyclk_d18_mhz = 667.0,
 126                         .phyclk_d32_mhz = 625.0,
 127                         .socclk_mhz = 1200.0,
 128                         .dscclk_mhz = 716.667,
 129                         .dram_speed_mts = 18000.0,
 130                         .dtbclk_mhz = 1564.0,
 131                 },
 132         },
 133         .num_states = 1,
 134         .sr_exit_time_us = 42.97,
 135         .sr_enter_plus_exit_time_us = 49.94,
 136         .sr_exit_z8_time_us = 285.0,
 137         .sr_enter_plus_exit_z8_time_us = 320,
 138         .writeback_latency_us = 12.0,
 139         .round_trip_ping_latency_dcfclk_cycles = 263,
 140         .urgent_latency_pixel_data_only_us = 4.0,
 141         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 142         .urgent_latency_vm_data_only_us = 4.0,
 143         .fclk_change_latency_us = 25,
 144         .usr_retraining_latency_us = 2,
 145         .smn_latency_us = 2,
 146         .mall_allocated_for_dcn_mbytes = 64,
 147         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 148         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 149         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 150         .pct_ideal_sdp_bw_after_urgent = 90.0,
 151         .pct_ideal_fabric_bw_after_urgent = 67.0,
 152         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 153         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 154         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 155         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 156         .max_avg_sdp_bw_use_normal_percent = 80.0,
 157         .max_avg_fabric_bw_use_normal_percent = 60.0,
 158         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 159         .max_avg_dram_bw_use_normal_percent = 15.0,
 160         .num_chans = 24,
 161         .dram_channel_width_bytes = 2,
 162         .fabric_datapath_to_dcn_data_return_bytes = 64,
 163         .return_bus_width_bytes = 64,
 164         .downspread_percent = 0.38,
 165         .dcn_downspread_percent = 0.5,
 166         .dram_clock_change_latency_us = 400,
 167         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 168         .do_urgent_latency_adjustment = true,
 169         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 170         .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
 171 };
 172
 173 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
 174 {
 175         /* defaults */
 176         double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
 177         double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
 178         double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
 179         double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
 180         /* For min clocks use as reported by PM FW and report those as min */
 181         uint16_t min_uclk_mhz                   = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
 182         uint16_t min_dcfclk_mhz                 = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 183         uint16_t setb_min_uclk_mhz              = min_uclk_mhz;
 184         uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
 185
 186         dc_assert_fp_enabled();
 187
 188         /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
 189         if (dcfclk_mhz_for_the_second_state)
 190                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
 191         else
 192                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 193
 194         if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
 195                 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
 196
 197         /* Set A - Normal - default values */
 198         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
 199         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
 200         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 201         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
 202         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 203         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 204         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 205         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
 206         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
 207         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
 208
 209         /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
 210         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
 211         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
 212         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 213         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
 214         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 215         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 216         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
 217         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
 218         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
 219
 220         /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 221         /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
 222         if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
 223                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
 224                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;
 225                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 226                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 227                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 228                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
 229                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 230                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 231                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 232                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
 233                 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
 234                 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;
 235                 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
 236                 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
 237                 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
 238                 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
 239                 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
 240                 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 241         }
 242         /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
 243         /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
 244         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
 245         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
 246         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 247         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
 248         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
 249         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
 250         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 251         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
 252         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
 253         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 254 }
 255
 256 /*
 257  * Finds dummy_latency_index when MCLK switching using firmware based
 258  * vblank stretch is enabled. This function will iterate through the
 259  * table of dummy pstate latencies until the lowest value that allows
 260  * dm_allow_self_refresh_and_mclk_switch to happen is found
 261  */
 262 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
 263                                                             struct dc_state *context,
 264                                                             display_e2e_pipe_params_st *pipes,
 265                                                             int pipe_cnt,
 266                                                             int vlevel)
 267 {
 268         const int max_latency_table_entries = 4;
 269         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 270         int dummy_latency_index = 0;
 271         enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 272
 273         dc_assert_fp_enabled();
 274
 275         while (dummy_latency_index < max_latency_table_entries) {
 276                 if (temp_clock_change_support != dm_dram_clock_change_unsupported)
 277                         vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
 278                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
 279                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
 280                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
 281
 282                 /* for subvp + DRR case, if subvp pipes are still present we support pstate */
 283                 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported &&
 284                                 dcn32_subvp_in_use(dc, context))
 285                         vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
 286
 287                 if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
 288                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
 289                         break;
 290
 291                 dummy_latency_index++;
 292         }
 293
 294         if (dummy_latency_index == max_latency_table_entries) {
 295                 ASSERT(dummy_latency_index != max_latency_table_entries);
 296                 /* If the execution gets here, it means dummy p_states are
 297                  * not possible. This should never happen and would mean
 298                  * something is severely wrong.
 299                  * Here we reset dummy_latency_index to 3, because it is
 300                  * better to have underflows than system crashes.
 301                  */
 302                 dummy_latency_index = max_latency_table_entries - 1;
 303         }
 304
 305         return dummy_latency_index;
 306 }
 307
 308 /**
 309  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
 310  * and populate pipe_ctx with those params.
 311  * @dc: [in] current dc state
 312  * @context: [in] new dc state
 313  * @pipes: [in] DML pipe params array
 314  * @pipe_cnt: [in] DML pipe count
 315  *
 316  * This function must be called AFTER the phantom pipes are added to context
 317  * and run through DML (so that the DLG params for the phantom pipes can be
 318  * populated), and BEFORE we program the timing for the phantom pipes.
 319  */
 320 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
 321                                               struct dc_state *context,
 322                                               display_e2e_pipe_params_st *pipes,
 323                                               int pipe_cnt)
 324 {
 325         uint32_t i, pipe_idx;
 326
 327         dc_assert_fp_enabled();
 328
 329         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 330                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 331
 332                 if (!pipe->stream)
 333                         continue;
 334
 335                 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 336                         pipes[pipe_idx].pipe.dest.vstartup_start =
 337                                 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 338                         pipes[pipe_idx].pipe.dest.vupdate_offset =
 339                                 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 340                         pipes[pipe_idx].pipe.dest.vupdate_width =
 341                                 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 342                         pipes[pipe_idx].pipe.dest.vready_offset =
 343                                 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 344                         pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
 345                 }
 346                 pipe_idx++;
 347         }
 348 }
 349
 350 /**
 351  * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe
 352  * @context: [in] New DC state to be programmed
 353  * @pipe_e2e: [in] DML pipe end to end context
 354  *
 355  * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both
 356  * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is
 357  * determined by DPPClk requirements
 358  *
 359  * This function follows the same policy as DML:
 360  * - Check for ODM combine requirements / policy first
 361  * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and
 362  *   MPC is required
 363  *
 364  * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits).
 365  */
 366 uint8_t dcn32_predict_pipe_split(struct dc_state *context,
 367                                   display_e2e_pipe_params_st *pipe_e2e)
 368 {
 369         double pscl_throughput;
 370         double pscl_throughput_chroma;
 371         double dpp_clk_single_dpp, clock;
 372         double clk_frequency = 0.0;
 373         double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;
 374         bool total_available_pipes_support = false;
 375         uint32_t number_of_dpp = 0;
 376         enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled;
 377         double req_dispclk_per_surface = 0;
 378         uint8_t num_splits = 0;
 379
 380         dc_assert_fp_enabled();
 381
 382         dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit,
 383                         pipe_e2e->pipe.dest.hactive,
 384                         pipe_e2e->dout.output_format,
 385                         pipe_e2e->dout.output_type,
 386                         pipe_e2e->pipe.dest.odm_combine_policy,
 387                         context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,
 388                         context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,
 389                         pipe_e2e->dout.dsc_enable != 0,
 390                         0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */
 391                         context->bw_ctx.dml.ip.max_num_dpp,
 392                         pipe_e2e->pipe.dest.pixel_rate_mhz,
 393                         context->bw_ctx.dml.soc.dcn_downspread_percent,
 394                         context->bw_ctx.dml.ip.dispclk_ramp_margin_percent,
 395                         context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz,
 396                         pipe_e2e->dout.dsc_slices,
 397                         /* Output */
 398                         &total_available_pipes_support,
 399                         &number_of_dpp,
 400                         &odm_mode,
 401                         &req_dispclk_per_surface);
 402
 403         dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio,
 404                         pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c,
 405                         pipe_e2e->pipe.scale_ratio_depth.vscl_ratio,
 406                         pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c,
 407                         context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,
 408                         context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,
 409                         pipe_e2e->pipe.dest.pixel_rate_mhz,
 410                         pipe_e2e->pipe.src.source_format,
 411                         pipe_e2e->pipe.scale_taps.htaps,
 412                         pipe_e2e->pipe.scale_taps.htaps_c,
 413                         pipe_e2e->pipe.scale_taps.vtaps,
 414                         pipe_e2e->pipe.scale_taps.vtaps_c,
 415                         /* Output */
 416                         &pscl_throughput, &pscl_throughput_chroma,
 417                         &dpp_clk_single_dpp);
 418
 419         clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100);
 420
 421         if (clock > 0)
 422                 clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock);
 423
 424         if (odm_mode == dm_odm_combine_mode_2to1)
 425                 num_splits = 1;
 426         else if (odm_mode == dm_odm_combine_mode_4to1)
 427                 num_splits = 3;
 428         else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz)
 429                 num_splits = 1;
 430
 431         return num_splits;
 432 }
 433
 434 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
 435 {
 436         float memory_bw_kbytes_sec;
 437         float fabric_bw_kbytes_sec;
 438         float sdp_bw_kbytes_sec;
 439         float limiting_bw_kbytes_sec;
 440
 441         memory_bw_kbytes_sec = entry->dram_speed_mts *
 442                                 dcn3_2_soc.num_chans *
 443                                 dcn3_2_soc.dram_channel_width_bytes *
 444                                 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 445
 446         fabric_bw_kbytes_sec = entry->fabricclk_mhz *
 447                                 dcn3_2_soc.return_bus_width_bytes *
 448                                 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 449
 450         sdp_bw_kbytes_sec = entry->dcfclk_mhz *
 451                                 dcn3_2_soc.return_bus_width_bytes *
 452                                 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 453
 454         limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
 455
 456         if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
 457                 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
 458
 459         if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
 460                 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
 461
 462         return limiting_bw_kbytes_sec;
 463 }
 464
 465 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
 466 {
 467         if (entry->dcfclk_mhz > 0) {
 468                 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 469
 470                 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 471                 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
 472                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 473         } else if (entry->fabricclk_mhz > 0) {
 474                 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 475
 476                 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 477                 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
 478                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 479         } else if (entry->dram_speed_mts > 0) {
 480                 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
 481                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 482
 483                 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 484                 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 485         }
 486 }
 487
 488 void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
 489                                     unsigned int *num_entries,
 490                                     struct _vcs_dpi_voltage_scaling_st *entry)
 491 {
 492         int i = 0;
 493         int index = 0;
 494         float net_bw_of_new_state = 0;
 495
 496         dc_assert_fp_enabled();
 497
 498         get_optimal_ntuple(entry);
 499
 500         if (*num_entries == 0) {
 501                 table[0] = *entry;
 502                 (*num_entries)++;
 503         } else {
 504                 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry);
 505                 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) {
 506                         index++;
 507                         if (index >= *num_entries)
 508                                 break;
 509                 }
 510
 511                 for (i = *num_entries; i > index; i--)
 512                         table[i] = table[i - 1];
 513
 514                 table[index] = *entry;
 515                 (*num_entries)++;
 516         }
 517 }
 518
 519 /**
 520  * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream
 521  * @dc: current dc state
 522  * @context: new dc state
 523  * @ref_pipe: Main pipe for the phantom stream
 524  * @phantom_stream: target phantom stream state
 525  * @pipes: DML pipe params
 526  * @pipe_cnt: number of DML pipes
 527  * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
 528  *
 529  * Set timing params of the phantom stream based on calculated output from DML.
 530  * This function first gets the DML pipe index using the DC pipe index, then
 531  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
 532  * lines required for SubVP MCLK switching and assigns to the phantom stream
 533  * accordingly.
 534  *
 535  * - The number of SubVP lines calculated in DML does not take into account
 536  * FW processing delays and required pstate allow width, so we must include
 537  * that separately.
 538  *
 539  * - Set phantom backporch = vstartup of main pipe
 540  */
 541 void dcn32_set_phantom_stream_timing(struct dc *dc,
 542                                      struct dc_state *context,
 543                                      struct pipe_ctx *ref_pipe,
 544                                      struct dc_stream_state *phantom_stream,
 545                                      display_e2e_pipe_params_st *pipes,
 546                                      unsigned int pipe_cnt,
 547                                      unsigned int dc_pipe_idx)
 548 {
 549         unsigned int i, pipe_idx;
 550         struct pipe_ctx *pipe;
 551         uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
 552         unsigned int num_dpp;
 553         unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
 554         unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 555         unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
 556         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 557         struct dc_stream_state *main_stream = ref_pipe->stream;
 558
 559         dc_assert_fp_enabled();
 560
 561         // Find DML pipe index (pipe_idx) using dc_pipe_idx
 562         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 563                 pipe = &context->res_ctx.pipe_ctx[i];
 564
 565                 if (!pipe->stream)
 566                         continue;
 567
 568                 if (i == dc_pipe_idx)
 569                         break;
 570
 571                 pipe_idx++;
 572         }
 573
 574         // Calculate lines required for pstate allow width and FW processing delays
 575         pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
 576                         dc->caps.subvp_pstate_allow_width_us) / 1000000) *
 577                         (ref_pipe->stream->timing.pix_clk_100hz * 100) /
 578                         (double)ref_pipe->stream->timing.h_total;
 579
 580         // Update clks_cfg for calling into recalculate
 581         pipes[0].clks_cfg.voltage = vlevel;
 582         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 583         pipes[0].clks_cfg.socclk_mhz = socclk;
 584
 585         // DML calculation for MALL region doesn't take into account FW delay
 586         // and required pstate allow width for multi-display cases
 587         /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned
 588          * to 2 swaths (i.e. 16 lines)
 589          */
 590         phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
 591                                 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines;
 592
 593         // W/A for DCC corruption with certain high resolution timings.
 594         // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive.
 595         num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]];
 596         phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0;
 597
 598         /* dc->debug.subvp_extra_lines 0 by default*/
 599         phantom_vactive += dc->debug.subvp_extra_lines;
 600
 601         // For backporch of phantom pipe, use vstartup of the main pipe
 602         phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 603
 604         phantom_stream->dst.y = 0;
 605         phantom_stream->dst.height = phantom_vactive;
 606         /* When scaling, DML provides the end to end required number of lines for MALL.
 607          * dst.height is always correct for this case, but src.height is not which causes a
 608          * delta between main and phantom pipe scaling outputs. Need to adjust src.height on
 609          * phantom for this case.
 610          */
 611         phantom_stream->src.y = 0;
 612         phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height;
 613
 614         phantom_stream->timing.v_addressable = phantom_vactive;
 615         phantom_stream->timing.v_front_porch = 1;
 616         phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
 617                                                 phantom_stream->timing.v_front_porch +
 618                                                 phantom_stream->timing.v_sync_width +
 619                                                 phantom_bp;
 620         phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
 621 }
 622
 623 /**
 624  * dcn32_get_num_free_pipes - Calculate number of free pipes
 625  * @dc: current dc state
 626  * @context: new dc state
 627  *
 628  * This function assumes that a "used" pipe is a pipe that has
 629  * both a stream and a plane assigned to it.
 630  *
 631  * Return: Number of free pipes available in the context
 632  */
 633 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
 634 {
 635         unsigned int i;
 636         unsigned int free_pipes = 0;
 637         unsigned int num_pipes = 0;
 638
 639         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 640                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 641
 642                 if (pipe->stream && !pipe->top_pipe) {
 643                         while (pipe) {
 644                                 num_pipes++;
 645                                 pipe = pipe->bottom_pipe;
 646                         }
 647                 }
 648         }
 649
 650         free_pipes = dc->res_pool->pipe_count - num_pipes;
 651         return free_pipes;
 652 }
 653
 654 /**
 655  * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP.
 656  * @dc: current dc state
 657  * @context: new dc state
 658  * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
 659  *
 660  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
 661  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
 662  * we are forcing SubVP P-State switching on the current config.
 663  *
 664  * The number of pipes used for the chosen surface must be less than or equal to the
 665  * number of free pipes available.
 666  *
 667  * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK).
 668  * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own
 669  * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't
 670  * support MCLK switching naturally [i.e. ACTIVE or VBLANK]).
 671  *
 672  * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
 673  */
 674 static bool dcn32_assign_subvp_pipe(struct dc *dc,
 675                                     struct dc_state *context,
 676                                     unsigned int *index)
 677 {
 678         unsigned int i, pipe_idx;
 679         unsigned int max_frame_time = 0;
 680         bool valid_assignment_found = false;
 681         unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
 682         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 683
 684         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 685                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 686                 unsigned int num_pipes = 0;
 687                 unsigned int refresh_rate = 0;
 688
 689                 if (!pipe->stream)
 690                         continue;
 691
 692                 // Round up
 693                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
 694                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
 695                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
 696                 /* SubVP pipe candidate requirements:
 697                  * - Refresh rate < 120hz
 698                  * - Not able to switch in vactive naturally (switching in active means the
 699                  *   DET provides enough buffer to hide the P-State switch latency -- trying
 700                  *   to combine this with SubVP can cause issues with the scheduling).
 701                  * - Not TMZ surface
 702                  */
 703                 if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&
 704                                 !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &&
 705                                 (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&
 706                                 pipe->stream->mall_stream_config.type == SUBVP_NONE &&
 707                                 (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &&
 708                                 !pipe->plane_state->address.tmz_surface &&
 709                                 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||
 710                                 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
 711                                                 dcn32_allow_subvp_with_active_margin(pipe)))) {
 712                         while (pipe) {
 713                                 num_pipes++;
 714                                 pipe = pipe->bottom_pipe;
 715                         }
 716
 717                         pipe = &context->res_ctx.pipe_ctx[i];
 718                         if (num_pipes <= free_pipes) {
 719                                 struct dc_stream_state *stream = pipe->stream;
 720                                 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
 721                                                 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
 722                                 if (frame_us > max_frame_time) {
 723                                         *index = i;
 724                                         max_frame_time = frame_us;
 725                                         valid_assignment_found = true;
 726                                 }
 727                         }
 728                 }
 729                 pipe_idx++;
 730         }
 731         return valid_assignment_found;
 732 }
 733
 734 /**
 735  * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP.
 736  * @dc: current dc state
 737  * @context: new dc state
 738  *
 739  * This function returns true if there are enough free pipes
 740  * to create the required phantom pipes for any given stream
 741  * (that does not already have phantom pipe assigned).
 742  *
 743  * e.g. For a 2 stream config where the first stream uses one
 744  * pipe and the second stream uses 2 pipes (i.e. pipe split),
 745  * this function will return true because there is 1 remaining
 746  * pipe which can be used as the phantom pipe for the non pipe
 747  * split pipe.
 748  *
 749  * Return:
 750  * True if there are enough free pipes to assign phantom pipes to at least one
 751  * stream that does not already have phantom pipes assigned. Otherwise false.
 752  */
 753 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
 754 {
 755         unsigned int i, split_cnt, free_pipes;
 756         unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
 757         bool subvp_possible = false;
 758
 759         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 760                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 761
 762                 // Find the minimum pipe split count for non SubVP pipes
 763                 if (pipe->stream && !pipe->top_pipe &&
 764                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 765                         split_cnt = 0;
 766                         while (pipe) {
 767                                 split_cnt++;
 768                                 pipe = pipe->bottom_pipe;
 769                         }
 770
 771                         if (split_cnt < min_pipe_split)
 772                                 min_pipe_split = split_cnt;
 773                 }
 774         }
 775
 776         free_pipes = dcn32_get_num_free_pipes(dc, context);
 777
 778         // SubVP only possible if at least one pipe is being used (i.e. free_pipes
 779         // should not equal to the pipe_count)
 780         if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
 781                 subvp_possible = true;
 782
 783         return subvp_possible;
 784 }
 785
 786 /**
 787  * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable
 788  * @dc: current dc state
 789  * @context: new dc state
 790  *
 791  * High level algorithm:
 792  * 1. Find longest microschedule length (in us) between the two SubVP pipes
 793  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
 794  * pipes still allows for the maximum microschedule to fit in the active
 795  * region for both pipes.
 796  *
 797  * Return: True if the SubVP + SubVP config is schedulable, false otherwise
 798  */
 799 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
 800 {
 801         struct pipe_ctx *subvp_pipes[2];
 802         struct dc_stream_state *phantom = NULL;
 803         uint32_t microschedule_lines = 0;
 804         uint32_t index = 0;
 805         uint32_t i;
 806         uint32_t max_microschedule_us = 0;
 807         int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
 808
 809         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 810                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 811                 uint32_t time_us = 0;
 812
 813                 /* Loop to calculate the maximum microschedule time between the two SubVP pipes,
 814                  * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
 815                  */
 816                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
 817                     pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 818                         phantom = pipe->stream->mall_stream_config.paired_stream;
 819                         microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
 820                                         phantom->timing.v_addressable;
 821
 822                         // Round up when calculating microschedule time (+ 1 at the end)
 823                         time_us = (microschedule_lines * phantom->timing.h_total) /
 824                                         (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
 825                                                 dc->caps.subvp_prefetch_end_to_mall_start_us +
 826                                                 dc->caps.subvp_fw_processing_delay_us + 1;
 827                         if (time_us > max_microschedule_us)
 828                                 max_microschedule_us = time_us;
 829
 830                         subvp_pipes[index] = pipe;
 831                         index++;
 832
 833                         // Maximum 2 SubVP pipes
 834                         if (index == 2)
 835                                 break;
 836                 }
 837         }
 838         vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
 839                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 840         vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
 841                                 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 842         vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
 843                         subvp_pipes[0]->stream->timing.h_total) /
 844                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 845         vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
 846                         subvp_pipes[1]->stream->timing.h_total) /
 847                         (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 848
 849         if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
 850             (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
 851                 return true;
 852
 853         return false;
 854 }
 855
 856 /**
 857  * subvp_drr_schedulable() - Determine if SubVP + DRR config is schedulable
 858  * @dc: current dc state
 859  * @context: new dc state
 860  *
 861  * High level algorithm:
 862  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 863  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
 864  * (the margin is equal to the MALL region + DRR margin (500us))
 865  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
 866  * then report the configuration as supported
 867  *
 868  * Return: True if the SubVP + DRR config is schedulable, false otherwise
 869  */
 870 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
 871 {
 872         bool schedulable = false;
 873         uint32_t i;
 874         struct pipe_ctx *pipe = NULL;
 875         struct pipe_ctx *drr_pipe = NULL;
 876         struct dc_crtc_timing *main_timing = NULL;
 877         struct dc_crtc_timing *phantom_timing = NULL;
 878         struct dc_crtc_timing *drr_timing = NULL;
 879         int16_t prefetch_us = 0;
 880         int16_t mall_region_us = 0;
 881         int16_t drr_frame_us = 0;       // nominal frame time
 882         int16_t subvp_active_us = 0;
 883         int16_t stretched_drr_us = 0;
 884         int16_t drr_stretched_vblank_us = 0;
 885         int16_t max_vblank_mallregion = 0;
 886
 887         // Find SubVP pipe
 888         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 889                 pipe = &context->res_ctx.pipe_ctx[i];
 890
 891                 // We check for master pipe, but it shouldn't matter since we only need
 892                 // the pipe for timing info (stream should be same for any pipe splits)
 893                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
 894                         continue;
 895
 896                 // Find the SubVP pipe
 897                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 898                         break;
 899         }
 900
 901         // Find the DRR pipe
 902         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 903                 drr_pipe = &context->res_ctx.pipe_ctx[i];
 904
 905                 // We check for master pipe only
 906                 if (!drr_pipe->stream || !drr_pipe->plane_state || drr_pipe->top_pipe || drr_pipe->prev_odm_pipe)
 907                         continue;
 908
 909                 if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
 910                                 (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable))
 911                         break;
 912         }
 913
 914         main_timing = &pipe->stream->timing;
 915         phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
 916         drr_timing = &drr_pipe->stream->timing;
 917         prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 918                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 919                         dc->caps.subvp_prefetch_end_to_mall_start_us;
 920         subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 921                         (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 922         drr_frame_us = drr_timing->v_total * drr_timing->h_total /
 923                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000;
 924         // P-State allow width and FW delays already included phantom_timing->v_addressable
 925         mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 926                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 927         stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 928         drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
 929                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
 930         max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
 931
 932         /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
 933          * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
 934          * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 935          * and the max of (VBLANK blanking time, MALL region)).
 936          */
 937         if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
 938                         subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
 939                 schedulable = true;
 940
 941         return schedulable;
 942 }
 943
 944
 945 /**
 946  * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable
 947  * @dc: current dc state
 948  * @context: new dc state
 949  *
 950  * High level algorithm:
 951  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
 952  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
 953  * then report the configuration as supported
 954  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
 955  *
 956  * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
 957  */
 958 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
 959 {
 960         struct pipe_ctx *pipe = NULL;
 961         struct pipe_ctx *subvp_pipe = NULL;
 962         bool found = false;
 963         bool schedulable = false;
 964         uint32_t i = 0;
 965         uint8_t vblank_index = 0;
 966         uint16_t prefetch_us = 0;
 967         uint16_t mall_region_us = 0;
 968         uint16_t vblank_frame_us = 0;
 969         uint16_t subvp_active_us = 0;
 970         uint16_t vblank_blank_us = 0;
 971         uint16_t max_vblank_mallregion = 0;
 972         struct dc_crtc_timing *main_timing = NULL;
 973         struct dc_crtc_timing *phantom_timing = NULL;
 974         struct dc_crtc_timing *vblank_timing = NULL;
 975
 976         /* For SubVP + VBLANK/DRR cases, we assume there can only be
 977          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
 978          * is supported, it is either a single VBLANK case or two VBLANK
 979          * displays which are synchronized (in which case they have identical
 980          * timings).
 981          */
 982         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 983                 pipe = &context->res_ctx.pipe_ctx[i];
 984
 985                 // We check for master pipe, but it shouldn't matter since we only need
 986                 // the pipe for timing info (stream should be same for any pipe splits)
 987                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
 988                         continue;
 989
 990                 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 991                         // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
 992                         vblank_index = i;
 993                         found = true;
 994                 }
 995
 996                 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 997                         subvp_pipe = pipe;
 998         }
 999         if (found) {
1000                 main_timing = &subvp_pipe->stream->timing;
1001                 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
1002                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
1003                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
1004                 // Also include the prefetch end to mallstart delay time
1005                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
1006                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
1007                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
1008                 // P-State allow width and FW delays already included phantom_timing->v_addressable
1009                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
1010                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
1011                 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
1012                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
1013                 vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
1014                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
1015                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
1016                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
1017                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
1018
1019                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
1020                 // and the max of (VBLANK blanking time, MALL region)
1021                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
1022                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
1023                         schedulable = true;
1024         }
1025         return schedulable;
1026 }
1027
1028 /**
1029  * subvp_subvp_admissable() - Determine if subvp + subvp config is admissible
1030  *
1031  * @dc: Current DC state
1032  * @context: New DC state to be programmed
1033  *
1034  * SubVP + SubVP is admissible under the following conditions:
1035  * - All SubVP pipes are < 120Hz OR
1036  * - All SubVP pipes are >= 120hz
1037  *
1038  * Return: True if admissible, false otherwise
1039  */
1040 static bool subvp_subvp_admissable(struct dc *dc,
1041                                 struct dc_state *context)
1042 {
1043         bool result = false;
1044         uint32_t i;
1045         uint8_t subvp_count = 0;
1046         uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
1047         uint32_t refresh_rate = 0;
1048
1049         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1050                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1051
1052                 if (!pipe->stream)
1053                         continue;
1054
1055                 if (pipe->plane_state && !pipe->top_pipe &&
1056                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
1057                         refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
1058                                         pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
1059                                         / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
1060                         if (refresh_rate < min_refresh)
1061                                 min_refresh = refresh_rate;
1062                         if (refresh_rate > max_refresh)
1063                                 max_refresh = refresh_rate;
1064                         subvp_count++;
1065                 }
1066         }
1067
1068         if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
1069                         (min_refresh >= 120 && max_refresh >= 120)))
1070                 result = true;
1071
1072         return result;
1073 }
1074
1075 /**
1076  * subvp_validate_static_schedulability - Check which SubVP case is calculated
1077  * and handle static analysis based on the case.
1078  * @dc: current dc state
1079  * @context: new dc state
1080  * @vlevel: Voltage level calculated by DML
1081  *
1082  * Three cases:
1083  * 1. SubVP + SubVP
1084  * 2. SubVP + VBLANK (DRR checked internally)
1085  * 3. SubVP + VACTIVE (currently unsupported)
1086  *
1087  * Return: True if statically schedulable, false otherwise
1088  */
1089 static bool subvp_validate_static_schedulability(struct dc *dc,
1090                                 struct dc_state *context,
1091                                 int vlevel)
1092 {
1093         bool schedulable = false;
1094         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1095         uint32_t i, pipe_idx;
1096         uint8_t subvp_count = 0;
1097         uint8_t vactive_count = 0;
1098         uint8_t non_subvp_pipes = 0;
1099
1100         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1101                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1102
1103                 if (!pipe->stream)
1104                         continue;
1105
1106                 if (pipe->plane_state && !pipe->top_pipe) {
1107                         if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
1108                                 subvp_count++;
1109                         if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1110                                 non_subvp_pipes++;
1111                         }
1112                 }
1113
1114                 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE
1115                 // switching (SubVP + VACTIVE unsupported). In situations where we force
1116                 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
1117                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
1118                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1119                         vactive_count++;
1120                 }
1121                 pipe_idx++;
1122         }
1123
1124         if (subvp_count == 2) {
1125                 // Static schedulability check for SubVP + SubVP case
1126                 schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);
1127         } else if (subvp_count == 1 && non_subvp_pipes == 0) {
1128                 // Single SubVP configs will be supported by default as long as it's suppported by DML
1129                 schedulable = true;
1130         } else if (subvp_count == 1 && non_subvp_pipes == 1) {
1131                 if (dcn32_subvp_drr_admissable(dc, context))
1132                         schedulable = subvp_drr_schedulable(dc, context);
1133                 else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))
1134                         schedulable = subvp_vblank_schedulable(dc, context);
1135         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
1136                         vactive_count > 0) {
1137                 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default.
1138                 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count.
1139                 // SubVP + VACTIVE currently unsupported
1140                 schedulable = false;
1141         }
1142         return schedulable;
1143 }
1144
1145 static void dcn32_full_validate_bw_helper(struct dc *dc,
1146                                    struct dc_state *context,
1147                                    display_e2e_pipe_params_st *pipes,
1148                                    int *vlevel,
1149                                    int *split,
1150                                    bool *merge,
1151                                    int *pipe_cnt)
1152 {
1153         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1154         unsigned int dc_pipe_idx = 0;
1155         int i = 0;
1156         bool found_supported_config = false;
1157
1158         dc_assert_fp_enabled();
1159
1160         /*
1161          * DML favors voltage over p-state, but we're more interested in
1162          * supporting p-state over voltage. We can't support p-state in
1163          * prefetch mode > 0 so try capping the prefetch mode to start.
1164          * Override present for testing.
1165          */
1166         if (dc->debug.dml_disallow_alternate_prefetch_modes)
1167                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1168                         dm_prefetch_support_uclk_fclk_and_stutter;
1169         else
1170                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1171                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
1172
1173         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1174         /* This may adjust vlevel and maxMpcComb */
1175         if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1176                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1177                 vba->VoltageLevel = *vlevel;
1178         }
1179
1180         /* Conditions for setting up phantom pipes for SubVP:
1181          * 1. Not force disable SubVP
1182          * 2. Full update (i.e. !fast_validate)
1183          * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
1184          * 4. Display configuration passes validation
1185          * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
1186          */
1187         if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
1188             !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) &&
1189                 (*vlevel == context->bw_ctx.dml.soc.num_states ||
1190             vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
1191             dc->debug.force_subvp_mclk_switch)) {
1192
1193                 dcn32_merge_pipes_for_subvp(dc, context);
1194                 memset(merge, 0, MAX_PIPES * sizeof(bool));
1195
1196                 /* to re-initialize viewport after the pipe merge */
1197                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1198                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1199
1200                         if (!pipe_ctx->plane_state || !pipe_ctx->stream)
1201                                 continue;
1202
1203                         resource_build_scaling_params(pipe_ctx);
1204                 }
1205
1206                 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
1207                         dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
1208                         /* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
1209                          * Adding phantom pipes won't change the validation result, so change the DML input param
1210                          * for P-State support before adding phantom pipes and recalculating the DML result.
1211                          * However, this case is only applicable for SubVP + DRR cases because the prefetch mode
1212                          * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched
1213                          * enough to support MCLK switching.
1214                          */
1215                         if (*vlevel == context->bw_ctx.dml.soc.num_states &&
1216                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final ==
1217                                         dm_prefetch_support_uclk_fclk_and_stutter) {
1218                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1219                                                                 dm_prefetch_support_fclk_and_stutter;
1220                                 /* There are params (such as FabricClock) that need to be recalculated
1221                                  * after validation fails (otherwise it will be 0). Calculation for
1222                                  * phantom vactive requires call into DML, so we must ensure all the
1223                                  * vba params are valid otherwise we'll get incorrect phantom vactive.
1224                                  */
1225                                 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1226                         }
1227
1228                         dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1229
1230                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1231                         // Populate dppclk to trigger a recalculate in dml_get_voltage_level
1232                         // so the phantom pipe DLG params can be assigned correctly.
1233                         pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
1234                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1235
1236                         /* Check that vlevel requested supports pstate or not
1237                          * if not, select the lowest vlevel that supports it
1238                          */
1239                         for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
1240                                 if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) {
1241                                         *vlevel = i;
1242                                         break;
1243                                 }
1244                         }
1245
1246                         if (*vlevel < context->bw_ctx.dml.soc.num_states
1247                             && subvp_validate_static_schedulability(dc, context, *vlevel))
1248                                 found_supported_config = true;
1249                         if (found_supported_config) {
1250                                 // For SubVP + DRR cases, we can force the lowest vlevel that supports the mode
1251                                 if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {
1252                                         /* find lowest vlevel that supports the config */
1253                                         for (i = *vlevel; i >= 0; i--) {
1254                                                 if (vba->ModeSupport[i][vba->maxMpcComb]) {
1255                                                         *vlevel = i;
1256                                                 } else {
1257                                                         break;
1258                                                 }
1259                                         }
1260                                 }
1261                         }
1262                 }
1263
1264                 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
1265                 // remove phantom pipes and repopulate dml pipes
1266                 if (!found_supported_config) {
1267                         dc->res_pool->funcs->remove_phantom_pipes(dc, context, false);
1268                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1269                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1270
1271                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1272                         /* This may adjust vlevel and maxMpcComb */
1273                         if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1274                                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1275                                 vba->VoltageLevel = *vlevel;
1276                         }
1277                 } else {
1278                         // Most populate phantom DLG params before programming hardware / timing for phantom pipe
1279                         dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
1280
1281                         /* Call validate_apply_pipe_split flags after calling DML getters for
1282                          * phantom dlg params, or some of the VBA params indicating pipe split
1283                          * can be overwritten by the getters.
1284                          *
1285                          * When setting up SubVP config, all pipes are merged before attempting to
1286                          * add phantom pipes. If pipe split (ODM / MPC) is required, both the main
1287                          * and phantom pipes will be split in the regular pipe splitting sequence.
1288                          */
1289                         memset(split, 0, MAX_PIPES * sizeof(int));
1290                         memset(merge, 0, MAX_PIPES * sizeof(bool));
1291                         *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1292                         vba->VoltageLevel = *vlevel;
1293                         // Note: We can't apply the phantom pipes to hardware at this time. We have to wait
1294                         // until driver has acquired the DMCUB lock to do it safely.
1295                 }
1296         }
1297 }
1298
1299 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
1300 {
1301         int i;
1302
1303         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1304                 if (!context->res_ctx.pipe_ctx[i].stream)
1305                         continue;
1306                 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
1307                         return true;
1308         }
1309         return false;
1310 }
1311
1312 static void dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
1313 {
1314         struct dc_crtc_timing patched_crtc_timing;
1315         uint32_t asic_blank_end   = 0;
1316         uint32_t asic_blank_start = 0;
1317         uint32_t newVstartup      = 0;
1318
1319         patched_crtc_timing = *dc_crtc_timing;
1320
1321         if (patched_crtc_timing.flags.INTERLACE == 1) {
1322                 if (patched_crtc_timing.v_front_porch < 2)
1323                         patched_crtc_timing.v_front_porch = 2;
1324         } else {
1325                 if (patched_crtc_timing.v_front_porch < 1)
1326                         patched_crtc_timing.v_front_porch = 1;
1327         }
1328
1329         /* blank_start = frame end - front porch */
1330         asic_blank_start = patched_crtc_timing.v_total -
1331                                         patched_crtc_timing.v_front_porch;
1332
1333         /* blank_end = blank_start - active */
1334         asic_blank_end = asic_blank_start -
1335                                         patched_crtc_timing.v_border_bottom -
1336                                         patched_crtc_timing.v_addressable -
1337                                         patched_crtc_timing.v_border_top;
1338
1339         newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start);
1340
1341         *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
1342 }
1343
1344 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
1345                                        display_e2e_pipe_params_st *pipes,
1346                                        int pipe_cnt, int vlevel)
1347 {
1348         int i, pipe_idx, active_hubp_count = 0;
1349         bool usr_retraining_support = false;
1350         bool unbounded_req_enabled = false;
1351         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1352
1353         dc_assert_fp_enabled();
1354
1355         /* Writeback MCIF_WB arbitration parameters */
1356         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1357
1358         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1359         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1360         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1361         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1362         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1363         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1364         context->bw_ctx.bw.dcn.clk.p_state_change_support =
1365                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1366                                         != dm_dram_clock_change_unsupported;
1367
1368         /* Pstate change might not be supported by hardware, but it might be
1369          * possible with firmware driven vertical blank stretching.
1370          */
1371         context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
1372
1373         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1374         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1375         context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
1376         if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
1377                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
1378         else
1379                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1380
1381         usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1382         ASSERT(usr_retraining_support);
1383
1384         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1385                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1386
1387         unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
1388
1389         if (unbounded_req_enabled && pipe_cnt > 1) {
1390                 // Unbounded requesting should not ever be used when more than 1 pipe is enabled.
1391                 ASSERT(false);
1392                 unbounded_req_enabled = false;
1393         }
1394
1395         context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;
1396         context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;
1397         context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;
1398
1399         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1400                 if (!context->res_ctx.pipe_ctx[i].stream)
1401                         continue;
1402                 if (context->res_ctx.pipe_ctx[i].plane_state)
1403                         active_hubp_count++;
1404                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
1405                                 pipe_idx);
1406                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1407                                 pipe_idx);
1408                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
1409                                 pipe_idx);
1410                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1411                                 pipe_idx);
1412
1413                 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1414                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1415                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1416                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
1417                 } else {
1418                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,
1419                                                         pipe_idx);
1420                         context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;
1421                 }
1422
1423                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1424                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1425                 if (context->res_ctx.pipe_ctx[i].plane_state)
1426                         context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1427                 else
1428                         context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
1429                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1430
1431                 context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1432
1433                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0)
1434                         context->res_ctx.pipe_ctx[i].has_vactive_margin = true;
1435                 else
1436                         context->res_ctx.pipe_ctx[i].has_vactive_margin = false;
1437
1438                 /* MALL Allocation Sizes */
1439                 /* count from active, top pipes per plane only */
1440                 if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&
1441                                 (context->res_ctx.pipe_ctx[i].top_pipe == NULL ||
1442                                 context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&
1443                                 context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1444                         /* SS: all active surfaces stored in MALL */
1445                         if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) {
1446                                 context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1447
1448                                 if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {
1449                                         /* SS PSR On: all active surfaces part of streams not supporting PSR stored in MALL */
1450                                         context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1451                                 }
1452                         } else {
1453                                 /* SUBVP: phantom surfaces only stored in MALL */
1454                                 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1455                         }
1456                 }
1457
1458                 if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
1459                         dcn20_adjust_freesync_v_startup(
1460                                 &context->res_ctx.pipe_ctx[i].stream->timing,
1461                                 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
1462
1463                 pipe_idx++;
1464         }
1465         /* If DCN isn't making memory requests we can allow pstate change and lower clocks */
1466         if (!active_hubp_count) {
1467                 context->bw_ctx.bw.dcn.clk.socclk_khz = 0;
1468                 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1469                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;
1470                 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;
1471                 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;
1472                 context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
1473                 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
1474                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1475         }
1476         /*save a original dppclock copy*/
1477         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1478         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1479         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
1480                         * 1000;
1481         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
1482                         * 1000;
1483
1484         context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);
1485
1486         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes;
1487
1488         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1489                 if (context->res_ctx.pipe_ctx[i].stream)
1490                         context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;
1491         }
1492
1493         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1494
1495                 if (!context->res_ctx.pipe_ctx[i].stream)
1496                         continue;
1497
1498                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
1499                                 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
1500                                 pipe_cnt, pipe_idx);
1501
1502                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
1503                                 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1504                 pipe_idx++;
1505         }
1506 }
1507
1508 static struct pipe_ctx *dcn32_find_split_pipe(
1509                 struct dc *dc,
1510                 struct dc_state *context,
1511                 int old_index)
1512 {
1513         struct pipe_ctx *pipe = NULL;
1514         int i;
1515
1516         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1517                 pipe = &context->res_ctx.pipe_ctx[old_index];
1518                 pipe->pipe_idx = old_index;
1519         }
1520
1521         if (!pipe)
1522                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1523                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1524                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1525                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1526                                         pipe = &context->res_ctx.pipe_ctx[i];
1527                                         pipe->pipe_idx = i;
1528                                         break;
1529                                 }
1530                         }
1531                 }
1532
1533         /*
1534          * May need to fix pipes getting tossed from 1 opp to another on flip
1535          * Add for debugging transient underflow during topology updates:
1536          * ASSERT(pipe);
1537          */
1538         if (!pipe)
1539                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1540                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1541                                 pipe = &context->res_ctx.pipe_ctx[i];
1542                                 pipe->pipe_idx = i;
1543                                 break;
1544                         }
1545                 }
1546
1547         return pipe;
1548 }
1549
1550 static bool dcn32_split_stream_for_mpc_or_odm(
1551                 const struct dc *dc,
1552                 struct resource_context *res_ctx,
1553                 struct pipe_ctx *pri_pipe,
1554                 struct pipe_ctx *sec_pipe,
1555                 bool odm)
1556 {
1557         int pipe_idx = sec_pipe->pipe_idx;
1558         const struct resource_pool *pool = dc->res_pool;
1559
1560         DC_LOGGER_INIT(dc->ctx->logger);
1561
1562         if (odm && pri_pipe->plane_state) {
1563                 /* ODM + window MPO, where MPO window is on left half only */
1564                 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
1565                                 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) {
1566
1567                         DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n",
1568                                         __func__,
1569                                         pri_pipe->pipe_idx);
1570                         return true;
1571                 }
1572
1573                 /* ODM + window MPO, where MPO window is on right half only */
1574                 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x +  pri_pipe->stream->src.width/2) {
1575
1576                         DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n",
1577                                         __func__,
1578                                         pri_pipe->pipe_idx);
1579                         return true;
1580                 }
1581         }
1582
1583         *sec_pipe = *pri_pipe;
1584
1585         sec_pipe->pipe_idx = pipe_idx;
1586         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1587         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1588         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1589         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1590         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1591         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1592         sec_pipe->stream_res.dsc = NULL;
1593         if (odm) {
1594                 if (pri_pipe->next_odm_pipe) {
1595                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1596                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1597                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1598                 }
1599                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1600                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1601                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1602                 }
1603                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1604                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1605                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1606                 }
1607                 pri_pipe->next_odm_pipe = sec_pipe;
1608                 sec_pipe->prev_odm_pipe = pri_pipe;
1609                 ASSERT(sec_pipe->top_pipe == NULL);
1610
1611                 if (!sec_pipe->top_pipe)
1612                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1613                 else
1614                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1615                 if (sec_pipe->stream->timing.flags.DSC == 1) {
1616                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1617                         ASSERT(sec_pipe->stream_res.dsc);
1618                         if (sec_pipe->stream_res.dsc == NULL)
1619                                 return false;
1620                 }
1621         } else {
1622                 if (pri_pipe->bottom_pipe) {
1623                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1624                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1625                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1626                 }
1627                 pri_pipe->bottom_pipe = sec_pipe;
1628                 sec_pipe->top_pipe = pri_pipe;
1629
1630                 ASSERT(pri_pipe->plane_state);
1631         }
1632
1633         return true;
1634 }
1635
1636 bool dcn32_internal_validate_bw(struct dc *dc,
1637                                 struct dc_state *context,
1638                                 display_e2e_pipe_params_st *pipes,
1639                                 int *pipe_cnt_out,
1640                                 int *vlevel_out,
1641                                 bool fast_validate)
1642 {
1643         bool out = false;
1644         bool repopulate_pipes = false;
1645         int split[MAX_PIPES] = { 0 };
1646         bool merge[MAX_PIPES] = { false };
1647         bool newly_split[MAX_PIPES] = { false };
1648         int pipe_cnt, i, pipe_idx;
1649         int vlevel = context->bw_ctx.dml.soc.num_states;
1650         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1651
1652         dc_assert_fp_enabled();
1653
1654         ASSERT(pipes);
1655         if (!pipes)
1656                 return false;
1657
1658         // For each full update, remove all existing phantom pipes first
1659         dc->res_pool->funcs->remove_phantom_pipes(dc, context, fast_validate);
1660
1661         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1662
1663         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1664
1665         if (!pipe_cnt) {
1666                 out = true;
1667                 goto validate_out;
1668         }
1669
1670         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1671         context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);
1672
1673         if (!fast_validate)
1674                 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
1675
1676         if (fast_validate ||
1677                         (dc->debug.dml_disallow_alternate_prefetch_modes &&
1678                         (vlevel == context->bw_ctx.dml.soc.num_states ||
1679                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) {
1680                 /*
1681                  * If dml_disallow_alternate_prefetch_modes is false, then we have already
1682                  * tried alternate prefetch modes during full validation.
1683                  *
1684                  * If mode is unsupported or there is no p-state support, then
1685                  * fall back to favouring voltage.
1686                  *
1687                  * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try
1688                  * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)
1689                  */
1690                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1691                         dm_prefetch_support_none;
1692
1693                 context->bw_ctx.dml.validate_max_state = fast_validate;
1694                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1695
1696                 context->bw_ctx.dml.validate_max_state = false;
1697
1698                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1699                         memset(split, 0, sizeof(split));
1700                         memset(merge, 0, sizeof(merge));
1701                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1702                         // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML
1703                         vba->VoltageLevel = vlevel;
1704                 }
1705         }
1706
1707         dml_log_mode_support_params(&context->bw_ctx.dml);
1708
1709         if (vlevel == context->bw_ctx.dml.soc.num_states)
1710                 goto validate_fail;
1711
1712         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1713                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1714                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1715
1716                 if (!pipe->stream)
1717                         continue;
1718
1719                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1720                                 && !dc->config.enable_windowed_mpo_odm
1721                                 && pipe->plane_state && mpo_pipe
1722                                 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1723                                                 &pipe->plane_res.scl_data.recout,
1724                                                 sizeof(struct rect)) != 0) {
1725                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1726                         goto validate_fail;
1727                 }
1728                 pipe_idx++;
1729         }
1730
1731         /* merge pipes if necessary */
1732         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1733                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1734
1735                 /*skip pipes that don't need merging*/
1736                 if (!merge[i])
1737                         continue;
1738
1739                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1740                 if (pipe->prev_odm_pipe) {
1741                         /*split off odm pipe*/
1742                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1743                         if (pipe->next_odm_pipe)
1744                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1745
1746                         /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/
1747                         if (pipe->bottom_pipe) {
1748                                 if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) {
1749                                         /*MPC split rules will handle this case*/
1750                                         pipe->bottom_pipe->top_pipe = NULL;
1751                                 } else {
1752                                         /* when merging an ODM pipes, the bottom MPC pipe must now point to
1753                                          * the previous ODM pipe and its associated stream assets
1754                                          */
1755                                         if (pipe->prev_odm_pipe->bottom_pipe) {
1756                                                 /* 3 plane MPO*/
1757                                                 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe;
1758                                                 pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe;
1759                                         } else {
1760                                                 /* 2 plane MPO*/
1761                                                 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe;
1762                                                 pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe;
1763                                         }
1764
1765                                         memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource));
1766                                 }
1767                         }
1768
1769                         if (pipe->top_pipe) {
1770                                 pipe->top_pipe->bottom_pipe = NULL;
1771                         }
1772
1773                         pipe->bottom_pipe = NULL;
1774                         pipe->next_odm_pipe = NULL;
1775                         pipe->plane_state = NULL;
1776                         pipe->stream = NULL;
1777                         pipe->top_pipe = NULL;
1778                         pipe->prev_odm_pipe = NULL;
1779                         if (pipe->stream_res.dsc)
1780                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1781                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1782                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1783                         memset(&pipe->link_res, 0, sizeof(pipe->link_res));
1784                         repopulate_pipes = true;
1785                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1786                         struct pipe_ctx *top_pipe = pipe->top_pipe;
1787                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1788
1789                         top_pipe->bottom_pipe = bottom_pipe;
1790                         if (bottom_pipe)
1791                                 bottom_pipe->top_pipe = top_pipe;
1792
1793                         pipe->top_pipe = NULL;
1794                         pipe->bottom_pipe = NULL;
1795                         pipe->plane_state = NULL;
1796                         pipe->stream = NULL;
1797                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1798                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1799                         memset(&pipe->link_res, 0, sizeof(pipe->link_res));
1800                         repopulate_pipes = true;
1801                 } else
1802                         ASSERT(0); /* Should never try to merge master pipe */
1803
1804         }
1805
1806         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1807                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1808                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1809                 struct pipe_ctx *hsplit_pipe = NULL;
1810                 bool odm;
1811                 int old_index = -1;
1812
1813                 if (!pipe->stream || newly_split[i])
1814                         continue;
1815
1816                 pipe_idx++;
1817                 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1818
1819                 if (!pipe->plane_state && !odm)
1820                         continue;
1821
1822                 if (split[i]) {
1823                         if (odm) {
1824                                 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1825                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1826                                 else if (old_pipe->next_odm_pipe)
1827                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
1828                         } else {
1829                                 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1830                                                 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1831                                         old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1832                                 else if (old_pipe->bottom_pipe &&
1833                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1834                                         old_index = old_pipe->bottom_pipe->pipe_idx;
1835                         }
1836                         hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
1837                         ASSERT(hsplit_pipe);
1838                         if (!hsplit_pipe)
1839                                 goto validate_fail;
1840
1841                         if (!dcn32_split_stream_for_mpc_or_odm(
1842                                         dc, &context->res_ctx,
1843                                         pipe, hsplit_pipe, odm))
1844                                 goto validate_fail;
1845
1846                         newly_split[hsplit_pipe->pipe_idx] = true;
1847                         repopulate_pipes = true;
1848                 }
1849                 if (split[i] == 4) {
1850                         struct pipe_ctx *pipe_4to1;
1851
1852                         if (odm && old_pipe->next_odm_pipe)
1853                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
1854                         else if (!odm && old_pipe->bottom_pipe &&
1855                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1856                                 old_index = old_pipe->bottom_pipe->pipe_idx;
1857                         else
1858                                 old_index = -1;
1859                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
1860                         ASSERT(pipe_4to1);
1861                         if (!pipe_4to1)
1862                                 goto validate_fail;
1863                         if (!dcn32_split_stream_for_mpc_or_odm(
1864                                         dc, &context->res_ctx,
1865                                         pipe, pipe_4to1, odm))
1866                                 goto validate_fail;
1867                         newly_split[pipe_4to1->pipe_idx] = true;
1868
1869                         if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1870                                         && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1871                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1872                         else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1873                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1874                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1875                                 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1876                         else
1877                                 old_index = -1;
1878                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
1879                         ASSERT(pipe_4to1);
1880                         if (!pipe_4to1)
1881                                 goto validate_fail;
1882                         if (!dcn32_split_stream_for_mpc_or_odm(
1883                                         dc, &context->res_ctx,
1884                                         hsplit_pipe, pipe_4to1, odm))
1885                                 goto validate_fail;
1886                         newly_split[pipe_4to1->pipe_idx] = true;
1887                 }
1888                 if (odm)
1889                         dcn20_build_mapped_resource(dc, context, pipe->stream);
1890         }
1891
1892         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1893                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1894
1895                 if (pipe->plane_state) {
1896                         if (!resource_build_scaling_params(pipe))
1897                                 goto validate_fail;
1898                 }
1899         }
1900
1901         /* Actual dsc count per stream dsc validation*/
1902         if (!dcn20_validate_dsc(dc, context)) {
1903                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1904                 goto validate_fail;
1905         }
1906
1907         if (repopulate_pipes) {
1908                 int flag_max_mpc_comb = vba->maxMpcComb;
1909                 int flag_vlevel = vlevel;
1910                 int i;
1911
1912                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1913
1914                 /* repopulate_pipes = 1 means the pipes were either split or merged. In this case
1915                  * we have to re-calculate the DET allocation and run through DML once more to
1916                  * ensure all the params are calculated correctly. We do not need to run the
1917                  * pipe split check again after this call (pipes are already split / merged).
1918                  * */
1919                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1920                                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
1921                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1922                 if (vlevel == context->bw_ctx.dml.soc.num_states) {
1923                         /* failed after DET size changes */
1924                         goto validate_fail;
1925                 } else if (flag_max_mpc_comb == 0 &&
1926                                 flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) {
1927                         /* check the context constructed with pipe split flags is still valid*/
1928                         bool flags_valid = false;
1929                         for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
1930                                 if (vba->ModeSupport[i][flag_max_mpc_comb]) {
1931                                         vba->maxMpcComb = flag_max_mpc_comb;
1932                                         vba->VoltageLevel = i;
1933                                         vlevel = i;
1934                                         flags_valid = true;
1935                                 }
1936                         }
1937
1938                         /* this should never happen */
1939                         if (!flags_valid)
1940                                 goto validate_fail;
1941                 }
1942         }
1943         *vlevel_out = vlevel;
1944         *pipe_cnt_out = pipe_cnt;
1945
1946         out = true;
1947         goto validate_out;
1948
1949 validate_fail:
1950         out = false;
1951
1952 validate_out:
1953         return out;
1954 }
1955
1956
1957 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
1958                                 display_e2e_pipe_params_st *pipes,
1959                                 int pipe_cnt,
1960                                 int vlevel)
1961 {
1962         int i, pipe_idx, vlevel_temp = 0;
1963         double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
1964         double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1965         double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;
1966         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
1967                         dm_dram_clock_change_unsupported;
1968         unsigned int dummy_latency_index = 0;
1969         int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
1970         unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
1971         bool subvp_in_use = dcn32_subvp_in_use(dc, context);
1972         unsigned int min_dram_speed_mts_margin;
1973         bool need_fclk_lat_as_dummy = false;
1974         bool is_subvp_p_drr = false;
1975         struct dc_stream_state *fpo_candidate_stream = NULL;
1976
1977         dc_assert_fp_enabled();
1978
1979         /* need to find dummy latency index for subvp */
1980         if (subvp_in_use) {
1981                 /* Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK */
1982                 if (!pstate_en) {
1983                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
1984                         context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = dm_prefetch_support_fclk_and_stutter;
1985                         pstate_en = true;
1986                         is_subvp_p_drr = true;
1987                 }
1988                 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
1989                                                 context, pipes, pipe_cnt, vlevel);
1990
1991                 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so prefetch is
1992                  * scheduled correctly to account for dummy pstate.
1993                  */
1994                 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
1995                         need_fclk_lat_as_dummy = true;
1996                         context->bw_ctx.dml.soc.fclk_change_latency_us =
1997                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
1998                 }
1999                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2000                                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2001                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2002                 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2003                 if (is_subvp_p_drr) {
2004                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2005                 }
2006         }
2007
2008         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
2009         for (i = 0; i < context->stream_count; i++) {
2010                 if (context->streams[i])
2011                         context->streams[i]->fpo_in_use = false;
2012         }
2013
2014         if (!pstate_en || (!dc->debug.disable_fpo_optimizations &&
2015                         pstate_en && vlevel != 0)) {
2016                 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */
2017                 fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
2018                 if (fpo_candidate_stream) {
2019                         fpo_candidate_stream->fpo_in_use = true;
2020                         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;
2021                 }
2022
2023                 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2024                         dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2025                                 context, pipes, pipe_cnt, vlevel);
2026
2027                         /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch
2028                          * we reinstate the original dram_clock_change_latency_us on the context
2029                          * and all variables that may have changed up to this point, except the
2030                          * newly found dummy_latency_index
2031                          */
2032                         context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2033                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2034                         /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so
2035                          * prefetch is scheduled correctly to account for dummy pstate.
2036                          */
2037                         if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2038                                 need_fclk_lat_as_dummy = true;
2039                                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2040                                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2041                         }
2042                         dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false);
2043                         if (vlevel_temp < vlevel) {
2044                                 vlevel = vlevel_temp;
2045                                 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2046                                 dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2047                                 pstate_en = true;
2048                                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank;
2049                         } else {
2050                                 /* Restore FCLK latency and re-run validation to go back to original validation
2051                                  * output if we find that enabling FPO does not give us any benefit (i.e. lower
2052                                  * voltage level)
2053                                  */
2054                                 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
2055                                 for (i = 0; i < context->stream_count; i++) {
2056                                         if (context->streams[i])
2057                                                 context->streams[i]->fpo_in_use = false;
2058                                 }
2059                                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2060                                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2061                         }
2062                 }
2063         }
2064
2065         /* Set B:
2066          * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
2067          * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
2068          * calculations to cover bootup clocks.
2069          * DCFCLK: soc.clock_limits[2] when available
2070          * UCLK: soc.clock_limits[2] when available
2071          */
2072         if (dcn3_2_soc.num_states > 2) {
2073                 vlevel_temp = 2;
2074                 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
2075         } else
2076                 dcfclk = 615; //DCFCLK Vmin_lv
2077
2078         pipes[0].clks_cfg.voltage = vlevel_temp;
2079         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2080         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2081
2082         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2083                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2084                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
2085                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2086                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2087         }
2088         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2089         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2090         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2091         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2092         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2093         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2094         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2095         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2096         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2097         context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2098
2099         /* Set D:
2100          * All clocks min.
2101          * DCFCLK: Min, as reported by PM FW when available
2102          * UCLK  : Min, as reported by PM FW when available
2103          * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
2104          */
2105
2106         /*
2107         if (dcn3_2_soc.num_states > 2) {
2108                 vlevel_temp = 0;
2109                 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
2110         } else
2111                 dcfclk = 615; //DCFCLK Vmin_lv
2112
2113         pipes[0].clks_cfg.voltage = vlevel_temp;
2114         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2115         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2116
2117         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2118                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2119                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
2120                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2121                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2122         }
2123         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2124         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2125         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2126         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2127         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2128         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2129         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2130         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2131         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2132         context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2133         */
2134
2135         /* Set C, for Dummy P-State:
2136          * All clocks min.
2137          * DCFCLK: Min, as reported by PM FW, when available
2138          * UCLK  : Min,  as reported by PM FW, when available
2139          * pstate latency as per UCLK state dummy pstate latency
2140          */
2141
2142         // For Set A and Set C use values from validation
2143         pipes[0].clks_cfg.voltage = vlevel;
2144         pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
2145         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2146
2147         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2148                 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching;
2149         }
2150
2151         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2152                 min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2153                 min_dram_speed_mts_margin = 160;
2154
2155                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2156                         dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
2157
2158                 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
2159                         dm_dram_clock_change_unsupported) {
2160                         int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;
2161
2162                         min_dram_speed_mts =
2163                                 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;
2164                 }
2165
2166                 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) {
2167                         /* find largest table entry that is lower than dram speed,
2168                          * but lower than DPM0 still uses DPM0
2169                          */
2170                         for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--)
2171                                 if (min_dram_speed_mts + min_dram_speed_mts_margin >
2172                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
2173                                         break;
2174                 }
2175
2176                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2177                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2178
2179                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
2180                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2181                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2182         }
2183
2184         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2185         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2186         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2187         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2188         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2189         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2190         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2191         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2192         /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state.
2193          * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM
2194          * value.
2195          */
2196         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2197         context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2198
2199         if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
2200                 /* The only difference between A and C is p-state latency, if p-state is not supported
2201                  * with full p-state latency we want to calculate DLG based on dummy p-state latency,
2202                  * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30.
2203                  */
2204                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2205                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2206                 /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case
2207                  * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported
2208                  */
2209                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2210         } else {
2211                 /* Set A:
2212                  * All clocks min.
2213                  * DCFCLK: Min, as reported by PM FW, when available
2214                  * UCLK: Min, as reported by PM FW, when available
2215                  */
2216
2217                 /* For set A set the correct latency values (i.e. non-dummy values) unconditionally
2218                  */
2219                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2220                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2221                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2222
2223                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2224                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2225                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2226                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2227                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2228                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2229                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2230                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2231                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2232                 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2233         }
2234
2235         /* Make set D = set A since we do not optimized watermarks for MALL */
2236         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2237
2238         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2239                 if (!context->res_ctx.pipe_ctx[i].stream)
2240                         continue;
2241
2242                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2243                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2244
2245                 if (dc->config.forced_clocks) {
2246                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2247                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2248                 }
2249                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2250                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2251                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2252                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2253
2254                 pipe_idx++;
2255         }
2256
2257         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2258
2259         /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */
2260         if (need_fclk_lat_as_dummy)
2261                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2262                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2263
2264         dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2265
2266         if (!pstate_en)
2267                 /* Restore full p-state latency */
2268                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2269                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2270
2271         /* revert fclk lat changes if required */
2272         if (need_fclk_lat_as_dummy)
2273                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2274                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2275 }
2276
2277 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2278                 unsigned int *optimal_dcfclk,
2279                 unsigned int *optimal_fclk)
2280 {
2281         double bw_from_dram, bw_from_dram1, bw_from_dram2;
2282
2283         bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
2284                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
2285         bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
2286                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
2287
2288         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2289
2290         if (optimal_fclk)
2291                 *optimal_fclk = bw_from_dram /
2292                 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2293
2294         if (optimal_dcfclk)
2295                 *optimal_dcfclk =  bw_from_dram /
2296                 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2297 }
2298
2299 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
2300                 unsigned int index)
2301 {
2302         int i;
2303
2304         if (*num_entries == 0)
2305                 return;
2306
2307         for (i = index; i < *num_entries - 1; i++) {
2308                 table[i] = table[i + 1];
2309         }
2310         memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
2311 }
2312
2313 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params)
2314 {
2315         int i;
2316         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
2317                         max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
2318
2319         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2320                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2321                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2322                 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
2323                         max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2324                 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
2325                         max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2326                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2327                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2328                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2329                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2330                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2331                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2332                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
2333                         max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2334         }
2335
2336         /* Scan through clock values we currently have and if they are 0,
2337          *  then populate it with dcn3_2_soc.clock_limits[] value.
2338          *
2339          * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being
2340          *  0, will cause it to skip building the clock table.
2341          */
2342         if (max_dcfclk_mhz == 0)
2343                 bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2344         if (max_dispclk_mhz == 0)
2345                 bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2346         if (max_dtbclk_mhz == 0)
2347                 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz;
2348         if (max_uclk_mhz == 0)
2349                 bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16;
2350 }
2351
2352 /*
2353  * override_max_clk_values - Overwrite the max clock frequencies with the max DC mode timings
2354  * Input:
2355  *      max_clk_limit - struct containing the desired clock timings
2356  * Output:
2357  *      curr_clk_limit  - struct containing the timings that need to be overwritten
2358  * Return: 0 upon success, non-zero for failure
2359  */
2360 static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit,
2361                 struct clk_limit_table_entry *curr_clk_limit)
2362 {
2363         if (NULL == max_clk_limit || NULL == curr_clk_limit)
2364                 return -1; //invalid parameters
2365
2366         //only overwrite if desired max clock frequency is initialized
2367         if (max_clk_limit->dcfclk_mhz != 0)
2368                 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz;
2369
2370         if (max_clk_limit->fclk_mhz != 0)
2371                 curr_clk_limit->fclk_mhz = max_clk_limit->fclk_mhz;
2372
2373         if (max_clk_limit->memclk_mhz != 0)
2374                 curr_clk_limit->memclk_mhz = max_clk_limit->memclk_mhz;
2375
2376         if (max_clk_limit->socclk_mhz != 0)
2377                 curr_clk_limit->socclk_mhz = max_clk_limit->socclk_mhz;
2378
2379         if (max_clk_limit->dtbclk_mhz != 0)
2380                 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz;
2381
2382         if (max_clk_limit->dispclk_mhz != 0)
2383                 curr_clk_limit->dispclk_mhz = max_clk_limit->dispclk_mhz;
2384
2385         return 0;
2386 }
2387
2388 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
2389                 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2390 {
2391         int i, j;
2392         struct _vcs_dpi_voltage_scaling_st entry = {0};
2393         struct clk_limit_table_entry max_clk_data = {0};
2394
2395         unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
2396
2397         static const unsigned int num_dcfclk_stas = 5;
2398         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2399
2400         unsigned int num_uclk_dpms = 0;
2401         unsigned int num_fclk_dpms = 0;
2402         unsigned int num_dcfclk_dpms = 0;
2403
2404         unsigned int num_dc_uclk_dpms = 0;
2405         unsigned int num_dc_fclk_dpms = 0;
2406         unsigned int num_dc_dcfclk_dpms = 0;
2407
2408         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2409                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz)
2410                         max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2411                 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz)
2412                         max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2413                 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz)
2414                         max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2415                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz)
2416                         max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2417                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz)
2418                         max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2419                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz)
2420                         max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2421                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz)
2422                         max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2423
2424                 if (bw_params->clk_table.entries[i].memclk_mhz > 0) {
2425                         num_uclk_dpms++;
2426                         if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz)
2427                                 num_dc_uclk_dpms++;
2428                 }
2429                 if (bw_params->clk_table.entries[i].fclk_mhz > 0) {
2430                         num_fclk_dpms++;
2431                         if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz)
2432                                 num_dc_fclk_dpms++;
2433                 }
2434                 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) {
2435                         num_dcfclk_dpms++;
2436                         if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz)
2437                                 num_dc_dcfclk_dpms++;
2438                 }
2439         }
2440
2441         if (!disable_dc_mode_overwrite) {
2442                 //Overwrite max frequencies with max DC mode frequencies for DC mode systems
2443                 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data);
2444                 num_uclk_dpms = num_dc_uclk_dpms;
2445                 num_fclk_dpms = num_dc_fclk_dpms;
2446                 num_dcfclk_dpms = num_dc_dcfclk_dpms;
2447                 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms;
2448                 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms;
2449         }
2450
2451         if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)
2452                 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;
2453
2454         if (!max_clk_data.dcfclk_mhz || !max_clk_data.dispclk_mhz || !max_clk_data.dtbclk_mhz)
2455                 return -1;
2456
2457         if (max_clk_data.dppclk_mhz == 0)
2458                 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz;
2459
2460         if (max_clk_data.fclk_mhz == 0)
2461                 max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz *
2462                                 dcn3_2_soc.pct_ideal_sdp_bw_after_urgent /
2463                                 dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;
2464
2465         if (max_clk_data.phyclk_mhz == 0)
2466                 max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2467
2468         *num_entries = 0;
2469         entry.dispclk_mhz = max_clk_data.dispclk_mhz;
2470         entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3;
2471         entry.dppclk_mhz = max_clk_data.dppclk_mhz;
2472         entry.dtbclk_mhz = max_clk_data.dtbclk_mhz;
2473         entry.phyclk_mhz = max_clk_data.phyclk_mhz;
2474         entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2475         entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2476
2477         // Insert all the DCFCLK STAs
2478         for (i = 0; i < num_dcfclk_stas; i++) {
2479                 entry.dcfclk_mhz = dcfclk_sta_targets[i];
2480                 entry.fabricclk_mhz = 0;
2481                 entry.dram_speed_mts = 0;
2482
2483                 insert_entry_into_table_sorted(table, num_entries, &entry);
2484         }
2485
2486         // Insert the max DCFCLK
2487         entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;
2488         entry.fabricclk_mhz = 0;
2489         entry.dram_speed_mts = 0;
2490
2491         insert_entry_into_table_sorted(table, num_entries, &entry);
2492
2493         // Insert the UCLK DPMS
2494         for (i = 0; i < num_uclk_dpms; i++) {
2495                 entry.dcfclk_mhz = 0;
2496                 entry.fabricclk_mhz = 0;
2497                 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
2498
2499                 insert_entry_into_table_sorted(table, num_entries, &entry);
2500         }
2501
2502         // If FCLK is coarse grained, insert individual DPMs.
2503         if (num_fclk_dpms > 2) {
2504                 for (i = 0; i < num_fclk_dpms; i++) {
2505                         entry.dcfclk_mhz = 0;
2506                         entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2507                         entry.dram_speed_mts = 0;
2508
2509                         insert_entry_into_table_sorted(table, num_entries, &entry);
2510                 }
2511         }
2512         // If FCLK fine grained, only insert max
2513         else {
2514                 entry.dcfclk_mhz = 0;
2515                 entry.fabricclk_mhz = max_clk_data.fclk_mhz;
2516                 entry.dram_speed_mts = 0;
2517
2518                 insert_entry_into_table_sorted(table, num_entries, &entry);
2519         }
2520
2521         // At this point, the table contains all "points of interest" based on
2522         // DPMs from PMFW, and STAs.  Table is sorted by BW, and all clock
2523         // ratios (by derate, are exact).
2524
2525         // Remove states that require higher clocks than are supported
2526         for (i = *num_entries - 1; i >= 0 ; i--) {
2527                 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz ||
2528                                 table[i].fabricclk_mhz > max_clk_data.fclk_mhz ||
2529                                 table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16)
2530                         remove_entry_from_table_at_index(table, num_entries, i);
2531         }
2532
2533         // At this point, the table only contains supported points of interest
2534         // it could be used as is, but some states may be redundant due to
2535         // coarse grained nature of some clocks, so we want to round up to
2536         // coarse grained DPMs and remove duplicates.
2537
2538         // Round up UCLKs
2539         for (i = *num_entries - 1; i >= 0 ; i--) {
2540                 for (j = 0; j < num_uclk_dpms; j++) {
2541                         if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
2542                                 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
2543                                 break;
2544                         }
2545                 }
2546         }
2547
2548         // If FCLK is coarse grained, round up to next DPMs
2549         if (num_fclk_dpms > 2) {
2550                 for (i = *num_entries - 1; i >= 0 ; i--) {
2551                         for (j = 0; j < num_fclk_dpms; j++) {
2552                                 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
2553                                         table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
2554                                         break;
2555                                 }
2556                         }
2557                 }
2558         }
2559         // Otherwise, round up to minimum.
2560         else {
2561                 for (i = *num_entries - 1; i >= 0 ; i--) {
2562                         if (table[i].fabricclk_mhz < min_fclk_mhz) {
2563                                 table[i].fabricclk_mhz = min_fclk_mhz;
2564                         }
2565                 }
2566         }
2567
2568         // Round DCFCLKs up to minimum
2569         for (i = *num_entries - 1; i >= 0 ; i--) {
2570                 if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
2571                         table[i].dcfclk_mhz = min_dcfclk_mhz;
2572                 }
2573         }
2574
2575         // Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
2576         i = 0;
2577         while (i < *num_entries - 1) {
2578                 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
2579                                 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
2580                                 table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
2581                         remove_entry_from_table_at_index(table, num_entries, i + 1);
2582                 else
2583                         i++;
2584         }
2585
2586         // Fix up the state indicies
2587         for (i = *num_entries - 1; i >= 0 ; i--) {
2588                 table[i].state = i;
2589         }
2590
2591         return 0;
2592 }
2593
2594 /*
2595  * dcn32_update_bw_bounding_box
2596  *
2597  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from
2598  * spreadsheet with actual values as per dGPU SKU:
2599  * - with passed few options from dc->config
2600  * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
2601  *   need to get it from PM FW)
2602  * - with passed latency values (passed in ns units) in dc-> bb override for
2603  *   debugging purposes
2604  * - with passed latencies from VBIOS (in 100_ns units) if available for
2605  *   certain dGPU SKU
2606  * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
2607  *   of the same ASIC)
2608  * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
2609  *   FW for different clocks (which might differ for certain dGPU SKU of the
2610  *   same ASIC)
2611  */
2612 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
2613 {
2614         dc_assert_fp_enabled();
2615
2616         /* Overrides from dc->config options */
2617         dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
2618
2619         /* Override from passed dc->bb_overrides if available*/
2620         if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2621                         && dc->bb_overrides.sr_exit_time_ns) {
2622                 dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2623         }
2624
2625         if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
2626                         != dc->bb_overrides.sr_enter_plus_exit_time_ns
2627                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2628                 dcn3_2_soc.sr_enter_plus_exit_time_us =
2629                         dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2630         }
2631
2632         if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2633                 && dc->bb_overrides.urgent_latency_ns) {
2634                 dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2635                 dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2636         }
2637
2638         if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
2639                         != dc->bb_overrides.dram_clock_change_latency_ns
2640                         && dc->bb_overrides.dram_clock_change_latency_ns) {
2641                 dcn3_2_soc.dram_clock_change_latency_us =
2642                         dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2643         }
2644
2645         if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000)
2646                         != dc->bb_overrides.fclk_clock_change_latency_ns
2647                         && dc->bb_overrides.fclk_clock_change_latency_ns) {
2648                 dcn3_2_soc.fclk_change_latency_us =
2649                         dc->bb_overrides.fclk_clock_change_latency_ns / 1000;
2650         }
2651
2652         if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
2653                         != dc->bb_overrides.dummy_clock_change_latency_ns
2654                         && dc->bb_overrides.dummy_clock_change_latency_ns) {
2655                 dcn3_2_soc.dummy_pstate_latency_us =
2656                         dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
2657         }
2658
2659         /* Override from VBIOS if VBIOS bb_info available */
2660         if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
2661                 struct bp_soc_bb_info bb_info = {0};
2662
2663                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
2664                         if (bb_info.dram_clock_change_latency_100ns > 0)
2665                                 dcn3_2_soc.dram_clock_change_latency_us =
2666                                         bb_info.dram_clock_change_latency_100ns * 10;
2667
2668                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
2669                                 dcn3_2_soc.sr_enter_plus_exit_time_us =
2670                                         bb_info.dram_sr_enter_exit_latency_100ns * 10;
2671
2672                         if (bb_info.dram_sr_exit_latency_100ns > 0)
2673                                 dcn3_2_soc.sr_exit_time_us =
2674                                         bb_info.dram_sr_exit_latency_100ns * 10;
2675                 }
2676         }
2677
2678         /* Override from VBIOS for num_chan */
2679         if (dc->ctx->dc_bios->vram_info.num_chans) {
2680                 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2681                 dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,
2682                         dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);
2683         }
2684
2685         if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2686                 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2687
2688         /* DML DSC delay factor workaround */
2689         dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
2690
2691         dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
2692
2693         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
2694         dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2695         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2696
2697         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
2698         if (bw_params->clk_table.entries[0].memclk_mhz) {
2699                 if (dc->debug.use_legacy_soc_bb_mechanism) {
2700                         unsigned int i = 0, j = 0, num_states = 0;
2701
2702                         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2703                         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2704                         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2705                         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2706                         unsigned int min_dcfclk = UINT_MAX;
2707                         /* Set 199 as first value in STA target array to have a minimum DCFCLK value.
2708                          * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */
2709                         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2710                         unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
2711                         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
2712
2713                         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2714                                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2715                                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2716                                 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&
2717                                                 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)
2718                                         min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;
2719                                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2720                                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2721                                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2722                                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2723                                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2724                                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2725                         }
2726                         if (min_dcfclk > dcfclk_sta_targets[0])
2727                                 dcfclk_sta_targets[0] = min_dcfclk;
2728                         if (!max_dcfclk_mhz)
2729                                 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2730                         if (!max_dispclk_mhz)
2731                                 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2732                         if (!max_dppclk_mhz)
2733                                 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
2734                         if (!max_phyclk_mhz)
2735                                 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2736
2737                         if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2738                                 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2739                                 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2740                                 num_dcfclk_sta_targets++;
2741                         } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2742                                 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2743                                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2744                                         if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2745                                                 dcfclk_sta_targets[i] = max_dcfclk_mhz;
2746                                                 break;
2747                                         }
2748                                 }
2749                                 // Update size of array since we "removed" duplicates
2750                                 num_dcfclk_sta_targets = i + 1;
2751                         }
2752
2753                         num_uclk_states = bw_params->clk_table.num_entries;
2754
2755                         // Calculate optimal dcfclk for each uclk
2756                         for (i = 0; i < num_uclk_states; i++) {
2757                                 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2758                                                 &optimal_dcfclk_for_uclk[i], NULL);
2759                                 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2760                                         optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2761                                 }
2762                         }
2763
2764                         // Calculate optimal uclk for each dcfclk sta target
2765                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
2766                                 for (j = 0; j < num_uclk_states; j++) {
2767                                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2768                                                 optimal_uclk_for_dcfclk_sta_targets[i] =
2769                                                                 bw_params->clk_table.entries[j].memclk_mhz * 16;
2770                                                 break;
2771                                         }
2772                                 }
2773                         }
2774
2775                         i = 0;
2776                         j = 0;
2777                         // create the final dcfclk and uclk table
2778                         while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2779                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2780                                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2781                                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2782                                 } else {
2783                                         if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2784                                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2785                                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2786                                         } else {
2787                                                 j = num_uclk_states;
2788                                         }
2789                                 }
2790                         }
2791
2792                         while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2793                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2794                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2795                         }
2796
2797                         while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2798                                         optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2799                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2800                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2801                         }
2802
2803                         dcn3_2_soc.num_states = num_states;
2804                         for (i = 0; i < dcn3_2_soc.num_states; i++) {
2805                                 dcn3_2_soc.clock_limits[i].state = i;
2806                                 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2807                                 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2808
2809                                 /* Fill all states with max values of all these clocks */
2810                                 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
2811                                 dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
2812                                 dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
2813                                 dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
2814
2815                                 /* Populate from bw_params for DTBCLK, SOCCLK */
2816                                 if (i > 0) {
2817                                         if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
2818                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
2819                                         } else {
2820                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
2821                                         }
2822                                 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
2823                                         dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
2824                                 }
2825
2826                                 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
2827                                         dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
2828                                 else
2829                                         dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
2830
2831                                 if (!dram_speed_mts[i] && i > 0)
2832                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
2833                                 else
2834                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2835
2836                                 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
2837                                 /* PHYCLK_D18, PHYCLK_D32 */
2838                                 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2839                                 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2840                         }
2841                 } else {
2842                         build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,
2843                                         dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states);
2844                 }
2845
2846                 /* Re-init DML with updated bb */
2847                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2848                 if (dc->current_state)
2849                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2850         }
2851 }
2852
2853 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
2854                                   int pipe_cnt)
2855 {
2856         dc_assert_fp_enabled();
2857
2858         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
2859         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
2860 }
2861
2862 bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
2863 {
2864         bool allow = false;
2865         uint32_t refresh_rate = 0;
2866
2867         /* Allow subvp on displays that have active margin for 2560x1440@60hz displays
2868          * only for now. There must be no scaling as well.
2869          *
2870          * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs
2871          * for p-state switching.
2872          */
2873         if (pipe->stream && pipe->plane_state) {
2874                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
2875                                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
2876                                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
2877                 if (pipe->stream->timing.v_addressable == 1440 &&
2878                                 pipe->stream->timing.h_addressable == 2560 &&
2879                                 refresh_rate >= 55 && refresh_rate <= 65 &&
2880                                 pipe->plane_state->src_rect.height == 1440 &&
2881                                 pipe->plane_state->src_rect.width == 2560 &&
2882                                 pipe->plane_state->dst_rect.height == 1440 &&
2883                                 pipe->plane_state->dst_rect.width == 2560)
2884                         allow = true;
2885         }
2886         return allow;
2887 }
2888
2889 /**
2890  * dcn32_allow_subvp_high_refresh_rate: Determine if the high refresh rate config will allow subvp
2891  *
2892  * @dc: Current DC state
2893  * @context: New DC state to be programmed
2894  * @pipe: Pipe to be considered for use in subvp
2895  *
2896  * On high refresh rate display configs, we will allow subvp under the following conditions:
2897  * 1. Resolution is 3840x2160, 3440x1440, or 2560x1440
2898  * 2. Refresh rate is between 120hz - 165hz
2899  * 3. No scaling
2900  * 4. Freesync is inactive
2901  * 5. For single display cases, freesync must be disabled
2902  *
2903  * Return: True if pipe can be used for subvp, false otherwise
2904  */
2905 bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)
2906 {
2907         bool allow = false;
2908         uint32_t refresh_rate = 0;
2909         uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh;
2910         uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh;
2911         uint32_t min_refresh = subvp_max_refresh;
2912         uint32_t i;
2913
2914         /* Only allow SubVP on high refresh displays if all connected displays
2915          * are considered "high refresh" (i.e. >= 120hz). We do not want to
2916          * allow combinations such as 120hz (SubVP) + 60hz (SubVP).
2917          */
2918         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2919                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2920
2921                 if (!pipe_ctx->stream)
2922                         continue;
2923                 refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +
2924                                 pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)
2925                                                 / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);
2926
2927                 if (refresh_rate < min_refresh)
2928                         min_refresh = refresh_rate;
2929         }
2930
2931         if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&
2932                         pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
2933                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
2934                                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
2935                                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
2936                 if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) {
2937                         for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) {
2938                                 uint32_t width = subvp_high_refresh_list.res[i].width;
2939                                 uint32_t height = subvp_high_refresh_list.res[i].height;
2940
2941                                 if (dcn32_check_native_scaling_for_res(pipe, width, height)) {
2942                                         if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) {
2943                                                 allow = true;
2944                                                 break;
2945                                         }
2946                                 }
2947                         }
2948                 }
2949         }
2950         return allow;
2951 }
2952
2953 /**
2954  * dcn32_determine_max_vratio_prefetch: Determine max Vratio for prefetch by driver policy
2955  *
2956  * @dc: Current DC state
2957  * @context: New DC state to be programmed
2958  *
2959  * Return: Max vratio for prefetch
2960  */
2961 double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)
2962 {
2963         double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4
2964         int i;
2965
2966         /* For single display MPO configs, allow the max vratio to be 8
2967          * if any plane is YUV420 format
2968          */
2969         if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) {
2970                 for (i = 0; i < context->stream_status[0].plane_count; i++) {
2971                         if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr ||
2972                                         context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) {
2973                                 max_vratio_pre = __DML_MAX_VRATIO_PRE__;
2974                         }
2975                 }
2976         }
2977         return max_vratio_pre;
2978 }
2979
2980 /**
2981  * dcn32_assign_fpo_vactive_candidate - Assign the FPO stream candidate for FPO + VActive case
2982  *
2983  * This function chooses the FPO candidate stream for FPO + VActive cases (2 stream config).
2984  * For FPO + VAtive cases, the assumption is that one display has ActiveMargin > 0, and the
2985  * other display has ActiveMargin <= 0. This function will choose the pipe/stream that has
2986  * ActiveMargin <= 0 to be the FPO stream candidate if found.
2987  *
2988  *
2989  * @dc: current dc state
2990  * @context: new dc state
2991  * @fpo_candidate_stream: pointer to FPO stream candidate if one is found
2992  *
2993  * Return: void
2994  */
2995 void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream)
2996 {
2997         unsigned int i, pipe_idx;
2998         const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
2999
3000         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3001                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3002
3003                 if (!pipe->stream)
3004                         continue;
3005
3006                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
3007                         *fpo_candidate_stream = pipe->stream;
3008                         break;
3009                 }
3010                 pipe_idx++;
3011         }
3012 }
3013
3014 /**
3015  * dcn32_find_vactive_pipe - Determines if the config has a pipe that can switch in VACTIVE
3016  *
3017  * @dc: current dc state
3018  * @context: new dc state
3019  * @vactive_margin_req_us: The vactive marign required for a vactive pipe to be considered "found"
3020  *
3021  * Return: True if VACTIVE display is found, false otherwise
3022  */
3023 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us)
3024 {
3025         unsigned int i, pipe_idx;
3026         const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
3027         bool vactive_found = false;
3028         unsigned int blank_us = 0;
3029
3030         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3031                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3032
3033                 if (!pipe->stream)
3034                         continue;
3035
3036                 blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total /
3037                                 (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000;
3038                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] >= vactive_margin_req_us &&
3039                                 !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed) && blank_us < dc->debug.fpo_vactive_max_blank_us) {
3040                         vactive_found = true;
3041                         break;
3042                 }
3043                 pipe_idx++;
3044         }
3045         return vactive_found;
3046 }
3047
3048 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb)
3049 {
3050         dc_assert_fp_enabled();
3051         dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0;
3052 }
3053
3054 void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)
3055 {
3056         // WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue)
3057         if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&
3058                         dc->dml.soc.num_chans <= 8) {
3059                 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
3060
3061                 if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&
3062                                 num_mclk_levels > 1) {
3063                         context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;
3064                         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3065                 }
3066         }
3067 }