drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "clk_mgr.h"
  28 #include "resource.h"
  29 #include "dcn31/dcn31_hubbub.h"
  30 #include "dcn314_fpu.h"
  31 #include "dml/dcn20/dcn20_fpu.h"
  32 #include "dml/dcn31/dcn31_fpu.h"
  33 #include "dml/display_mode_vba.h"
  34
  35 struct _vcs_dpi_ip_params_st dcn3_14_ip = {
  36         .VBlankNomDefaultUS = 668,
  37         .gpuvm_enable = 1,
  38         .gpuvm_max_page_table_levels = 1,
  39         .hostvm_enable = 1,
  40         .hostvm_max_page_table_levels = 2,
  41         .rob_buffer_size_kbytes = 64,
  42         .det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE,
  43         .config_return_buffer_size_in_kbytes = 1792,
  44         .compressed_buffer_segment_size_in_kbytes = 64,
  45         .meta_fifo_size_in_kentries = 32,
  46         .zero_size_buffer_entries = 512,
  47         .compbuf_reserved_space_64b = 256,
  48         .compbuf_reserved_space_zs = 64,
  49         .dpp_output_buffer_pixels = 2560,
  50         .opp_output_buffer_lines = 1,
  51         .pixel_chunk_size_kbytes = 8,
  52         .meta_chunk_size_kbytes = 2,
  53         .min_meta_chunk_size_bytes = 256,
  54         .writeback_chunk_size_kbytes = 8,
  55         .ptoi_supported = false,
  56         .num_dsc = 4,
  57         .maximum_dsc_bits_per_component = 10,
  58         .dsc422_native_support = false,
  59         .is_line_buffer_bpp_fixed = true,
  60         .line_buffer_fixed_bpp = 48,
  61         .line_buffer_size_bits = 789504,
  62         .max_line_buffer_lines = 12,
  63         .writeback_interface_buffer_size_kbytes = 90,
  64         .max_num_dpp = 4,
  65         .max_num_otg = 4,
  66         .max_num_hdmi_frl_outputs = 1,
  67         .max_num_wb = 1,
  68         .max_dchub_pscl_bw_pix_per_clk = 4,
  69         .max_pscl_lb_bw_pix_per_clk = 2,
  70         .max_lb_vscl_bw_pix_per_clk = 4,
  71         .max_vscl_hscl_bw_pix_per_clk = 4,
  72         .max_hscl_ratio = 6,
  73         .max_vscl_ratio = 6,
  74         .max_hscl_taps = 8,
  75         .max_vscl_taps = 8,
  76         .dpte_buffer_size_in_pte_reqs_luma = 64,
  77         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  78         .dispclk_ramp_margin_percent = 1,
  79         .max_inter_dcn_tile_repeaters = 8,
  80         .cursor_buffer_size = 16,
  81         .cursor_chunk_size = 2,
  82         .writeback_line_buffer_buffer_size = 0,
  83         .writeback_min_hscl_ratio = 1,
  84         .writeback_min_vscl_ratio = 1,
  85         .writeback_max_hscl_ratio = 1,
  86         .writeback_max_vscl_ratio = 1,
  87         .writeback_max_hscl_taps = 1,
  88         .writeback_max_vscl_taps = 1,
  89         .dppclk_delay_subtotal = 46,
  90         .dppclk_delay_scl = 50,
  91         .dppclk_delay_scl_lb_only = 16,
  92         .dppclk_delay_cnvc_formatter = 27,
  93         .dppclk_delay_cnvc_cursor = 6,
  94         .dispclk_delay_subtotal = 119,
  95         .dynamic_metadata_vm_enabled = false,
  96         .odm_combine_4to1_supported = false,
  97         .dcc_supported = true,
  98 };
  99
 100 static struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {
 101                 /*TODO: correct dispclk/dppclk voltage level determination*/
 102         .clock_limits = {
 103                 {
 104                         .state = 0,
 105                         .dispclk_mhz = 1200.0,
 106                         .dppclk_mhz = 1200.0,
 107                         .phyclk_mhz = 600.0,
 108                         .phyclk_d18_mhz = 667.0,
 109                         .dscclk_mhz = 186.0,
 110                         .dtbclk_mhz = 600.0,
 111                 },
 112                 {
 113                         .state = 1,
 114                         .dispclk_mhz = 1200.0,
 115                         .dppclk_mhz = 1200.0,
 116                         .phyclk_mhz = 810.0,
 117                         .phyclk_d18_mhz = 667.0,
 118                         .dscclk_mhz = 209.0,
 119                         .dtbclk_mhz = 600.0,
 120                 },
 121                 {
 122                         .state = 2,
 123                         .dispclk_mhz = 1200.0,
 124                         .dppclk_mhz = 1200.0,
 125                         .phyclk_mhz = 810.0,
 126                         .phyclk_d18_mhz = 667.0,
 127                         .dscclk_mhz = 209.0,
 128                         .dtbclk_mhz = 600.0,
 129                 },
 130                 {
 131                         .state = 3,
 132                         .dispclk_mhz = 1200.0,
 133                         .dppclk_mhz = 1200.0,
 134                         .phyclk_mhz = 810.0,
 135                         .phyclk_d18_mhz = 667.0,
 136                         .dscclk_mhz = 371.0,
 137                         .dtbclk_mhz = 600.0,
 138                 },
 139                 {
 140                         .state = 4,
 141                         .dispclk_mhz = 1200.0,
 142                         .dppclk_mhz = 1200.0,
 143                         .phyclk_mhz = 810.0,
 144                         .phyclk_d18_mhz = 667.0,
 145                         .dscclk_mhz = 417.0,
 146                         .dtbclk_mhz = 600.0,
 147                 },
 148         },
 149         .num_states = 5,
 150         .sr_exit_time_us = 16.5,
 151         .sr_enter_plus_exit_time_us = 18.5,
 152         .sr_exit_z8_time_us = 268.0,
 153         .sr_enter_plus_exit_z8_time_us = 393.0,
 154         .writeback_latency_us = 12.0,
 155         .dram_channel_width_bytes = 4,
 156         .round_trip_ping_latency_dcfclk_cycles = 106,
 157         .urgent_latency_pixel_data_only_us = 4.0,
 158         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 159         .urgent_latency_vm_data_only_us = 4.0,
 160         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 161         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 162         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 163         .pct_ideal_sdp_bw_after_urgent = 80.0,
 164         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 165         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 166         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 167         .max_avg_sdp_bw_use_normal_percent = 60.0,
 168         .max_avg_dram_bw_use_normal_percent = 60.0,
 169         .fabric_datapath_to_dcn_data_return_bytes = 32,
 170         .return_bus_width_bytes = 64,
 171         .downspread_percent = 0.38,
 172         .dcn_downspread_percent = 0.5,
 173         .gpuvm_min_page_size_bytes = 4096,
 174         .hostvm_min_page_size_bytes = 4096,
 175         .do_urgent_latency_adjustment = false,
 176         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 177         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 178 };
 179
 180
 181 void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
 182 {
 183         struct clk_limit_table *clk_table = &bw_params->clk_table;
 184         struct _vcs_dpi_voltage_scaling_st *clock_limits =
 185                 dcn3_14_soc.clock_limits;
 186         unsigned int i, closest_clk_lvl;
 187         int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 188         int j;
 189
 190         dc_assert_fp_enabled();
 191
 192         // Default clock levels are used for diags, which may lead to overclocking.
 193         if (!IS_DIAG_DC(dc->ctx->dce_environment) && dc->config.use_default_clock_table == false) {
 194
 195                 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
 196                 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;
 197
 198                 if (bw_params->dram_channel_width_bytes > 0)
 199                         dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes;
 200
 201                 if (bw_params->num_channels > 0)
 202                         dcn3_14_soc.num_chans = bw_params->num_channels;
 203
 204                 ASSERT(dcn3_14_soc.num_chans);
 205                 ASSERT(clk_table->num_entries);
 206
 207                 /* Prepass to find max clocks independent of voltage level. */
 208                 for (i = 0; i < clk_table->num_entries; ++i) {
 209                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
 210                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
 211                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
 212                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
 213                 }
 214
 215                 for (i = 0; i < clk_table->num_entries; i++) {
 216                         /* loop backwards*/
 217                         for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) {
 218                                 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
 219                                         closest_clk_lvl = j;
 220                                         break;
 221                                 }
 222                         }
 223                         if (clk_table->num_entries == 1) {
 224                                 /*smu gives one DPM level, let's take the highest one*/
 225                                 closest_clk_lvl = dcn3_14_soc.num_states - 1;
 226                         }
 227
 228                         clock_limits[i].state = i;
 229
 230                         /* Clocks dependent on voltage level. */
 231                         clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 232                         if (clk_table->num_entries == 1 &&
 233                                 clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
 234                                 /*SMU fix not released yet*/
 235                                 clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
 236                         }
 237                         clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
 238                         clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
 239
 240                         if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio)
 241                                 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 242
 243                         /* Clocks independent of voltage level. */
 244                         clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 245                                 dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 246
 247                         clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 248                                 dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 249
 250                         clock_limits[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
 251                         clock_limits[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
 252                         clock_limits[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
 253                         clock_limits[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
 254                         clock_limits[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 255                 }
 256                 for (i = 0; i < clk_table->num_entries; i++)
 257                         dcn3_14_soc.clock_limits[i] = clock_limits[i];
 258                 if (clk_table->num_entries) {
 259                         dcn3_14_soc.num_states = clk_table->num_entries;
 260                 }
 261         }
 262
 263         if (max_dispclk_mhz) {
 264                 dcn3_14_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 265                 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 266         }
 267
 268         dcn20_patch_bounding_box(dc, &dcn3_14_soc);
 269
 270         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 271                 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314);
 272         else
 273                 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA);
 274 }
 275
 276 static bool is_dual_plane(enum surface_pixel_format format)
 277 {
 278         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
 279 }
 280
 281 int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,
 282                                                display_e2e_pipe_params_st *pipes,
 283                                                bool fast_validate)
 284 {
 285         int i, pipe_cnt;
 286         struct resource_context *res_ctx = &context->res_ctx;
 287         struct pipe_ctx *pipe;
 288         bool upscaled = false;
 289         bool isFreesyncVideo = false;
 290
 291         dc_assert_fp_enabled();
 292
 293         dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
 294
 295         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
 296                 struct dc_crtc_timing *timing;
 297
 298                 if (!res_ctx->pipe_ctx[i].stream)
 299                         continue;
 300                 pipe = &res_ctx->pipe_ctx[i];
 301                 timing = &pipe->stream->timing;
 302
 303                 isFreesyncVideo = pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min;
 304                 isFreesyncVideo = isFreesyncVideo && pipe->stream->adjust.v_total_min > timing->v_total;
 305
 306                 if (!isFreesyncVideo) {
 307                         pipes[pipe_cnt].pipe.dest.vblank_nom =
 308                                 dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0));
 309                 } else {
 310                         pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min;
 311                         pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
 312                 }
 313
 314                 if (pipe->plane_state &&
 315                                 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
 316                                 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
 317                         upscaled = true;
 318
 319                 /* Apply HostVM policy - either based on hypervisor globally enabled, or rIOMMU active */
 320                 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)
 321                         pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active;
 322
 323                 /*
 324                  * Immediate flip can be set dynamically after enabling the plane.
 325                  * We need to require support for immediate flip or underflow can be
 326                  * intermittently experienced depending on peak b/w requirements.
 327                  */
 328                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
 329
 330                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
 331                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
 332                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
 333                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
 334                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
 335                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
 336
 337                 if (pipes[pipe_cnt].dout.dsc_enable) {
 338                         switch (timing->display_color_depth) {
 339                         case COLOR_DEPTH_888:
 340                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
 341                                 break;
 342                         case COLOR_DEPTH_101010:
 343                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
 344                                 break;
 345                         case COLOR_DEPTH_121212:
 346                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
 347                                 break;
 348                         default:
 349                                 ASSERT(0);
 350                                 break;
 351                         }
 352                 }
 353
 354                 pipe_cnt++;
 355         }
 356         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE;
 357
 358         dc->config.enable_4to1MPC = false;
 359         if (pipe_cnt == 1 && pipe->plane_state
 360                 && pipe->plane_state->rotation == ROTATION_ANGLE_0 && !dc->debug.disable_z9_mpc) {
 361                 if (is_dual_plane(pipe->plane_state->format)
 362                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
 363                         dc->config.enable_4to1MPC = true;
 364                 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
 365                         /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
 366                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
 367                         pipes[0].pipe.src.unbounded_req_mode = true;
 368                 }
 369         } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
 370                         && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
 371                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
 372         } else if (context->stream_count >= 3 && upscaled) {
 373                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
 374         }
 375
 376         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 377                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 378
 379                 if (!pipe->stream)
 380                         continue;
 381
 382                 if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine &&
 383                                 pipe->stream->apply_seamless_boot_optimization) {
 384
 385                         if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) {
 386                                 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1;
 387                                 break;
 388                         }
 389                 }
 390         }
 391
 392         return pipe_cnt;
 393 }