drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

   1 /*
   2  * Copyright 2019-2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "resource.h"
  27 #include "clk_mgr.h"
  28 #include "dcn31/dcn31_resource.h"
  29 #include "dcn315/dcn315_resource.h"
  30 #include "dcn316/dcn316_resource.h"
  31
  32 #include "dml/dcn20/dcn20_fpu.h"
  33 #include "dcn31_fpu.h"
  34
  35 /**
  36  * DOC: DCN31x FPU manipulation Overview
  37  *
  38  * The DCN architecture relies on FPU operations, which require special
  39  * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
  40  * want to avoid spreading FPU access across multiple files. With this idea in
  41  * mind, this file aims to centralize all DCN3.1.x functions that require FPU
  42  * access in a single place. Code in this file follows the following code
  43  * pattern:
  44  *
  45  * 1. Functions that use FPU operations should be isolated in static functions.
  46  * 2. The FPU functions should have the noinline attribute to ensure anything
  47  *    that deals with FP register is contained within this call.
  48  * 3. All function that needs to be accessed outside this file requires a
  49  *    public interface that not uses any FPU reference.
  50  * 4. Developers **must not** use DC_FP_START/END in this file, but they need
  51  *    to ensure that the caller invokes it before access any function available
  52  *    in this file. For this reason, public functions in this file must invoke
  53  *    dc_assert_fp_enabled();
  54  */
  55
  56 struct _vcs_dpi_ip_params_st dcn3_1_ip = {
  57         .gpuvm_enable = 1,
  58         .gpuvm_max_page_table_levels = 1,
  59         .hostvm_enable = 1,
  60         .hostvm_max_page_table_levels = 2,
  61         .rob_buffer_size_kbytes = 64,
  62         .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
  63         .config_return_buffer_size_in_kbytes = 1792,
  64         .compressed_buffer_segment_size_in_kbytes = 64,
  65         .meta_fifo_size_in_kentries = 32,
  66         .zero_size_buffer_entries = 512,
  67         .compbuf_reserved_space_64b = 256,
  68         .compbuf_reserved_space_zs = 64,
  69         .dpp_output_buffer_pixels = 2560,
  70         .opp_output_buffer_lines = 1,
  71         .pixel_chunk_size_kbytes = 8,
  72         .meta_chunk_size_kbytes = 2,
  73         .min_meta_chunk_size_bytes = 256,
  74         .writeback_chunk_size_kbytes = 8,
  75         .ptoi_supported = false,
  76         .num_dsc = 3,
  77         .maximum_dsc_bits_per_component = 10,
  78         .dsc422_native_support = false,
  79         .is_line_buffer_bpp_fixed = true,
  80         .line_buffer_fixed_bpp = 48,
  81         .line_buffer_size_bits = 789504,
  82         .max_line_buffer_lines = 12,
  83         .writeback_interface_buffer_size_kbytes = 90,
  84         .max_num_dpp = 4,
  85         .max_num_otg = 4,
  86         .max_num_hdmi_frl_outputs = 1,
  87         .max_num_wb = 1,
  88         .max_dchub_pscl_bw_pix_per_clk = 4,
  89         .max_pscl_lb_bw_pix_per_clk = 2,
  90         .max_lb_vscl_bw_pix_per_clk = 4,
  91         .max_vscl_hscl_bw_pix_per_clk = 4,
  92         .max_hscl_ratio = 6,
  93         .max_vscl_ratio = 6,
  94         .max_hscl_taps = 8,
  95         .max_vscl_taps = 8,
  96         .dpte_buffer_size_in_pte_reqs_luma = 64,
  97         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  98         .dispclk_ramp_margin_percent = 1,
  99         .max_inter_dcn_tile_repeaters = 8,
 100         .cursor_buffer_size = 16,
 101         .cursor_chunk_size = 2,
 102         .writeback_line_buffer_buffer_size = 0,
 103         .writeback_min_hscl_ratio = 1,
 104         .writeback_min_vscl_ratio = 1,
 105         .writeback_max_hscl_ratio = 1,
 106         .writeback_max_vscl_ratio = 1,
 107         .writeback_max_hscl_taps = 1,
 108         .writeback_max_vscl_taps = 1,
 109         .dppclk_delay_subtotal = 46,
 110         .dppclk_delay_scl = 50,
 111         .dppclk_delay_scl_lb_only = 16,
 112         .dppclk_delay_cnvc_formatter = 27,
 113         .dppclk_delay_cnvc_cursor = 6,
 114         .dispclk_delay_subtotal = 119,
 115         .dynamic_metadata_vm_enabled = false,
 116         .odm_combine_4to1_supported = false,
 117         .dcc_supported = true,
 118 };
 119
 120 static struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
 121                 /*TODO: correct dispclk/dppclk voltage level determination*/
 122         .clock_limits = {
 123                 {
 124                         .state = 0,
 125                         .dispclk_mhz = 1200.0,
 126                         .dppclk_mhz = 1200.0,
 127                         .phyclk_mhz = 600.0,
 128                         .phyclk_d18_mhz = 667.0,
 129                         .dscclk_mhz = 186.0,
 130                         .dtbclk_mhz = 625.0,
 131                 },
 132                 {
 133                         .state = 1,
 134                         .dispclk_mhz = 1200.0,
 135                         .dppclk_mhz = 1200.0,
 136                         .phyclk_mhz = 810.0,
 137                         .phyclk_d18_mhz = 667.0,
 138                         .dscclk_mhz = 209.0,
 139                         .dtbclk_mhz = 625.0,
 140                 },
 141                 {
 142                         .state = 2,
 143                         .dispclk_mhz = 1200.0,
 144                         .dppclk_mhz = 1200.0,
 145                         .phyclk_mhz = 810.0,
 146                         .phyclk_d18_mhz = 667.0,
 147                         .dscclk_mhz = 209.0,
 148                         .dtbclk_mhz = 625.0,
 149                 },
 150                 {
 151                         .state = 3,
 152                         .dispclk_mhz = 1200.0,
 153                         .dppclk_mhz = 1200.0,
 154                         .phyclk_mhz = 810.0,
 155                         .phyclk_d18_mhz = 667.0,
 156                         .dscclk_mhz = 371.0,
 157                         .dtbclk_mhz = 625.0,
 158                 },
 159                 {
 160                         .state = 4,
 161                         .dispclk_mhz = 1200.0,
 162                         .dppclk_mhz = 1200.0,
 163                         .phyclk_mhz = 810.0,
 164                         .phyclk_d18_mhz = 667.0,
 165                         .dscclk_mhz = 417.0,
 166                         .dtbclk_mhz = 625.0,
 167                 },
 168         },
 169         .num_states = 5,
 170         .sr_exit_time_us = 9.0,
 171         .sr_enter_plus_exit_time_us = 11.0,
 172         .sr_exit_z8_time_us = 442.0,
 173         .sr_enter_plus_exit_z8_time_us = 560.0,
 174         .writeback_latency_us = 12.0,
 175         .dram_channel_width_bytes = 4,
 176         .round_trip_ping_latency_dcfclk_cycles = 106,
 177         .urgent_latency_pixel_data_only_us = 4.0,
 178         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 179         .urgent_latency_vm_data_only_us = 4.0,
 180         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 181         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 182         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 183         .pct_ideal_sdp_bw_after_urgent = 80.0,
 184         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 185         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 186         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 187         .max_avg_sdp_bw_use_normal_percent = 60.0,
 188         .max_avg_dram_bw_use_normal_percent = 60.0,
 189         .fabric_datapath_to_dcn_data_return_bytes = 32,
 190         .return_bus_width_bytes = 64,
 191         .downspread_percent = 0.38,
 192         .dcn_downspread_percent = 0.5,
 193         .gpuvm_min_page_size_bytes = 4096,
 194         .hostvm_min_page_size_bytes = 4096,
 195         .do_urgent_latency_adjustment = false,
 196         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 197         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 198 };
 199
 200 struct _vcs_dpi_ip_params_st dcn3_15_ip = {
 201         .gpuvm_enable = 1,
 202         .gpuvm_max_page_table_levels = 1,
 203         .hostvm_enable = 1,
 204         .hostvm_max_page_table_levels = 2,
 205         .rob_buffer_size_kbytes = 64,
 206         .det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE,
 207         .min_comp_buffer_size_kbytes = 64,
 208         .config_return_buffer_size_in_kbytes = 1024,
 209         .compressed_buffer_segment_size_in_kbytes = 64,
 210         .meta_fifo_size_in_kentries = 32,
 211         .zero_size_buffer_entries = 512,
 212         .compbuf_reserved_space_64b = 256,
 213         .compbuf_reserved_space_zs = 64,
 214         .dpp_output_buffer_pixels = 2560,
 215         .opp_output_buffer_lines = 1,
 216         .pixel_chunk_size_kbytes = 8,
 217         .meta_chunk_size_kbytes = 2,
 218         .min_meta_chunk_size_bytes = 256,
 219         .writeback_chunk_size_kbytes = 8,
 220         .ptoi_supported = false,
 221         .num_dsc = 3,
 222         .maximum_dsc_bits_per_component = 10,
 223         .dsc422_native_support = false,
 224         .is_line_buffer_bpp_fixed = true,
 225         .line_buffer_fixed_bpp = 49,
 226         .line_buffer_size_bits = 789504,
 227         .max_line_buffer_lines = 12,
 228         .writeback_interface_buffer_size_kbytes = 90,
 229         .max_num_dpp = 4,
 230         .max_num_otg = 4,
 231         .max_num_hdmi_frl_outputs = 1,
 232         .max_num_wb = 1,
 233         .max_dchub_pscl_bw_pix_per_clk = 4,
 234         .max_pscl_lb_bw_pix_per_clk = 2,
 235         .max_lb_vscl_bw_pix_per_clk = 4,
 236         .max_vscl_hscl_bw_pix_per_clk = 4,
 237         .max_hscl_ratio = 6,
 238         .max_vscl_ratio = 6,
 239         .max_hscl_taps = 8,
 240         .max_vscl_taps = 8,
 241         .dpte_buffer_size_in_pte_reqs_luma = 64,
 242         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 243         .dispclk_ramp_margin_percent = 1,
 244         .max_inter_dcn_tile_repeaters = 9,
 245         .cursor_buffer_size = 16,
 246         .cursor_chunk_size = 2,
 247         .writeback_line_buffer_buffer_size = 0,
 248         .writeback_min_hscl_ratio = 1,
 249         .writeback_min_vscl_ratio = 1,
 250         .writeback_max_hscl_ratio = 1,
 251         .writeback_max_vscl_ratio = 1,
 252         .writeback_max_hscl_taps = 1,
 253         .writeback_max_vscl_taps = 1,
 254         .dppclk_delay_subtotal = 46,
 255         .dppclk_delay_scl = 50,
 256         .dppclk_delay_scl_lb_only = 16,
 257         .dppclk_delay_cnvc_formatter = 27,
 258         .dppclk_delay_cnvc_cursor = 6,
 259         .dispclk_delay_subtotal = 119,
 260         .dynamic_metadata_vm_enabled = false,
 261         .odm_combine_4to1_supported = false,
 262         .dcc_supported = true,
 263 };
 264
 265 static struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = {
 266         .sr_exit_time_us = 9.0,
 267         .sr_enter_plus_exit_time_us = 11.0,
 268         .sr_exit_z8_time_us = 50.0,
 269         .sr_enter_plus_exit_z8_time_us = 50.0,
 270         .writeback_latency_us = 12.0,
 271         .dram_channel_width_bytes = 4,
 272         .round_trip_ping_latency_dcfclk_cycles = 106,
 273         .urgent_latency_pixel_data_only_us = 4.0,
 274         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 275         .urgent_latency_vm_data_only_us = 4.0,
 276         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 277         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 278         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 279         .pct_ideal_sdp_bw_after_urgent = 80.0,
 280         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 281         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 282         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 283         .max_avg_sdp_bw_use_normal_percent = 60.0,
 284         .max_avg_dram_bw_use_normal_percent = 60.0,
 285         .fabric_datapath_to_dcn_data_return_bytes = 32,
 286         .return_bus_width_bytes = 64,
 287         .downspread_percent = 0.38,
 288         .dcn_downspread_percent = 0.38,
 289         .gpuvm_min_page_size_bytes = 4096,
 290         .hostvm_min_page_size_bytes = 4096,
 291         .do_urgent_latency_adjustment = false,
 292         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 293         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 294 };
 295
 296 struct _vcs_dpi_ip_params_st dcn3_16_ip = {
 297         .gpuvm_enable = 1,
 298         .gpuvm_max_page_table_levels = 1,
 299         .hostvm_enable = 1,
 300         .hostvm_max_page_table_levels = 2,
 301         .rob_buffer_size_kbytes = 64,
 302         .det_buffer_size_kbytes = DCN3_16_DEFAULT_DET_SIZE,
 303         .min_comp_buffer_size_kbytes = 64,
 304         .config_return_buffer_size_in_kbytes = 1024,
 305         .compressed_buffer_segment_size_in_kbytes = 64,
 306         .meta_fifo_size_in_kentries = 32,
 307         .zero_size_buffer_entries = 512,
 308         .compbuf_reserved_space_64b = 256,
 309         .compbuf_reserved_space_zs = 64,
 310         .dpp_output_buffer_pixels = 2560,
 311         .opp_output_buffer_lines = 1,
 312         .pixel_chunk_size_kbytes = 8,
 313         .meta_chunk_size_kbytes = 2,
 314         .min_meta_chunk_size_bytes = 256,
 315         .writeback_chunk_size_kbytes = 8,
 316         .ptoi_supported = false,
 317         .num_dsc = 3,
 318         .maximum_dsc_bits_per_component = 10,
 319         .dsc422_native_support = false,
 320         .is_line_buffer_bpp_fixed = true,
 321         .line_buffer_fixed_bpp = 48,
 322         .line_buffer_size_bits = 789504,
 323         .max_line_buffer_lines = 12,
 324         .writeback_interface_buffer_size_kbytes = 90,
 325         .max_num_dpp = 4,
 326         .max_num_otg = 4,
 327         .max_num_hdmi_frl_outputs = 1,
 328         .max_num_wb = 1,
 329         .max_dchub_pscl_bw_pix_per_clk = 4,
 330         .max_pscl_lb_bw_pix_per_clk = 2,
 331         .max_lb_vscl_bw_pix_per_clk = 4,
 332         .max_vscl_hscl_bw_pix_per_clk = 4,
 333         .max_hscl_ratio = 6,
 334         .max_vscl_ratio = 6,
 335         .max_hscl_taps = 8,
 336         .max_vscl_taps = 8,
 337         .dpte_buffer_size_in_pte_reqs_luma = 64,
 338         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 339         .dispclk_ramp_margin_percent = 1,
 340         .max_inter_dcn_tile_repeaters = 8,
 341         .cursor_buffer_size = 16,
 342         .cursor_chunk_size = 2,
 343         .writeback_line_buffer_buffer_size = 0,
 344         .writeback_min_hscl_ratio = 1,
 345         .writeback_min_vscl_ratio = 1,
 346         .writeback_max_hscl_ratio = 1,
 347         .writeback_max_vscl_ratio = 1,
 348         .writeback_max_hscl_taps = 1,
 349         .writeback_max_vscl_taps = 1,
 350         .dppclk_delay_subtotal = 46,
 351         .dppclk_delay_scl = 50,
 352         .dppclk_delay_scl_lb_only = 16,
 353         .dppclk_delay_cnvc_formatter = 27,
 354         .dppclk_delay_cnvc_cursor = 6,
 355         .dispclk_delay_subtotal = 119,
 356         .dynamic_metadata_vm_enabled = false,
 357         .odm_combine_4to1_supported = false,
 358         .dcc_supported = true,
 359 };
 360
 361 static struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
 362                 /*TODO: correct dispclk/dppclk voltage level determination*/
 363         .clock_limits = {
 364                 {
 365                         .state = 0,
 366                         .dispclk_mhz = 556.0,
 367                         .dppclk_mhz = 556.0,
 368                         .phyclk_mhz = 600.0,
 369                         .phyclk_d18_mhz = 445.0,
 370                         .dscclk_mhz = 186.0,
 371                         .dtbclk_mhz = 625.0,
 372                 },
 373                 {
 374                         .state = 1,
 375                         .dispclk_mhz = 625.0,
 376                         .dppclk_mhz = 625.0,
 377                         .phyclk_mhz = 810.0,
 378                         .phyclk_d18_mhz = 667.0,
 379                         .dscclk_mhz = 209.0,
 380                         .dtbclk_mhz = 625.0,
 381                 },
 382                 {
 383                         .state = 2,
 384                         .dispclk_mhz = 625.0,
 385                         .dppclk_mhz = 625.0,
 386                         .phyclk_mhz = 810.0,
 387                         .phyclk_d18_mhz = 667.0,
 388                         .dscclk_mhz = 209.0,
 389                         .dtbclk_mhz = 625.0,
 390                 },
 391                 {
 392                         .state = 3,
 393                         .dispclk_mhz = 1112.0,
 394                         .dppclk_mhz = 1112.0,
 395                         .phyclk_mhz = 810.0,
 396                         .phyclk_d18_mhz = 667.0,
 397                         .dscclk_mhz = 371.0,
 398                         .dtbclk_mhz = 625.0,
 399                 },
 400                 {
 401                         .state = 4,
 402                         .dispclk_mhz = 1250.0,
 403                         .dppclk_mhz = 1250.0,
 404                         .phyclk_mhz = 810.0,
 405                         .phyclk_d18_mhz = 667.0,
 406                         .dscclk_mhz = 417.0,
 407                         .dtbclk_mhz = 625.0,
 408                 },
 409         },
 410         .num_states = 5,
 411         .sr_exit_time_us = 9.0,
 412         .sr_enter_plus_exit_time_us = 11.0,
 413         .sr_exit_z8_time_us = 442.0,
 414         .sr_enter_plus_exit_z8_time_us = 560.0,
 415         .writeback_latency_us = 12.0,
 416         .dram_channel_width_bytes = 4,
 417         .round_trip_ping_latency_dcfclk_cycles = 106,
 418         .urgent_latency_pixel_data_only_us = 4.0,
 419         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 420         .urgent_latency_vm_data_only_us = 4.0,
 421         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 422         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 423         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 424         .pct_ideal_sdp_bw_after_urgent = 80.0,
 425         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 426         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 427         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 428         .max_avg_sdp_bw_use_normal_percent = 60.0,
 429         .max_avg_dram_bw_use_normal_percent = 60.0,
 430         .fabric_datapath_to_dcn_data_return_bytes = 32,
 431         .return_bus_width_bytes = 64,
 432         .downspread_percent = 0.38,
 433         .dcn_downspread_percent = 0.5,
 434         .gpuvm_min_page_size_bytes = 4096,
 435         .hostvm_min_page_size_bytes = 4096,
 436         .do_urgent_latency_adjustment = false,
 437         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 438         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 439 };
 440
 441 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
 442                                   int pipe_cnt)
 443 {
 444         dc_assert_fp_enabled();
 445
 446         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
 447         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
 448 }
 449
 450 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
 451 {
 452         dc_assert_fp_enabled();
 453
 454         if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
 455                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
 456                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
 457                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
 458         }
 459 }
 460
 461 void dcn31_calculate_wm_and_dlg_fp(
 462                 struct dc *dc, struct dc_state *context,
 463                 display_e2e_pipe_params_st *pipes,
 464                 int pipe_cnt,
 465                 int vlevel)
 466 {
 467         int i, pipe_idx;
 468         double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 469
 470         dc_assert_fp_enabled();
 471
 472         if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
 473                 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
 474
 475         /* We don't recalculate clocks for 0 pipe configs, which can block
 476          * S0i3 as high clocks will block low power states
 477          * Override any clocks that can block S0i3 to min here
 478          */
 479         if (pipe_cnt == 0) {
 480                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0
 481                 return;
 482         }
 483
 484         pipes[0].clks_cfg.voltage = vlevel;
 485         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 486         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
 487
 488 #if 0 // TODO
 489         /* Set B:
 490          * TODO
 491          */
 492         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
 493                 if (vlevel == 0) {
 494                         pipes[0].clks_cfg.voltage = 1;
 495                         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
 496                 }
 497                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
 498                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
 499                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
 500         }
 501         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 502         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 503         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 504         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 505         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 506         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 507         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 508         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 509         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 510         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 511
 512         pipes[0].clks_cfg.voltage = vlevel;
 513         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 514
 515         /* Set C:
 516          * TODO
 517          */
 518         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
 519                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
 520                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
 521                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
 522         }
 523         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 524         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 525         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 526         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 527         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 528         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 529         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 530         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 531         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 532         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 533
 534         /* Set D:
 535          * TODO
 536          */
 537         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
 538                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
 539                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
 540                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
 541         }
 542         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 543         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 544         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 545         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 546         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 547         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 548         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 549         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 550         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 551         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 552 #endif
 553
 554         /* Set A:
 555          * All clocks min required
 556          *
 557          * Set A calculated last so that following calculations are based on Set A
 558          */
 559         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
 560         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 561         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 562         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 563         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 564         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 565         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 566         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 567         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 568         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 569         context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 570         /* TODO: remove: */
 571         context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
 572         context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
 573         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
 574         /* end remove*/
 575
 576         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 577                 if (!context->res_ctx.pipe_ctx[i].stream)
 578                         continue;
 579
 580                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
 581                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 582
 583                 if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
 584                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
 585                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
 586                 }
 587                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
 588                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
 589                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
 590                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
 591
 592                 pipe_idx++;
 593         }
 594
 595         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
 596 }
 597
 598 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 599 {
 600         struct clk_limit_table *clk_table = &bw_params->clk_table;
 601         unsigned int i, closest_clk_lvl;
 602         int j;
 603
 604         dc_assert_fp_enabled();
 605
 606         memcpy(&dcn3_1_soc._clock_tmp, &dcn3_1_soc.clock_limits,
 607                sizeof(dcn3_1_soc.clock_limits));
 608
 609         // Default clock levels are used for diags, which may lead to overclocking.
 610         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 611                 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 612
 613                 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
 614                 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
 615                 dcn3_1_soc.num_chans = bw_params->num_channels;
 616
 617                 ASSERT(clk_table->num_entries);
 618
 619                 /* Prepass to find max clocks independent of voltage level. */
 620                 for (i = 0; i < clk_table->num_entries; ++i) {
 621                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
 622                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
 623                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
 624                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
 625                 }
 626
 627                 for (i = 0; i < clk_table->num_entries; i++) {
 628                         /* loop backwards*/
 629                         for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
 630                                 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
 631                                         closest_clk_lvl = j;
 632                                         break;
 633                                 }
 634                         }
 635
 636                         dcn3_1_soc._clock_tmp[i].state = i;
 637
 638                         /* Clocks dependent on voltage level. */
 639                         dcn3_1_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 640                         dcn3_1_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
 641                         dcn3_1_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
 642                         dcn3_1_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 643
 644                         /* Clocks independent of voltage level. */
 645                         dcn3_1_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 646                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 647
 648                         dcn3_1_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 649                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 650
 651                         dcn3_1_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
 652                         dcn3_1_soc._clock_tmp[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
 653                         dcn3_1_soc._clock_tmp[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
 654                         dcn3_1_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
 655                         dcn3_1_soc._clock_tmp[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 656                 }
 657                 if (clk_table->num_entries) {
 658                         dcn3_1_soc.num_states = clk_table->num_entries;
 659                 }
 660         }
 661
 662         memcpy(&dcn3_1_soc.clock_limits, &dcn3_1_soc._clock_tmp,
 663                sizeof(dcn3_1_soc.clock_limits));
 664
 665         dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 666         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 667
 668         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 669                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
 670         else
 671                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
 672 }
 673
 674 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 675 {
 676         struct clk_limit_table *clk_table = &bw_params->clk_table;
 677         int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 678
 679         dc_assert_fp_enabled();
 680
 681         dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
 682         dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;
 683         dcn3_15_soc.num_chans = bw_params->num_channels;
 684
 685         ASSERT(clk_table->num_entries);
 686
 687         /* Setup soc to always use max dispclk/dppclk to avoid odm-to-lower-voltage */
 688         for (i = 0; i < clk_table->num_entries; ++i) {
 689                 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
 690                         max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
 691                 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
 692                         max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
 693         }
 694
 695         for (i = 0; i < clk_table->num_entries; i++) {
 696                 dcn3_15_soc.clock_limits[i].state = i;
 697
 698                 /* Clocks dependent on voltage level. */
 699                 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 700                 dcn3_15_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
 701                 dcn3_15_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
 702                 dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 703
 704                 /* These aren't actually read from smu, but rather set in clk_mgr defaults */
 705                 dcn3_15_soc.clock_limits[i].dtbclk_mhz = clk_table->entries[i].dtbclk_mhz;
 706                 dcn3_15_soc.clock_limits[i].phyclk_d18_mhz = clk_table->entries[i].phyclk_d18_mhz;
 707                 dcn3_15_soc.clock_limits[i].phyclk_mhz = clk_table->entries[i].phyclk_mhz;
 708
 709                 /* Clocks independent of voltage level. */
 710                 dcn3_15_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
 711                 dcn3_15_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
 712                 dcn3_15_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3.0;
 713         }
 714         dcn3_15_soc.num_states = clk_table->num_entries;
 715
 716
 717         /* Set vco to max_dispclk * 2 to make sure the highest dispclk is always available for dml calcs,
 718          * no impact outside of dml validation
 719          */
 720         dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 721
 722         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 723                 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31);
 724         else
 725                 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31_FPGA);
 726 }
 727
 728 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 729 {
 730         struct clk_limit_table *clk_table = &bw_params->clk_table;
 731         unsigned int i, closest_clk_lvl;
 732         int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 733         int j;
 734
 735         dc_assert_fp_enabled();
 736
 737         memcpy(&dcn3_16_soc._clock_tmp, &dcn3_16_soc.clock_limits,
 738                sizeof(dcn3_16_soc.clock_limits));
 739
 740         // Default clock levels are used for diags, which may lead to overclocking.
 741         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 742
 743                 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
 744                 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count;
 745                 dcn3_16_soc.num_chans = bw_params->num_channels;
 746
 747                 ASSERT(clk_table->num_entries);
 748
 749                 /* Prepass to find max clocks independent of voltage level. */
 750                 for (i = 0; i < clk_table->num_entries; ++i) {
 751                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
 752                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
 753                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
 754                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
 755                 }
 756
 757                 for (i = 0; i < clk_table->num_entries; i++) {
 758                         /* loop backwards*/
 759                         for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) {
 760                                 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
 761                                         closest_clk_lvl = j;
 762                                         break;
 763                                 }
 764                         }
 765                         // Ported from DCN315
 766                         if (clk_table->num_entries == 1) {
 767                                 /*smu gives one DPM level, let's take the highest one*/
 768                                 closest_clk_lvl = dcn3_16_soc.num_states - 1;
 769                         }
 770
 771                         dcn3_16_soc._clock_tmp[i].state = i;
 772
 773                         /* Clocks dependent on voltage level. */
 774                         dcn3_16_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 775                         if (clk_table->num_entries == 1 &&
 776                             dcn3_16_soc._clock_tmp[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
 777                                 /*SMU fix not released yet*/
 778                                 dcn3_16_soc._clock_tmp[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
 779                         }
 780                         dcn3_16_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
 781                         dcn3_16_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
 782                         dcn3_16_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 783
 784                         /* Clocks independent of voltage level. */
 785                         dcn3_16_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 786                                 dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 787
 788                         dcn3_16_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 789                                 dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 790
 791                         dcn3_16_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
 792                         dcn3_16_soc._clock_tmp[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
 793                         dcn3_16_soc._clock_tmp[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
 794                         dcn3_16_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
 795                         dcn3_16_soc._clock_tmp[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 796                 }
 797                 if (clk_table->num_entries) {
 798                         dcn3_16_soc.num_states = clk_table->num_entries;
 799                 }
 800         }
 801
 802         memcpy(&dcn3_16_soc.clock_limits, &dcn3_16_soc._clock_tmp,
 803                sizeof(dcn3_16_soc.clock_limits));
 804
 805         if (max_dispclk_mhz) {
 806                 dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 807                 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 808         }
 809
 810         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 811                 dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31);
 812         else
 813                 dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31_FPGA);
 814 }