drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2021 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "resource.h"
  28 #include "clk_mgr.h"
  29 #include "dc_link_dp.h"
  30 #include "dchubbub.h"
  31 #include "dcn20/dcn20_resource.h"
  32 #include "dcn21/dcn21_resource.h"
  33
  34 #include "dcn20_fpu.h"
  35
  36 #define DC_LOGGER_INIT(logger)
  37
  38 #ifndef MAX
  39 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
  40 #endif
  41 #ifndef MIN
  42 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
  43 #endif
  44
  45 /* Constant */
  46 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
  47
  48 /**
  49  * DOC: DCN2x FPU manipulation Overview
  50  *
  51  * The DCN architecture relies on FPU operations, which require special
  52  * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
  53  * want to avoid spreading FPU access across multiple files. With this idea in
  54  * mind, this file aims to centralize all DCN20 and DCN2.1 (DCN2x) functions
  55  * that require FPU access in a single place. Code in this file follows the
  56  * following code pattern:
  57  *
  58  * 1. Functions that use FPU operations should be isolated in static functions.
  59  * 2. The FPU functions should have the noinline attribute to ensure anything
  60  *    that deals with FP register is contained within this call.
  61  * 3. All function that needs to be accessed outside this file requires a
  62  *    public interface that not uses any FPU reference.
  63  * 4. Developers **must not** use DC_FP_START/END in this file, but they need
  64  *    to ensure that the caller invokes it before access any function available
  65  *    in this file. For this reason, public functions in this file must invoke
  66  *    dc_assert_fp_enabled();
  67  *
  68  * Let's expand a little bit more the idea in the code pattern. To fully
  69  * isolate FPU operations in a single place, we must avoid situations where
  70  * compilers spill FP values to registers due to FP enable in a specific C
  71  * file. Note that even if we isolate all FPU functions in a single file and
  72  * call its interface from other files, the compiler might enable the use of
  73  * FPU before we call DC_FP_START. Nevertheless, it is the programmer's
  74  * responsibility to invoke DC_FP_START/END in the correct place. To highlight
  75  * situations where developers forgot to use the FP protection before calling
  76  * the DC FPU interface functions, we introduce a helper that checks if the
  77  * function is invoked under FP protection. If not, it will trigger a kernel
  78  * warning.
  79  */
  80
  81 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
  82         .odm_capable = 1,
  83         .gpuvm_enable = 0,
  84         .hostvm_enable = 0,
  85         .gpuvm_max_page_table_levels = 4,
  86         .hostvm_max_page_table_levels = 4,
  87         .hostvm_cached_page_table_levels = 0,
  88         .pte_group_size_bytes = 2048,
  89         .num_dsc = 6,
  90         .rob_buffer_size_kbytes = 168,
  91         .det_buffer_size_kbytes = 164,
  92         .dpte_buffer_size_in_pte_reqs_luma = 84,
  93         .pde_proc_buffer_size_64k_reqs = 48,
  94         .dpp_output_buffer_pixels = 2560,
  95         .opp_output_buffer_lines = 1,
  96         .pixel_chunk_size_kbytes = 8,
  97         .pte_chunk_size_kbytes = 2,
  98         .meta_chunk_size_kbytes = 2,
  99         .writeback_chunk_size_kbytes = 2,
 100         .line_buffer_size_bits = 789504,
 101         .is_line_buffer_bpp_fixed = 0,
 102         .line_buffer_fixed_bpp = 0,
 103         .dcc_supported = true,
 104         .max_line_buffer_lines = 12,
 105         .writeback_luma_buffer_size_kbytes = 12,
 106         .writeback_chroma_buffer_size_kbytes = 8,
 107         .writeback_chroma_line_buffer_width_pixels = 4,
 108         .writeback_max_hscl_ratio = 1,
 109         .writeback_max_vscl_ratio = 1,
 110         .writeback_min_hscl_ratio = 1,
 111         .writeback_min_vscl_ratio = 1,
 112         .writeback_max_hscl_taps = 12,
 113         .writeback_max_vscl_taps = 12,
 114         .writeback_line_buffer_luma_buffer_size = 0,
 115         .writeback_line_buffer_chroma_buffer_size = 14643,
 116         .cursor_buffer_size = 8,
 117         .cursor_chunk_size = 2,
 118         .max_num_otg = 6,
 119         .max_num_dpp = 6,
 120         .max_num_wb = 1,
 121         .max_dchub_pscl_bw_pix_per_clk = 4,
 122         .max_pscl_lb_bw_pix_per_clk = 2,
 123         .max_lb_vscl_bw_pix_per_clk = 4,
 124         .max_vscl_hscl_bw_pix_per_clk = 4,
 125         .max_hscl_ratio = 8,
 126         .max_vscl_ratio = 8,
 127         .hscl_mults = 4,
 128         .vscl_mults = 4,
 129         .max_hscl_taps = 8,
 130         .max_vscl_taps = 8,
 131         .dispclk_ramp_margin_percent = 1,
 132         .underscan_factor = 1.10,
 133         .min_vblank_lines = 32, //
 134         .dppclk_delay_subtotal = 77, //
 135         .dppclk_delay_scl_lb_only = 16,
 136         .dppclk_delay_scl = 50,
 137         .dppclk_delay_cnvc_formatter = 8,
 138         .dppclk_delay_cnvc_cursor = 6,
 139         .dispclk_delay_subtotal = 87, //
 140         .dcfclk_cstate_latency = 10, // SRExitTime
 141         .max_inter_dcn_tile_repeaters = 8,
 142         .xfc_supported = true,
 143         .xfc_fill_bw_overhead_percent = 10.0,
 144         .xfc_fill_constant_bytes = 0,
 145         .number_of_cursors = 1,
 146 };
 147
 148 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
 149         .odm_capable = 1,
 150         .gpuvm_enable = 0,
 151         .hostvm_enable = 0,
 152         .gpuvm_max_page_table_levels = 4,
 153         .hostvm_max_page_table_levels = 4,
 154         .hostvm_cached_page_table_levels = 0,
 155         .num_dsc = 5,
 156         .rob_buffer_size_kbytes = 168,
 157         .det_buffer_size_kbytes = 164,
 158         .dpte_buffer_size_in_pte_reqs_luma = 84,
 159         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 160         .dpp_output_buffer_pixels = 2560,
 161         .opp_output_buffer_lines = 1,
 162         .pixel_chunk_size_kbytes = 8,
 163         .pte_enable = 1,
 164         .max_page_table_levels = 4,
 165         .pte_chunk_size_kbytes = 2,
 166         .meta_chunk_size_kbytes = 2,
 167         .writeback_chunk_size_kbytes = 2,
 168         .line_buffer_size_bits = 789504,
 169         .is_line_buffer_bpp_fixed = 0,
 170         .line_buffer_fixed_bpp = 0,
 171         .dcc_supported = true,
 172         .max_line_buffer_lines = 12,
 173         .writeback_luma_buffer_size_kbytes = 12,
 174         .writeback_chroma_buffer_size_kbytes = 8,
 175         .writeback_chroma_line_buffer_width_pixels = 4,
 176         .writeback_max_hscl_ratio = 1,
 177         .writeback_max_vscl_ratio = 1,
 178         .writeback_min_hscl_ratio = 1,
 179         .writeback_min_vscl_ratio = 1,
 180         .writeback_max_hscl_taps = 12,
 181         .writeback_max_vscl_taps = 12,
 182         .writeback_line_buffer_luma_buffer_size = 0,
 183         .writeback_line_buffer_chroma_buffer_size = 14643,
 184         .cursor_buffer_size = 8,
 185         .cursor_chunk_size = 2,
 186         .max_num_otg = 5,
 187         .max_num_dpp = 5,
 188         .max_num_wb = 1,
 189         .max_dchub_pscl_bw_pix_per_clk = 4,
 190         .max_pscl_lb_bw_pix_per_clk = 2,
 191         .max_lb_vscl_bw_pix_per_clk = 4,
 192         .max_vscl_hscl_bw_pix_per_clk = 4,
 193         .max_hscl_ratio = 8,
 194         .max_vscl_ratio = 8,
 195         .hscl_mults = 4,
 196         .vscl_mults = 4,
 197         .max_hscl_taps = 8,
 198         .max_vscl_taps = 8,
 199         .dispclk_ramp_margin_percent = 1,
 200         .underscan_factor = 1.10,
 201         .min_vblank_lines = 32, //
 202         .dppclk_delay_subtotal = 77, //
 203         .dppclk_delay_scl_lb_only = 16,
 204         .dppclk_delay_scl = 50,
 205         .dppclk_delay_cnvc_formatter = 8,
 206         .dppclk_delay_cnvc_cursor = 6,
 207         .dispclk_delay_subtotal = 87, //
 208         .dcfclk_cstate_latency = 10, // SRExitTime
 209         .max_inter_dcn_tile_repeaters = 8,
 210         .xfc_supported = true,
 211         .xfc_fill_bw_overhead_percent = 10.0,
 212         .xfc_fill_constant_bytes = 0,
 213         .ptoi_supported = 0,
 214         .number_of_cursors = 1,
 215 };
 216
 217 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
 218         /* Defaults that get patched on driver load from firmware. */
 219         .clock_limits = {
 220                         {
 221                                 .state = 0,
 222                                 .dcfclk_mhz = 560.0,
 223                                 .fabricclk_mhz = 560.0,
 224                                 .dispclk_mhz = 513.0,
 225                                 .dppclk_mhz = 513.0,
 226                                 .phyclk_mhz = 540.0,
 227                                 .socclk_mhz = 560.0,
 228                                 .dscclk_mhz = 171.0,
 229                                 .dram_speed_mts = 8960.0,
 230                         },
 231                         {
 232                                 .state = 1,
 233                                 .dcfclk_mhz = 694.0,
 234                                 .fabricclk_mhz = 694.0,
 235                                 .dispclk_mhz = 642.0,
 236                                 .dppclk_mhz = 642.0,
 237                                 .phyclk_mhz = 600.0,
 238                                 .socclk_mhz = 694.0,
 239                                 .dscclk_mhz = 214.0,
 240                                 .dram_speed_mts = 11104.0,
 241                         },
 242                         {
 243                                 .state = 2,
 244                                 .dcfclk_mhz = 875.0,
 245                                 .fabricclk_mhz = 875.0,
 246                                 .dispclk_mhz = 734.0,
 247                                 .dppclk_mhz = 734.0,
 248                                 .phyclk_mhz = 810.0,
 249                                 .socclk_mhz = 875.0,
 250                                 .dscclk_mhz = 245.0,
 251                                 .dram_speed_mts = 14000.0,
 252                         },
 253                         {
 254                                 .state = 3,
 255                                 .dcfclk_mhz = 1000.0,
 256                                 .fabricclk_mhz = 1000.0,
 257                                 .dispclk_mhz = 1100.0,
 258                                 .dppclk_mhz = 1100.0,
 259                                 .phyclk_mhz = 810.0,
 260                                 .socclk_mhz = 1000.0,
 261                                 .dscclk_mhz = 367.0,
 262                                 .dram_speed_mts = 16000.0,
 263                         },
 264                         {
 265                                 .state = 4,
 266                                 .dcfclk_mhz = 1200.0,
 267                                 .fabricclk_mhz = 1200.0,
 268                                 .dispclk_mhz = 1284.0,
 269                                 .dppclk_mhz = 1284.0,
 270                                 .phyclk_mhz = 810.0,
 271                                 .socclk_mhz = 1200.0,
 272                                 .dscclk_mhz = 428.0,
 273                                 .dram_speed_mts = 16000.0,
 274                         },
 275                         /*Extra state, no dispclk ramping*/
 276                         {
 277                                 .state = 5,
 278                                 .dcfclk_mhz = 1200.0,
 279                                 .fabricclk_mhz = 1200.0,
 280                                 .dispclk_mhz = 1284.0,
 281                                 .dppclk_mhz = 1284.0,
 282                                 .phyclk_mhz = 810.0,
 283                                 .socclk_mhz = 1200.0,
 284                                 .dscclk_mhz = 428.0,
 285                                 .dram_speed_mts = 16000.0,
 286                         },
 287                 },
 288         .num_states = 5,
 289         .sr_exit_time_us = 8.6,
 290         .sr_enter_plus_exit_time_us = 10.9,
 291         .urgent_latency_us = 4.0,
 292         .urgent_latency_pixel_data_only_us = 4.0,
 293         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 294         .urgent_latency_vm_data_only_us = 4.0,
 295         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 296         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 297         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 298         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 299         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 300         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 301         .max_avg_sdp_bw_use_normal_percent = 40.0,
 302         .max_avg_dram_bw_use_normal_percent = 40.0,
 303         .writeback_latency_us = 12.0,
 304         .ideal_dram_bw_after_urgent_percent = 40.0,
 305         .max_request_size_bytes = 256,
 306         .dram_channel_width_bytes = 2,
 307         .fabric_datapath_to_dcn_data_return_bytes = 64,
 308         .dcn_downspread_percent = 0.5,
 309         .downspread_percent = 0.38,
 310         .dram_page_open_time_ns = 50.0,
 311         .dram_rw_turnaround_time_ns = 17.5,
 312         .dram_return_buffer_per_channel_bytes = 8192,
 313         .round_trip_ping_latency_dcfclk_cycles = 131,
 314         .urgent_out_of_order_return_per_channel_bytes = 256,
 315         .channel_interleave_bytes = 256,
 316         .num_banks = 8,
 317         .num_chans = 16,
 318         .vmm_page_size_bytes = 4096,
 319         .dram_clock_change_latency_us = 404.0,
 320         .dummy_pstate_latency_us = 5.0,
 321         .writeback_dram_clock_change_latency_us = 23.0,
 322         .return_bus_width_bytes = 64,
 323         .dispclk_dppclk_vco_speed_mhz = 3850,
 324         .xfc_bus_transport_time_us = 20,
 325         .xfc_xbuf_latency_tolerance_us = 4,
 326         .use_urgent_burst_bw = 0
 327 };
 328
 329 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
 330         .clock_limits = {
 331                         {
 332                                 .state = 0,
 333                                 .dcfclk_mhz = 560.0,
 334                                 .fabricclk_mhz = 560.0,
 335                                 .dispclk_mhz = 513.0,
 336                                 .dppclk_mhz = 513.0,
 337                                 .phyclk_mhz = 540.0,
 338                                 .socclk_mhz = 560.0,
 339                                 .dscclk_mhz = 171.0,
 340                                 .dram_speed_mts = 8960.0,
 341                         },
 342                         {
 343                                 .state = 1,
 344                                 .dcfclk_mhz = 694.0,
 345                                 .fabricclk_mhz = 694.0,
 346                                 .dispclk_mhz = 642.0,
 347                                 .dppclk_mhz = 642.0,
 348                                 .phyclk_mhz = 600.0,
 349                                 .socclk_mhz = 694.0,
 350                                 .dscclk_mhz = 214.0,
 351                                 .dram_speed_mts = 11104.0,
 352                         },
 353                         {
 354                                 .state = 2,
 355                                 .dcfclk_mhz = 875.0,
 356                                 .fabricclk_mhz = 875.0,
 357                                 .dispclk_mhz = 734.0,
 358                                 .dppclk_mhz = 734.0,
 359                                 .phyclk_mhz = 810.0,
 360                                 .socclk_mhz = 875.0,
 361                                 .dscclk_mhz = 245.0,
 362                                 .dram_speed_mts = 14000.0,
 363                         },
 364                         {
 365                                 .state = 3,
 366                                 .dcfclk_mhz = 1000.0,
 367                                 .fabricclk_mhz = 1000.0,
 368                                 .dispclk_mhz = 1100.0,
 369                                 .dppclk_mhz = 1100.0,
 370                                 .phyclk_mhz = 810.0,
 371                                 .socclk_mhz = 1000.0,
 372                                 .dscclk_mhz = 367.0,
 373                                 .dram_speed_mts = 16000.0,
 374                         },
 375                         {
 376                                 .state = 4,
 377                                 .dcfclk_mhz = 1200.0,
 378                                 .fabricclk_mhz = 1200.0,
 379                                 .dispclk_mhz = 1284.0,
 380                                 .dppclk_mhz = 1284.0,
 381                                 .phyclk_mhz = 810.0,
 382                                 .socclk_mhz = 1200.0,
 383                                 .dscclk_mhz = 428.0,
 384                                 .dram_speed_mts = 16000.0,
 385                         },
 386                         /*Extra state, no dispclk ramping*/
 387                         {
 388                                 .state = 5,
 389                                 .dcfclk_mhz = 1200.0,
 390                                 .fabricclk_mhz = 1200.0,
 391                                 .dispclk_mhz = 1284.0,
 392                                 .dppclk_mhz = 1284.0,
 393                                 .phyclk_mhz = 810.0,
 394                                 .socclk_mhz = 1200.0,
 395                                 .dscclk_mhz = 428.0,
 396                                 .dram_speed_mts = 16000.0,
 397                         },
 398                 },
 399         .num_states = 5,
 400         .sr_exit_time_us = 11.6,
 401         .sr_enter_plus_exit_time_us = 13.9,
 402         .urgent_latency_us = 4.0,
 403         .urgent_latency_pixel_data_only_us = 4.0,
 404         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 405         .urgent_latency_vm_data_only_us = 4.0,
 406         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 407         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 408         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 409         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 410         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 411         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 412         .max_avg_sdp_bw_use_normal_percent = 40.0,
 413         .max_avg_dram_bw_use_normal_percent = 40.0,
 414         .writeback_latency_us = 12.0,
 415         .ideal_dram_bw_after_urgent_percent = 40.0,
 416         .max_request_size_bytes = 256,
 417         .dram_channel_width_bytes = 2,
 418         .fabric_datapath_to_dcn_data_return_bytes = 64,
 419         .dcn_downspread_percent = 0.5,
 420         .downspread_percent = 0.38,
 421         .dram_page_open_time_ns = 50.0,
 422         .dram_rw_turnaround_time_ns = 17.5,
 423         .dram_return_buffer_per_channel_bytes = 8192,
 424         .round_trip_ping_latency_dcfclk_cycles = 131,
 425         .urgent_out_of_order_return_per_channel_bytes = 256,
 426         .channel_interleave_bytes = 256,
 427         .num_banks = 8,
 428         .num_chans = 8,
 429         .vmm_page_size_bytes = 4096,
 430         .dram_clock_change_latency_us = 404.0,
 431         .dummy_pstate_latency_us = 5.0,
 432         .writeback_dram_clock_change_latency_us = 23.0,
 433         .return_bus_width_bytes = 64,
 434         .dispclk_dppclk_vco_speed_mhz = 3850,
 435         .xfc_bus_transport_time_us = 20,
 436         .xfc_xbuf_latency_tolerance_us = 4,
 437         .use_urgent_burst_bw = 0
 438 };
 439
 440 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
 441
 442 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
 443         .odm_capable = 1,
 444         .gpuvm_enable = 1,
 445         .hostvm_enable = 1,
 446         .gpuvm_max_page_table_levels = 1,
 447         .hostvm_max_page_table_levels = 4,
 448         .hostvm_cached_page_table_levels = 2,
 449         .num_dsc = 3,
 450         .rob_buffer_size_kbytes = 168,
 451         .det_buffer_size_kbytes = 164,
 452         .dpte_buffer_size_in_pte_reqs_luma = 44,
 453         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 454         .dpp_output_buffer_pixels = 2560,
 455         .opp_output_buffer_lines = 1,
 456         .pixel_chunk_size_kbytes = 8,
 457         .pte_enable = 1,
 458         .max_page_table_levels = 4,
 459         .pte_chunk_size_kbytes = 2,
 460         .meta_chunk_size_kbytes = 2,
 461         .min_meta_chunk_size_bytes = 256,
 462         .writeback_chunk_size_kbytes = 2,
 463         .line_buffer_size_bits = 789504,
 464         .is_line_buffer_bpp_fixed = 0,
 465         .line_buffer_fixed_bpp = 0,
 466         .dcc_supported = true,
 467         .max_line_buffer_lines = 12,
 468         .writeback_luma_buffer_size_kbytes = 12,
 469         .writeback_chroma_buffer_size_kbytes = 8,
 470         .writeback_chroma_line_buffer_width_pixels = 4,
 471         .writeback_max_hscl_ratio = 1,
 472         .writeback_max_vscl_ratio = 1,
 473         .writeback_min_hscl_ratio = 1,
 474         .writeback_min_vscl_ratio = 1,
 475         .writeback_max_hscl_taps = 12,
 476         .writeback_max_vscl_taps = 12,
 477         .writeback_line_buffer_luma_buffer_size = 0,
 478         .writeback_line_buffer_chroma_buffer_size = 14643,
 479         .cursor_buffer_size = 8,
 480         .cursor_chunk_size = 2,
 481         .max_num_otg = 4,
 482         .max_num_dpp = 4,
 483         .max_num_wb = 1,
 484         .max_dchub_pscl_bw_pix_per_clk = 4,
 485         .max_pscl_lb_bw_pix_per_clk = 2,
 486         .max_lb_vscl_bw_pix_per_clk = 4,
 487         .max_vscl_hscl_bw_pix_per_clk = 4,
 488         .max_hscl_ratio = 4,
 489         .max_vscl_ratio = 4,
 490         .hscl_mults = 4,
 491         .vscl_mults = 4,
 492         .max_hscl_taps = 8,
 493         .max_vscl_taps = 8,
 494         .dispclk_ramp_margin_percent = 1,
 495         .underscan_factor = 1.10,
 496         .min_vblank_lines = 32, //
 497         .dppclk_delay_subtotal = 77, //
 498         .dppclk_delay_scl_lb_only = 16,
 499         .dppclk_delay_scl = 50,
 500         .dppclk_delay_cnvc_formatter = 8,
 501         .dppclk_delay_cnvc_cursor = 6,
 502         .dispclk_delay_subtotal = 87, //
 503         .dcfclk_cstate_latency = 10, // SRExitTime
 504         .max_inter_dcn_tile_repeaters = 8,
 505
 506         .xfc_supported = false,
 507         .xfc_fill_bw_overhead_percent = 10.0,
 508         .xfc_fill_constant_bytes = 0,
 509         .ptoi_supported = 0,
 510         .number_of_cursors = 1,
 511 };
 512
 513 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
 514         .clock_limits = {
 515                         {
 516                                 .state = 0,
 517                                 .dcfclk_mhz = 400.0,
 518                                 .fabricclk_mhz = 400.0,
 519                                 .dispclk_mhz = 600.0,
 520                                 .dppclk_mhz = 400.00,
 521                                 .phyclk_mhz = 600.0,
 522                                 .socclk_mhz = 278.0,
 523                                 .dscclk_mhz = 205.67,
 524                                 .dram_speed_mts = 1600.0,
 525                         },
 526                         {
 527                                 .state = 1,
 528                                 .dcfclk_mhz = 464.52,
 529                                 .fabricclk_mhz = 800.0,
 530                                 .dispclk_mhz = 654.55,
 531                                 .dppclk_mhz = 626.09,
 532                                 .phyclk_mhz = 600.0,
 533                                 .socclk_mhz = 278.0,
 534                                 .dscclk_mhz = 205.67,
 535                                 .dram_speed_mts = 1600.0,
 536                         },
 537                         {
 538                                 .state = 2,
 539                                 .dcfclk_mhz = 514.29,
 540                                 .fabricclk_mhz = 933.0,
 541                                 .dispclk_mhz = 757.89,
 542                                 .dppclk_mhz = 685.71,
 543                                 .phyclk_mhz = 600.0,
 544                                 .socclk_mhz = 278.0,
 545                                 .dscclk_mhz = 287.67,
 546                                 .dram_speed_mts = 1866.0,
 547                         },
 548                         {
 549                                 .state = 3,
 550                                 .dcfclk_mhz = 576.00,
 551                                 .fabricclk_mhz = 1067.0,
 552                                 .dispclk_mhz = 847.06,
 553                                 .dppclk_mhz = 757.89,
 554                                 .phyclk_mhz = 600.0,
 555                                 .socclk_mhz = 715.0,
 556                                 .dscclk_mhz = 318.334,
 557                                 .dram_speed_mts = 2134.0,
 558                         },
 559                         {
 560                                 .state = 4,
 561                                 .dcfclk_mhz = 626.09,
 562                                 .fabricclk_mhz = 1200.0,
 563                                 .dispclk_mhz = 900.00,
 564                                 .dppclk_mhz = 847.06,
 565                                 .phyclk_mhz = 810.0,
 566                                 .socclk_mhz = 953.0,
 567                                 .dscclk_mhz = 489.0,
 568                                 .dram_speed_mts = 2400.0,
 569                         },
 570                         {
 571                                 .state = 5,
 572                                 .dcfclk_mhz = 685.71,
 573                                 .fabricclk_mhz = 1333.0,
 574                                 .dispclk_mhz = 1028.57,
 575                                 .dppclk_mhz = 960.00,
 576                                 .phyclk_mhz = 810.0,
 577                                 .socclk_mhz = 278.0,
 578                                 .dscclk_mhz = 287.67,
 579                                 .dram_speed_mts = 2666.0,
 580                         },
 581                         {
 582                                 .state = 6,
 583                                 .dcfclk_mhz = 757.89,
 584                                 .fabricclk_mhz = 1467.0,
 585                                 .dispclk_mhz = 1107.69,
 586                                 .dppclk_mhz = 1028.57,
 587                                 .phyclk_mhz = 810.0,
 588                                 .socclk_mhz = 715.0,
 589                                 .dscclk_mhz = 318.334,
 590                                 .dram_speed_mts = 3200.0,
 591                         },
 592                         {
 593                                 .state = 7,
 594                                 .dcfclk_mhz = 847.06,
 595                                 .fabricclk_mhz = 1600.0,
 596                                 .dispclk_mhz = 1395.0,
 597                                 .dppclk_mhz = 1285.00,
 598                                 .phyclk_mhz = 1325.0,
 599                                 .socclk_mhz = 953.0,
 600                                 .dscclk_mhz = 489.0,
 601                                 .dram_speed_mts = 4266.0,
 602                         },
 603                         /*Extra state, no dispclk ramping*/
 604                         {
 605                                 .state = 8,
 606                                 .dcfclk_mhz = 847.06,
 607                                 .fabricclk_mhz = 1600.0,
 608                                 .dispclk_mhz = 1395.0,
 609                                 .dppclk_mhz = 1285.0,
 610                                 .phyclk_mhz = 1325.0,
 611                                 .socclk_mhz = 953.0,
 612                                 .dscclk_mhz = 489.0,
 613                                 .dram_speed_mts = 4266.0,
 614                         },
 615
 616                 },
 617
 618         .sr_exit_time_us = 12.5,
 619         .sr_enter_plus_exit_time_us = 17.0,
 620         .urgent_latency_us = 4.0,
 621         .urgent_latency_pixel_data_only_us = 4.0,
 622         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 623         .urgent_latency_vm_data_only_us = 4.0,
 624         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 625         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 626         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 627         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 628         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
 629         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 630         .max_avg_sdp_bw_use_normal_percent = 60.0,
 631         .max_avg_dram_bw_use_normal_percent = 100.0,
 632         .writeback_latency_us = 12.0,
 633         .max_request_size_bytes = 256,
 634         .dram_channel_width_bytes = 4,
 635         .fabric_datapath_to_dcn_data_return_bytes = 32,
 636         .dcn_downspread_percent = 0.5,
 637         .downspread_percent = 0.38,
 638         .dram_page_open_time_ns = 50.0,
 639         .dram_rw_turnaround_time_ns = 17.5,
 640         .dram_return_buffer_per_channel_bytes = 8192,
 641         .round_trip_ping_latency_dcfclk_cycles = 128,
 642         .urgent_out_of_order_return_per_channel_bytes = 4096,
 643         .channel_interleave_bytes = 256,
 644         .num_banks = 8,
 645         .num_chans = 4,
 646         .vmm_page_size_bytes = 4096,
 647         .dram_clock_change_latency_us = 23.84,
 648         .return_bus_width_bytes = 64,
 649         .dispclk_dppclk_vco_speed_mhz = 3600,
 650         .xfc_bus_transport_time_us = 4,
 651         .xfc_xbuf_latency_tolerance_us = 4,
 652         .use_urgent_burst_bw = 1,
 653         .num_states = 8
 654 };
 655
 656 struct wm_table ddr4_wm_table_gs = {
 657         .entries = {
 658                 {
 659                         .wm_inst = WM_A,
 660                         .wm_type = WM_TYPE_PSTATE_CHG,
 661                         .pstate_latency_us = 11.72,
 662                         .sr_exit_time_us = 7.09,
 663                         .sr_enter_plus_exit_time_us = 8.14,
 664                         .valid = true,
 665                 },
 666                 {
 667                         .wm_inst = WM_B,
 668                         .wm_type = WM_TYPE_PSTATE_CHG,
 669                         .pstate_latency_us = 11.72,
 670                         .sr_exit_time_us = 10.12,
 671                         .sr_enter_plus_exit_time_us = 11.48,
 672                         .valid = true,
 673                 },
 674                 {
 675                         .wm_inst = WM_C,
 676                         .wm_type = WM_TYPE_PSTATE_CHG,
 677                         .pstate_latency_us = 11.72,
 678                         .sr_exit_time_us = 10.12,
 679                         .sr_enter_plus_exit_time_us = 11.48,
 680                         .valid = true,
 681                 },
 682                 {
 683                         .wm_inst = WM_D,
 684                         .wm_type = WM_TYPE_PSTATE_CHG,
 685                         .pstate_latency_us = 11.72,
 686                         .sr_exit_time_us = 10.12,
 687                         .sr_enter_plus_exit_time_us = 11.48,
 688                         .valid = true,
 689                 },
 690         }
 691 };
 692
 693 struct wm_table lpddr4_wm_table_gs = {
 694         .entries = {
 695                 {
 696                         .wm_inst = WM_A,
 697                         .wm_type = WM_TYPE_PSTATE_CHG,
 698                         .pstate_latency_us = 11.65333,
 699                         .sr_exit_time_us = 5.32,
 700                         .sr_enter_plus_exit_time_us = 6.38,
 701                         .valid = true,
 702                 },
 703                 {
 704                         .wm_inst = WM_B,
 705                         .wm_type = WM_TYPE_PSTATE_CHG,
 706                         .pstate_latency_us = 11.65333,
 707                         .sr_exit_time_us = 9.82,
 708                         .sr_enter_plus_exit_time_us = 11.196,
 709                         .valid = true,
 710                 },
 711                 {
 712                         .wm_inst = WM_C,
 713                         .wm_type = WM_TYPE_PSTATE_CHG,
 714                         .pstate_latency_us = 11.65333,
 715                         .sr_exit_time_us = 9.89,
 716                         .sr_enter_plus_exit_time_us = 11.24,
 717                         .valid = true,
 718                 },
 719                 {
 720                         .wm_inst = WM_D,
 721                         .wm_type = WM_TYPE_PSTATE_CHG,
 722                         .pstate_latency_us = 11.65333,
 723                         .sr_exit_time_us = 9.748,
 724                         .sr_enter_plus_exit_time_us = 11.102,
 725                         .valid = true,
 726                 },
 727         }
 728 };
 729
 730 struct wm_table lpddr4_wm_table_with_disabled_ppt = {
 731         .entries = {
 732                 {
 733                         .wm_inst = WM_A,
 734                         .wm_type = WM_TYPE_PSTATE_CHG,
 735                         .pstate_latency_us = 11.65333,
 736                         .sr_exit_time_us = 8.32,
 737                         .sr_enter_plus_exit_time_us = 9.38,
 738                         .valid = true,
 739                 },
 740                 {
 741                         .wm_inst = WM_B,
 742                         .wm_type = WM_TYPE_PSTATE_CHG,
 743                         .pstate_latency_us = 11.65333,
 744                         .sr_exit_time_us = 9.82,
 745                         .sr_enter_plus_exit_time_us = 11.196,
 746                         .valid = true,
 747                 },
 748                 {
 749                         .wm_inst = WM_C,
 750                         .wm_type = WM_TYPE_PSTATE_CHG,
 751                         .pstate_latency_us = 11.65333,
 752                         .sr_exit_time_us = 9.89,
 753                         .sr_enter_plus_exit_time_us = 11.24,
 754                         .valid = true,
 755                 },
 756                 {
 757                         .wm_inst = WM_D,
 758                         .wm_type = WM_TYPE_PSTATE_CHG,
 759                         .pstate_latency_us = 11.65333,
 760                         .sr_exit_time_us = 9.748,
 761                         .sr_enter_plus_exit_time_us = 11.102,
 762                         .valid = true,
 763                 },
 764         }
 765 };
 766
 767 struct wm_table ddr4_wm_table_rn = {
 768         .entries = {
 769                 {
 770                         .wm_inst = WM_A,
 771                         .wm_type = WM_TYPE_PSTATE_CHG,
 772                         .pstate_latency_us = 11.72,
 773                         .sr_exit_time_us = 11.90,
 774                         .sr_enter_plus_exit_time_us = 12.80,
 775                         .valid = true,
 776                 },
 777                 {
 778                         .wm_inst = WM_B,
 779                         .wm_type = WM_TYPE_PSTATE_CHG,
 780                         .pstate_latency_us = 11.72,
 781                         .sr_exit_time_us = 13.18,
 782                         .sr_enter_plus_exit_time_us = 14.30,
 783                         .valid = true,
 784                 },
 785                 {
 786                         .wm_inst = WM_C,
 787                         .wm_type = WM_TYPE_PSTATE_CHG,
 788                         .pstate_latency_us = 11.72,
 789                         .sr_exit_time_us = 13.18,
 790                         .sr_enter_plus_exit_time_us = 14.30,
 791                         .valid = true,
 792                 },
 793                 {
 794                         .wm_inst = WM_D,
 795                         .wm_type = WM_TYPE_PSTATE_CHG,
 796                         .pstate_latency_us = 11.72,
 797                         .sr_exit_time_us = 13.18,
 798                         .sr_enter_plus_exit_time_us = 14.30,
 799                         .valid = true,
 800                 },
 801         }
 802 };
 803
 804 struct wm_table ddr4_1R_wm_table_rn = {
 805         .entries = {
 806                 {
 807                         .wm_inst = WM_A,
 808                         .wm_type = WM_TYPE_PSTATE_CHG,
 809                         .pstate_latency_us = 11.72,
 810                         .sr_exit_time_us = 13.90,
 811                         .sr_enter_plus_exit_time_us = 14.80,
 812                         .valid = true,
 813                 },
 814                 {
 815                         .wm_inst = WM_B,
 816                         .wm_type = WM_TYPE_PSTATE_CHG,
 817                         .pstate_latency_us = 11.72,
 818                         .sr_exit_time_us = 13.90,
 819                         .sr_enter_plus_exit_time_us = 14.80,
 820                         .valid = true,
 821                 },
 822                 {
 823                         .wm_inst = WM_C,
 824                         .wm_type = WM_TYPE_PSTATE_CHG,
 825                         .pstate_latency_us = 11.72,
 826                         .sr_exit_time_us = 13.90,
 827                         .sr_enter_plus_exit_time_us = 14.80,
 828                         .valid = true,
 829                 },
 830                 {
 831                         .wm_inst = WM_D,
 832                         .wm_type = WM_TYPE_PSTATE_CHG,
 833                         .pstate_latency_us = 11.72,
 834                         .sr_exit_time_us = 13.90,
 835                         .sr_enter_plus_exit_time_us = 14.80,
 836                         .valid = true,
 837                 },
 838         }
 839 };
 840
 841 struct wm_table lpddr4_wm_table_rn = {
 842         .entries = {
 843                 {
 844                         .wm_inst = WM_A,
 845                         .wm_type = WM_TYPE_PSTATE_CHG,
 846                         .pstate_latency_us = 11.65333,
 847                         .sr_exit_time_us = 7.32,
 848                         .sr_enter_plus_exit_time_us = 8.38,
 849                         .valid = true,
 850                 },
 851                 {
 852                         .wm_inst = WM_B,
 853                         .wm_type = WM_TYPE_PSTATE_CHG,
 854                         .pstate_latency_us = 11.65333,
 855                         .sr_exit_time_us = 9.82,
 856                         .sr_enter_plus_exit_time_us = 11.196,
 857                         .valid = true,
 858                 },
 859                 {
 860                         .wm_inst = WM_C,
 861                         .wm_type = WM_TYPE_PSTATE_CHG,
 862                         .pstate_latency_us = 11.65333,
 863                         .sr_exit_time_us = 9.89,
 864                         .sr_enter_plus_exit_time_us = 11.24,
 865                         .valid = true,
 866                 },
 867                 {
 868                         .wm_inst = WM_D,
 869                         .wm_type = WM_TYPE_PSTATE_CHG,
 870                         .pstate_latency_us = 11.65333,
 871                         .sr_exit_time_us = 9.748,
 872                         .sr_enter_plus_exit_time_us = 11.102,
 873                         .valid = true,
 874                 },
 875         }
 876 };
 877
 878 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
 879                                                struct resource_context *res_ctx,
 880                                                display_e2e_pipe_params_st *pipes)
 881 {
 882         int pipe_cnt, i;
 883
 884         dc_assert_fp_enabled();
 885
 886         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
 887                 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
 888
 889                 if (!res_ctx->pipe_ctx[i].stream)
 890                         continue;
 891
 892                 /* Set writeback information */
 893                 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
 894                 pipes[pipe_cnt].dout.num_active_wb++;
 895                 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
 896                 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
 897                 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
 898                 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
 899                 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
 900                 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
 901                 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
 902                 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
 903                 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
 904                 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
 905                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
 906                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
 907                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
 908                         else
 909                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
 910                 } else {
 911                         pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
 912                 }
 913
 914                 pipe_cnt++;
 915         }
 916 }
 917
 918 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
 919                                 struct dc_state *context,
 920                                 display_e2e_pipe_params_st *pipes,
 921                                 int pipe_cnt, int i)
 922 {
 923        int k;
 924
 925        dc_assert_fp_enabled();
 926
 927        for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
 928                wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 929                wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 930        }
 931        wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
 932 }
 933
 934 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
 935 {
 936         int i;
 937         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 938                 if (!context->res_ctx.pipe_ctx[i].stream)
 939                         continue;
 940                 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
 941                         return true;
 942         }
 943         return false;
 944 }
 945
 946 static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struct dc_state *context)
 947 {
 948         int plane_count;
 949         int i;
 950         unsigned int optimized_min_dst_y_next_start_us;
 951
 952         plane_count = 0;
 953         optimized_min_dst_y_next_start_us = 0;
 954         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 955                 if (context->res_ctx.pipe_ctx[i].plane_state)
 956                         plane_count++;
 957         }
 958
 959         /*
 960          * Z9 and Z10 allowed cases:
 961          *      1. 0 Planes enabled
 962          *      2. single eDP, on link 0, 1 plane and stutter period > 5ms
 963          * Z10 only cases:
 964          *      1. single eDP, on link 0, 1 plane and stutter period >= 5ms
 965          * Zstate not allowed cases:
 966          *      1. Everything else
 967          */
 968         if (plane_count == 0)
 969                 return DCN_ZSTATE_SUPPORT_ALLOW;
 970         else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
 971                 struct dc_link *link = context->streams[0]->sink->link;
 972                 struct dc_stream_status *stream_status = &context->stream_status[0];
 973
 974                 if (dc_extended_blank_supported(dc)) {
 975                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 976                                 if (context->res_ctx.pipe_ctx[i].stream == context->streams[0]
 977                                         && context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min == context->res_ctx.pipe_ctx[i].stream->adjust.v_total_max
 978                                         && context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min > context->res_ctx.pipe_ctx[i].stream->timing.v_total) {
 979                                                 optimized_min_dst_y_next_start_us =
 980                                                         context->res_ctx.pipe_ctx[i].dlg_regs.optimized_min_dst_y_next_start_us;
 981                                                 break;
 982                                 }
 983                         }
 984                 }
 985                 /* zstate only supported on PWRSEQ0  and when there's <2 planes*/
 986                 if (link->link_index != 0 || stream_status->plane_count > 1)
 987                         return DCN_ZSTATE_SUPPORT_DISALLOW;
 988
 989                 if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000)
 990                         return DCN_ZSTATE_SUPPORT_ALLOW;
 991                 else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !dc->debug.disable_psr)
 992                         return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
 993                 else
 994                         return DCN_ZSTATE_SUPPORT_DISALLOW;
 995         } else
 996                 return DCN_ZSTATE_SUPPORT_DISALLOW;
 997 }
 998
 999 void dcn20_calculate_dlg_params(
1000                 struct dc *dc, struct dc_state *context,
1001                 display_e2e_pipe_params_st *pipes,
1002                 int pipe_cnt,
1003                 int vlevel)
1004 {
1005         int i, pipe_idx;
1006
1007         dc_assert_fp_enabled();
1008
1009         /* Writeback MCIF_WB arbitration parameters */
1010         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1011
1012         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1013         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1014         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1015         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1016
1017         if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
1018                 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
1019
1020         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1021         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1022         context->bw_ctx.bw.dcn.clk.p_state_change_support =
1023                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1024                                                         != dm_dram_clock_change_unsupported;
1025
1026         /* Pstate change might not be supported by hardware, but it might be
1027          * possible with firmware driven vertical blank stretching.
1028          */
1029         context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
1030
1031         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1032
1033         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1034
1035         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1036                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1037
1038         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1039                 if (!context->res_ctx.pipe_ctx[i].stream)
1040                         continue;
1041                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1042                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1043                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1044                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1045                 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1046                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1047                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1048                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
1049                 } else {
1050                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
1051                         context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
1052                 }
1053                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1054                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1055                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
1056                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1057                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1058                 pipe_idx++;
1059         }
1060         /*save a original dppclock copy*/
1061         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1062         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1063         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
1064         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
1065
1066         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
1067                                                 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
1068
1069         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1070                 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
1071
1072                 if (!context->res_ctx.pipe_ctx[i].stream)
1073                         continue;
1074
1075                 if (dc->ctx->dce_version == DCN_VERSION_2_01)
1076                         cstate_en = false;
1077
1078                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
1079                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
1080                                 &context->res_ctx.pipe_ctx[i].ttu_regs,
1081                                 pipes,
1082                                 pipe_cnt,
1083                                 pipe_idx,
1084                                 cstate_en,
1085                                 context->bw_ctx.bw.dcn.clk.p_state_change_support,
1086                                 false, false, true);
1087
1088                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
1089                                 &context->res_ctx.pipe_ctx[i].rq_regs,
1090                                 &pipes[pipe_idx].pipe);
1091                 pipe_idx++;
1092         }
1093         context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
1094 }
1095
1096 static void swizzle_to_dml_params(
1097                 enum swizzle_mode_values swizzle,
1098                 unsigned int *sw_mode)
1099 {
1100         switch (swizzle) {
1101         case DC_SW_LINEAR:
1102                 *sw_mode = dm_sw_linear;
1103                 break;
1104         case DC_SW_4KB_S:
1105                 *sw_mode = dm_sw_4kb_s;
1106                 break;
1107         case DC_SW_4KB_S_X:
1108                 *sw_mode = dm_sw_4kb_s_x;
1109                 break;
1110         case DC_SW_4KB_D:
1111                 *sw_mode = dm_sw_4kb_d;
1112                 break;
1113         case DC_SW_4KB_D_X:
1114                 *sw_mode = dm_sw_4kb_d_x;
1115                 break;
1116         case DC_SW_64KB_S:
1117                 *sw_mode = dm_sw_64kb_s;
1118                 break;
1119         case DC_SW_64KB_S_X:
1120                 *sw_mode = dm_sw_64kb_s_x;
1121                 break;
1122         case DC_SW_64KB_S_T:
1123                 *sw_mode = dm_sw_64kb_s_t;
1124                 break;
1125         case DC_SW_64KB_D:
1126                 *sw_mode = dm_sw_64kb_d;
1127                 break;
1128         case DC_SW_64KB_D_X:
1129                 *sw_mode = dm_sw_64kb_d_x;
1130                 break;
1131         case DC_SW_64KB_D_T:
1132                 *sw_mode = dm_sw_64kb_d_t;
1133                 break;
1134         case DC_SW_64KB_R_X:
1135                 *sw_mode = dm_sw_64kb_r_x;
1136                 break;
1137         case DC_SW_VAR_S:
1138                 *sw_mode = dm_sw_var_s;
1139                 break;
1140         case DC_SW_VAR_S_X:
1141                 *sw_mode = dm_sw_var_s_x;
1142                 break;
1143         case DC_SW_VAR_D:
1144                 *sw_mode = dm_sw_var_d;
1145                 break;
1146         case DC_SW_VAR_D_X:
1147                 *sw_mode = dm_sw_var_d_x;
1148                 break;
1149         case DC_SW_VAR_R_X:
1150                 *sw_mode = dm_sw_var_r_x;
1151                 break;
1152         default:
1153                 ASSERT(0); /* Not supported */
1154                 break;
1155         }
1156 }
1157
1158 int dcn20_populate_dml_pipes_from_context(
1159                 struct dc *dc,
1160                 struct dc_state *context,
1161                 display_e2e_pipe_params_st *pipes,
1162                 bool fast_validate)
1163 {
1164         int pipe_cnt, i;
1165         bool synchronized_vblank = true;
1166         struct resource_context *res_ctx = &context->res_ctx;
1167
1168         dc_assert_fp_enabled();
1169
1170         for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1171                 if (!res_ctx->pipe_ctx[i].stream)
1172                         continue;
1173
1174                 if (pipe_cnt < 0) {
1175                         pipe_cnt = i;
1176                         continue;
1177                 }
1178
1179                 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
1180                         continue;
1181
1182                 if (dc->debug.disable_timing_sync ||
1183                         (!resource_are_streams_timing_synchronizable(
1184                                 res_ctx->pipe_ctx[pipe_cnt].stream,
1185                                 res_ctx->pipe_ctx[i].stream) &&
1186                         !resource_are_vblanks_synchronizable(
1187                                 res_ctx->pipe_ctx[pipe_cnt].stream,
1188                                 res_ctx->pipe_ctx[i].stream))) {
1189                         synchronized_vblank = false;
1190                         break;
1191                 }
1192         }
1193
1194         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1195                 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1196                 unsigned int v_total;
1197                 unsigned int front_porch;
1198                 int output_bpc;
1199                 struct audio_check aud_check = {0};
1200
1201                 if (!res_ctx->pipe_ctx[i].stream)
1202                         continue;
1203
1204                 v_total = timing->v_total;
1205                 front_porch = timing->v_front_porch;
1206
1207                 /* todo:
1208                 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1209                 pipes[pipe_cnt].pipe.src.dcc = 0;
1210                 pipes[pipe_cnt].pipe.src.vm = 0;*/
1211
1212                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1213
1214                 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1215                 /* todo: rotation?*/
1216                 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1217                 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1218                         pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1219                         /* 1/2 vblank */
1220                         pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1221                                 (v_total - timing->v_addressable
1222                                         - timing->v_border_top - timing->v_border_bottom) / 2;
1223                         /* 36 bytes dp, 32 hdmi */
1224                         pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1225                                 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1226                 }
1227                 pipes[pipe_cnt].pipe.src.dcc = false;
1228                 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1229                 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1230                 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1231                 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1232                                 - timing->h_addressable
1233                                 - timing->h_border_left
1234                                 - timing->h_border_right;
1235                 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
1236                 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1237                                 - timing->v_addressable
1238                                 - timing->v_border_top
1239                                 - timing->v_border_bottom;
1240                 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1241                 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
1242                 pipes[pipe_cnt].pipe.dest.hactive =
1243                         timing->h_addressable + timing->h_border_left + timing->h_border_right;
1244                 pipes[pipe_cnt].pipe.dest.vactive =
1245                         timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1246                 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1247                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1248                 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1249                         pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1250                 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1251                 pipes[pipe_cnt].dout.dp_lanes = 4;
1252                 if (res_ctx->pipe_ctx[i].stream->link)
1253                         pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
1254                 pipes[pipe_cnt].dout.is_virtual = 0;
1255                 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1256                 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1257                 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
1258                 case 1:
1259                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
1260                         break;
1261                 case 3:
1262                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
1263                         break;
1264                 default:
1265                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
1266                 }
1267                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1268                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1269                                 == res_ctx->pipe_ctx[i].plane_state) {
1270                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
1271                         int split_idx = 0;
1272
1273                         while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
1274                                         == res_ctx->pipe_ctx[i].plane_state) {
1275                                 first_pipe = first_pipe->top_pipe;
1276                                 split_idx++;
1277                         }
1278                         /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
1279                         if (split_idx == 0)
1280                                 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1281                         else if (split_idx == 1)
1282                                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1283                         else if (split_idx == 2)
1284                                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1285                 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1286                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1287
1288                         while (first_pipe->prev_odm_pipe)
1289                                 first_pipe = first_pipe->prev_odm_pipe;
1290                         pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1291                 }
1292
1293                 switch (res_ctx->pipe_ctx[i].stream->signal) {
1294                 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1295                 case SIGNAL_TYPE_DISPLAY_PORT:
1296                         pipes[pipe_cnt].dout.output_type = dm_dp;
1297                         break;
1298                 case SIGNAL_TYPE_EDP:
1299                         pipes[pipe_cnt].dout.output_type = dm_edp;
1300                         break;
1301                 case SIGNAL_TYPE_HDMI_TYPE_A:
1302                 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1303                 case SIGNAL_TYPE_DVI_DUAL_LINK:
1304                         pipes[pipe_cnt].dout.output_type = dm_hdmi;
1305                         break;
1306                 default:
1307                         /* In case there is no signal, set dp with 4 lanes to allow max config */
1308                         pipes[pipe_cnt].dout.is_virtual = 1;
1309                         pipes[pipe_cnt].dout.output_type = dm_dp;
1310                         pipes[pipe_cnt].dout.dp_lanes = 4;
1311                         pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
1312                 }
1313
1314                 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1315                 case COLOR_DEPTH_666:
1316                         output_bpc = 6;
1317                         break;
1318                 case COLOR_DEPTH_888:
1319                         output_bpc = 8;
1320                         break;
1321                 case COLOR_DEPTH_101010:
1322                         output_bpc = 10;
1323                         break;
1324                 case COLOR_DEPTH_121212:
1325                         output_bpc = 12;
1326                         break;
1327                 case COLOR_DEPTH_141414:
1328                         output_bpc = 14;
1329                         break;
1330                 case COLOR_DEPTH_161616:
1331                         output_bpc = 16;
1332                         break;
1333                 case COLOR_DEPTH_999:
1334                         output_bpc = 9;
1335                         break;
1336                 case COLOR_DEPTH_111111:
1337                         output_bpc = 11;
1338                         break;
1339                 default:
1340                         output_bpc = 8;
1341                         break;
1342                 }
1343
1344                 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1345                 case PIXEL_ENCODING_RGB:
1346                 case PIXEL_ENCODING_YCBCR444:
1347                         pipes[pipe_cnt].dout.output_format = dm_444;
1348                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1349                         break;
1350                 case PIXEL_ENCODING_YCBCR420:
1351                         pipes[pipe_cnt].dout.output_format = dm_420;
1352                         pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
1353                         break;
1354                 case PIXEL_ENCODING_YCBCR422:
1355                         if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
1356                             !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
1357                                 pipes[pipe_cnt].dout.output_format = dm_n422;
1358                         else
1359                                 pipes[pipe_cnt].dout.output_format = dm_s422;
1360                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1361                         break;
1362                 default:
1363                         pipes[pipe_cnt].dout.output_format = dm_444;
1364                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1365                 }
1366
1367                 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
1368                         pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
1369
1370                 /* todo: default max for now, until there is logic reflecting this in dc*/
1371                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1372                 /*fill up the audio sample rate (unit in kHz)*/
1373                 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
1374                 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
1375                 /*
1376                  * For graphic plane, cursor number is 1, nv12 is 0
1377                  * bw calculations due to cursor on/off
1378                  */
1379                 if (res_ctx->pipe_ctx[i].plane_state &&
1380                                 (res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||
1381                                  res_ctx->pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM))
1382                         pipes[pipe_cnt].pipe.src.num_cursors = 0;
1383                 else
1384                         pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
1385
1386                 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1387                 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1388
1389                 if (!res_ctx->pipe_ctx[i].plane_state) {
1390                         pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1391                         pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1392                         pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1393                         pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
1394                         pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1395                         pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1396                         if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1397                                 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1398                         pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1399                         if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1400                                 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1401                         pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
1402                         pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
1403                         pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
1404                         pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
1405                         pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
1406                         pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1407                         pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1408                         pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1409                         pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
1410                         pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1411                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1412                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1413                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1414                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1415                         pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1416                         pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1417                         pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
1418                         pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
1419
1420                         if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
1421                                 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
1422                                 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
1423                         } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
1424                                 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
1425                                 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
1426                         }
1427                 } else {
1428                         struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1429                         struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1430
1431                         pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1432                         pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1433                                         || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
1434                                         || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1435
1436                         /* stereo is not split */
1437                         if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
1438                             pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
1439                                 pipes[pipe_cnt].pipe.src.is_hsplit = false;
1440                                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1441                         }
1442
1443                         pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1444                                         || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1445                         switch (pln->rotation) {
1446                         case ROTATION_ANGLE_0:
1447                                 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1448                                 break;
1449                         case ROTATION_ANGLE_90:
1450                                 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90;
1451                                 break;
1452                         case ROTATION_ANGLE_180:
1453                                 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180;
1454                                 break;
1455                         case ROTATION_ANGLE_270:
1456                                 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270;
1457                                 break;
1458                         default:
1459                                 break;
1460                         }
1461                         pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1462                         pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1463                         pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x;
1464                         pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x;
1465                         pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1466                         pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1467                         pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1468                         pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1469                         pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
1470                         pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
1471                         pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
1472                         pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
1473                         pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
1474                         pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
1475                         if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
1476                                         || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1477                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1478                                 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1479                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1480                                 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
1481                         } else {
1482                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1483                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1484                         }
1485                         pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1486                         pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1487                         pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1488                         pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1489                         pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1490                         if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
1491                                 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
1492                         else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
1493                                 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
1494                         else {
1495                                 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
1496
1497                                 while (split_pipe && split_pipe->plane_state == pln) {
1498                                         pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1499                                         split_pipe = split_pipe->bottom_pipe;
1500                                 }
1501                                 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
1502                                 while (split_pipe && split_pipe->plane_state == pln) {
1503                                         pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1504                                         split_pipe = split_pipe->top_pipe;
1505                                 }
1506                         }
1507
1508                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1509                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1510                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1511                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1512                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1513                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1514                                         scl->ratios.vert.value != dc_fixpt_one.value
1515                                         || scl->ratios.horz.value != dc_fixpt_one.value
1516                                         || scl->ratios.vert_c.value != dc_fixpt_one.value
1517                                         || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1518                                         || dc->debug.always_scale; /*support always scale*/
1519                         pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1520                         pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1521                         pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1522                         pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1523
1524                         pipes[pipe_cnt].pipe.src.macro_tile_size =
1525                                         swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
1526                         swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1527                                         &pipes[pipe_cnt].pipe.src.sw_mode);
1528
1529                         switch (pln->format) {
1530                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1531                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1532                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1533                                 break;
1534                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1535                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1536                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1537                                 break;
1538                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1539                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
1540                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1541                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1542                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1543                                 break;
1544                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1545                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1546                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1547                                 break;
1548                         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1549                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1550                                 break;
1551                         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
1552                                 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
1553                                 break;
1554                         default:
1555                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1556                                 break;
1557                         }
1558                 }
1559
1560                 pipe_cnt++;
1561         }
1562
1563         /* populate writeback information */
1564         dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1565
1566         return pipe_cnt;
1567 }
1568
1569 void dcn20_calculate_wm(
1570                 struct dc *dc, struct dc_state *context,
1571                 display_e2e_pipe_params_st *pipes,
1572                 int *out_pipe_cnt,
1573                 int *pipe_split_from,
1574                 int vlevel,
1575                 bool fast_validate)
1576 {
1577         int pipe_cnt, i, pipe_idx;
1578
1579         dc_assert_fp_enabled();
1580
1581         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1582                 if (!context->res_ctx.pipe_ctx[i].stream)
1583                         continue;
1584
1585                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1586                 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1587
1588                 if (pipe_split_from[i] < 0) {
1589                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1590                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1591                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1592                                 pipes[pipe_cnt].pipe.dest.odm_combine =
1593                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
1594                         else
1595                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1596                         pipe_idx++;
1597                 } else {
1598                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1599                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1600                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1601                                 pipes[pipe_cnt].pipe.dest.odm_combine =
1602                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
1603                         else
1604                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1605                 }
1606
1607                 if (dc->config.forced_clocks) {
1608                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1609                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1610                 }
1611                 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
1612                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1613                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
1614                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1615
1616                 pipe_cnt++;
1617         }
1618
1619         if (pipe_cnt != pipe_idx) {
1620                 if (dc->res_pool->funcs->populate_dml_pipes)
1621                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1622                                 context, pipes, fast_validate);
1623                 else
1624                         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
1625                                 context, pipes, fast_validate);
1626         }
1627
1628         *out_pipe_cnt = pipe_cnt;
1629
1630         pipes[0].clks_cfg.voltage = vlevel;
1631         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1632         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1633
1634         /* only pipe 0 is read for voltage and dcf/soc clocks */
1635         if (vlevel < 1) {
1636                 pipes[0].clks_cfg.voltage = 1;
1637                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
1638                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
1639         }
1640         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1641         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1642         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1643         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1644         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1645         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1646         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1647         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1648
1649         if (vlevel < 2) {
1650                 pipes[0].clks_cfg.voltage = 2;
1651                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1652                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1653         }
1654         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1655         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1656         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1657         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1658         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1659         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1660         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1661
1662         if (vlevel < 3) {
1663                 pipes[0].clks_cfg.voltage = 3;
1664                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1665                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1666         }
1667         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1668         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1669         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1670         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1671         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1672         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1673         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1674
1675         pipes[0].clks_cfg.voltage = vlevel;
1676         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1677         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1678         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1679         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1680         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1681         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1682         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1683         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1684         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1685 }
1686
1687 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
1688                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
1689 {
1690         int num_calculated_states = 0;
1691         int min_dcfclk = 0;
1692         int i;
1693
1694         dc_assert_fp_enabled();
1695
1696         if (num_states == 0)
1697                 return;
1698
1699         memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
1700
1701         if (dc->bb_overrides.min_dcfclk_mhz > 0) {
1702                 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
1703         } else {
1704                 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
1705                         min_dcfclk = 310;
1706                 else
1707                         // Accounting for SOC/DCF relationship, we can go as high as
1708                         // 506Mhz in Vmin.
1709                         min_dcfclk = 506;
1710         }
1711
1712         for (i = 0; i < num_states; i++) {
1713                 int min_fclk_required_by_uclk;
1714                 bb->clock_limits[i].state = i;
1715                 bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
1716
1717                 // FCLK:UCLK ratio is 1.08
1718                 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
1719                         1000000);
1720
1721                 bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
1722                                 min_dcfclk : min_fclk_required_by_uclk;
1723
1724                 bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
1725                                 max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
1726
1727                 bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
1728                                 max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
1729
1730                 bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
1731                 bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
1732                 bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
1733
1734                 bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
1735
1736                 num_calculated_states++;
1737         }
1738
1739         bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
1740         bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
1741         bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
1742
1743         bb->num_states = num_calculated_states;
1744
1745         // Duplicate the last state, DML always an extra state identical to max state to work
1746         memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
1747         bb->clock_limits[num_calculated_states].state = bb->num_states;
1748 }
1749
1750 void dcn20_cap_soc_clocks(
1751                 struct _vcs_dpi_soc_bounding_box_st *bb,
1752                 struct pp_smu_nv_clock_table max_clocks)
1753 {
1754         int i;
1755
1756         dc_assert_fp_enabled();
1757
1758         // First pass - cap all clocks higher than the reported max
1759         for (i = 0; i < bb->num_states; i++) {
1760                 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
1761                                 && max_clocks.dcfClockInKhz != 0)
1762                         bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
1763
1764                 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
1765                                                 && max_clocks.uClockInKhz != 0)
1766                         bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
1767
1768                 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
1769                                                 && max_clocks.fabricClockInKhz != 0)
1770                         bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
1771
1772                 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
1773                                                 && max_clocks.displayClockInKhz != 0)
1774                         bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
1775
1776                 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
1777                                                 && max_clocks.dppClockInKhz != 0)
1778                         bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
1779
1780                 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
1781                                                 && max_clocks.phyClockInKhz != 0)
1782                         bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
1783
1784                 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
1785                                                 && max_clocks.socClockInKhz != 0)
1786                         bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
1787
1788                 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
1789                                                 && max_clocks.dscClockInKhz != 0)
1790                         bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
1791         }
1792
1793         // Second pass - remove all duplicate clock states
1794         for (i = bb->num_states - 1; i > 1; i--) {
1795                 bool duplicate = true;
1796
1797                 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
1798                         duplicate = false;
1799                 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
1800                         duplicate = false;
1801                 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
1802                         duplicate = false;
1803                 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
1804                         duplicate = false;
1805                 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
1806                         duplicate = false;
1807                 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
1808                         duplicate = false;
1809                 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
1810                         duplicate = false;
1811                 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
1812                         duplicate = false;
1813
1814                 if (duplicate)
1815                         bb->num_states--;
1816         }
1817 }
1818
1819 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1820 {
1821         dc_assert_fp_enabled();
1822
1823         if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
1824                         && dc->bb_overrides.sr_exit_time_ns) {
1825                 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
1826         }
1827
1828         if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
1829                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
1830                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1831                 bb->sr_enter_plus_exit_time_us =
1832                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1833         }
1834
1835         if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
1836                         && dc->bb_overrides.urgent_latency_ns) {
1837                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1838         }
1839
1840         if ((int)(bb->dram_clock_change_latency_us * 1000)
1841                                 != dc->bb_overrides.dram_clock_change_latency_ns
1842                         && dc->bb_overrides.dram_clock_change_latency_ns) {
1843                 bb->dram_clock_change_latency_us =
1844                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1845         }
1846
1847         if ((int)(bb->dummy_pstate_latency_us * 1000)
1848                                 != dc->bb_overrides.dummy_clock_change_latency_ns
1849                         && dc->bb_overrides.dummy_clock_change_latency_ns) {
1850                 bb->dummy_pstate_latency_us =
1851                                 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
1852         }
1853 }
1854
1855 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
1856                 bool fast_validate)
1857 {
1858         bool out = false;
1859
1860         BW_VAL_TRACE_SETUP();
1861
1862         int vlevel = 0;
1863         int pipe_split_from[MAX_PIPES];
1864         int pipe_cnt = 0;
1865         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1866         DC_LOGGER_INIT(dc->ctx->logger);
1867
1868         BW_VAL_TRACE_COUNT();
1869
1870         out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1871
1872         if (pipe_cnt == 0)
1873                 goto validate_out;
1874
1875         if (!out)
1876                 goto validate_fail;
1877
1878         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1879
1880         if (fast_validate) {
1881                 BW_VAL_TRACE_SKIP(fast);
1882                 goto validate_out;
1883         }
1884
1885         dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1886         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1887
1888         BW_VAL_TRACE_END_WATERMARKS();
1889
1890         goto validate_out;
1891
1892 validate_fail:
1893         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1894                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1895
1896         BW_VAL_TRACE_SKIP(fail);
1897         out = false;
1898
1899 validate_out:
1900         kfree(pipes);
1901
1902         BW_VAL_TRACE_FINISH();
1903
1904         return out;
1905 }
1906
1907 bool dcn20_validate_bandwidth_fp(struct dc *dc,
1908                                 struct dc_state *context,
1909                                 bool fast_validate)
1910 {
1911        bool voltage_supported = false;
1912        bool full_pstate_supported = false;
1913        bool dummy_pstate_supported = false;
1914        double p_state_latency_us;
1915
1916        dc_assert_fp_enabled();
1917
1918        p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
1919        context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
1920                dc->debug.disable_dram_clock_change_vactive_support;
1921        context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
1922                dc->debug.enable_dram_clock_change_one_display_vactive;
1923
1924        /*Unsafe due to current pipe merge and split logic*/
1925        ASSERT(context != dc->current_state);
1926
1927        if (fast_validate) {
1928                return dcn20_validate_bandwidth_internal(dc, context, true);
1929        }
1930
1931        // Best case, we support full UCLK switch latency
1932        voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
1933        full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1934
1935        if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
1936                (voltage_supported && full_pstate_supported)) {
1937                context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
1938                goto restore_dml_state;
1939        }
1940
1941        // Fallback: Try to only support G6 temperature read latency
1942        context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
1943
1944        voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
1945        dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1946
1947        if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
1948                context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1949                goto restore_dml_state;
1950        }
1951
1952        // ERROR: fallback is supposed to always work.
1953        ASSERT(false);
1954
1955 restore_dml_state:
1956        context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
1957        return voltage_supported;
1958 }
1959
1960 void dcn20_fpu_set_wm_ranges(int i,
1961                             struct pp_smu_wm_range_sets *ranges,
1962                             struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1963 {
1964        dc_assert_fp_enabled();
1965
1966        ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
1967        ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
1968 }
1969
1970 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
1971                             int vlevel,
1972                             int max_mpc_comb,
1973                             int pipe_idx,
1974                             bool is_validating_bw)
1975 {
1976        dc_assert_fp_enabled();
1977
1978        if (is_validating_bw)
1979                v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2;
1980        else
1981                v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
1982 }
1983
1984 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
1985                                           struct dc_state *context,
1986                                           display_e2e_pipe_params_st *pipes,
1987                                           bool fast_validate)
1988 {
1989         uint32_t pipe_cnt;
1990         int i;
1991
1992         dc_assert_fp_enabled();
1993
1994         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1995
1996         for (i = 0; i < pipe_cnt; i++) {
1997
1998                 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1999                 pipes[i].pipe.src.gpuvm = 1;
2000         }
2001
2002         return pipe_cnt;
2003 }
2004
2005 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2006 {
2007         int i;
2008
2009         if (dc->bb_overrides.sr_exit_time_ns) {
2010                 for (i = 0; i < WM_SET_COUNT; i++) {
2011                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
2012                                           dc->bb_overrides.sr_exit_time_ns / 1000.0;
2013                 }
2014         }
2015
2016         if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2017                 for (i = 0; i < WM_SET_COUNT; i++) {
2018                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
2019                                           dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2020                 }
2021         }
2022
2023         if (dc->bb_overrides.urgent_latency_ns) {
2024                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2025         }
2026
2027         if (dc->bb_overrides.dram_clock_change_latency_ns) {
2028                 for (i = 0; i < WM_SET_COUNT; i++) {
2029                         dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
2030                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2031                 }
2032         }
2033 }
2034
2035 static void calculate_wm_set_for_vlevel(int vlevel,
2036                                         struct wm_range_table_entry *table_entry,
2037                                         struct dcn_watermarks *wm_set,
2038                                         struct display_mode_lib *dml,
2039                                         display_e2e_pipe_params_st *pipes,
2040                                         int pipe_cnt)
2041 {
2042         double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
2043
2044         ASSERT(vlevel < dml->soc.num_states);
2045         /* only pipe 0 is read for voltage and dcf/soc clocks */
2046         pipes[0].clks_cfg.voltage = vlevel;
2047         pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
2048         pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
2049
2050         dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
2051         dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
2052         dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
2053
2054         wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
2055         wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
2056         wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
2057         wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
2058         wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
2059         wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
2060         wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
2061         wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
2062         dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
2063 }
2064
2065 static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,
2066                         display_e2e_pipe_params_st *pipes,
2067                         int *out_pipe_cnt,
2068                         int *pipe_split_from,
2069                         int vlevel_req,
2070                         bool fast_validate)
2071 {
2072         int pipe_cnt, i, pipe_idx;
2073         int vlevel, vlevel_max;
2074         struct wm_range_table_entry *table_entry;
2075         struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
2076
2077         ASSERT(bw_params);
2078
2079         patch_bounding_box(dc, &context->bw_ctx.dml.soc);
2080
2081         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2082                         if (!context->res_ctx.pipe_ctx[i].stream)
2083                                 continue;
2084
2085                         pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2086                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
2087
2088                         if (pipe_split_from[i] < 0) {
2089                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2090                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2091                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2092                                         pipes[pipe_cnt].pipe.dest.odm_combine =
2093                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
2094                                 else
2095                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2096                                 pipe_idx++;
2097                         } else {
2098                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2099                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2100                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2101                                         pipes[pipe_cnt].pipe.dest.odm_combine =
2102                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
2103                                 else
2104                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2105                         }
2106                         pipe_cnt++;
2107         }
2108
2109         if (pipe_cnt != pipe_idx) {
2110                 if (dc->res_pool->funcs->populate_dml_pipes)
2111                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2112                                 context, pipes, fast_validate);
2113                 else
2114                         pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2115                                 context, pipes, fast_validate);
2116         }
2117
2118         *out_pipe_cnt = pipe_cnt;
2119
2120         vlevel_max = bw_params->clk_table.num_entries - 1;
2121
2122
2123         /* WM Set D */
2124         table_entry = &bw_params->wm_table.entries[WM_D];
2125         if (table_entry->wm_type == WM_TYPE_RETRAINING)
2126                 vlevel = 0;
2127         else
2128                 vlevel = vlevel_max;
2129         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
2130                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
2131         /* WM Set C */
2132         table_entry = &bw_params->wm_table.entries[WM_C];
2133         vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
2134         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
2135                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
2136         /* WM Set B */
2137         table_entry = &bw_params->wm_table.entries[WM_B];
2138         vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
2139         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
2140                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
2141
2142         /* WM Set A */
2143         table_entry = &bw_params->wm_table.entries[WM_A];
2144         vlevel = MIN(vlevel_req, vlevel_max);
2145         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
2146                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
2147 }
2148
2149 bool dcn21_validate_bandwidth_fp(struct dc *dc,
2150                                  struct dc_state *context,
2151                                  bool fast_validate)
2152 {
2153         bool out = false;
2154
2155         BW_VAL_TRACE_SETUP();
2156
2157         int vlevel = 0;
2158         int pipe_split_from[MAX_PIPES];
2159         int pipe_cnt = 0;
2160         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
2161         DC_LOGGER_INIT(dc->ctx->logger);
2162
2163         BW_VAL_TRACE_COUNT();
2164
2165         dc_assert_fp_enabled();
2166
2167         /*Unsafe due to current pipe merge and split logic*/
2168         ASSERT(context != dc->current_state);
2169
2170         out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2171
2172         if (pipe_cnt == 0)
2173                 goto validate_out;
2174
2175         if (!out)
2176                 goto validate_fail;
2177
2178         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2179
2180         if (fast_validate) {
2181                 BW_VAL_TRACE_SKIP(fast);
2182                 goto validate_out;
2183         }
2184
2185         dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2186         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2187
2188         BW_VAL_TRACE_END_WATERMARKS();
2189
2190         goto validate_out;
2191
2192 validate_fail:
2193         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2194                         dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2195
2196         BW_VAL_TRACE_SKIP(fail);
2197         out = false;
2198
2199 validate_out:
2200         kfree(pipes);
2201
2202         BW_VAL_TRACE_FINISH();
2203
2204         return out;
2205 }
2206
2207 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
2208 {
2209         struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
2210         int i;
2211
2212         low_pstate_lvl.state = 1;
2213         low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
2214         low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
2215         low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
2216         low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
2217
2218         low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
2219         low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
2220         low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
2221         low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
2222         low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
2223         low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
2224         low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
2225
2226         for (i = clk_table->num_entries; i > 1; i--)
2227                 clk_table->entries[i] = clk_table->entries[i-1];
2228         clk_table->entries[1] = clk_table->entries[0];
2229         clk_table->num_entries++;
2230
2231         return low_pstate_lvl;
2232 }
2233
2234 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2235 {
2236         struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
2237         struct clk_limit_table *clk_table = &bw_params->clk_table;
2238         unsigned int i, closest_clk_lvl = 0, k = 0;
2239         int j;
2240
2241         dc_assert_fp_enabled();
2242
2243         dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2244         dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
2245         dcn2_1_soc.num_chans = bw_params->num_channels;
2246
2247         ASSERT(clk_table->num_entries);
2248         /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
2249         memcpy(&dcn2_1_soc._clock_tmp, &dcn2_1_soc.clock_limits,
2250                sizeof(dcn2_1_soc.clock_limits));
2251
2252         for (i = 0; i < clk_table->num_entries; i++) {
2253                 /* loop backwards*/
2254                 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
2255                         if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2256                                 closest_clk_lvl = j;
2257                                 break;
2258                         }
2259                 }
2260
2261                 /* clk_table[1] is reserved for min DF PState.  skip here to fill in later. */
2262                 if (i == 1)
2263                         k++;
2264
2265                 dcn2_1_soc._clock_tmp[k].state = k;
2266                 dcn2_1_soc._clock_tmp[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2267                 dcn2_1_soc._clock_tmp[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2268                 dcn2_1_soc._clock_tmp[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
2269                 dcn2_1_soc._clock_tmp[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
2270
2271                 dcn2_1_soc._clock_tmp[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2272                 dcn2_1_soc._clock_tmp[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2273                 dcn2_1_soc._clock_tmp[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2274                 dcn2_1_soc._clock_tmp[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2275                 dcn2_1_soc._clock_tmp[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2276                 dcn2_1_soc._clock_tmp[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2277                 dcn2_1_soc._clock_tmp[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2278
2279                 k++;
2280         }
2281
2282         memcpy(&dcn2_1_soc.clock_limits, &dcn2_1_soc._clock_tmp,
2283                sizeof(dcn2_1_soc.clock_limits));
2284
2285         if (clk_table->num_entries) {
2286                 dcn2_1_soc.num_states = clk_table->num_entries + 1;
2287                 /* fill in min DF PState */
2288                 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
2289                 /* duplicate last level */
2290                 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
2291                 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
2292         }
2293
2294         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2295 }
2296
2297 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params)
2298 {
2299         dc_assert_fp_enabled();
2300
2301         bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
2302         bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
2303         bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
2304         bw_params->wm_table.entries[WM_D].valid = true;
2305 }
2306
2307 void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
2308                                                     struct resource_context *res_ctx,
2309                                                     display_e2e_pipe_params_st *pipes)
2310 {
2311         int pipe_cnt, i, j;
2312         double max_calc_writeback_dispclk;
2313         double writeback_dispclk;
2314         struct writeback_st dout_wb;
2315
2316         dc_assert_fp_enabled();
2317
2318         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2319                 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
2320
2321                 if (!stream)
2322                         continue;
2323                 max_calc_writeback_dispclk = 0;
2324
2325                 /* Set writeback information */
2326                 pipes[pipe_cnt].dout.wb_enable = 0;
2327                 pipes[pipe_cnt].dout.num_active_wb = 0;
2328                 for (j = 0; j < stream->num_wb_info; j++) {
2329                         struct dc_writeback_info *wb_info = &stream->writeback_info[j];
2330
2331                         if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
2332                                         (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
2333                                 pipes[pipe_cnt].dout.wb_enable = 1;
2334                                 pipes[pipe_cnt].dout.num_active_wb++;
2335                                 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
2336                                         wb_info->dwb_params.cnv_params.crop_height :
2337                                         wb_info->dwb_params.cnv_params.src_height;
2338                                 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
2339                                         wb_info->dwb_params.cnv_params.crop_width :
2340                                         wb_info->dwb_params.cnv_params.src_width;
2341                                 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
2342                                 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
2343                                 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
2344                                 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
2345                                 dout_wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
2346                                 dout_wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
2347                                 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
2348                                         (double)wb_info->dwb_params.cnv_params.crop_width /
2349                                                 (double)wb_info->dwb_params.dest_width :
2350                                         (double)wb_info->dwb_params.cnv_params.src_width /
2351                                                 (double)wb_info->dwb_params.dest_width;
2352                                 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
2353                                         (double)wb_info->dwb_params.cnv_params.crop_height /
2354                                                 (double)wb_info->dwb_params.dest_height :
2355                                         (double)wb_info->dwb_params.cnv_params.src_height /
2356                                                 (double)wb_info->dwb_params.dest_height;
2357                                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
2358                                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2359                                                 dout_wb.wb_pixel_format = dm_420_8;
2360                                         else
2361                                                 dout_wb.wb_pixel_format = dm_420_10;
2362                                 } else
2363                                         dout_wb.wb_pixel_format = dm_444_32;
2364
2365                                 /* Workaround for cases where multiple writebacks are connected to same plane
2366                                  * In which case, need to compute worst case and set the associated writeback parameters
2367                                  * This workaround is necessary due to DML computation assuming only 1 set of writeback
2368                                  * parameters per pipe */
2369                                 writeback_dispclk = CalculateWriteBackDISPCLK(
2370                                                 dout_wb.wb_pixel_format,
2371                                                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
2372                                                 dout_wb.wb_hratio,
2373                                                 dout_wb.wb_vratio,
2374                                                 dout_wb.wb_htaps_luma,
2375                                                 dout_wb.wb_vtaps_luma,
2376                                                 dout_wb.wb_htaps_chroma,
2377                                                 dout_wb.wb_vtaps_chroma,
2378                                                 dout_wb.wb_dst_width,
2379                                                 pipes[pipe_cnt].pipe.dest.htotal,
2380                                                 2);
2381
2382                                 if (writeback_dispclk > max_calc_writeback_dispclk) {
2383                                         max_calc_writeback_dispclk = writeback_dispclk;
2384                                         pipes[pipe_cnt].dout.wb = dout_wb;
2385                                 }
2386                         }
2387                 }
2388
2389                 pipe_cnt++;
2390         }
2391
2392 }