drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "reg_helper.h"
  27 #include "dcn30/dcn30_mpc.h"
  28 #include "dcn30/dcn30_cm_common.h"
  29 #include "dcn32_mpc.h"
  30 #include "basics/conversion.h"
  31 #include "dcn10/dcn10_cm_common.h"
  32 #include "dc.h"
  33
  34 #define REG(reg)\
  35         mpc30->mpc_regs->reg
  36
  37 #define CTX \
  38         mpc30->base.ctx
  39
  40 #undef FN
  41 #define FN(reg_name, field_name) \
  42         mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
  43
  44
  45 void mpc32_mpc_init(struct mpc *mpc)
  46 {
  47         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
  48         int mpcc_id;
  49
  50         mpc1_mpc_init(mpc);
  51
  52         if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
  53                 if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
  54                         for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
  55                                 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
  56                                 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
  57                                 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
  58                         }
  59                 }
  60                 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
  61                         for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
  62                                 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
  63                 }
  64         }
  65 }
  66
  67 void mpc32_power_on_blnd_lut(
  68         struct mpc *mpc,
  69         uint32_t mpcc_id,
  70         bool power_on)
  71 {
  72         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
  73
  74         if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
  75                 if (power_on) {
  76                         REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
  77                         REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
  78                 } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
  79                         ASSERT(false);
  80                         /* TODO: change to mpc
  81                          *  dpp_base->ctx->dc->optimized_required = true;
  82                          *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
  83                          */
  84                 }
  85         } else {
  86                 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
  87                                 MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
  88         }
  89 }
  90
  91 static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)
  92 {
  93         enum dc_lut_mode mode;
  94         uint32_t mode_current = 0;
  95         uint32_t in_use = 0;
  96
  97         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
  98
  99         REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
 100                         MPCC_MCM_1DLUT_MODE_CURRENT, &mode_current);
 101         REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
 102                         MPCC_MCM_1DLUT_SELECT_CURRENT, &in_use);
 103
 104         switch (mode_current) {
 105         case 0:
 106         case 1:
 107                 mode = LUT_BYPASS;
 108                 break;
 109
 110         case 2:
 111                 if (in_use == 0)
 112                         mode = LUT_RAM_A;
 113                 else
 114                         mode = LUT_RAM_B;
 115                 break;
 116         default:
 117                 mode = LUT_BYPASS;
 118                 break;
 119         }
 120         return mode;
 121 }
 122
 123 void mpc32_configure_post1dlut(
 124                 struct mpc *mpc,
 125                 uint32_t mpcc_id,
 126                 bool is_ram_a)
 127 {
 128         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 129
 130         //TODO: this
 131         REG_UPDATE_2(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id],
 132                         MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 7,
 133                         MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
 134
 135         REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
 136 }
 137
 138 static void mpc32_post1dlut_get_reg_field(
 139                 struct dcn30_mpc *mpc,
 140                 struct dcn3_xfer_func_reg *reg)
 141 {
 142         reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
 143         reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
 144         reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
 145         reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
 146         reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
 147         reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
 148         reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
 149         reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
 150
 151         reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
 152         reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
 153         reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
 154         reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
 155         reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
 156         reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
 157         reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
 158         reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
 159         reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
 160         reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
 161         reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
 162         reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
 163 }
 164
 165 /*program blnd lut RAM A*/
 166 void mpc32_program_post1dluta_settings(
 167                 struct mpc *mpc,
 168                 uint32_t mpcc_id,
 169                 const struct pwl_params *params)
 170 {
 171         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 172         struct dcn3_xfer_func_reg gam_regs;
 173
 174         mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
 175
 176         gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
 177         gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
 178         gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
 179         gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
 180         gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
 181         gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
 182         gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
 183         gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);
 184         gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[mpcc_id]);
 185         gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[mpcc_id]);
 186         gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[mpcc_id]);
 187         gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[mpcc_id]);
 188         gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]);
 189         gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]);
 190
 191         cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
 192 }
 193
 194 /*program blnd lut RAM B*/
 195 void mpc32_program_post1dlutb_settings(
 196                 struct mpc *mpc,
 197                 uint32_t mpcc_id,
 198                 const struct pwl_params *params)
 199 {
 200         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 201         struct dcn3_xfer_func_reg gam_regs;
 202
 203         mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
 204
 205         gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_B[mpcc_id]);
 206         gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_G[mpcc_id]);
 207         gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_R[mpcc_id]);
 208         gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[mpcc_id]);
 209         gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[mpcc_id]);
 210         gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[mpcc_id]);
 211         gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[mpcc_id]);
 212         gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[mpcc_id]);
 213         gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[mpcc_id]);
 214         gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[mpcc_id]);
 215         gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[mpcc_id]);
 216         gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[mpcc_id]);
 217         gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]);
 218         gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]);
 219
 220         cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
 221 }
 222
 223 void mpc32_program_post1dlut_pwl(
 224                 struct mpc *mpc,
 225                 uint32_t mpcc_id,
 226                 const struct pwl_result_data *rgb,
 227                 uint32_t num)
 228 {
 229         uint32_t i;
 230         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 231         uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
 232         uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
 233         uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
 234
 235         if (is_rgb_equal(rgb, num)) {
 236                 for (i = 0 ; i < num; i++)
 237                         REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
 238                 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
 239         } else {
 240                 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4);
 241                 for (i = 0 ; i < num; i++)
 242                         REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
 243                 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
 244
 245                 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2);
 246                 for (i = 0 ; i < num; i++)
 247                         REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].green_reg);
 248                 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_green);
 249
 250                 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1);
 251                 for (i = 0 ; i < num; i++)
 252                         REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].blue_reg);
 253                 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_blue);
 254         }
 255 }
 256
 257 bool mpc32_program_post1dlut(
 258                 struct mpc *mpc,
 259                 const struct pwl_params *params,
 260                 uint32_t mpcc_id)
 261 {
 262         enum dc_lut_mode current_mode;
 263         enum dc_lut_mode next_mode;
 264         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 265
 266         if (params == NULL) {
 267                 REG_SET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], 0, MPCC_MCM_1DLUT_MODE, 0);
 268                 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)
 269                         mpc32_power_on_blnd_lut(mpc, mpcc_id, false);
 270                 return false;
 271         }
 272
 273         current_mode = mpc32_get_post1dlut_current(mpc, mpcc_id);
 274         if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
 275                 next_mode = LUT_RAM_A;
 276         else
 277                 next_mode = LUT_RAM_B;
 278
 279         mpc32_power_on_blnd_lut(mpc, mpcc_id, true);
 280         mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);
 281
 282         if (next_mode == LUT_RAM_A)
 283                 mpc32_program_post1dluta_settings(mpc, mpcc_id, params);
 284         else
 285                 mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);
 286
 287         mpc32_program_post1dlut_pwl(
 288                         mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);
 289
 290         REG_UPDATE_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
 291                         MPCC_MCM_1DLUT_MODE, 2,
 292                         MPCC_MCM_1DLUT_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
 293
 294         return true;
 295 }
 296
 297 static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)
 298 {
 299         enum dc_lut_mode mode;
 300         uint32_t state_mode;
 301         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 302
 303         REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
 304
 305         switch (state_mode) {
 306         case 0:
 307                 mode = LUT_BYPASS;
 308                 break;
 309         case 1:
 310                 mode = LUT_RAM_A;
 311                 break;
 312         case 2:
 313                 mode = LUT_RAM_B;
 314                 break;
 315         default:
 316                 mode = LUT_BYPASS;
 317                 break;
 318         }
 319
 320         return mode;
 321 }
 322
 323
 324 void mpc32_configure_shaper_lut(
 325                 struct mpc *mpc,
 326                 bool is_ram_a,
 327                 uint32_t mpcc_id)
 328 {
 329         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 330
 331         REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
 332                         MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7);
 333         REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
 334                         MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
 335         REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);
 336 }
 337
 338
 339 void mpc32_program_shaper_luta_settings(
 340                 struct mpc *mpc,
 341                 const struct pwl_params *params,
 342                 uint32_t mpcc_id)
 343 {
 344         const struct gamma_curve *curve;
 345         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 346
 347         REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
 348                 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
 349                 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 350         REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
 351                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
 352                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 353         REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
 354                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
 355                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 356
 357         REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
 358                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
 359                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
 360         REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
 361                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
 362                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
 363         REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
 364                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
 365                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
 366
 367         curve = params->arr_curve_points;
 368         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,
 369                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 370                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 371                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 372                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 373
 374         curve += 2;
 375         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,
 376                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 377                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 378                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 379                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 380
 381         curve += 2;
 382         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,
 383                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 384                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 385                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 386                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 387
 388         curve += 2;
 389         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,
 390                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 391                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 392                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 393                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 394
 395         curve += 2;
 396         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,
 397                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 398                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 399                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 400                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 401
 402         curve += 2;
 403         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,
 404                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 405                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 406                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 407                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 408
 409         curve += 2;
 410         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,
 411                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 412                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 413                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 414                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 415
 416         curve += 2;
 417         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,
 418                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 419                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 420                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 421                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 422
 423
 424         curve += 2;
 425         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,
 426                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 427                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 428                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 429                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 430
 431         curve += 2;
 432         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,
 433                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 434                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 435                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 436                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 437
 438         curve += 2;
 439         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,
 440                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 441                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 442                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 443                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 444
 445         curve += 2;
 446         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,
 447                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 448                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 449                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 450                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 451
 452         curve += 2;
 453         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,
 454                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 455                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 456                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 457                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 458
 459         curve += 2;
 460         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,
 461                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 462                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 463                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 464                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 465
 466         curve += 2;
 467         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,
 468                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 469                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 470                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 471                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 472
 473         curve += 2;
 474         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,
 475                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 476                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 477                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 478                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 479
 480         curve += 2;
 481         REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,
 482                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 483                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 484                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 485                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 486 }
 487
 488
 489 void mpc32_program_shaper_lutb_settings(
 490                 struct mpc *mpc,
 491                 const struct pwl_params *params,
 492                 uint32_t mpcc_id)
 493 {
 494         const struct gamma_curve *curve;
 495         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 496
 497         REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
 498                 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
 499                 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 500         REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
 501                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
 502                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 503         REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
 504                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
 505                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 506
 507         REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
 508                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
 509                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
 510         REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
 511                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
 512                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
 513         REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
 514                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
 515                         MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
 516
 517         curve = params->arr_curve_points;
 518         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,
 519                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 520                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 521                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 522                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 523
 524         curve += 2;
 525         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,
 526                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 527                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 528                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 529                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 530
 531
 532         curve += 2;
 533         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,
 534                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 535                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 536                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 537                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 538
 539         curve += 2;
 540         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,
 541                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 542                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 543                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 544                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 545
 546         curve += 2;
 547         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,
 548                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 549                 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 550                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 551                 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 552
 553         curve += 2;
 554         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,
 555                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 556                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 557                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 558                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 559
 560         curve += 2;
 561         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,
 562                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 563                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 564                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 565                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 566
 567         curve += 2;
 568         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,
 569                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 570                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 571                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 572                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 573
 574
 575         curve += 2;
 576         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,
 577                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 578                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 579                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 580                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 581
 582         curve += 2;
 583         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,
 584                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 585                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 586                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 587                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 588
 589         curve += 2;
 590         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,
 591                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 592                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 593                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 594                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 595
 596         curve += 2;
 597         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,
 598                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 599                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 600                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 601                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 602
 603         curve += 2;
 604         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,
 605                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 606                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 607                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 608                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 609
 610         curve += 2;
 611         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,
 612                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 613                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 614                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 615                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 616
 617         curve += 2;
 618         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,
 619                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 620                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 621                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 622                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 623
 624         curve += 2;
 625         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,
 626                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 627                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 628                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 629                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 630
 631         curve += 2;
 632         REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,
 633                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 634                         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 635                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 636                         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 637 }
 638
 639
 640 void mpc32_program_shaper_lut(
 641                 struct mpc *mpc,
 642                 const struct pwl_result_data *rgb,
 643                 uint32_t num,
 644                 uint32_t mpcc_id)
 645 {
 646         uint32_t i, red, green, blue;
 647         uint32_t  red_delta, green_delta, blue_delta;
 648         uint32_t  red_value, green_value, blue_value;
 649
 650         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 651
 652         for (i = 0 ; i < num; i++) {
 653
 654                 red   = rgb[i].red_reg;
 655                 green = rgb[i].green_reg;
 656                 blue  = rgb[i].blue_reg;
 657
 658                 red_delta   = rgb[i].delta_red_reg;
 659                 green_delta = rgb[i].delta_green_reg;
 660                 blue_delta  = rgb[i].delta_blue_reg;
 661
 662                 red_value   = ((red_delta   & 0x3ff) << 14) | (red   & 0x3fff);
 663                 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
 664                 blue_value  = ((blue_delta  & 0x3ff) << 14) | (blue  & 0x3fff);
 665
 666                 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);
 667                 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);
 668                 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);
 669         }
 670
 671 }
 672
 673
 674 void mpc32_power_on_shaper_3dlut(
 675                 struct mpc *mpc,
 676                 uint32_t mpcc_id,
 677                 bool power_on)
 678 {
 679         uint32_t power_status_shaper = 2;
 680         uint32_t power_status_3dlut  = 2;
 681         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 682         int max_retries = 10;
 683
 684         REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
 685         MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
 686         /* wait for memory to fully power up */
 687         if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
 688                 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
 689                 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
 690         }
 691
 692         /*read status is not mandatory, it is just for debugging*/
 693         REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
 694         REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
 695
 696         if (power_status_shaper != 0 && power_on == true)
 697                 BREAK_TO_DEBUGGER();
 698
 699         if (power_status_3dlut != 0 && power_on == true)
 700                 BREAK_TO_DEBUGGER();
 701 }
 702
 703
 704 bool mpc32_program_shaper(
 705                 struct mpc *mpc,
 706                 const struct pwl_params *params,
 707                 uint32_t mpcc_id)
 708 {
 709         enum dc_lut_mode current_mode;
 710         enum dc_lut_mode next_mode;
 711
 712         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 713
 714         if (params == NULL) {
 715                 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);
 716                 return false;
 717         }
 718
 719         if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
 720                 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
 721
 722         current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
 723
 724         if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
 725                 next_mode = LUT_RAM_B;
 726         else
 727                 next_mode = LUT_RAM_A;
 728
 729         mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);
 730
 731         if (next_mode == LUT_RAM_A)
 732                 mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);
 733         else
 734                 mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);
 735
 736         mpc32_program_shaper_lut(
 737                         mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);
 738
 739         REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
 740         mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
 741
 742         return true;
 743 }
 744
 745
 746 static enum dc_lut_mode get3dlut_config(
 747                         struct mpc *mpc,
 748                         bool *is_17x17x17,
 749                         bool *is_12bits_color_channel,
 750                         int mpcc_id)
 751 {
 752         uint32_t i_mode, i_enable_10bits, lut_size;
 753         enum dc_lut_mode mode;
 754         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 755
 756         REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
 757                         MPCC_MCM_3DLUT_MODE_CURRENT,  &i_mode);
 758
 759         REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
 760                         MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits);
 761
 762         switch (i_mode) {
 763         case 0:
 764                 mode = LUT_BYPASS;
 765                 break;
 766         case 1:
 767                 mode = LUT_RAM_A;
 768                 break;
 769         case 2:
 770                 mode = LUT_RAM_B;
 771                 break;
 772         default:
 773                 mode = LUT_BYPASS;
 774                 break;
 775         }
 776         if (i_enable_10bits > 0)
 777                 *is_12bits_color_channel = false;
 778         else
 779                 *is_12bits_color_channel = true;
 780
 781         REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
 782
 783         if (lut_size == 0)
 784                 *is_17x17x17 = true;
 785         else
 786                 *is_17x17x17 = false;
 787
 788         return mode;
 789 }
 790
 791
 792 void mpc32_select_3dlut_ram(
 793                 struct mpc *mpc,
 794                 enum dc_lut_mode mode,
 795                 bool is_color_channel_12bits,
 796                 uint32_t mpcc_id)
 797 {
 798         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 799
 800         REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
 801                 MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
 802                 MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);
 803 }
 804
 805
 806 void mpc32_select_3dlut_ram_mask(
 807                 struct mpc *mpc,
 808                 uint32_t ram_selection_mask,
 809                 uint32_t mpcc_id)
 810 {
 811         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 812
 813         REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,
 814                         ram_selection_mask);
 815         REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);
 816 }
 817
 818
 819 void mpc32_set3dlut_ram12(
 820                 struct mpc *mpc,
 821                 const struct dc_rgb *lut,
 822                 uint32_t entries,
 823                 uint32_t mpcc_id)
 824 {
 825         uint32_t i, red, green, blue, red1, green1, blue1;
 826         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 827
 828         for (i = 0 ; i < entries; i += 2) {
 829                 red   = lut[i].red<<4;
 830                 green = lut[i].green<<4;
 831                 blue  = lut[i].blue<<4;
 832                 red1   = lut[i+1].red<<4;
 833                 green1 = lut[i+1].green<<4;
 834                 blue1  = lut[i+1].blue<<4;
 835
 836                 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
 837                                 MPCC_MCM_3DLUT_DATA0, red,
 838                                 MPCC_MCM_3DLUT_DATA1, red1);
 839
 840                 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
 841                                 MPCC_MCM_3DLUT_DATA0, green,
 842                                 MPCC_MCM_3DLUT_DATA1, green1);
 843
 844                 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
 845                                 MPCC_MCM_3DLUT_DATA0, blue,
 846                                 MPCC_MCM_3DLUT_DATA1, blue1);
 847         }
 848 }
 849
 850
 851 void mpc32_set3dlut_ram10(
 852                 struct mpc *mpc,
 853                 const struct dc_rgb *lut,
 854                 uint32_t entries,
 855                 uint32_t mpcc_id)
 856 {
 857         uint32_t i, red, green, blue, value;
 858         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 859
 860         for (i = 0; i < entries; i++) {
 861                 red   = lut[i].red;
 862                 green = lut[i].green;
 863                 blue  = lut[i].blue;
 864                 //should we shift red 22bit and green 12?
 865                 value = (red<<20) | (green<<10) | blue;
 866
 867                 REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);
 868         }
 869
 870 }
 871
 872
 873 static void mpc32_set_3dlut_mode(
 874                 struct mpc *mpc,
 875                 enum dc_lut_mode mode,
 876                 bool is_color_channel_12bits,
 877                 bool is_lut_size17x17x17,
 878                 uint32_t mpcc_id)
 879 {
 880         uint32_t lut_mode;
 881         struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 882
 883         // set default 3DLUT to pre-blend
 884         // TODO: implement movable CM location
 885         REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], MPCC_MOVABLE_CM_LOCATION_CNTL, 0);
 886
 887         if (mode == LUT_BYPASS)
 888                 lut_mode = 0;
 889         else if (mode == LUT_RAM_A)
 890                 lut_mode = 1;
 891         else
 892                 lut_mode = 2;
 893
 894         REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
 895                         MPCC_MCM_3DLUT_MODE, lut_mode,
 896                         MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
 897 }
 898
 899
 900 bool mpc32_program_3dlut(
 901                 struct mpc *mpc,
 902                 const struct tetrahedral_params *params,
 903                 int mpcc_id)
 904 {
 905         enum dc_lut_mode mode;
 906         bool is_17x17x17;
 907         bool is_12bits_color_channel;
 908         const struct dc_rgb *lut0;
 909         const struct dc_rgb *lut1;
 910         const struct dc_rgb *lut2;
 911         const struct dc_rgb *lut3;
 912         int lut_size0;
 913         int lut_size;
 914
 915         if (params == NULL) {
 916                 mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);
 917                 return false;
 918         }
 919         mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
 920
 921         mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);
 922
 923         if (mode == LUT_BYPASS || mode == LUT_RAM_B)
 924                 mode = LUT_RAM_A;
 925         else
 926                 mode = LUT_RAM_B;
 927
 928         is_17x17x17 = !params->use_tetrahedral_9;
 929         is_12bits_color_channel = params->use_12bits;
 930         if (is_17x17x17) {
 931                 lut0 = params->tetrahedral_17.lut0;
 932                 lut1 = params->tetrahedral_17.lut1;
 933                 lut2 = params->tetrahedral_17.lut2;
 934                 lut3 = params->tetrahedral_17.lut3;
 935                 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
 936                                         sizeof(params->tetrahedral_17.lut0[0]);
 937                 lut_size  = sizeof(params->tetrahedral_17.lut1)/
 938                                         sizeof(params->tetrahedral_17.lut1[0]);
 939         } else {
 940                 lut0 = params->tetrahedral_9.lut0;
 941                 lut1 = params->tetrahedral_9.lut1;
 942                 lut2 = params->tetrahedral_9.lut2;
 943                 lut3 = params->tetrahedral_9.lut3;
 944                 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
 945                                 sizeof(params->tetrahedral_9.lut0[0]);
 946                 lut_size  = sizeof(params->tetrahedral_9.lut1)/
 947                                 sizeof(params->tetrahedral_9.lut1[0]);
 948                 }
 949
 950         mpc32_select_3dlut_ram(mpc, mode,
 951                                 is_12bits_color_channel, mpcc_id);
 952         mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);
 953         if (is_12bits_color_channel)
 954                 mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);
 955         else
 956                 mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);
 957
 958         mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);
 959         if (is_12bits_color_channel)
 960                 mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);
 961         else
 962                 mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);
 963
 964         mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);
 965         if (is_12bits_color_channel)
 966                 mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);
 967         else
 968                 mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);
 969
 970         mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);
 971         if (is_12bits_color_channel)
 972                 mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);
 973         else
 974                 mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);
 975
 976         mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
 977                                         is_17x17x17, mpcc_id);
 978
 979         if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
 980                 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
 981
 982         return true;
 983 }
 984
 985 static const struct mpc_funcs dcn32_mpc_funcs = {
 986         .read_mpcc_state = mpc1_read_mpcc_state,
 987         .insert_plane = mpc1_insert_plane,
 988         .remove_mpcc = mpc1_remove_mpcc,
 989         .mpc_init = mpc32_mpc_init,
 990         .mpc_init_single_inst = mpc1_mpc_init_single_inst,
 991         .update_blending = mpc2_update_blending,
 992         .cursor_lock = mpc1_cursor_lock,
 993         .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
 994         .wait_for_idle = mpc2_assert_idle_mpcc,
 995         .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
 996         .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
 997         .set_denorm =  mpc3_set_denorm,
 998         .set_denorm_clamp = mpc3_set_denorm_clamp,
 999         .set_output_csc = mpc3_set_output_csc,
1000         .set_ocsc_default = mpc3_set_ocsc_default,
1001         .set_output_gamma = mpc3_set_output_gamma,
1002         .insert_plane_to_secondary = NULL,
1003         .remove_mpcc_from_secondary =  NULL,
1004         .set_dwb_mux = mpc3_set_dwb_mux,
1005         .disable_dwb_mux = mpc3_disable_dwb_mux,
1006         .is_dwb_idle = mpc3_is_dwb_idle,
1007         .set_out_rate_control = mpc3_set_out_rate_control,
1008         .set_gamut_remap = mpc3_set_gamut_remap,
1009         .program_shaper = mpc32_program_shaper,
1010         .program_3dlut = mpc32_program_3dlut,
1011         .program_1dlut = mpc32_program_post1dlut,
1012         .acquire_rmu = NULL,
1013         .release_rmu = NULL,
1014         .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
1015         .get_mpc_out_mux = mpc1_get_mpc_out_mux,
1016         .set_bg_color = mpc1_set_bg_color,
1017 };
1018
1019
1020 void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
1021         struct dc_context *ctx,
1022         const struct dcn30_mpc_registers *mpc_regs,
1023         const struct dcn30_mpc_shift *mpc_shift,
1024         const struct dcn30_mpc_mask *mpc_mask,
1025         int num_mpcc,
1026         int num_rmu)
1027 {
1028         int i;
1029
1030         mpc30->base.ctx = ctx;
1031
1032         mpc30->base.funcs = &dcn32_mpc_funcs;
1033
1034         mpc30->mpc_regs = mpc_regs;
1035         mpc30->mpc_shift = mpc_shift;
1036         mpc30->mpc_mask = mpc_mask;
1037
1038         mpc30->mpcc_in_use_mask = 0;
1039         mpc30->num_mpcc = num_mpcc;
1040         mpc30->num_rmu = num_rmu;
1041
1042         for (i = 0; i < MAX_MPCC; i++)
1043                 mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i);
1044 }