drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "reg_helper.h"
  27 #include "core_types.h"
  28 #include "dcn32_dccg.h"
  29
  30 #define TO_DCN_DCCG(dccg)\
  31         container_of(dccg, struct dcn_dccg, base)
  32
  33 #define REG(reg) \
  34         (dccg_dcn->regs->reg)
  35
  36 #undef FN
  37 #define FN(reg_name, field_name) \
  38         dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
  39
  40 #define CTX \
  41         dccg_dcn->base.ctx
  42 #define DC_LOGGER \
  43         dccg->ctx->logger
  44
  45 enum pixel_rate_div {
  46         PIXEL_RATE_DIV_BY_1 = 0,
  47         PIXEL_RATE_DIV_BY_2 = 1,
  48         PIXEL_RATE_DIV_BY_4 = 3
  49 };
  50
  51 static void dccg32_set_pixel_rate_div(
  52                 struct dccg *dccg,
  53                 uint32_t otg_inst,
  54                 enum pixel_rate_div k1,
  55                 enum pixel_rate_div k2)
  56 {
  57         struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
  58
  59         switch (otg_inst) {
  60         case 0:
  61                 REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
  62                                 OTG0_PIXEL_RATE_DIVK1, k1,
  63                                 OTG0_PIXEL_RATE_DIVK2, k2);
  64                 break;
  65         case 1:
  66                 REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
  67                                 OTG1_PIXEL_RATE_DIVK1, k1,
  68                                 OTG1_PIXEL_RATE_DIVK2, k2);
  69                 break;
  70         case 2:
  71                 REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
  72                                 OTG2_PIXEL_RATE_DIVK1, k1,
  73                                 OTG2_PIXEL_RATE_DIVK2, k2);
  74                 break;
  75         case 3:
  76                 REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
  77                                 OTG3_PIXEL_RATE_DIVK1, k1,
  78                                 OTG3_PIXEL_RATE_DIVK2, k2);
  79                 break;
  80         default:
  81                 BREAK_TO_DEBUGGER();
  82                 return;
  83         }
  84 }
  85
  86 static void dccg32_set_dtbclk_p_src(
  87                 struct dccg *dccg,
  88                 enum streamclk_source src,
  89                 uint32_t otg_inst)
  90 {
  91         struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
  92
  93         uint32_t p_src_sel = 0; /* selects dprefclk */
  94         if (src == DTBCLK0)
  95                 p_src_sel = 2;  /* selects dtbclk0 */
  96
  97         switch (otg_inst) {
  98         case 0:
  99                 if (src == REFCLK)
 100                         REG_UPDATE(DTBCLK_P_CNTL,
 101                                         DTBCLK_P0_EN, 0);
 102                 else
 103                         REG_UPDATE_2(DTBCLK_P_CNTL,
 104                                         DTBCLK_P0_SRC_SEL, p_src_sel,
 105                                         DTBCLK_P0_EN, 1);
 106                 break;
 107         case 1:
 108                 if (src == REFCLK)
 109                         REG_UPDATE(DTBCLK_P_CNTL,
 110                                         DTBCLK_P1_EN, 0);
 111                 else
 112                         REG_UPDATE_2(DTBCLK_P_CNTL,
 113                                         DTBCLK_P1_SRC_SEL, p_src_sel,
 114                                         DTBCLK_P1_EN, 1);
 115                 break;
 116         case 2:
 117                 if (src == REFCLK)
 118                         REG_UPDATE(DTBCLK_P_CNTL,
 119                                         DTBCLK_P2_EN, 0);
 120                 else
 121                         REG_UPDATE_2(DTBCLK_P_CNTL,
 122                                         DTBCLK_P2_SRC_SEL, p_src_sel,
 123                                         DTBCLK_P2_EN, 1);
 124                 break;
 125         case 3:
 126                 if (src == REFCLK)
 127                         REG_UPDATE(DTBCLK_P_CNTL,
 128                                         DTBCLK_P3_EN, 0);
 129                 else
 130                         REG_UPDATE_2(DTBCLK_P_CNTL,
 131                                         DTBCLK_P3_SRC_SEL, p_src_sel,
 132                                         DTBCLK_P3_EN, 1);
 133                 break;
 134         default:
 135                 BREAK_TO_DEBUGGER();
 136                 return;
 137         }
 138
 139 }
 140
 141 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
 142 void dccg32_set_dtbclk_dto(
 143                 struct dccg *dccg,
 144                 int otg_inst,
 145                 int pixclk_khz,
 146                 int num_odm_segments,
 147                 const struct dc_crtc_timing *timing)
 148 {
 149         struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 150         /* DTO Output Rate / Pixel Rate = 1/4 */
 151         int req_dtbclk_khz = pixclk_khz / 4;
 152
 153         if (dccg->ref_dtbclk_khz && req_dtbclk_khz) {
 154                 uint32_t modulo, phase;
 155
 156                 // phase / modulo = dtbclk / dtbclk ref
 157                 modulo = 0xffffffff;
 158                 phase = (((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1) / dccg->ref_dtbclk_khz;
 159
 160                 REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], modulo);
 161                 REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], phase);
 162
 163                 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
 164                                 DTBCLK_DTO_ENABLE[otg_inst], 1);
 165
 166                 REG_WAIT(OTG_PIXEL_RATE_CNTL[otg_inst],
 167                                 DTBCLKDTO_ENABLE_STATUS[otg_inst], 1,
 168                                 1, 100);
 169
 170                 /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
 171                 dccg32_set_pixel_rate_div(dccg, otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
 172
 173                 /* The recommended programming sequence to enable DTBCLK DTO to generate
 174                  * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
 175                  * be set only after DTO is enabled
 176                  */
 177                 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
 178                                 PIPE_DTO_SRC_SEL[otg_inst], 2);
 179
 180                 dccg->dtbclk_khz[otg_inst] = req_dtbclk_khz;
 181         } else {
 182                 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
 183                                 DTBCLK_DTO_ENABLE[otg_inst], 0,
 184                                 PIPE_DTO_SRC_SEL[otg_inst], 1);
 185
 186                 REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], 0);
 187                 REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], 0);
 188
 189                 dccg->dtbclk_khz[otg_inst] = 0;
 190         }
 191 }
 192
 193 static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
 194                 unsigned int xtalin_freq_inKhz,
 195                 unsigned int *dccg_ref_freq_inKhz)
 196 {
 197         /*
 198          * Assume refclk is sourced from xtalin
 199          * expect 100MHz
 200          */
 201         *dccg_ref_freq_inKhz = xtalin_freq_inKhz;
 202         return;
 203 }
 204
 205 void dccg32_set_dpstreamclk(
 206                 struct dccg *dccg,
 207                 enum streamclk_source src,
 208                 int otg_inst)
 209 {
 210         struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 211
 212         /* set the dtbclk_p source */
 213         dccg32_set_dtbclk_p_src(dccg, src, otg_inst);
 214
 215         /* enabled to select one of the DTBCLKs for pipe */
 216         switch (otg_inst)
 217         {
 218         case 0:
 219                 REG_UPDATE_2(DPSTREAMCLK_CNTL,
 220                              DPSTREAMCLK0_EN,
 221                              (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, 0);
 222                 break;
 223         case 1:
 224                 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
 225                              (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, 1);
 226                 break;
 227         case 2:
 228                 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
 229                              (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, 2);
 230                 break;
 231         case 3:
 232                 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
 233                              (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, 3);
 234                 break;
 235         default:
 236                 BREAK_TO_DEBUGGER();
 237                 return;
 238         }
 239 }
 240
 241 void dccg32_otg_add_pixel(struct dccg *dccg,
 242                 uint32_t otg_inst)
 243 {
 244         struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 245
 246         REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
 247                         OTG_ADD_PIXEL[otg_inst], 1);
 248 }
 249
 250 void dccg32_otg_drop_pixel(struct dccg *dccg,
 251                 uint32_t otg_inst)
 252 {
 253         struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 254
 255         REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
 256                         OTG_DROP_PIXEL[otg_inst], 1);
 257 }
 258
 259 static const struct dccg_funcs dccg32_funcs = {
 260         .update_dpp_dto = dccg2_update_dpp_dto,
 261         .get_dccg_ref_freq = dccg32_get_dccg_ref_freq,
 262         .dccg_init = dccg31_init,
 263         .set_dpstreamclk = dccg32_set_dpstreamclk,
 264         .enable_symclk32_se = dccg31_enable_symclk32_se,
 265         .disable_symclk32_se = dccg31_disable_symclk32_se,
 266         .enable_symclk32_le = dccg31_enable_symclk32_le,
 267         .disable_symclk32_le = dccg31_disable_symclk32_le,
 268         .set_physymclk = dccg31_set_physymclk,
 269         .set_dtbclk_dto = dccg32_set_dtbclk_dto,
 270         .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
 271         .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
 272         .otg_add_pixel = dccg32_otg_add_pixel,
 273         .otg_drop_pixel = dccg32_otg_drop_pixel,
 274 };
 275
 276 struct dccg *dccg32_create(
 277         struct dc_context *ctx,
 278         const struct dccg_registers *regs,
 279         const struct dccg_shift *dccg_shift,
 280         const struct dccg_mask *dccg_mask)
 281 {
 282         struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
 283         struct dccg *base;
 284
 285         if (dccg_dcn == NULL) {
 286                 BREAK_TO_DEBUGGER();
 287                 return NULL;
 288         }
 289
 290         base = &dccg_dcn->base;
 291         base->ctx = ctx;
 292         base->funcs = &dccg32_funcs;
 293
 294         dccg_dcn->regs = regs;
 295         dccg_dcn->dccg_shift = dccg_shift;
 296         dccg_dcn->dccg_mask = dccg_mask;
 297
 298         return &dccg_dcn->base;
 299 }