1 // SPDX-License-Identifier: MIT
3 * Copyright 2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "dm_services.h"
31 #include "dcn31/dcn31_init.h"
32 #include "dcn314/dcn314_init.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn314_resource.h"
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40 #include "dcn31/dcn31_resource.h"
42 #include "dcn10/dcn10_ipp.h"
43 #include "dcn30/dcn30_hubbub.h"
44 #include "dcn31/dcn31_hubbub.h"
45 #include "dcn30/dcn30_mpc.h"
46 #include "dcn31/dcn31_hubp.h"
47 #include "irq/dcn31/irq_service_dcn31.h"
48 #include "irq/dcn314/irq_service_dcn314.h"
49 #include "dcn30/dcn30_dpp.h"
50 #include "dcn314/dcn314_optc.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_hwseq.h"
53 #include "dce110/dce110_hw_sequencer.h"
54 #include "dcn30/dcn30_opp.h"
55 #include "dcn20/dcn20_dsc.h"
56 #include "dcn30/dcn30_vpg.h"
57 #include "dcn30/dcn30_afmt.h"
58 #include "dcn31/dcn31_dio_link_encoder.h"
59 #include "dcn314/dcn314_dio_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 #include "dcn31/dcn31_apg.h"
63 #include "dcn31/dcn31_vpg.h"
64 #include "dcn31/dcn31_afmt.h"
65 #include "dce/dce_clock_source.h"
66 #include "dce/dce_audio.h"
67 #include "dce/dce_hwseq.h"
69 #include "virtual/virtual_stream_encoder.h"
70 #include "dce110/dce110_resource.h"
71 #include "dml/display_mode_vba.h"
72 #include "dml/dcn31/dcn31_fpu.h"
73 #include "dml/dcn314/dcn314_fpu.h"
74 #include "dcn314/dcn314_dccg.h"
75 #include "dcn10/dcn10_resource.h"
76 #include "dcn31/dcn31_panel_cntl.h"
77 #include "dcn314/dcn314_hwseq.h"
79 #include "dcn30/dcn30_dwb.h"
80 #include "dcn30/dcn30_mmhubbub.h"
82 #include "dcn/dcn_3_1_4_offset.h"
83 #include "dcn/dcn_3_1_4_sh_mask.h"
84 #include "dpcs/dpcs_3_1_4_offset.h"
85 #include "dpcs/dpcs_3_1_4_sh_mask.h"
87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
90 #include "reg_helper.h"
91 #include "dce/dmub_abm.h"
92 #include "dce/dmub_psr.h"
93 #include "dce/dce_aux.h"
94 #include "dce/dce_i2c.h"
95 #include "dml/dcn314/display_mode_vba_314.h"
96 #include "vm_helper.h"
97 #include "dcn20/dcn20_vmid.h"
99 #include "link_enc_cfg.h"
101 #define DCN_BASE__INST0_SEG1 0x000000C0
102 #define DCN_BASE__INST0_SEG2 0x000034C0
103 #define DCN_BASE__INST0_SEG3 0x00009000
105 #define NBIO_BASE__INST0_SEG1 0x00000014
107 #define MAX_INSTANCE 7
108 #define MAX_SEGMENT 8
110 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a
111 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1
112 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b
113 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1
114 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e
115 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
117 struct IP_BASE_INSTANCE {
118 unsigned int segment[MAX_SEGMENT];
122 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
125 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } };
134 #define DC_LOGGER_INIT(logger)
136 enum dcn31_clk_src_array_id {
145 /* begin *********************
146 * macros to expend register list macro defined in HW object header file
150 /* TODO awful hack. fixup dcn20_dwb.h */
152 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
154 #define BASE(seg) BASE_INNER(seg)
156 #define SR(reg_name)\
157 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
160 #define SRI(reg_name, block, id)\
161 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
164 #define SRI2(reg_name, block, id)\
165 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
168 #define SRIR(var_name, reg_name, block, id)\
169 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## reg_name
172 #define SRII(reg_name, block, id)\
173 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
174 reg ## block ## id ## _ ## reg_name
176 #define SRII_MPC_RMU(reg_name, block, id)\
177 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178 reg ## block ## id ## _ ## reg_name
180 #define SRII_DWB(reg_name, temp_name, block, id)\
181 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
182 reg ## block ## id ## _ ## temp_name
184 #define DCCG_SRII(reg_name, block, id)\
185 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 reg ## block ## id ## _ ## reg_name
188 #define VUPDATE_SRII(reg_name, block, id)\
189 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
190 reg ## reg_name ## _ ## block ## id
193 #define NBIO_BASE_INNER(seg) \
194 NBIO_BASE__INST0_SEG ## seg
196 #define NBIO_BASE(seg) \
199 #define NBIO_SR(reg_name)\
200 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
201 regBIF_BX2_ ## reg_name
204 #define MMHUB_BASE_INNER(seg) \
205 MMHUB_BASE__INST0_SEG ## seg
207 #define MMHUB_BASE(seg) \
208 MMHUB_BASE_INNER(seg)
210 #define MMHUB_SR(reg_name)\
211 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
215 #define CLK_BASE_INNER(seg) \
216 CLK_BASE__INST0_SEG ## seg
218 #define CLK_BASE(seg) \
221 #define CLK_SRI(reg_name, block, inst)\
222 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
223 reg ## block ## _ ## inst ## _ ## reg_name
226 static const struct bios_registers bios_regs = {
227 NBIO_SR(BIOS_SCRATCH_3),
228 NBIO_SR(BIOS_SCRATCH_6)
231 #define clk_src_regs(index, pllid)\
233 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
236 static const struct dce110_clk_src_regs clk_src_regs[] = {
244 static const struct dce110_clk_src_shift cs_shift = {
245 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
248 static const struct dce110_clk_src_mask cs_mask = {
249 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
252 #define abm_regs(id)\
254 ABM_DCN302_REG_LIST(id)\
257 static const struct dce_abm_registers abm_regs[] = {
264 static const struct dce_abm_shift abm_shift = {
265 ABM_MASK_SH_LIST_DCN30(__SHIFT)
268 static const struct dce_abm_mask abm_mask = {
269 ABM_MASK_SH_LIST_DCN30(_MASK)
272 #define audio_regs(id)\
274 AUD_COMMON_REG_LIST(id)\
277 static const struct dce_audio_registers audio_regs[] = {
287 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
288 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
289 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
290 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
292 static const struct dce_audio_shift audio_shift = {
293 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
296 static const struct dce_audio_mask audio_mask = {
297 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
300 #define vpg_regs(id)\
302 VPG_DCN31_REG_LIST(id)\
305 static const struct dcn31_vpg_registers vpg_regs[] = {
318 static const struct dcn31_vpg_shift vpg_shift = {
319 DCN31_VPG_MASK_SH_LIST(__SHIFT)
322 static const struct dcn31_vpg_mask vpg_mask = {
323 DCN31_VPG_MASK_SH_LIST(_MASK)
326 #define afmt_regs(id)\
328 AFMT_DCN31_REG_LIST(id)\
331 static const struct dcn31_afmt_registers afmt_regs[] = {
340 static const struct dcn31_afmt_shift afmt_shift = {
341 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
344 static const struct dcn31_afmt_mask afmt_mask = {
345 DCN31_AFMT_MASK_SH_LIST(_MASK)
348 #define apg_regs(id)\
350 APG_DCN31_REG_LIST(id)\
353 static const struct dcn31_apg_registers apg_regs[] = {
360 static const struct dcn31_apg_shift apg_shift = {
361 DCN31_APG_MASK_SH_LIST(__SHIFT)
364 static const struct dcn31_apg_mask apg_mask = {
365 DCN31_APG_MASK_SH_LIST(_MASK)
368 #define stream_enc_regs(id)\
370 SE_DCN314_REG_LIST(id)\
373 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
381 static const struct dcn10_stream_encoder_shift se_shift = {
382 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
385 static const struct dcn10_stream_encoder_mask se_mask = {
386 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
390 #define aux_regs(id)\
392 DCN2_AUX_REG_LIST(id)\
395 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
403 #define hpd_regs(id)\
408 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
416 #define link_regs(id, phyid)\
418 LE_DCN31_REG_LIST(id), \
419 UNIPHY_DCN2_REG_LIST(phyid), \
422 static const struct dce110_aux_registers_shift aux_shift = {
423 DCN_AUX_MASK_SH_LIST(__SHIFT)
426 static const struct dce110_aux_registers_mask aux_mask = {
427 DCN_AUX_MASK_SH_LIST(_MASK)
430 static const struct dcn10_link_enc_registers link_enc_regs[] = {
438 static const struct dcn10_link_enc_shift le_shift = {
439 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
440 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
443 static const struct dcn10_link_enc_mask le_mask = {
444 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
445 DPCS_DCN31_MASK_SH_LIST(_MASK)
448 #define hpo_dp_stream_encoder_reg_list(id)\
450 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
453 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
454 hpo_dp_stream_encoder_reg_list(0),
455 hpo_dp_stream_encoder_reg_list(1),
456 hpo_dp_stream_encoder_reg_list(2),
459 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
460 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
463 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
464 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
468 #define hpo_dp_link_encoder_reg_list(id)\
470 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
471 DCN3_1_RDPCSTX_REG_LIST(0),\
472 DCN3_1_RDPCSTX_REG_LIST(1),\
473 DCN3_1_RDPCSTX_REG_LIST(2),\
476 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
477 hpo_dp_link_encoder_reg_list(0),
478 hpo_dp_link_encoder_reg_list(1),
481 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
482 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
485 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
486 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
489 #define dpp_regs(id)\
491 DPP_REG_LIST_DCN30(id),\
494 static const struct dcn3_dpp_registers dpp_regs[] = {
501 static const struct dcn3_dpp_shift tf_shift = {
502 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
505 static const struct dcn3_dpp_mask tf_mask = {
506 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
509 #define opp_regs(id)\
511 OPP_REG_LIST_DCN30(id),\
514 static const struct dcn20_opp_registers opp_regs[] = {
521 static const struct dcn20_opp_shift opp_shift = {
522 OPP_MASK_SH_LIST_DCN20(__SHIFT)
525 static const struct dcn20_opp_mask opp_mask = {
526 OPP_MASK_SH_LIST_DCN20(_MASK)
529 #define aux_engine_regs(id)\
531 AUX_COMMON_REG_LIST0(id), \
534 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
537 static const struct dce110_aux_registers aux_engine_regs[] = {
545 #define dwbc_regs_dcn3(id)\
547 DWBC_COMMON_REG_LIST_DCN30(id),\
550 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
554 static const struct dcn30_dwbc_shift dwbc30_shift = {
555 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
558 static const struct dcn30_dwbc_mask dwbc30_mask = {
559 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
562 #define mcif_wb_regs_dcn3(id)\
564 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
567 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
571 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
572 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
575 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
576 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
579 #define dsc_regsDCN314(id)\
581 DSC_REG_LIST_DCN314(id)\
584 static const struct dcn20_dsc_registers dsc_regs[] = {
591 static const struct dcn20_dsc_shift dsc_shift = {
592 DSC_REG_LIST_SH_MASK_DCN314(__SHIFT)
595 static const struct dcn20_dsc_mask dsc_mask = {
596 DSC_REG_LIST_SH_MASK_DCN314(_MASK)
599 static const struct dcn30_mpc_registers mpc_regs = {
600 MPC_REG_LIST_DCN3_0(0),
601 MPC_REG_LIST_DCN3_0(1),
602 MPC_REG_LIST_DCN3_0(2),
603 MPC_REG_LIST_DCN3_0(3),
604 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
605 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
606 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
607 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
608 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
609 MPC_RMU_REG_LIST_DCN3AG(0),
610 MPC_RMU_REG_LIST_DCN3AG(1),
611 //MPC_RMU_REG_LIST_DCN3AG(2),
612 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
615 static const struct dcn30_mpc_shift mpc_shift = {
616 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
619 static const struct dcn30_mpc_mask mpc_mask = {
620 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
623 #define optc_regs(id)\
624 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
626 static const struct dcn_optc_registers optc_regs[] = {
633 static const struct dcn_optc_shift optc_shift = {
634 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
637 static const struct dcn_optc_mask optc_mask = {
638 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
641 #define hubp_regs(id)\
643 HUBP_REG_LIST_DCN30(id)\
646 static const struct dcn_hubp2_registers hubp_regs[] = {
654 static const struct dcn_hubp2_shift hubp_shift = {
655 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
658 static const struct dcn_hubp2_mask hubp_mask = {
659 HUBP_MASK_SH_LIST_DCN31(_MASK)
661 static const struct dcn_hubbub_registers hubbub_reg = {
662 HUBBUB_REG_LIST_DCN31(0)
665 static const struct dcn_hubbub_shift hubbub_shift = {
666 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
669 static const struct dcn_hubbub_mask hubbub_mask = {
670 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
673 static const struct dccg_registers dccg_regs = {
674 DCCG_REG_LIST_DCN314()
677 static const struct dccg_shift dccg_shift = {
678 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
681 static const struct dccg_mask dccg_mask = {
682 DCCG_MASK_SH_LIST_DCN314(_MASK)
686 #define SRII2(reg_name_pre, reg_name_post, id)\
687 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
688 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
689 reg ## reg_name_pre ## id ## _ ## reg_name_post
692 #define HWSEQ_DCN31_REG_LIST()\
693 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
694 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
695 SR(DIO_MEM_PWR_CTRL), \
696 SR(ODM_MEM_PWR_CTRL3), \
697 SR(DMU_MEM_PWR_CNTL), \
698 SR(MMHUBBUB_MEM_PWR_CNTL), \
699 SR(DCCG_GATE_DISABLE_CNTL), \
700 SR(DCCG_GATE_DISABLE_CNTL2), \
702 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
703 SRII(PIXEL_RATE_CNTL, OTG, 0), \
704 SRII(PIXEL_RATE_CNTL, OTG, 1),\
705 SRII(PIXEL_RATE_CNTL, OTG, 2),\
706 SRII(PIXEL_RATE_CNTL, OTG, 3),\
707 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
708 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
709 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
710 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
711 SR(MICROSECOND_TIME_BASE_DIV), \
712 SR(MILLISECOND_TIME_BASE_DIV), \
713 SR(DISPCLK_FREQ_CHANGE_CNTL), \
714 SR(RBBMIF_TIMEOUT_DIS), \
715 SR(RBBMIF_TIMEOUT_DIS_2), \
716 SR(DCHUBBUB_CRC_CTRL), \
717 SR(DPP_TOP0_DPP_CRC_CTRL), \
718 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
719 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
721 SR(MPC_CRC_RESULT_GB), \
722 SR(MPC_CRC_RESULT_C), \
723 SR(MPC_CRC_RESULT_AR), \
724 SR(DOMAIN0_PG_CONFIG), \
725 SR(DOMAIN1_PG_CONFIG), \
726 SR(DOMAIN2_PG_CONFIG), \
727 SR(DOMAIN3_PG_CONFIG), \
728 SR(DOMAIN16_PG_CONFIG), \
729 SR(DOMAIN17_PG_CONFIG), \
730 SR(DOMAIN18_PG_CONFIG), \
731 SR(DOMAIN19_PG_CONFIG), \
732 SR(DOMAIN0_PG_STATUS), \
733 SR(DOMAIN1_PG_STATUS), \
734 SR(DOMAIN2_PG_STATUS), \
735 SR(DOMAIN3_PG_STATUS), \
736 SR(DOMAIN16_PG_STATUS), \
737 SR(DOMAIN17_PG_STATUS), \
738 SR(DOMAIN18_PG_STATUS), \
739 SR(DOMAIN19_PG_STATUS), \
746 SR(DC_IP_REQUEST_CNTL), \
747 SR(AZALIA_AUDIO_DTO), \
748 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
749 SR(HPO_TOP_HW_CONTROL)
751 static const struct dce_hwseq_registers hwseq_reg = {
752 HWSEQ_DCN31_REG_LIST()
755 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
756 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
757 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
758 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
759 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
760 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
761 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
762 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
763 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
764 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
765 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
766 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
767 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
768 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
769 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
770 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
771 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
772 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
773 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
774 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
775 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
776 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
777 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
778 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
779 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
780 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
781 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
782 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
783 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
784 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
785 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
786 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
787 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
788 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
789 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
790 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
791 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
793 static const struct dce_hwseq_shift hwseq_shift = {
794 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
797 static const struct dce_hwseq_mask hwseq_mask = {
798 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
800 #define vmid_regs(id)\
802 DCN20_VMID_REG_LIST(id)\
805 static const struct dcn_vmid_registers vmid_regs[] = {
824 static const struct dcn20_vmid_shift vmid_shifts = {
825 DCN20_VMID_MASK_SH_LIST(__SHIFT)
828 static const struct dcn20_vmid_mask vmid_masks = {
829 DCN20_VMID_MASK_SH_LIST(_MASK)
832 static const struct resource_caps res_cap_dcn314 = {
833 .num_timing_generator = 4,
835 .num_video_plane = 4,
837 .num_stream_encoder = 5,
838 .num_dig_link_enc = 5,
839 .num_hpo_dp_stream_encoder = 4,
840 .num_hpo_dp_link_encoder = 2,
849 static const struct dc_plane_cap plane_cap = {
850 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
851 .blends_with_above = true,
852 .blends_with_below = true,
853 .per_pixel_alpha = true,
855 .pixel_format_support = {
863 .max_upscale_factor = {
869 // 6:1 downscaling ratio: 1000/6 = 166.666
870 .max_downscale_factor = {
879 static const struct dc_debug_options debug_defaults_drv = {
880 .disable_z10 = true, /*hw not support it*/
881 .disable_dmcu = true,
882 .force_abm_enable = false,
883 .timing_trace = false,
885 .disable_pplib_clock_request = false,
886 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
887 .force_single_disp_pipe_split = false,
888 .disable_dcc = DCC_ENABLE,
890 .performance_trace = false,
891 .max_downscale_src_width = 4096,/*upto true 4k*/
892 .disable_pplib_wm_range = false,
893 .scl_reset_length10 = true,
894 .sanity_checks = false,
895 .underflow_assert_delay_us = 0xFFFFFFFF,
896 .dwb_fi_phase = -1, // -1 = disable,
897 .dmub_command_table = true,
898 .pstate_enabled = true,
900 .enable_mem_low_power = {
904 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
913 .optimize_edp_link_rate = true,
914 .enable_sw_cntl_psr = true,
915 .seamless_boot_odm_combine = true
918 static const struct dc_debug_options debug_defaults_diags = {
919 .disable_dmcu = true,
920 .force_abm_enable = false,
921 .timing_trace = true,
923 .disable_dpp_power_gate = true,
924 .disable_hubp_power_gate = true,
925 .disable_clock_gate = true,
926 .disable_pplib_clock_request = true,
927 .disable_pplib_wm_range = true,
928 .disable_stutter = false,
929 .scl_reset_length10 = true,
930 .dwb_fi_phase = -1, // -1 = disable
931 .dmub_command_table = true,
932 .enable_tri_buf = true,
936 static void dcn31_dpp_destroy(struct dpp **dpp)
938 kfree(TO_DCN20_DPP(*dpp));
942 static struct dpp *dcn31_dpp_create(
943 struct dc_context *ctx,
946 struct dcn3_dpp *dpp =
947 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
952 if (dpp3_construct(dpp, ctx, inst,
953 &dpp_regs[inst], &tf_shift, &tf_mask))
961 static struct output_pixel_processor *dcn31_opp_create(
962 struct dc_context *ctx, uint32_t inst)
964 struct dcn20_opp *opp =
965 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
972 dcn20_opp_construct(opp, ctx, inst,
973 &opp_regs[inst], &opp_shift, &opp_mask);
977 static struct dce_aux *dcn31_aux_engine_create(
978 struct dc_context *ctx,
981 struct aux_engine_dce110 *aux_engine =
982 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
987 dce110_aux_engine_construct(aux_engine, ctx, inst,
988 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
989 &aux_engine_regs[inst],
992 ctx->dc->caps.extended_aux_timeout_support);
994 return &aux_engine->base;
996 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
998 static const struct dce_i2c_registers i2c_hw_regs[] = {
1006 static const struct dce_i2c_shift i2c_shifts = {
1007 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1010 static const struct dce_i2c_mask i2c_masks = {
1011 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1014 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1015 struct dc_context *ctx,
1018 struct dce_i2c_hw *dce_i2c_hw =
1019 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1024 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1025 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1029 static struct mpc *dcn31_mpc_create(
1030 struct dc_context *ctx,
1034 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1040 dcn30_mpc_construct(mpc30, ctx,
1047 return &mpc30->base;
1050 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1054 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1060 hubbub31_construct(hubbub3, ctx,
1064 dcn3_14_ip.det_buffer_size_kbytes,
1065 dcn3_14_ip.pixel_chunk_size_kbytes,
1066 dcn3_14_ip.config_return_buffer_size_in_kbytes);
1069 for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1070 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1074 vmid->regs = &vmid_regs[i];
1075 vmid->shifts = &vmid_shifts;
1076 vmid->masks = &vmid_masks;
1079 return &hubbub3->base;
1082 static struct timing_generator *dcn31_timing_generator_create(
1083 struct dc_context *ctx,
1086 struct optc *tgn10 =
1087 kzalloc(sizeof(struct optc), GFP_KERNEL);
1092 tgn10->base.inst = instance;
1093 tgn10->base.ctx = ctx;
1095 tgn10->tg_regs = &optc_regs[instance];
1096 tgn10->tg_shift = &optc_shift;
1097 tgn10->tg_mask = &optc_mask;
1099 dcn314_timing_generator_init(tgn10);
1101 return &tgn10->base;
1104 static const struct encoder_feature_support link_enc_feature = {
1105 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1106 .max_hdmi_pixel_clock = 600000,
1107 .hdmi_ycbcr420_supported = true,
1108 .dp_ycbcr420_supported = true,
1109 .fec_supported = true,
1110 .flags.bits.IS_HBR2_CAPABLE = true,
1111 .flags.bits.IS_HBR3_CAPABLE = true,
1112 .flags.bits.IS_TPS3_CAPABLE = true,
1113 .flags.bits.IS_TPS4_CAPABLE = true
1116 static struct link_encoder *dcn31_link_encoder_create(
1117 struct dc_context *ctx,
1118 const struct encoder_init_data *enc_init_data)
1120 struct dcn20_link_encoder *enc20 =
1121 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1126 dcn31_link_encoder_construct(enc20,
1129 &link_enc_regs[enc_init_data->transmitter],
1130 &link_enc_aux_regs[enc_init_data->channel - 1],
1131 &link_enc_hpd_regs[enc_init_data->hpd_source],
1135 return &enc20->enc10.base;
1138 /* Create a minimal link encoder object not associated with a particular
1139 * physical connector.
1140 * resource_funcs.link_enc_create_minimal
1142 static struct link_encoder *dcn31_link_enc_create_minimal(
1143 struct dc_context *ctx, enum engine_id eng_id)
1145 struct dcn20_link_encoder *enc20;
1147 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1150 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1154 dcn31_link_encoder_construct_minimal(
1158 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1161 return &enc20->enc10.base;
1164 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1166 struct dcn31_panel_cntl *panel_cntl =
1167 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1172 dcn31_panel_cntl_construct(panel_cntl, init_data);
1174 return &panel_cntl->base;
1177 static void read_dce_straps(
1178 struct dc_context *ctx,
1179 struct resource_straps *straps)
1181 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1182 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1186 static struct audio *dcn31_create_audio(
1187 struct dc_context *ctx, unsigned int inst)
1189 return dce_audio_create(ctx, inst,
1190 &audio_regs[inst], &audio_shift, &audio_mask);
1193 static struct vpg *dcn31_vpg_create(
1194 struct dc_context *ctx,
1197 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1202 vpg31_construct(vpg31, ctx, inst,
1207 return &vpg31->base;
1210 static struct afmt *dcn31_afmt_create(
1211 struct dc_context *ctx,
1214 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1219 afmt31_construct(afmt31, ctx, inst,
1224 // Light sleep by default, no need to power down here
1226 return &afmt31->base;
1229 static struct apg *dcn31_apg_create(
1230 struct dc_context *ctx,
1233 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1238 apg31_construct(apg31, ctx, inst,
1243 return &apg31->base;
1246 static struct stream_encoder *dcn314_stream_encoder_create(
1247 enum engine_id eng_id,
1248 struct dc_context *ctx)
1250 struct dcn10_stream_encoder *enc1;
1256 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1257 if (eng_id < ENGINE_ID_DIGF) {
1263 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1264 vpg = dcn31_vpg_create(ctx, vpg_inst);
1265 afmt = dcn31_afmt_create(ctx, afmt_inst);
1267 if (!enc1 || !vpg || !afmt) {
1274 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1276 &stream_enc_regs[eng_id],
1277 &se_shift, &se_mask);
1282 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1283 enum engine_id eng_id,
1284 struct dc_context *ctx)
1286 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1289 uint32_t hpo_dp_inst;
1293 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1294 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1296 /* Mapping of VPG register blocks to HPO DP block instance:
1297 * VPG[6] -> HPO_DP[0]
1298 * VPG[7] -> HPO_DP[1]
1299 * VPG[8] -> HPO_DP[2]
1300 * VPG[9] -> HPO_DP[3]
1302 //Uses offset index 5-8, but actually maps to vpg_inst 6-9
1303 vpg_inst = hpo_dp_inst + 5;
1305 /* Mapping of APG register blocks to HPO DP block instance:
1306 * APG[0] -> HPO_DP[0]
1307 * APG[1] -> HPO_DP[1]
1308 * APG[2] -> HPO_DP[2]
1309 * APG[3] -> HPO_DP[3]
1311 apg_inst = hpo_dp_inst;
1313 /* allocate HPO stream encoder and create VPG sub-block */
1314 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1315 vpg = dcn31_vpg_create(ctx, vpg_inst);
1316 apg = dcn31_apg_create(ctx, apg_inst);
1318 if (!hpo_dp_enc31 || !vpg || !apg) {
1319 kfree(hpo_dp_enc31);
1325 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1326 hpo_dp_inst, eng_id, vpg, apg,
1327 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1328 &hpo_dp_se_shift, &hpo_dp_se_mask);
1330 return &hpo_dp_enc31->base;
1333 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1335 struct dc_context *ctx)
1337 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1339 /* allocate HPO link encoder */
1340 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1342 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1343 &hpo_dp_link_enc_regs[inst],
1344 &hpo_dp_le_shift, &hpo_dp_le_mask);
1346 return &hpo_dp_enc31->base;
1349 static struct dce_hwseq *dcn314_hwseq_create(
1350 struct dc_context *ctx)
1352 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1356 hws->regs = &hwseq_reg;
1357 hws->shifts = &hwseq_shift;
1358 hws->masks = &hwseq_mask;
1359 /* DCN3.1 FPGA Workaround
1360 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1361 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1362 * function core_link_enable_stream
1364 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1365 hws->wa.dp_hpo_and_otg_sequence = true;
1369 static const struct resource_create_funcs res_create_funcs = {
1370 .read_dce_straps = read_dce_straps,
1371 .create_audio = dcn31_create_audio,
1372 .create_stream_encoder = dcn314_stream_encoder_create,
1373 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1374 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1375 .create_hwseq = dcn314_hwseq_create,
1378 static const struct resource_create_funcs res_create_maximus_funcs = {
1379 .read_dce_straps = NULL,
1380 .create_audio = NULL,
1381 .create_stream_encoder = NULL,
1382 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1383 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1384 .create_hwseq = dcn314_hwseq_create,
1387 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1391 for (i = 0; i < pool->base.stream_enc_count; i++) {
1392 if (pool->base.stream_enc[i] != NULL) {
1393 if (pool->base.stream_enc[i]->vpg != NULL) {
1394 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1395 pool->base.stream_enc[i]->vpg = NULL;
1397 if (pool->base.stream_enc[i]->afmt != NULL) {
1398 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1399 pool->base.stream_enc[i]->afmt = NULL;
1401 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1402 pool->base.stream_enc[i] = NULL;
1406 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1407 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1408 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1409 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1410 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1412 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1413 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1414 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1416 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1417 pool->base.hpo_dp_stream_enc[i] = NULL;
1421 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1422 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1423 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1424 pool->base.hpo_dp_link_enc[i] = NULL;
1428 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1429 if (pool->base.dscs[i] != NULL)
1430 dcn20_dsc_destroy(&pool->base.dscs[i]);
1433 if (pool->base.mpc != NULL) {
1434 kfree(TO_DCN20_MPC(pool->base.mpc));
1435 pool->base.mpc = NULL;
1437 if (pool->base.hubbub != NULL) {
1438 kfree(pool->base.hubbub);
1439 pool->base.hubbub = NULL;
1441 for (i = 0; i < pool->base.pipe_count; i++) {
1442 if (pool->base.dpps[i] != NULL)
1443 dcn31_dpp_destroy(&pool->base.dpps[i]);
1445 if (pool->base.ipps[i] != NULL)
1446 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1448 if (pool->base.hubps[i] != NULL) {
1449 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1450 pool->base.hubps[i] = NULL;
1453 if (pool->base.irqs != NULL)
1454 dal_irq_service_destroy(&pool->base.irqs);
1457 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1458 if (pool->base.engines[i] != NULL)
1459 dce110_engine_destroy(&pool->base.engines[i]);
1460 if (pool->base.hw_i2cs[i] != NULL) {
1461 kfree(pool->base.hw_i2cs[i]);
1462 pool->base.hw_i2cs[i] = NULL;
1464 if (pool->base.sw_i2cs[i] != NULL) {
1465 kfree(pool->base.sw_i2cs[i]);
1466 pool->base.sw_i2cs[i] = NULL;
1470 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1471 if (pool->base.opps[i] != NULL)
1472 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1475 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1476 if (pool->base.timing_generators[i] != NULL) {
1477 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1478 pool->base.timing_generators[i] = NULL;
1482 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1483 if (pool->base.dwbc[i] != NULL) {
1484 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1485 pool->base.dwbc[i] = NULL;
1487 if (pool->base.mcif_wb[i] != NULL) {
1488 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1489 pool->base.mcif_wb[i] = NULL;
1493 for (i = 0; i < pool->base.audio_count; i++) {
1494 if (pool->base.audios[i])
1495 dce_aud_destroy(&pool->base.audios[i]);
1498 for (i = 0; i < pool->base.clk_src_count; i++) {
1499 if (pool->base.clock_sources[i] != NULL) {
1500 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1501 pool->base.clock_sources[i] = NULL;
1505 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1506 if (pool->base.mpc_lut[i] != NULL) {
1507 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1508 pool->base.mpc_lut[i] = NULL;
1510 if (pool->base.mpc_shaper[i] != NULL) {
1511 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1512 pool->base.mpc_shaper[i] = NULL;
1516 if (pool->base.dp_clock_source != NULL) {
1517 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1518 pool->base.dp_clock_source = NULL;
1521 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1522 if (pool->base.multiple_abms[i] != NULL)
1523 dce_abm_destroy(&pool->base.multiple_abms[i]);
1526 if (pool->base.psr != NULL)
1527 dmub_psr_destroy(&pool->base.psr);
1529 if (pool->base.dccg != NULL)
1530 dcn_dccg_destroy(&pool->base.dccg);
1533 static struct hubp *dcn31_hubp_create(
1534 struct dc_context *ctx,
1537 struct dcn20_hubp *hubp2 =
1538 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1543 if (hubp31_construct(hubp2, ctx, inst,
1544 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1545 return &hubp2->base;
1547 BREAK_TO_DEBUGGER();
1552 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1555 uint32_t pipe_count = pool->res_cap->num_dwb;
1557 for (i = 0; i < pipe_count; i++) {
1558 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1562 dm_error("DC: failed to create dwbc30!\n");
1566 dcn30_dwbc_construct(dwbc30, ctx,
1572 pool->dwbc[i] = &dwbc30->base;
1577 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1580 uint32_t pipe_count = pool->res_cap->num_dwb;
1582 for (i = 0; i < pipe_count; i++) {
1583 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1587 dm_error("DC: failed to create mcif_wb30!\n");
1591 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1597 pool->mcif_wb[i] = &mcif_wb30->base;
1602 static struct display_stream_compressor *dcn314_dsc_create(
1603 struct dc_context *ctx, uint32_t inst)
1605 struct dcn20_dsc *dsc =
1606 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1609 BREAK_TO_DEBUGGER();
1613 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1617 static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1619 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1621 dcn314_resource_destruct(dcn314_pool);
1626 static struct clock_source *dcn31_clock_source_create(
1627 struct dc_context *ctx,
1628 struct dc_bios *bios,
1629 enum clock_source_id id,
1630 const struct dce110_clk_src_regs *regs,
1633 struct dce110_clk_src *clk_src =
1634 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1639 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1640 regs, &cs_shift, &cs_mask)) {
1641 clk_src->base.dp_clk_src = dp_clk_src;
1642 return &clk_src->base;
1645 BREAK_TO_DEBUGGER();
1649 static int dcn314_populate_dml_pipes_from_context(
1650 struct dc *dc, struct dc_state *context,
1651 display_e2e_pipe_params_st *pipes,
1657 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);
1663 static struct dc_cap_funcs cap_funcs = {
1664 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1667 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1670 dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1674 static struct resource_funcs dcn314_res_pool_funcs = {
1675 .destroy = dcn314_destroy_resource_pool,
1676 .link_enc_create = dcn31_link_encoder_create,
1677 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1678 .link_encs_assign = link_enc_cfg_link_encs_assign,
1679 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1680 .panel_cntl_create = dcn31_panel_cntl_create,
1681 .validate_bandwidth = dcn31_validate_bandwidth,
1682 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1683 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1684 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1685 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1686 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1687 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1688 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1689 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1690 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1691 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1692 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1693 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1694 .update_bw_bounding_box = dcn314_update_bw_bounding_box,
1695 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1698 static struct clock_source *dcn30_clock_source_create(
1699 struct dc_context *ctx,
1700 struct dc_bios *bios,
1701 enum clock_source_id id,
1702 const struct dce110_clk_src_regs *regs,
1705 struct dce110_clk_src *clk_src =
1706 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1711 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1712 regs, &cs_shift, &cs_mask)) {
1713 clk_src->base.dp_clk_src = dp_clk_src;
1714 return &clk_src->base;
1717 BREAK_TO_DEBUGGER();
1721 static bool dcn314_resource_construct(
1722 uint8_t num_virtual_links,
1724 struct dcn314_resource_pool *pool)
1727 struct dc_context *ctx = dc->ctx;
1728 struct irq_service_init_data init_data;
1730 ctx->dc_bios->regs = &bios_regs;
1732 pool->base.res_cap = &res_cap_dcn314;
1733 pool->base.funcs = &dcn314_res_pool_funcs;
1735 /*************************************************
1736 * Resource + asic cap harcoding *
1737 *************************************************/
1738 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1739 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1740 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1741 dc->caps.max_downscale_ratio = 600;
1742 dc->caps.i2c_speed_in_khz = 100;
1743 dc->caps.i2c_speed_in_khz_hdcp = 100;
1744 dc->caps.max_cursor_size = 256;
1745 dc->caps.min_horizontal_blanking_period = 80;
1746 dc->caps.dmdata_alloc_size = 2048;
1747 dc->caps.max_slave_planes = 2;
1748 dc->caps.max_slave_yuv_planes = 2;
1749 dc->caps.max_slave_rgb_planes = 2;
1750 dc->caps.post_blend_color_processing = true;
1751 dc->caps.force_dp_tps4_for_cp2520 = true;
1752 dc->caps.dp_hpo = true;
1753 dc->caps.edp_dsc_support = true;
1754 dc->caps.extended_aux_timeout_support = true;
1755 dc->caps.dmcub_support = true;
1756 dc->caps.is_apu = true;
1757 dc->caps.seamless_odm = true;
1759 dc->caps.zstate_support = true;
1761 /* Color pipeline capabilities */
1762 dc->caps.color.dpp.dcn_arch = 1;
1763 dc->caps.color.dpp.input_lut_shared = 0;
1764 dc->caps.color.dpp.icsc = 1;
1765 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1766 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1767 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1768 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1769 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1770 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1771 dc->caps.color.dpp.post_csc = 1;
1772 dc->caps.color.dpp.gamma_corr = 1;
1773 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1775 dc->caps.color.dpp.hw_3d_lut = 1;
1776 dc->caps.color.dpp.ogam_ram = 1;
1777 // no OGAM ROM on DCN301
1778 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1779 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1780 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1781 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1782 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1783 dc->caps.color.dpp.ocsc = 0;
1785 dc->caps.color.mpc.gamut_remap = 1;
1786 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1787 dc->caps.color.mpc.ogam_ram = 1;
1788 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1789 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1790 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1791 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1792 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1793 dc->caps.color.mpc.ocsc = 1;
1795 /* Use pipe context based otg sync logic */
1796 dc->config.use_pipe_ctx_sync_logic = true;
1798 /* read VBIOS LTTPR caps */
1800 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1801 enum bp_result bp_query_result;
1802 uint8_t is_vbios_lttpr_enable = 0;
1804 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1805 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1808 /* interop bit is implicit */
1810 dc->caps.vbios_lttpr_aware = true;
1814 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1815 dc->debug = debug_defaults_drv;
1816 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)
1817 dc->debug = debug_defaults_diags;
1819 dc->debug = debug_defaults_diags;
1820 // Init the vm_helper
1822 vm_helper_init(dc->vm_helper, 16);
1824 /*************************************************
1825 * Create resources *
1826 *************************************************/
1828 /* Clock Sources for Pixel Clock*/
1829 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1830 dcn30_clock_source_create(ctx, ctx->dc_bios,
1831 CLOCK_SOURCE_COMBO_PHY_PLL0,
1832 &clk_src_regs[0], false);
1833 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1834 dcn30_clock_source_create(ctx, ctx->dc_bios,
1835 CLOCK_SOURCE_COMBO_PHY_PLL1,
1836 &clk_src_regs[1], false);
1837 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1838 dcn30_clock_source_create(ctx, ctx->dc_bios,
1839 CLOCK_SOURCE_COMBO_PHY_PLL2,
1840 &clk_src_regs[2], false);
1841 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1842 dcn30_clock_source_create(ctx, ctx->dc_bios,
1843 CLOCK_SOURCE_COMBO_PHY_PLL3,
1844 &clk_src_regs[3], false);
1845 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1846 dcn30_clock_source_create(ctx, ctx->dc_bios,
1847 CLOCK_SOURCE_COMBO_PHY_PLL4,
1848 &clk_src_regs[4], false);
1850 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1852 /* todo: not reuse phy_pll registers */
1853 pool->base.dp_clock_source =
1854 dcn31_clock_source_create(ctx, ctx->dc_bios,
1855 CLOCK_SOURCE_ID_DP_DTO,
1856 &clk_src_regs[0], true);
1858 for (i = 0; i < pool->base.clk_src_count; i++) {
1859 if (pool->base.clock_sources[i] == NULL) {
1860 dm_error("DC: failed to create clock sources!\n");
1861 BREAK_TO_DEBUGGER();
1866 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1867 if (pool->base.dccg == NULL) {
1868 dm_error("DC: failed to create dccg!\n");
1869 BREAK_TO_DEBUGGER();
1873 init_data.ctx = dc->ctx;
1874 pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
1875 if (!pool->base.irqs)
1879 pool->base.hubbub = dcn31_hubbub_create(ctx);
1880 if (pool->base.hubbub == NULL) {
1881 BREAK_TO_DEBUGGER();
1882 dm_error("DC: failed to create hubbub!\n");
1886 /* HUBPs, DPPs, OPPs and TGs */
1887 for (i = 0; i < pool->base.pipe_count; i++) {
1888 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1889 if (pool->base.hubps[i] == NULL) {
1890 BREAK_TO_DEBUGGER();
1892 "DC: failed to create hubps!\n");
1896 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1897 if (pool->base.dpps[i] == NULL) {
1898 BREAK_TO_DEBUGGER();
1900 "DC: failed to create dpps!\n");
1905 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1906 pool->base.opps[i] = dcn31_opp_create(ctx, i);
1907 if (pool->base.opps[i] == NULL) {
1908 BREAK_TO_DEBUGGER();
1910 "DC: failed to create output pixel processor!\n");
1915 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1916 pool->base.timing_generators[i] = dcn31_timing_generator_create(
1918 if (pool->base.timing_generators[i] == NULL) {
1919 BREAK_TO_DEBUGGER();
1920 dm_error("DC: failed to create tg!\n");
1924 pool->base.timing_generator_count = i;
1927 pool->base.psr = dmub_psr_create(ctx);
1928 if (pool->base.psr == NULL) {
1929 dm_error("DC: failed to create psr obj!\n");
1930 BREAK_TO_DEBUGGER();
1935 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1936 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1940 if (pool->base.multiple_abms[i] == NULL) {
1941 dm_error("DC: failed to create abm for pipe %d!\n", i);
1942 BREAK_TO_DEBUGGER();
1948 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1949 if (pool->base.mpc == NULL) {
1950 BREAK_TO_DEBUGGER();
1951 dm_error("DC: failed to create mpc!\n");
1955 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1956 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
1957 if (pool->base.dscs[i] == NULL) {
1958 BREAK_TO_DEBUGGER();
1959 dm_error("DC: failed to create display stream compressor %d!\n", i);
1964 /* DWB and MMHUBBUB */
1965 if (!dcn31_dwbc_create(ctx, &pool->base)) {
1966 BREAK_TO_DEBUGGER();
1967 dm_error("DC: failed to create dwbc!\n");
1971 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1972 BREAK_TO_DEBUGGER();
1973 dm_error("DC: failed to create mcif_wb!\n");
1978 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1979 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
1980 if (pool->base.engines[i] == NULL) {
1981 BREAK_TO_DEBUGGER();
1983 "DC:failed to create aux engine!!\n");
1986 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
1987 if (pool->base.hw_i2cs[i] == NULL) {
1988 BREAK_TO_DEBUGGER();
1990 "DC:failed to create hw i2c!!\n");
1993 pool->base.sw_i2cs[i] = NULL;
1996 /* DCN314 has 4 DPIA */
1997 pool->base.usb4_dpia_count = 4;
1999 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2000 if (!resource_construct(num_virtual_links, dc, &pool->base,
2001 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2002 &res_create_funcs : &res_create_maximus_funcs)))
2005 /* HW Sequencer and Plane caps */
2006 dcn314_hw_sequencer_construct(dc);
2008 dc->caps.max_planes = pool->base.pipe_count;
2010 for (i = 0; i < dc->caps.max_planes; ++i)
2011 dc->caps.planes[i] = plane_cap;
2013 dc->cap_funcs = cap_funcs;
2015 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2021 dcn314_resource_destruct(pool);
2026 struct resource_pool *dcn314_create_resource_pool(
2027 const struct dc_init_data *init_data,
2030 struct dcn314_resource_pool *pool =
2031 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);
2036 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2039 BREAK_TO_DEBUGGER();