2 * Copyright 2020 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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26 #ifndef _DCN31_RESOURCE_H_
27 #define _DCN31_RESOURCE_H_
29 #include "core_types.h"
31 #define TO_DCN31_RES_POOL(pool)\
32 container_of(pool, struct dcn31_resource_pool, base)
34 extern struct _vcs_dpi_ip_params_st dcn3_1_ip;
36 struct dcn31_resource_pool {
37 struct resource_pool base;
40 bool dcn31_validate_bandwidth(struct dc *dc,
41 struct dc_state *context,
43 void dcn31_calculate_wm_and_dlg(
44 struct dc *dc, struct dc_state *context,
45 display_e2e_pipe_params_st *pipes,
48 int dcn31_populate_dml_pipes_from_context(
49 struct dc *dc, struct dc_state *context,
50 display_e2e_pipe_params_st *pipes,
53 dcn31_populate_dml_writeback_from_context(struct dc *dc,
54 struct resource_context *res_ctx,
55 display_e2e_pipe_params_st *pipes);
57 dcn31_set_mcif_arb_params(struct dc *dc,
58 struct dc_state *context,
59 display_e2e_pipe_params_st *pipes,
62 struct resource_pool *dcn31_create_resource_pool(
63 const struct dc_init_data *init_data,
66 /*temp: B0 specific before switch to dcn313 headers*/
67 #ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL
68 #define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
69 #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
70 #define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
71 #define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
73 //PHYPLLF_PIXCLK_RESYNC_CNTL
74 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
75 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
76 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
77 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
78 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
79 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
80 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
81 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
82 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
83 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
85 //PHYPLLG_PIXCLK_RESYNC_CNTL
86 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
87 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
88 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
89 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
90 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
91 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
92 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
93 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
94 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
95 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
97 #endif /* _DCN31_RESOURCE_H_ */