drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright (C) 2021 Advanced Micro Devices, Inc.
   4  *
   5  * Authors: AMD
   6  */
   7
   8 #include "dcn303_init.h"
   9 #include "dcn303_resource.h"
  10 #include "dcn303_dccg.h"
  11 #include "irq/dcn303/irq_service_dcn303.h"
  12
  13 #include "dcn30/dcn30_dio_link_encoder.h"
  14 #include "dcn30/dcn30_dio_stream_encoder.h"
  15 #include "dcn30/dcn30_dpp.h"
  16 #include "dcn30/dcn30_dwb.h"
  17 #include "dcn30/dcn30_hubbub.h"
  18 #include "dcn30/dcn30_hubp.h"
  19 #include "dcn30/dcn30_mmhubbub.h"
  20 #include "dcn30/dcn30_mpc.h"
  21 #include "dcn30/dcn30_opp.h"
  22 #include "dcn30/dcn30_optc.h"
  23 #include "dcn30/dcn30_resource.h"
  24
  25 #include "dcn20/dcn20_dsc.h"
  26 #include "dcn20/dcn20_resource.h"
  27
  28 #include "dml/dcn30/dcn30_fpu.h"
  29
  30 #include "dcn10/dcn10_resource.h"
  31
  32 #include "dc_link_ddc.h"
  33
  34 #include "dce/dce_abm.h"
  35 #include "dce/dce_audio.h"
  36 #include "dce/dce_aux.h"
  37 #include "dce/dce_clock_source.h"
  38 #include "dce/dce_hwseq.h"
  39 #include "dce/dce_i2c_hw.h"
  40 #include "dce/dce_panel_cntl.h"
  41 #include "dce/dmub_abm.h"
  42 #include "dce/dmub_psr.h"
  43 #include "clk_mgr.h"
  44
  45 #include "hw_sequencer_private.h"
  46 #include "reg_helper.h"
  47 #include "resource.h"
  48 #include "vm_helper.h"
  49
  50 #include "sienna_cichlid_ip_offset.h"
  51 #include "dcn/dcn_3_0_3_offset.h"
  52 #include "dcn/dcn_3_0_3_sh_mask.h"
  53 #include "dpcs/dpcs_3_0_3_offset.h"
  54 #include "dpcs/dpcs_3_0_3_sh_mask.h"
  55 #include "nbio/nbio_2_3_offset.h"
  56
  57 #include "dml/dcn303/dcn303_fpu.h"
  58
  59 #define DC_LOGGER_INIT(logger)
  60
  61
  62 static const struct dc_debug_options debug_defaults_drv = {
  63                 .disable_dmcu = true,
  64                 .force_abm_enable = false,
  65                 .timing_trace = false,
  66                 .clock_trace = true,
  67                 .disable_pplib_clock_request = true,
  68                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
  69                 .force_single_disp_pipe_split = false,
  70                 .disable_dcc = DCC_ENABLE,
  71                 .vsr_support = true,
  72                 .performance_trace = false,
  73                 .max_downscale_src_width = 7680,/*upto 8K*/
  74                 .disable_pplib_wm_range = false,
  75                 .scl_reset_length10 = true,
  76                 .sanity_checks = false,
  77                 .underflow_assert_delay_us = 0xFFFFFFFF,
  78                 .dwb_fi_phase = -1, // -1 = disable,
  79                 .dmub_command_table = true,
  80                 .disable_idle_power_optimizations = false,
  81 };
  82
  83 static const struct dc_debug_options debug_defaults_diags = {
  84                 .disable_dmcu = true,
  85                 .force_abm_enable = false,
  86                 .timing_trace = true,
  87                 .clock_trace = true,
  88                 .disable_dpp_power_gate = true,
  89                 .disable_hubp_power_gate = true,
  90                 .disable_clock_gate = true,
  91                 .disable_pplib_clock_request = true,
  92                 .disable_pplib_wm_range = true,
  93                 .disable_stutter = false,
  94                 .scl_reset_length10 = true,
  95                 .dwb_fi_phase = -1, // -1 = disable
  96                 .dmub_command_table = true,
  97                 .enable_tri_buf = true,
  98                 .disable_psr = true,
  99 };
 100
 101 enum dcn303_clk_src_array_id {
 102         DCN303_CLK_SRC_PLL0,
 103         DCN303_CLK_SRC_PLL1,
 104         DCN303_CLK_SRC_TOTAL
 105 };
 106
 107 static const struct resource_caps res_cap_dcn303 = {
 108                 .num_timing_generator = 2,
 109                 .num_opp = 2,
 110                 .num_video_plane = 2,
 111                 .num_audio = 2,
 112                 .num_stream_encoder = 2,
 113                 .num_dwb = 1,
 114                 .num_ddc = 2,
 115                 .num_vmid = 16,
 116                 .num_mpc_3dlut = 1,
 117                 .num_dsc = 2,
 118 };
 119
 120 static const struct dc_plane_cap plane_cap = {
 121                 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 122                 .blends_with_above = true,
 123                 .blends_with_below = true,
 124                 .per_pixel_alpha = true,
 125                 .pixel_format_support = {
 126                                 .argb8888 = true,
 127                                 .nv12 = true,
 128                                 .fp16 = true,
 129                                 .p010 = true,
 130                                 .ayuv = false,
 131                 },
 132                 .max_upscale_factor = {
 133                                 .argb8888 = 16000,
 134                                 .nv12 = 16000,
 135                                 .fp16 = 16000
 136                 },
 137                 .max_downscale_factor = {
 138                                 .argb8888 = 600,
 139                                 .nv12 = 600,
 140                                 .fp16 = 600
 141                 },
 142                 16,
 143                 16
 144 };
 145
 146 /* NBIO */
 147 #define NBIO_BASE_INNER(seg) \
 148                 NBIO_BASE__INST0_SEG ## seg
 149
 150 #define NBIO_BASE(seg) \
 151                 NBIO_BASE_INNER(seg)
 152
 153 #define NBIO_SR(reg_name)\
 154                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 155                 mm ## reg_name
 156
 157 /* DCN */
 158 #undef BASE_INNER
 159 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 160
 161 #define BASE(seg) BASE_INNER(seg)
 162
 163 #define SR(reg_name)\
 164                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 165
 166 #define SF(reg_name, field_name, post_fix)\
 167                 .field_name = reg_name ## __ ## field_name ## post_fix
 168
 169 #define SRI(reg_name, block, id)\
 170                 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
 171
 172 #define SRI2(reg_name, block, id)\
 173                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 174
 175 #define SRII(reg_name, block, id)\
 176                 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 177                 mm ## block ## id ## _ ## reg_name
 178
 179 #define DCCG_SRII(reg_name, block, id)\
 180                 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 181                 mm ## block ## id ## _ ## reg_name
 182
 183 #define VUPDATE_SRII(reg_name, block, id)\
 184                 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 185                 mm ## reg_name ## _ ## block ## id
 186
 187 #define SRII_DWB(reg_name, temp_name, block, id)\
 188                 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 189                 mm ## block ## id ## _ ## temp_name
 190
 191 #define SRII_MPC_RMU(reg_name, block, id)\
 192                 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 193                 mm ## block ## id ## _ ## reg_name
 194
 195 static const struct dcn_hubbub_registers hubbub_reg = {
 196                 HUBBUB_REG_LIST_DCN30(0)
 197 };
 198
 199 static const struct dcn_hubbub_shift hubbub_shift = {
 200                 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
 201 };
 202
 203 static const struct dcn_hubbub_mask hubbub_mask = {
 204                 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
 205 };
 206
 207 #define vmid_regs(id)\
 208                 [id] = { DCN20_VMID_REG_LIST(id) }
 209
 210 static const struct dcn_vmid_registers vmid_regs[] = {
 211                 vmid_regs(0),
 212                 vmid_regs(1),
 213                 vmid_regs(2),
 214                 vmid_regs(3),
 215                 vmid_regs(4),
 216                 vmid_regs(5),
 217                 vmid_regs(6),
 218                 vmid_regs(7),
 219                 vmid_regs(8),
 220                 vmid_regs(9),
 221                 vmid_regs(10),
 222                 vmid_regs(11),
 223                 vmid_regs(12),
 224                 vmid_regs(13),
 225                 vmid_regs(14),
 226                 vmid_regs(15)
 227 };
 228
 229 static const struct dcn20_vmid_shift vmid_shifts = {
 230                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 231 };
 232
 233 static const struct dcn20_vmid_mask vmid_masks = {
 234                 DCN20_VMID_MASK_SH_LIST(_MASK)
 235 };
 236
 237 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)
 238 {
 239         int i;
 240
 241         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
 242
 243         if (!hubbub3)
 244                 return NULL;
 245
 246         hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
 247
 248         for (i = 0; i < res_cap_dcn303.num_vmid; i++) {
 249                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 250
 251                 vmid->ctx = ctx;
 252
 253                 vmid->regs = &vmid_regs[i];
 254                 vmid->shifts = &vmid_shifts;
 255                 vmid->masks = &vmid_masks;
 256         }
 257
 258         return &hubbub3->base;
 259 }
 260
 261 #define vpg_regs(id)\
 262                 [id] = { VPG_DCN3_REG_LIST(id) }
 263
 264 static const struct dcn30_vpg_registers vpg_regs[] = {
 265                 vpg_regs(0),
 266                 vpg_regs(1),
 267                 vpg_regs(2)
 268 };
 269
 270 static const struct dcn30_vpg_shift vpg_shift = {
 271                 DCN3_VPG_MASK_SH_LIST(__SHIFT)
 272 };
 273
 274 static const struct dcn30_vpg_mask vpg_mask = {
 275                 DCN3_VPG_MASK_SH_LIST(_MASK)
 276 };
 277
 278 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
 279 {
 280         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
 281
 282         if (!vpg3)
 283                 return NULL;
 284
 285         vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
 286
 287         return &vpg3->base;
 288 }
 289
 290 #define afmt_regs(id)\
 291                 [id] = { AFMT_DCN3_REG_LIST(id) }
 292
 293 static const struct dcn30_afmt_registers afmt_regs[] = {
 294                 afmt_regs(0),
 295                 afmt_regs(1),
 296                 afmt_regs(2)
 297 };
 298
 299 static const struct dcn30_afmt_shift afmt_shift = {
 300                 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 301 };
 302
 303 static const struct dcn30_afmt_mask afmt_mask = {
 304                 DCN3_AFMT_MASK_SH_LIST(_MASK)
 305 };
 306
 307 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
 308 {
 309         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
 310
 311         if (!afmt3)
 312                 return NULL;
 313
 314         afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
 315
 316         return &afmt3->base;
 317 }
 318
 319 #define audio_regs(id)\
 320                 [id] = { AUD_COMMON_REG_LIST(id) }
 321
 322 static const struct dce_audio_registers audio_regs[] = {
 323                 audio_regs(0),
 324                 audio_regs(1),
 325                 audio_regs(2),
 326                 audio_regs(3),
 327                 audio_regs(4),
 328                 audio_regs(5),
 329                 audio_regs(6)
 330 };
 331
 332 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 333                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 334                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 335                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 336
 337 static const struct dce_audio_shift audio_shift = {
 338                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 339 };
 340
 341 static const struct dce_audio_mask audio_mask = {
 342                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 343 };
 344
 345 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
 346 {
 347         return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
 348 }
 349
 350 #define stream_enc_regs(id)\
 351                 [id] = { SE_DCN3_REG_LIST(id) }
 352
 353 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 354                 stream_enc_regs(0),
 355                 stream_enc_regs(1)
 356 };
 357
 358 static const struct dcn10_stream_encoder_shift se_shift = {
 359                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 360 };
 361
 362 static const struct dcn10_stream_encoder_mask se_mask = {
 363                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 364 };
 365
 366 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
 367 {
 368         struct dcn10_stream_encoder *enc1;
 369         struct vpg *vpg;
 370         struct afmt *afmt;
 371         int vpg_inst;
 372         int afmt_inst;
 373
 374         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
 375         if (eng_id <= ENGINE_ID_DIGE) {
 376                 vpg_inst = eng_id;
 377                 afmt_inst = eng_id;
 378         } else
 379                 return NULL;
 380
 381         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 382         vpg = dcn303_vpg_create(ctx, vpg_inst);
 383         afmt = dcn303_afmt_create(ctx, afmt_inst);
 384
 385         if (!enc1 || !vpg || !afmt) {
 386                 kfree(enc1);
 387                 kfree(vpg);
 388                 kfree(afmt);
 389                 return NULL;
 390         }
 391
 392         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
 393                         &se_shift, &se_mask);
 394
 395         return &enc1->base;
 396 }
 397
 398 #define clk_src_regs(index, pllid)\
 399                 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }
 400
 401 static const struct dce110_clk_src_regs clk_src_regs[] = {
 402                 clk_src_regs(0, A),
 403                 clk_src_regs(1, B)
 404 };
 405
 406 static const struct dce110_clk_src_shift cs_shift = {
 407                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 408 };
 409
 410 static const struct dce110_clk_src_mask cs_mask = {
 411                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 412 };
 413
 414 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
 415                 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
 416 {
 417         struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 418
 419         if (!clk_src)
 420                 return NULL;
 421
 422         if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
 423                 clk_src->base.dp_clk_src = dp_clk_src;
 424                 return &clk_src->base;
 425         }
 426
 427         BREAK_TO_DEBUGGER();
 428         return NULL;
 429 }
 430
 431 static const struct dce_hwseq_registers hwseq_reg = {
 432                 HWSEQ_DCN303_REG_LIST()
 433 };
 434
 435 static const struct dce_hwseq_shift hwseq_shift = {
 436                 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)
 437 };
 438
 439 static const struct dce_hwseq_mask hwseq_mask = {
 440                 HWSEQ_DCN303_MASK_SH_LIST(_MASK)
 441 };
 442
 443 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)
 444 {
 445         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 446
 447         if (hws) {
 448                 hws->ctx = ctx;
 449                 hws->regs = &hwseq_reg;
 450                 hws->shifts = &hwseq_shift;
 451                 hws->masks = &hwseq_mask;
 452         }
 453         return hws;
 454 }
 455
 456 #define hubp_regs(id)\
 457                 [id] = { HUBP_REG_LIST_DCN30(id) }
 458
 459 static const struct dcn_hubp2_registers hubp_regs[] = {
 460                 hubp_regs(0),
 461                 hubp_regs(1)
 462 };
 463
 464 static const struct dcn_hubp2_shift hubp_shift = {
 465                 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 466 };
 467
 468 static const struct dcn_hubp2_mask hubp_mask = {
 469                 HUBP_MASK_SH_LIST_DCN30(_MASK)
 470 };
 471
 472 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
 473 {
 474         struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
 475
 476         if (!hubp2)
 477                 return NULL;
 478
 479         if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
 480                 return &hubp2->base;
 481
 482         BREAK_TO_DEBUGGER();
 483         kfree(hubp2);
 484         return NULL;
 485 }
 486
 487 #define dpp_regs(id)\
 488                 [id] = { DPP_REG_LIST_DCN30(id) }
 489
 490 static const struct dcn3_dpp_registers dpp_regs[] = {
 491                 dpp_regs(0),
 492                 dpp_regs(1)
 493 };
 494
 495 static const struct dcn3_dpp_shift tf_shift = {
 496                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 497 };
 498
 499 static const struct dcn3_dpp_mask tf_mask = {
 500                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 501 };
 502
 503 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
 504 {
 505         struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 506
 507         if (!dpp)
 508                 return NULL;
 509
 510         if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
 511                 return &dpp->base;
 512
 513         BREAK_TO_DEBUGGER();
 514         kfree(dpp);
 515         return NULL;
 516 }
 517
 518 #define opp_regs(id)\
 519                 [id] = { OPP_REG_LIST_DCN30(id) }
 520
 521 static const struct dcn20_opp_registers opp_regs[] = {
 522                 opp_regs(0),
 523                 opp_regs(1)
 524 };
 525
 526 static const struct dcn20_opp_shift opp_shift = {
 527                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 528 };
 529
 530 static const struct dcn20_opp_mask opp_mask = {
 531                 OPP_MASK_SH_LIST_DCN20(_MASK)
 532 };
 533
 534 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
 535 {
 536         struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 537
 538         if (!opp) {
 539                 BREAK_TO_DEBUGGER();
 540                 return NULL;
 541         }
 542
 543         dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 544         return &opp->base;
 545 }
 546
 547 #define optc_regs(id)\
 548                 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
 549
 550 static const struct dcn_optc_registers optc_regs[] = {
 551                 optc_regs(0),
 552                 optc_regs(1)
 553 };
 554
 555 static const struct dcn_optc_shift optc_shift = {
 556                 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 557 };
 558
 559 static const struct dcn_optc_mask optc_mask = {
 560                 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 561 };
 562
 563 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)
 564 {
 565         struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
 566
 567         if (!tgn10)
 568                 return NULL;
 569
 570         tgn10->base.inst = instance;
 571         tgn10->base.ctx = ctx;
 572
 573         tgn10->tg_regs = &optc_regs[instance];
 574         tgn10->tg_shift = &optc_shift;
 575         tgn10->tg_mask = &optc_mask;
 576
 577         dcn30_timing_generator_init(tgn10);
 578
 579         return &tgn10->base;
 580 }
 581
 582 static const struct dcn30_mpc_registers mpc_regs = {
 583                 MPC_REG_LIST_DCN3_0(0),
 584                 MPC_REG_LIST_DCN3_0(1),
 585                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 586                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 587                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 588                 MPC_RMU_REG_LIST_DCN3AG(0),
 589                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 590 };
 591
 592 static const struct dcn30_mpc_shift mpc_shift = {
 593                 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)
 594 };
 595
 596 static const struct dcn30_mpc_mask mpc_mask = {
 597                 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)
 598 };
 599
 600 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
 601 {
 602         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 603
 604         if (!mpc30)
 605                 return NULL;
 606
 607         dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
 608
 609         return &mpc30->base;
 610 }
 611
 612 #define dsc_regsDCN20(id)\
 613 [id] = { DSC_REG_LIST_DCN20(id) }
 614
 615 static const struct dcn20_dsc_registers dsc_regs[] = {
 616                 dsc_regsDCN20(0),
 617                 dsc_regsDCN20(1)
 618 };
 619
 620 static const struct dcn20_dsc_shift dsc_shift = {
 621                 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 622 };
 623
 624 static const struct dcn20_dsc_mask dsc_mask = {
 625                 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 626 };
 627
 628 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
 629 {
 630         struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
 631
 632         if (!dsc) {
 633                 BREAK_TO_DEBUGGER();
 634                 return NULL;
 635         }
 636
 637         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
 638         return &dsc->base;
 639 }
 640
 641 #define dwbc_regs_dcn3(id)\
 642 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
 643
 644 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 645                 dwbc_regs_dcn3(0)
 646 };
 647
 648 static const struct dcn30_dwbc_shift dwbc30_shift = {
 649                 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 650 };
 651
 652 static const struct dcn30_dwbc_mask dwbc30_mask = {
 653                 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 654 };
 655
 656 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
 657 {
 658         int i;
 659         uint32_t pipe_count = pool->res_cap->num_dwb;
 660
 661         for (i = 0; i < pipe_count; i++) {
 662                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
 663
 664                 if (!dwbc30) {
 665                         dm_error("DC: failed to create dwbc30!\n");
 666                         return false;
 667                 }
 668
 669                 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
 670
 671                 pool->dwbc[i] = &dwbc30->base;
 672         }
 673         return true;
 674 }
 675
 676 #define mcif_wb_regs_dcn3(id)\
 677 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
 678
 679 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 680                 mcif_wb_regs_dcn3(0)
 681 };
 682
 683 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 684                 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 685 };
 686
 687 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 688                 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 689 };
 690
 691 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
 692 {
 693         int i;
 694         uint32_t pipe_count = pool->res_cap->num_dwb;
 695
 696         for (i = 0; i < pipe_count; i++) {
 697                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
 698
 699                 if (!mcif_wb30) {
 700                         dm_error("DC: failed to create mcif_wb30!\n");
 701                         return false;
 702                 }
 703
 704                 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
 705
 706                 pool->mcif_wb[i] = &mcif_wb30->base;
 707         }
 708         return true;
 709 }
 710
 711 #define aux_engine_regs(id)\
 712 [id] = {\
 713                 AUX_COMMON_REG_LIST0(id), \
 714                 .AUXN_IMPCAL = 0, \
 715                 .AUXP_IMPCAL = 0, \
 716                 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 717 }
 718
 719 static const struct dce110_aux_registers aux_engine_regs[] = {
 720                 aux_engine_regs(0),
 721                 aux_engine_regs(1)
 722 };
 723
 724 static const struct dce110_aux_registers_shift aux_shift = {
 725                 DCN_AUX_MASK_SH_LIST(__SHIFT)
 726 };
 727
 728 static const struct dce110_aux_registers_mask aux_mask = {
 729                 DCN_AUX_MASK_SH_LIST(_MASK)
 730 };
 731
 732 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
 733 {
 734         struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 735
 736         if (!aux_engine)
 737                 return NULL;
 738
 739         dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 740                         &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
 741
 742         return &aux_engine->base;
 743 }
 744
 745 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 746
 747 static const struct dce_i2c_registers i2c_hw_regs[] = {
 748                 i2c_inst_regs(1),
 749                 i2c_inst_regs(2)
 750 };
 751
 752 static const struct dce_i2c_shift i2c_shifts = {
 753                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 754 };
 755
 756 static const struct dce_i2c_mask i2c_masks = {
 757                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 758 };
 759
 760 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
 761 {
 762         struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 763
 764         if (!dce_i2c_hw)
 765                 return NULL;
 766
 767         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 768
 769         return dce_i2c_hw;
 770 }
 771
 772 static const struct encoder_feature_support link_enc_feature = {
 773                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 774                 .max_hdmi_pixel_clock = 600000,
 775                 .hdmi_ycbcr420_supported = true,
 776                 .dp_ycbcr420_supported = true,
 777                 .fec_supported = true,
 778                 .flags.bits.IS_HBR2_CAPABLE = true,
 779                 .flags.bits.IS_HBR3_CAPABLE = true,
 780                 .flags.bits.IS_TPS3_CAPABLE = true,
 781                 .flags.bits.IS_TPS4_CAPABLE = true
 782 };
 783
 784 #define link_regs(id, phyid)\
 785                 [id] = {\
 786                                 LE_DCN3_REG_LIST(id), \
 787                                 UNIPHY_DCN2_REG_LIST(phyid), \
 788                                 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 789                 }
 790
 791 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 792                 link_regs(0, A),
 793                 link_regs(1, B)
 794 };
 795
 796 static const struct dcn10_link_enc_shift le_shift = {
 797                 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
 798                 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 799 };
 800
 801 static const struct dcn10_link_enc_mask le_mask = {
 802                 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
 803                 DPCS_DCN2_MASK_SH_LIST(_MASK)
 804 };
 805
 806 #define aux_regs(id)\
 807                 [id] = { DCN2_AUX_REG_LIST(id) }
 808
 809 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 810                 aux_regs(0),
 811                 aux_regs(1)
 812 };
 813
 814 #define hpd_regs(id)\
 815                 [id] = { HPD_REG_LIST(id) }
 816
 817 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 818                 hpd_regs(0),
 819                 hpd_regs(1)
 820 };
 821
 822 static struct link_encoder *dcn303_link_encoder_create(
 823         struct dc_context *ctx,
 824         const struct encoder_init_data *enc_init_data)
 825 {
 826         struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
 827
 828         if (!enc20)
 829                 return NULL;
 830
 831         dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
 832                         &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
 833                         &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
 834
 835         return &enc20->enc10.base;
 836 }
 837
 838 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 839                 { DCN_PANEL_CNTL_REG_LIST() }
 840 };
 841
 842 static const struct dce_panel_cntl_shift panel_cntl_shift = {
 843                 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 844 };
 845
 846 static const struct dce_panel_cntl_mask panel_cntl_mask = {
 847                 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 848 };
 849
 850 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 851 {
 852         struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 853
 854         if (!panel_cntl)
 855                 return NULL;
 856
 857         dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
 858                         &panel_cntl_shift, &panel_cntl_mask);
 859
 860         return &panel_cntl->base;
 861 }
 862
 863 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
 864 {
 865         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 866                         FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 867 }
 868
 869 static const struct resource_create_funcs res_create_funcs = {
 870                 .read_dce_straps = read_dce_straps,
 871                 .create_audio = dcn303_create_audio,
 872                 .create_stream_encoder = dcn303_stream_encoder_create,
 873                 .create_hwseq = dcn303_hwseq_create,
 874 };
 875
 876 static const struct resource_create_funcs res_create_maximus_funcs = {
 877                 .read_dce_straps = NULL,
 878                 .create_audio = NULL,
 879                 .create_stream_encoder = NULL,
 880                 .create_hwseq = dcn303_hwseq_create,
 881 };
 882
 883 static bool is_soc_bounding_box_valid(struct dc *dc)
 884 {
 885         uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
 886
 887         if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
 888                 return true;
 889
 890         return false;
 891 }
 892
 893 static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
 894 {
 895         struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;
 896         struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;
 897
 898         DC_LOGGER_INIT(dc->ctx->logger);
 899
 900         if (!is_soc_bounding_box_valid(dc)) {
 901                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
 902                 return false;
 903         }
 904
 905         loaded_ip->max_num_otg = pool->pipe_count;
 906         loaded_ip->max_num_dpp = pool->pipe_count;
 907         loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
 908         DC_FP_START();
 909         dcn20_patch_bounding_box(dc, loaded_bb);
 910         DC_FP_END();
 911
 912         if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
 913                 struct bp_soc_bb_info bb_info = { 0 };
 914
 915                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
 916                             dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
 917                                         DC_FP_START();
 918                                         dcn303_fpu_init_soc_bounding_box(bb_info);
 919                                         DC_FP_END();
 920                 }
 921         }
 922
 923         return true;
 924 }
 925
 926 static void dcn303_resource_destruct(struct resource_pool *pool)
 927 {
 928         unsigned int i;
 929
 930         for (i = 0; i < pool->stream_enc_count; i++) {
 931                 if (pool->stream_enc[i] != NULL) {
 932                         if (pool->stream_enc[i]->vpg != NULL) {
 933                                 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
 934                                 pool->stream_enc[i]->vpg = NULL;
 935                         }
 936                         if (pool->stream_enc[i]->afmt != NULL) {
 937                                 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
 938                                 pool->stream_enc[i]->afmt = NULL;
 939                         }
 940                         kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
 941                         pool->stream_enc[i] = NULL;
 942                 }
 943         }
 944
 945         for (i = 0; i < pool->res_cap->num_dsc; i++) {
 946                 if (pool->dscs[i] != NULL)
 947                         dcn20_dsc_destroy(&pool->dscs[i]);
 948         }
 949
 950         if (pool->mpc != NULL) {
 951                 kfree(TO_DCN20_MPC(pool->mpc));
 952                 pool->mpc = NULL;
 953         }
 954
 955         if (pool->hubbub != NULL) {
 956                 kfree(pool->hubbub);
 957                 pool->hubbub = NULL;
 958         }
 959
 960         for (i = 0; i < pool->pipe_count; i++) {
 961                 if (pool->dpps[i] != NULL) {
 962                         kfree(TO_DCN20_DPP(pool->dpps[i]));
 963                         pool->dpps[i] = NULL;
 964                 }
 965
 966                 if (pool->hubps[i] != NULL) {
 967                         kfree(TO_DCN20_HUBP(pool->hubps[i]));
 968                         pool->hubps[i] = NULL;
 969                 }
 970
 971                 if (pool->irqs != NULL)
 972                         dal_irq_service_destroy(&pool->irqs);
 973         }
 974
 975         for (i = 0; i < pool->res_cap->num_ddc; i++) {
 976                 if (pool->engines[i] != NULL)
 977                         dce110_engine_destroy(&pool->engines[i]);
 978                 if (pool->hw_i2cs[i] != NULL) {
 979                         kfree(pool->hw_i2cs[i]);
 980                         pool->hw_i2cs[i] = NULL;
 981                 }
 982                 if (pool->sw_i2cs[i] != NULL) {
 983                         kfree(pool->sw_i2cs[i]);
 984                         pool->sw_i2cs[i] = NULL;
 985                 }
 986         }
 987
 988         for (i = 0; i < pool->res_cap->num_opp; i++) {
 989                 if (pool->opps[i] != NULL)
 990                         pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
 991         }
 992
 993         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
 994                 if (pool->timing_generators[i] != NULL) {
 995                         kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
 996                         pool->timing_generators[i] = NULL;
 997                 }
 998         }
 999
1000         for (i = 0; i < pool->res_cap->num_dwb; i++) {
1001                 if (pool->dwbc[i] != NULL) {
1002                         kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1003                         pool->dwbc[i] = NULL;
1004                 }
1005                 if (pool->mcif_wb[i] != NULL) {
1006                         kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1007                         pool->mcif_wb[i] = NULL;
1008                 }
1009         }
1010
1011         for (i = 0; i < pool->audio_count; i++) {
1012                 if (pool->audios[i])
1013                         dce_aud_destroy(&pool->audios[i]);
1014         }
1015
1016         for (i = 0; i < pool->clk_src_count; i++) {
1017                 if (pool->clock_sources[i] != NULL)
1018                         dcn20_clock_source_destroy(&pool->clock_sources[i]);
1019         }
1020
1021         if (pool->dp_clock_source != NULL)
1022                 dcn20_clock_source_destroy(&pool->dp_clock_source);
1023
1024         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1025                 if (pool->mpc_lut[i] != NULL) {
1026                         dc_3dlut_func_release(pool->mpc_lut[i]);
1027                         pool->mpc_lut[i] = NULL;
1028                 }
1029                 if (pool->mpc_shaper[i] != NULL) {
1030                         dc_transfer_func_release(pool->mpc_shaper[i]);
1031                         pool->mpc_shaper[i] = NULL;
1032                 }
1033         }
1034
1035         for (i = 0; i < pool->pipe_count; i++) {
1036                 if (pool->multiple_abms[i] != NULL)
1037                         dce_abm_destroy(&pool->multiple_abms[i]);
1038         }
1039
1040         if (pool->psr != NULL)
1041                 dmub_psr_destroy(&pool->psr);
1042
1043         if (pool->dccg != NULL)
1044                 dcn_dccg_destroy(&pool->dccg);
1045
1046         if (pool->oem_device != NULL)
1047                 dal_ddc_service_destroy(&pool->oem_device);
1048 }
1049
1050 static void dcn303_destroy_resource_pool(struct resource_pool **pool)
1051 {
1052         dcn303_resource_destruct(*pool);
1053         kfree(*pool);
1054         *pool = NULL;
1055 }
1056
1057
1058 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1059 {
1060         DC_FP_START();
1061         dcn303_fpu_update_bw_bounding_box(dc, bw_params);
1062         DC_FP_END();
1063 }
1064
1065 static struct resource_funcs dcn303_res_pool_funcs = {
1066                 .destroy = dcn303_destroy_resource_pool,
1067                 .link_enc_create = dcn303_link_encoder_create,
1068                 .panel_cntl_create = dcn303_panel_cntl_create,
1069                 .validate_bandwidth = dcn30_validate_bandwidth,
1070                 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1071                 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1072                 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1073                 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1074                 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1075                 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1076                 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1077                 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1078                 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1079                 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1080                 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1081                 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1082                 .update_bw_bounding_box = dcn303_update_bw_bounding_box,
1083                 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1084 };
1085
1086 static struct dc_cap_funcs cap_funcs = {
1087                 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1088 };
1089
1090 static const struct bios_registers bios_regs = {
1091                 NBIO_SR(BIOS_SCRATCH_3),
1092                 NBIO_SR(BIOS_SCRATCH_6)
1093 };
1094
1095 static const struct dccg_registers dccg_regs = {
1096                 DCCG_REG_LIST_DCN3_03()
1097 };
1098
1099 static const struct dccg_shift dccg_shift = {
1100                 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)
1101 };
1102
1103 static const struct dccg_mask dccg_mask = {
1104                 DCCG_MASK_SH_LIST_DCN3_03(_MASK)
1105 };
1106
1107 #define abm_regs(id)\
1108                 [id] = { ABM_DCN302_REG_LIST(id) }
1109
1110 static const struct dce_abm_registers abm_regs[] = {
1111                 abm_regs(0),
1112                 abm_regs(1)
1113 };
1114
1115 static const struct dce_abm_shift abm_shift = {
1116                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1117 };
1118
1119 static const struct dce_abm_mask abm_mask = {
1120                 ABM_MASK_SH_LIST_DCN30(_MASK)
1121 };
1122
1123 static bool dcn303_resource_construct(
1124                 uint8_t num_virtual_links,
1125                 struct dc *dc,
1126                 struct resource_pool *pool)
1127 {
1128         int i;
1129         struct dc_context *ctx = dc->ctx;
1130         struct irq_service_init_data init_data;
1131         struct ddc_service_init_data ddc_init_data;
1132
1133         ctx->dc_bios->regs = &bios_regs;
1134
1135         pool->res_cap = &res_cap_dcn303;
1136
1137         pool->funcs = &dcn303_res_pool_funcs;
1138
1139         /*************************************************
1140          *  Resource + asic cap harcoding                *
1141          *************************************************/
1142         pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1143         pool->pipe_count = pool->res_cap->num_timing_generator;
1144         pool->mpcc_count = pool->res_cap->num_timing_generator;
1145         dc->caps.max_downscale_ratio = 600;
1146         dc->caps.i2c_speed_in_khz = 100;
1147         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1148         dc->caps.max_cursor_size = 256;
1149         dc->caps.min_horizontal_blanking_period = 80;
1150         dc->caps.dmdata_alloc_size = 2048;
1151 #if defined(CONFIG_DRM_AMD_DC_DCN)
1152         dc->caps.mall_size_per_mem_channel = 4;
1153         /* total size = mall per channel * num channels * 1024 * 1024 */
1154         dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
1155                                    dc->ctx->dc_bios->vram_info.num_chans *
1156                                    1024 * 1024;
1157         dc->caps.cursor_cache_size =
1158                 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1159 #endif
1160         dc->caps.max_slave_planes = 1;
1161         dc->caps.post_blend_color_processing = true;
1162         dc->caps.force_dp_tps4_for_cp2520 = true;
1163         dc->caps.extended_aux_timeout_support = true;
1164         dc->caps.dmcub_support = true;
1165
1166         /* Color pipeline capabilities */
1167         dc->caps.color.dpp.dcn_arch = 1;
1168         dc->caps.color.dpp.input_lut_shared = 0;
1169         dc->caps.color.dpp.icsc = 1;
1170         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1171         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1172         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1173         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1174         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1175         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1176         dc->caps.color.dpp.post_csc = 1;
1177         dc->caps.color.dpp.gamma_corr = 1;
1178         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1179
1180         dc->caps.color.dpp.hw_3d_lut = 1;
1181         dc->caps.color.dpp.ogam_ram = 1;
1182         // no OGAM ROM on DCN3
1183         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1184         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1185         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1186         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1187         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1188         dc->caps.color.dpp.ocsc = 0;
1189
1190         dc->caps.color.mpc.gamut_remap = 1;
1191         dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1192         dc->caps.color.mpc.ogam_ram = 1;
1193         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1194         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1195         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1196         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1197         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1198         dc->caps.color.mpc.ocsc = 1;
1199
1200         /* read VBIOS LTTPR caps */
1201         if (ctx->dc_bios->funcs->get_lttpr_caps) {
1202                 enum bp_result bp_query_result;
1203                 uint8_t is_vbios_lttpr_enable = 0;
1204
1205                 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1206                 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1207         }
1208
1209         if (ctx->dc_bios->funcs->get_lttpr_interop) {
1210                 enum bp_result bp_query_result;
1211                 uint8_t is_vbios_interop_enabled = 0;
1212
1213                 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1214                 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1215         }
1216
1217         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1218                 dc->debug = debug_defaults_drv;
1219         else
1220                 dc->debug = debug_defaults_diags;
1221
1222         // Init the vm_helper
1223         if (dc->vm_helper)
1224                 vm_helper_init(dc->vm_helper, 16);
1225
1226         /*************************************************
1227          *  Create resources                             *
1228          *************************************************/
1229
1230         /* Clock Sources for Pixel Clock*/
1231         pool->clock_sources[DCN303_CLK_SRC_PLL0] =
1232                         dcn303_clock_source_create(ctx, ctx->dc_bios,
1233                                         CLOCK_SOURCE_COMBO_PHY_PLL0,
1234                                         &clk_src_regs[0], false);
1235         pool->clock_sources[DCN303_CLK_SRC_PLL1] =
1236                         dcn303_clock_source_create(ctx, ctx->dc_bios,
1237                                         CLOCK_SOURCE_COMBO_PHY_PLL1,
1238                                         &clk_src_regs[1], false);
1239
1240         pool->clk_src_count = DCN303_CLK_SRC_TOTAL;
1241
1242         /* todo: not reuse phy_pll registers */
1243         pool->dp_clock_source =
1244                         dcn303_clock_source_create(ctx, ctx->dc_bios,
1245                                         CLOCK_SOURCE_ID_DP_DTO,
1246                                         &clk_src_regs[0], true);
1247
1248         for (i = 0; i < pool->clk_src_count; i++) {
1249                 if (pool->clock_sources[i] == NULL) {
1250                         dm_error("DC: failed to create clock sources!\n");
1251                         BREAK_TO_DEBUGGER();
1252                         goto create_fail;
1253                 }
1254         }
1255
1256         /* DCCG */
1257         pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1258         if (pool->dccg == NULL) {
1259                 dm_error("DC: failed to create dccg!\n");
1260                 BREAK_TO_DEBUGGER();
1261                 goto create_fail;
1262         }
1263
1264         /* PP Lib and SMU interfaces */
1265         init_soc_bounding_box(dc, pool);
1266
1267         /* DML */
1268         dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
1269
1270         /* IRQ */
1271         init_data.ctx = dc->ctx;
1272         pool->irqs = dal_irq_service_dcn303_create(&init_data);
1273         if (!pool->irqs)
1274                 goto create_fail;
1275
1276         /* HUBBUB */
1277         pool->hubbub = dcn303_hubbub_create(ctx);
1278         if (pool->hubbub == NULL) {
1279                 BREAK_TO_DEBUGGER();
1280                 dm_error("DC: failed to create hubbub!\n");
1281                 goto create_fail;
1282         }
1283
1284         /* HUBPs, DPPs, OPPs and TGs */
1285         for (i = 0; i < pool->pipe_count; i++) {
1286                 pool->hubps[i] = dcn303_hubp_create(ctx, i);
1287                 if (pool->hubps[i] == NULL) {
1288                         BREAK_TO_DEBUGGER();
1289                         dm_error("DC: failed to create hubps!\n");
1290                         goto create_fail;
1291                 }
1292
1293                 pool->dpps[i] = dcn303_dpp_create(ctx, i);
1294                 if (pool->dpps[i] == NULL) {
1295                         BREAK_TO_DEBUGGER();
1296                         dm_error("DC: failed to create dpps!\n");
1297                         goto create_fail;
1298                 }
1299         }
1300
1301         for (i = 0; i < pool->res_cap->num_opp; i++) {
1302                 pool->opps[i] = dcn303_opp_create(ctx, i);
1303                 if (pool->opps[i] == NULL) {
1304                         BREAK_TO_DEBUGGER();
1305                         dm_error("DC: failed to create output pixel processor!\n");
1306                         goto create_fail;
1307                 }
1308         }
1309
1310         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1311                 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);
1312                 if (pool->timing_generators[i] == NULL) {
1313                         BREAK_TO_DEBUGGER();
1314                         dm_error("DC: failed to create tg!\n");
1315                         goto create_fail;
1316                 }
1317         }
1318         pool->timing_generator_count = i;
1319
1320         /* PSR */
1321         pool->psr = dmub_psr_create(ctx);
1322         if (pool->psr == NULL) {
1323                 dm_error("DC: failed to create psr!\n");
1324                 BREAK_TO_DEBUGGER();
1325                 goto create_fail;
1326         }
1327
1328         /* ABM */
1329         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1330                 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1331                 if (pool->multiple_abms[i] == NULL) {
1332                         dm_error("DC: failed to create abm for pipe %d!\n", i);
1333                         BREAK_TO_DEBUGGER();
1334                         goto create_fail;
1335                 }
1336         }
1337
1338         /* MPC and DSC */
1339         pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1340         if (pool->mpc == NULL) {
1341                 BREAK_TO_DEBUGGER();
1342                 dm_error("DC: failed to create mpc!\n");
1343                 goto create_fail;
1344         }
1345
1346         for (i = 0; i < pool->res_cap->num_dsc; i++) {
1347                 pool->dscs[i] = dcn303_dsc_create(ctx, i);
1348                 if (pool->dscs[i] == NULL) {
1349                         BREAK_TO_DEBUGGER();
1350                         dm_error("DC: failed to create display stream compressor %d!\n", i);
1351                         goto create_fail;
1352                 }
1353         }
1354
1355         /* DWB and MMHUBBUB */
1356         if (!dcn303_dwbc_create(ctx, pool)) {
1357                 BREAK_TO_DEBUGGER();
1358                 dm_error("DC: failed to create dwbc!\n");
1359                 goto create_fail;
1360         }
1361
1362         if (!dcn303_mmhubbub_create(ctx, pool)) {
1363                 BREAK_TO_DEBUGGER();
1364                 dm_error("DC: failed to create mcif_wb!\n");
1365                 goto create_fail;
1366         }
1367
1368         /* AUX and I2C */
1369         for (i = 0; i < pool->res_cap->num_ddc; i++) {
1370                 pool->engines[i] = dcn303_aux_engine_create(ctx, i);
1371                 if (pool->engines[i] == NULL) {
1372                         BREAK_TO_DEBUGGER();
1373                         dm_error("DC:failed to create aux engine!!\n");
1374                         goto create_fail;
1375                 }
1376                 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);
1377                 if (pool->hw_i2cs[i] == NULL) {
1378                         BREAK_TO_DEBUGGER();
1379                         dm_error("DC:failed to create hw i2c!!\n");
1380                         goto create_fail;
1381                 }
1382                 pool->sw_i2cs[i] = NULL;
1383         }
1384
1385         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1386         if (!resource_construct(num_virtual_links, dc, pool,
1387                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1388                                         &res_create_funcs : &res_create_maximus_funcs)))
1389                 goto create_fail;
1390
1391         /* HW Sequencer and Plane caps */
1392         dcn303_hw_sequencer_construct(dc);
1393
1394         dc->caps.max_planes =  pool->pipe_count;
1395
1396         for (i = 0; i < dc->caps.max_planes; ++i)
1397                 dc->caps.planes[i] = plane_cap;
1398
1399         dc->cap_funcs = cap_funcs;
1400
1401         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1402                 ddc_init_data.ctx = dc->ctx;
1403                 ddc_init_data.link = NULL;
1404                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1405                 ddc_init_data.id.enum_id = 0;
1406                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1407                 pool->oem_device = dal_ddc_service_create(&ddc_init_data);
1408         } else {
1409                 pool->oem_device = NULL;
1410         }
1411
1412         return true;
1413
1414 create_fail:
1415
1416         dcn303_resource_destruct(pool);
1417
1418         return false;
1419 }
1420
1421 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1422 {
1423         struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1424
1425         if (!pool)
1426                 return NULL;
1427
1428         if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
1429                 return pool;
1430
1431         BREAK_TO_DEBUGGER();
1432         kfree(pool);
1433         return NULL;
1434 }