drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "reg_helper.h"
  27
  28 #include "core_types.h"
  29 #include "link_encoder.h"
  30 #include "dcn301_dio_link_encoder.h"
  31 #include "stream_encoder.h"
  32 #include "dc_bios_types.h"
  33 #include "gpio_service_interface.h"
  34
  35 #define CTX \
  36         enc10->base.ctx
  37 #define DC_LOGGER \
  38         enc10->base.ctx->logger
  39
  40 #define REG(reg)\
  41         (enc10->link_regs->reg)
  42
  43 #undef FN
  44 #define FN(reg_name, field_name) \
  45         enc10->link_shift->field_name, enc10->link_mask->field_name
  46
  47 #define IND_REG(index) \
  48         (enc10->link_regs->index)
  49
  50 static const struct link_encoder_funcs dcn301_link_enc_funcs = {
  51         .read_state = link_enc2_read_state,
  52         .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream,
  53         .hw_init = enc3_hw_init,
  54         .setup = dcn10_link_encoder_setup,
  55         .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
  56         .enable_dp_output = dcn20_link_encoder_enable_dp_output,
  57         .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
  58         .disable_output = dcn10_link_encoder_disable_output,
  59         .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
  60         .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
  61         .update_mst_stream_allocation_table = dcn10_link_encoder_update_mst_stream_allocation_table,
  62         .psr_program_dp_dphy_fast_training = dcn10_psr_program_dp_dphy_fast_training,
  63         .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
  64         .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
  65         .enable_hpd = dcn10_link_encoder_enable_hpd,
  66         .disable_hpd = dcn10_link_encoder_disable_hpd,
  67         .is_dig_enabled = dcn10_is_dig_enabled,
  68         .destroy = dcn10_link_encoder_destroy,
  69         .fec_set_enable = enc2_fec_set_enable,
  70         .fec_set_ready = enc2_fec_set_ready,
  71         .fec_is_active = enc2_fec_is_active,
  72         .get_dig_frontend = dcn10_get_dig_frontend,
  73         .get_dig_mode = dcn10_get_dig_mode,
  74         .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
  75         .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
  76 };
  77
  78 void dcn301_link_encoder_construct(
  79         struct dcn20_link_encoder *enc20,
  80         const struct encoder_init_data *init_data,
  81         const struct encoder_feature_support *enc_features,
  82         const struct dcn10_link_enc_registers *link_regs,
  83         const struct dcn10_link_enc_aux_registers *aux_regs,
  84         const struct dcn10_link_enc_hpd_registers *hpd_regs,
  85         const struct dcn10_link_enc_shift *link_shift,
  86         const struct dcn10_link_enc_mask *link_mask)
  87 {
  88         struct bp_encoder_cap_info bp_cap_info = {0};
  89         const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
  90         enum bp_result result = BP_RESULT_OK;
  91         struct dcn10_link_encoder *enc10 = &enc20->enc10;
  92
  93         enc10->base.funcs = &dcn301_link_enc_funcs;
  94         enc10->base.ctx = init_data->ctx;
  95         enc10->base.id = init_data->encoder;
  96
  97         enc10->base.hpd_source = init_data->hpd_source;
  98         enc10->base.connector = init_data->connector;
  99
 100         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 101
 102         enc10->base.features = *enc_features;
 103
 104         enc10->base.transmitter = init_data->transmitter;
 105
 106         /* set the flag to indicate whether driver poll the I2C data pin
 107          * while doing the DP sink detect
 108          */
 109
 110 /*      if (dal_adapter_service_is_feature_supported(as,
 111                 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 112                 enc10->base.features.flags.bits.
 113                         DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 114
 115         enc10->base.output_signals =
 116                 SIGNAL_TYPE_DVI_SINGLE_LINK |
 117                 SIGNAL_TYPE_DVI_DUAL_LINK |
 118                 SIGNAL_TYPE_LVDS |
 119                 SIGNAL_TYPE_DISPLAY_PORT |
 120                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 121                 SIGNAL_TYPE_EDP |
 122                 SIGNAL_TYPE_HDMI_TYPE_A;
 123
 124         /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 125          * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 126          * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 127          * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 128          * Prefer DIG assignment is decided by board design.
 129          * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 130          * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 131          * By this, adding DIGG should not hurt DCE 8.0.
 132          * This will let DCE 8.1 share DCE 8.0 as much as possible
 133          */
 134
 135         enc10->link_regs = link_regs;
 136         enc10->aux_regs = aux_regs;
 137         enc10->hpd_regs = hpd_regs;
 138         enc10->link_shift = link_shift;
 139         enc10->link_mask = link_mask;
 140
 141         switch (enc10->base.transmitter) {
 142         case TRANSMITTER_UNIPHY_A:
 143                 enc10->base.preferred_engine = ENGINE_ID_DIGA;
 144         break;
 145         case TRANSMITTER_UNIPHY_B:
 146                 enc10->base.preferred_engine = ENGINE_ID_DIGB;
 147         break;
 148         case TRANSMITTER_UNIPHY_C:
 149                 enc10->base.preferred_engine = ENGINE_ID_DIGC;
 150         break;
 151         case TRANSMITTER_UNIPHY_D:
 152                 enc10->base.preferred_engine = ENGINE_ID_DIGD;
 153         break;
 154         case TRANSMITTER_UNIPHY_E:
 155                 enc10->base.preferred_engine = ENGINE_ID_DIGE;
 156         break;
 157         case TRANSMITTER_UNIPHY_F:
 158                 enc10->base.preferred_engine = ENGINE_ID_DIGF;
 159         break;
 160         case TRANSMITTER_UNIPHY_G:
 161                 enc10->base.preferred_engine = ENGINE_ID_DIGG;
 162         break;
 163         default:
 164                 ASSERT_CRITICAL(false);
 165                 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 166         }
 167
 168         /* default to one to mirror Windows behavior */
 169         enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
 170
 171         result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
 172                                                 enc10->base.id, &bp_cap_info);
 173
 174         /* Override features with DCE-specific values */
 175         if (result == BP_RESULT_OK) {
 176                 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
 177                                 bp_cap_info.DP_HBR2_EN;
 178                 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
 179                                 bp_cap_info.DP_HBR3_EN;
 180                 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 181                 enc10->base.features.flags.bits.DP_IS_USB_C =
 182                                 bp_cap_info.DP_IS_USB_C;
 183         } else {
 184                 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 185                                 __func__,
 186                                 result);
 187         }
 188         if (enc10->base.ctx->dc->debug.hdmi20_disable) {
 189                 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
 190         }
 191 }