2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
31 #include "dcn30_hwseq.h"
33 #include "dce/dce_hwseq.h"
34 #include "dcn30_mpc.h"
35 #include "dcn30_dpp.h"
36 #include "dcn10/dcn10_cm_common.h"
37 #include "dcn30_cm_common.h"
38 #include "reg_helper.h"
43 #include "timing_generator.h"
48 #include "dc_dmub_srv.h"
49 #include "link_hwss.h"
50 #include "dpcd_defs.h"
51 #include "../dcn20/dcn20_hwseq.h"
52 #include "dcn30_resource.h"
58 #define DC_LOGGER_INIT(logger)
69 #define FN(reg_name, field_name) \
70 hws->shifts->field_name, hws->masks->field_name
72 bool dcn30_set_blend_lut(
73 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
75 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
77 struct pwl_params *blend_lut = NULL;
79 if (plane_state->blend_tf) {
80 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
81 blend_lut = &plane_state->blend_tf->pwl;
82 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
83 cm3_helper_translate_curve_to_hw_format(
84 plane_state->blend_tf, &dpp_base->regamma_params, false);
85 blend_lut = &dpp_base->regamma_params;
88 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
93 static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
94 const struct dc_stream_state *stream)
96 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
97 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
98 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
100 int acquired_rmu = 0;
101 int mpcc_id_projected = 0;
103 const struct pwl_params *shaper_lut = NULL;
104 //get the shaper lut params
105 if (stream->func_shaper) {
106 if (stream->func_shaper->type == TF_TYPE_HWPWL) {
107 shaper_lut = &stream->func_shaper->pwl;
108 } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
109 cm_helper_translate_curve_to_hw_format(stream->func_shaper,
110 &dpp_base->shaper_params, true);
111 shaper_lut = &dpp_base->shaper_params;
115 if (stream->lut3d_func &&
116 stream->lut3d_func->state.bits.initialized == 1 &&
117 stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
118 if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
119 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
120 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
121 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
122 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
123 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
124 if (mpcc_id_projected != mpcc_id)
126 /* find the reason why logical layer assigned a different
127 * mpcc_id into acquire_post_bldn_3dlut
129 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
130 stream->lut3d_func->state.bits.rmu_mux_num);
131 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
134 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,
135 stream->lut3d_func->state.bits.rmu_mux_num);
136 result = mpc->funcs->program_shaper(mpc, shaper_lut,
137 stream->lut3d_func->state.bits.rmu_mux_num);
139 // loop through the available mux and release the requested mpcc_id
140 mpc->funcs->release_rmu(mpc, mpcc_id);
146 bool dcn30_set_input_transfer_func(struct dc *dc,
147 struct pipe_ctx *pipe_ctx,
148 const struct dc_plane_state *plane_state)
150 struct dce_hwseq *hws = dc->hwseq;
151 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
152 enum dc_transfer_func_predefined tf;
154 struct pwl_params *params = NULL;
156 if (dpp_base == NULL || plane_state == NULL)
159 tf = TRANSFER_FUNCTION_UNITY;
161 if (plane_state->in_transfer_func &&
162 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
163 tf = plane_state->in_transfer_func->tf;
165 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
167 if (plane_state->in_transfer_func) {
168 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
169 params = &plane_state->in_transfer_func->pwl;
170 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
171 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
172 &dpp_base->degamma_params, false))
173 params = &dpp_base->degamma_params;
176 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
178 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
179 if (dpp_base->funcs->dpp_program_blnd_lut)
180 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
181 if (dpp_base->funcs->dpp_program_shaper_lut &&
182 dpp_base->funcs->dpp_program_3dlut)
183 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
189 bool dcn30_set_output_transfer_func(struct dc *dc,
190 struct pipe_ctx *pipe_ctx,
191 const struct dc_stream_state *stream)
193 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
194 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
195 struct pwl_params *params = NULL;
198 /* program OGAM or 3DLUT only for the top pipe*/
199 if (pipe_ctx->top_pipe == NULL) {
200 /*program rmu shaper and 3dlut in MPC*/
201 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
202 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
203 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
204 params = &stream->out_transfer_func->pwl;
205 else if (pipe_ctx->stream->out_transfer_func->type ==
206 TF_TYPE_DISTRIBUTED_POINTS &&
207 cm3_helper_translate_curve_to_hw_format(
208 stream->out_transfer_func,
209 &mpc->blender_params, false))
210 params = &mpc->blender_params;
211 /* there are no ROM LUTs in OUTGAM */
212 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
217 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
221 static void dcn30_set_writeback(
223 struct dc_writeback_info *wb_info,
224 struct dc_state *context)
226 struct mcif_wb *mcif_wb;
227 struct mcif_buf_params *mcif_buf_params;
229 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
230 ASSERT(wb_info->wb_enabled);
231 ASSERT(wb_info->mpcc_inst >= 0);
232 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
233 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
234 mcif_buf_params = &wb_info->mcif_buf_params;
236 /* set DWB MPC mux */
237 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
238 wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
239 /* set MCIF_WB buffer and arbitration configuration */
240 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
241 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
244 void dcn30_update_writeback(
246 struct dc_writeback_info *wb_info,
247 struct dc_state *context)
250 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
251 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
252 __func__, wb_info->dwb_pipe_inst,\
255 dcn30_set_writeback(dc, wb_info, context);
258 dwb->funcs->update(dwb, &wb_info->dwb_params);
261 bool dcn30_mmhubbub_warmup(
263 unsigned int num_dwb,
264 struct dc_writeback_info *wb_info)
267 struct mcif_wb *mcif_wb;
268 struct mcif_warmup_params warmup_params = {0};
269 unsigned int i, i_buf;
270 /*make sure there is no active DWB eanbled */
271 for (i = 0; i < num_dwb; i++) {
272 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
273 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
274 /*can not do warmup while any dwb enabled*/
279 if (wb_info->mcif_warmup_params.p_vmid == 0)
282 /*check whether this is new interface: warmup big buffer once*/
283 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
284 wb_info->mcif_warmup_params.region_size != 0) {
285 /*mmhubbub is shared, so it does not matter which MCIF*/
286 mcif_wb = dc->res_pool->mcif_wb[0];
287 /*warmup a big chunk of VM buffer at once*/
288 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
289 warmup_params.address_increment = wb_info->mcif_warmup_params.region_size;
290 warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
291 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
293 if (warmup_params.address_increment == 0)
294 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
296 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
299 /*following is the original: warmup each DWB's mcif buffer*/
300 for (i = 0; i < num_dwb; i++) {
301 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
302 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
303 /*warmup is for VM mode only*/
304 if (wb_info[i].mcif_buf_params.p_vmid == 0)
308 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
309 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
310 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
311 warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
312 warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
313 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
319 void dcn30_enable_writeback(
321 struct dc_writeback_info *wb_info,
322 struct dc_state *context)
325 struct mcif_wb *mcif_wb;
327 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
328 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
330 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
331 __func__, wb_info->dwb_pipe_inst,\
333 if (IS_DIAG_DC(dc->ctx->dce_environment)) {
334 /*till diags switch to warmup interface*/
335 dcn30_mmhubbub_warmup(dc, 1, wb_info);
337 /* Update writeback pipe */
338 dcn30_set_writeback(dc, wb_info, context);
341 mcif_wb->funcs->enable_mcif(mcif_wb);
343 dwb->funcs->enable(dwb, &wb_info->dwb_params);
346 void dcn30_disable_writeback(
348 unsigned int dwb_pipe_inst)
351 struct mcif_wb *mcif_wb;
353 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
354 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
355 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
356 DC_LOG_DWB("%s dwb_pipe_inst = %d",\
357 __func__, dwb_pipe_inst);
360 dwb->funcs->disable(dwb);
362 mcif_wb->funcs->disable_mcif(mcif_wb);
363 /* disable MPC DWB mux */
364 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
367 void dcn30_program_all_writeback_pipes_in_tree(
369 const struct dc_stream_state *stream,
370 struct dc_state *context)
372 struct dc_writeback_info wb_info;
374 struct dc_stream_status *stream_status = NULL;
375 int i_wb, i_pipe, i_stream;
376 DC_LOG_DWB("%s", __func__);
379 for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
380 if (context->streams[i_stream] == stream) {
381 stream_status = &context->stream_status[i_stream];
385 ASSERT(stream_status);
387 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
388 /* For each writeback pipe */
389 for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
391 /* copy writeback info to local non-const so mpcc_inst can be set */
392 wb_info = stream->writeback_info[i_wb];
393 if (wb_info.wb_enabled) {
395 /* get the MPCC instance for writeback_source_plane */
396 wb_info.mpcc_inst = -1;
397 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
398 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
400 if (!pipe_ctx->plane_state)
403 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
404 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
409 if (wb_info.mpcc_inst == -1) {
410 /* Disable writeback pipe and disconnect from MPCC
411 * if source plane has been removed
413 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
417 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
418 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
419 if (dwb->funcs->is_enabled(dwb)) {
420 /* writeback pipe already enabled, only need to update */
421 dc->hwss.update_writeback(dc, &wb_info, context);
423 /* Enable writeback pipe and connect to MPCC */
424 dc->hwss.enable_writeback(dc, &wb_info, context);
427 /* Disable writeback pipe and disconnect from MPCC */
428 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
433 void dcn30_init_hw(struct dc *dc)
435 struct abm **abms = dc->res_pool->multiple_abms;
436 struct dce_hwseq *hws = dc->hwseq;
437 struct dc_bios *dcb = dc->ctx->dc_bios;
438 struct resource_pool *res_pool = dc->res_pool;
441 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
443 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
444 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
446 // Initialize the dccg
447 if (res_pool->dccg->funcs->dccg_init)
448 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
450 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
452 REG_WRITE(REFCLK_CNTL, 0);
453 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
454 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
456 if (!dc->debug.disable_clock_gate) {
457 /* enable all DCN clock gating */
458 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
460 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
462 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
465 //Enable ability to power gate / don't force power on permanently
466 if (hws->funcs.enable_power_gating_plane)
467 hws->funcs.enable_power_gating_plane(hws, true);
472 if (!dcb->funcs->is_accelerated_mode(dcb)) {
473 hws->funcs.bios_golden_init(dc);
474 hws->funcs.disable_vga(dc->hwseq);
477 if (dc->debug.enable_mem_low_power.bits.dmcu) {
478 // Force ERAM to shutdown if DMCU is not enabled
479 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
480 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
484 // Set default OPTC memory power states
485 if (dc->debug.enable_mem_low_power.bits.optc) {
486 // Shutdown when unassigned and light sleep in VBLANK
487 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
490 if (dc->ctx->dc_bios->fw_info_valid) {
491 res_pool->ref_clocks.xtalin_clock_inKhz =
492 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
494 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
495 if (res_pool->dccg && res_pool->hubbub) {
497 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
498 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
499 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
501 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
502 res_pool->ref_clocks.dccg_ref_clock_inKhz,
503 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
505 // Not all ASICs have DCCG sw component
506 res_pool->ref_clocks.dccg_ref_clock_inKhz =
507 res_pool->ref_clocks.xtalin_clock_inKhz;
508 res_pool->ref_clocks.dchub_ref_clock_inKhz =
509 res_pool->ref_clocks.xtalin_clock_inKhz;
513 ASSERT_CRITICAL(false);
515 for (i = 0; i < dc->link_count; i++) {
516 /* Power up AND update implementation according to the
517 * required signal (which may be different from the
518 * default signal on connector).
520 struct dc_link *link = dc->links[i];
522 link->link_enc->funcs->hw_init(link->link_enc);
524 /* Check for enabled DIG to identify enabled display */
525 if (link->link_enc->funcs->is_dig_enabled &&
526 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
527 link->link_status.link_active = true;
528 if (link->link_enc->funcs->fec_is_active &&
529 link->link_enc->funcs->fec_is_active(link->link_enc))
530 link->fec_state = dc_link_fec_enabled;
534 /* we want to turn off all dp displays before doing detection */
535 dc->link_srv->blank_all_dp_displays(dc);
537 if (hws->funcs.enable_power_gating_plane)
538 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
540 /* If taking control over from VBIOS, we may want to optimize our first
541 * mode set, so we need to skip powering down pipes until we know which
542 * pipes we want to use.
543 * Otherwise, if taking control is not possible, we need to power
546 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
547 hws->funcs.init_pipes(dc, dc->current_state);
548 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
549 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
550 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
553 /* In headless boot cases, DIG may be turned
554 * on which causes HW/SW discrepancies.
555 * To avoid this, power down hardware on boot
556 * if DIG is turned on and seamless boot not enabled
558 if (!dc->config.seamless_boot_edp_requested) {
559 struct dc_link *edp_links[MAX_NUM_EDP];
560 struct dc_link *edp_link = NULL;
562 dc_get_edp_links(dc, edp_links, &edp_num);
564 edp_link = edp_links[0];
565 if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
566 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
567 dc->hwss.edp_backlight_control &&
568 dc->hwss.power_down &&
569 dc->hwss.edp_power_control) {
570 dc->hwss.edp_backlight_control(edp_link, false);
571 dc->hwss.power_down(dc);
572 dc->hwss.edp_power_control(edp_link, false);
574 for (i = 0; i < dc->link_count; i++) {
575 struct dc_link *link = dc->links[i];
577 if (link->link_enc->funcs->is_dig_enabled &&
578 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
579 dc->hwss.power_down) {
580 dc->hwss.power_down(dc);
588 for (i = 0; i < res_pool->audio_count; i++) {
589 struct audio *audio = res_pool->audios[i];
591 audio->funcs->hw_init(audio);
594 for (i = 0; i < dc->link_count; i++) {
595 struct dc_link *link = dc->links[i];
597 if (link->panel_cntl)
598 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
601 for (i = 0; i < dc->res_pool->pipe_count; i++) {
603 abms[i]->funcs->abm_init(abms[i], backlight);
606 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
607 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
609 if (!dc->debug.disable_clock_gate) {
610 /* enable all DCN clock gating */
611 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
613 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
615 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
618 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
619 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
621 if (dc->clk_mgr->funcs->notify_wm_ranges)
622 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
624 //if softmax is enabled then hardmax will be set by a different call
625 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
626 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
628 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
629 dc->res_pool->hubbub->funcs->force_pstate_change_control(
630 dc->res_pool->hubbub, false, false);
631 if (dc->res_pool->hubbub->funcs->init_crb)
632 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
634 // Get DMCUB capabilities
635 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
636 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
637 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
640 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
642 if (pipe_ctx == NULL)
645 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL)
646 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
647 pipe_ctx->stream_res.stream_enc,
651 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
656 ASSERT(pipe_ctx->stream);
658 if (pipe_ctx->stream_res.stream_enc == NULL)
659 return; /* this is not root pipe */
661 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
662 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
664 if (!is_hdmi_tmds && !is_dp)
668 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
669 pipe_ctx->stream_res.stream_enc,
670 &pipe_ctx->stream_res.encoder_info_frame);
672 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
673 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
674 pipe_ctx->stream_res.stream_enc,
675 &pipe_ctx->stream_res.encoder_info_frame);
677 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
678 pipe_ctx->stream_res.stream_enc,
679 &pipe_ctx->stream_res.encoder_info_frame);
683 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
685 struct dc_stream_state *stream = pipe_ctx->stream;
686 struct hubp *hubp = pipe_ctx->plane_res.hubp;
688 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
689 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
693 /* if using dynamic meta, don't set up generic infopackets */
694 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
695 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
702 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
705 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
709 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
711 union dmub_rb_cmd cmd;
712 uint32_t tmr_delay = 0, tmr_scale = 0;
713 struct dc_cursor_attributes cursor_attr;
714 bool cursor_cache_enable = false;
715 struct dc_stream_state *stream = NULL;
716 struct dc_plane_state *plane = NULL;
718 if (!dc->ctx->dmub_srv)
722 if (dc->current_state) {
725 /* First, check no-memory-requests case */
726 for (i = 0; i < dc->current_state->stream_count; i++) {
727 if (dc->current_state->stream_status[i].plane_count)
728 /* Fail eligibility on a visible stream */
732 if (i == dc->current_state->stream_count) {
733 /* Enable no-memory-requests case */
734 memset(&cmd, 0, sizeof(cmd));
735 cmd.mall.header.type = DMUB_CMD__MALL;
736 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
737 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
739 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
740 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
745 stream = dc->current_state->streams[0];
746 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
748 if (stream && plane) {
749 cursor_cache_enable = stream->cursor_position.enable &&
750 plane->address.grph.cursor_cache_addr.quad_part;
751 cursor_attr = stream->cursor_attributes;
755 * Second, check MALL eligibility
757 * single display only, single surface only, 8 and 16 bit formats only, no VM,
758 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
760 * TODO: When we implement multi-display, PSR displays will be allowed if there is
761 * a non-PSR display present, since in that case we can't do D0i3.2
763 if (dc->current_state->stream_count == 1 &&
764 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
765 dc->current_state->stream_status[0].plane_count == 1 &&
766 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
767 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
768 plane->address.page_table_base.quad_part == 0 &&
769 dc->hwss.does_plane_fit_in_mall &&
770 dc->hwss.does_plane_fit_in_mall(dc, plane,
771 cursor_cache_enable ? &cursor_attr : NULL)) {
772 unsigned int v_total = stream->adjust.v_total_max ?
773 stream->adjust.v_total_max : stream->timing.v_total;
774 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
775 100LL, (v_total * stream->timing.h_total));
778 * one frame time in microsec:
779 * Delay_Us = 1000000 / refresh
780 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
782 * one frame time modified by 'additional timer percent' (p):
783 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
784 * = dynamic_delay_us * (1 + p / 100)
785 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
786 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
788 * formula for timer duration based on parameters, from regspec:
789 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
791 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
792 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
793 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
794 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
795 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
797 * need to round up the result of the division before the subtraction
799 unsigned int denom = refresh_hz * 6528;
800 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
802 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
803 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
806 /* In some cases the stutter period is really big (tiny modes) in these
807 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
809 * We can check if stutter_period is more than 1/10th the frame time to
810 * consider if we can actually meet the range of hysteresis timer
812 if (stutter_period > 100000/refresh_hz)
815 /* scale should be increased until it fits into 6 bits */
816 while (tmr_delay & ~0x3F) {
820 /* Delay exceeds range of hysteresis timer */
826 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
827 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
832 if (cursor_cache_enable) {
833 memset(&cmd, 0, sizeof(cmd));
834 cmd.mall.header.type = DMUB_CMD__MALL;
835 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
836 cmd.mall.header.payload_bytes =
837 sizeof(cmd.mall) - sizeof(cmd.mall.header);
839 switch (cursor_attr.color_format) {
840 case CURSOR_MODE_MONO:
841 cmd.mall.cursor_bpp = 2;
843 case CURSOR_MODE_COLOR_1BIT_AND:
844 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
845 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
846 cmd.mall.cursor_bpp = 32;
849 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
850 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
851 cmd.mall.cursor_bpp = 64;
855 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
856 cmd.mall.cursor_copy_dst.quad_part =
857 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
858 cmd.mall.cursor_width = cursor_attr.width;
859 cmd.mall.cursor_height = cursor_attr.height;
860 cmd.mall.cursor_pitch = cursor_attr.pitch;
862 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
863 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
864 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
866 /* Use copied cursor, and it's okay to not switch back */
867 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
868 dc_stream_set_cursor_attributes(stream, &cursor_attr);
872 memset(&cmd, 0, sizeof(cmd));
873 cmd.mall.header.type = DMUB_CMD__MALL;
874 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
875 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
876 cmd.mall.tmr_delay = tmr_delay;
877 cmd.mall.tmr_scale = tmr_scale;
878 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
880 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
881 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
887 /* No applicable optimizations */
892 memset(&cmd, 0, sizeof(cmd));
893 cmd.mall.header.type = DMUB_CMD__MALL;
894 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
895 cmd.mall.header.payload_bytes =
896 sizeof(cmd.mall) - sizeof(cmd.mall.header);
898 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
899 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
900 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
905 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
908 unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
909 (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
910 unsigned int mall_size = dc->caps.mall_size_total;
911 unsigned int cursor_size = 0;
913 if (dc->debug.mall_size_override)
914 mall_size = 1024 * 1024 * dc->debug.mall_size_override;
917 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
919 switch (cursor_attr->color_format) {
920 case CURSOR_MODE_MONO:
923 case CURSOR_MODE_COLOR_1BIT_AND:
924 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
925 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
929 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
930 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
936 return (surface_size + cursor_size) < mall_size;
939 void dcn30_hardware_release(struct dc *dc)
941 bool subvp_in_use = false;
944 dc_dmub_srv_p_state_delegate(dc, false, NULL);
945 dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);
947 /* SubVP treated the same way as FPO. If driver disable and
948 * we are using a SubVP config, disable and force on DCN side
949 * to prevent P-State hang on driver enable.
951 for (i = 0; i < dc->res_pool->pipe_count; i++) {
952 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
957 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
962 /* If pstate unsupported, or still supported
963 * by firmware, force it supported by dcn
965 if (dc->current_state)
966 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||
967 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&
968 dc->res_pool->hubbub->funcs->force_pstate_change_control)
969 dc->res_pool->hubbub->funcs->force_pstate_change_control(
970 dc->res_pool->hubbub, true, true);
973 void dcn30_set_disp_pattern_generator(const struct dc *dc,
974 struct pipe_ctx *pipe_ctx,
975 enum controller_dp_test_pattern test_pattern,
976 enum controller_dp_color_space color_space,
977 enum dc_color_depth color_depth,
978 const struct tg_color *solid_color,
979 int width, int height, int offset)
981 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
982 color_space, color_depth, solid_color, width, height, offset);
985 void dcn30_prepare_bandwidth(struct dc *dc,
986 struct dc_state *context)
988 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
989 /* Any transition into an FPO config should disable MCLK switching first to avoid
990 * driver and FW P-State synchronization issues.
992 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
993 dc->optimized_required = true;
994 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
997 if (dc->clk_mgr->dc_mode_softmax_enabled)
998 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
999 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1000 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1002 dcn20_prepare_bandwidth(dc, context);
1004 * enabled -> enabled: do not disable
1005 * enabled -> disabled: disable
1006 * disabled -> enabled: don't care
1007 * disabled -> disabled: don't care
1009 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1010 dc_dmub_srv_p_state_delegate(dc, false, context);
1012 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1013 /* After disabling P-State, restore the original value to ensure we get the correct P-State
1014 * on the next optimize. */
1015 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;