drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

   1 /*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3  * Copyright 2019 Raptor Engineering, LLC
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "dc.h"
  31
  32 #include "dcn21_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn21/dcn21_resource.h"
  38
  39 #include "dml/dcn20/dcn20_fpu.h"
  40
  41 #include "clk_mgr.h"
  42 #include "dcn10/dcn10_hubp.h"
  43 #include "dcn10/dcn10_ipp.h"
  44 #include "dcn20/dcn20_hubbub.h"
  45 #include "dcn20/dcn20_mpc.h"
  46 #include "dcn20/dcn20_hubp.h"
  47 #include "dcn21_hubp.h"
  48 #include "irq/dcn21/irq_service_dcn21.h"
  49 #include "dcn20/dcn20_dpp.h"
  50 #include "dcn20/dcn20_optc.h"
  51 #include "dcn21/dcn21_hwseq.h"
  52 #include "dce110/dce110_hw_sequencer.h"
  53 #include "dcn20/dcn20_opp.h"
  54 #include "dcn20/dcn20_dsc.h"
  55 #include "dcn21/dcn21_link_encoder.h"
  56 #include "dcn20/dcn20_stream_encoder.h"
  57 #include "dce/dce_clock_source.h"
  58 #include "dce/dce_audio.h"
  59 #include "dce/dce_hwseq.h"
  60 #include "virtual/virtual_stream_encoder.h"
  61 #include "dml/display_mode_vba.h"
  62 #include "dcn20/dcn20_dccg.h"
  63 #include "dcn21/dcn21_dccg.h"
  64 #include "dcn21_hubbub.h"
  65 #include "dcn10/dcn10_resource.h"
  66 #include "dce/dce_panel_cntl.h"
  67
  68 #include "dcn20/dcn20_dwb.h"
  69 #include "dcn20/dcn20_mmhubbub.h"
  70 #include "dpcs/dpcs_2_1_0_offset.h"
  71 #include "dpcs/dpcs_2_1_0_sh_mask.h"
  72
  73 #include "renoir_ip_offset.h"
  74 #include "dcn/dcn_2_1_0_offset.h"
  75 #include "dcn/dcn_2_1_0_sh_mask.h"
  76
  77 #include "nbio/nbio_7_0_offset.h"
  78
  79 #include "mmhub/mmhub_2_0_0_offset.h"
  80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  81
  82 #include "reg_helper.h"
  83 #include "dce/dce_abm.h"
  84 #include "dce/dce_dmcu.h"
  85 #include "dce/dce_aux.h"
  86 #include "dce/dce_i2c.h"
  87 #include "dcn21_resource.h"
  88 #include "vm_helper.h"
  89 #include "dcn20/dcn20_vmid.h"
  90 #include "dce/dmub_psr.h"
  91 #include "dce/dmub_abm.h"
  92
  93 /* begin *********************
  94  * macros to expend register list macro defined in HW object header file */
  95
  96 /* DCN */
  97 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
  98
  99 #define BASE(seg) BASE_INNER(seg)
 100
 101 #define SR(reg_name)\
 102                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 103                                         mm ## reg_name
 104
 105 #define SRI(reg_name, block, id)\
 106         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 107                                         mm ## block ## id ## _ ## reg_name
 108
 109 #define SRIR(var_name, reg_name, block, id)\
 110         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 111                                         mm ## block ## id ## _ ## reg_name
 112
 113 #define SRII(reg_name, block, id)\
 114         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 115                                         mm ## block ## id ## _ ## reg_name
 116
 117 #define DCCG_SRII(reg_name, block, id)\
 118         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 119                                         mm ## block ## id ## _ ## reg_name
 120
 121 #define VUPDATE_SRII(reg_name, block, id)\
 122         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 123                                         mm ## reg_name ## _ ## block ## id
 124
 125 /* NBIO */
 126 #define NBIO_BASE_INNER(seg) \
 127         NBIF0_BASE__INST0_SEG ## seg
 128
 129 #define NBIO_BASE(seg) \
 130         NBIO_BASE_INNER(seg)
 131
 132 #define NBIO_SR(reg_name)\
 133                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 134                                         mm ## reg_name
 135
 136 /* MMHUB */
 137 #define MMHUB_BASE_INNER(seg) \
 138         MMHUB_BASE__INST0_SEG ## seg
 139
 140 #define MMHUB_BASE(seg) \
 141         MMHUB_BASE_INNER(seg)
 142
 143 #define MMHUB_SR(reg_name)\
 144                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 145                                         mmMM ## reg_name
 146
 147 #define clk_src_regs(index, pllid)\
 148 [index] = {\
 149         CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
 150 }
 151
 152 static const struct dce110_clk_src_regs clk_src_regs[] = {
 153         clk_src_regs(0, A),
 154         clk_src_regs(1, B),
 155         clk_src_regs(2, C),
 156         clk_src_regs(3, D),
 157         clk_src_regs(4, E),
 158 };
 159
 160 static const struct dce110_clk_src_shift cs_shift = {
 161                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 162 };
 163
 164 static const struct dce110_clk_src_mask cs_mask = {
 165                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 166 };
 167
 168 static const struct bios_registers bios_regs = {
 169                 NBIO_SR(BIOS_SCRATCH_3),
 170                 NBIO_SR(BIOS_SCRATCH_6)
 171 };
 172
 173 static const struct dce_dmcu_registers dmcu_regs = {
 174                 DMCU_DCN20_REG_LIST()
 175 };
 176
 177 static const struct dce_dmcu_shift dmcu_shift = {
 178                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 179 };
 180
 181 static const struct dce_dmcu_mask dmcu_mask = {
 182                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 183 };
 184
 185 static const struct dce_abm_registers abm_regs = {
 186                 ABM_DCN20_REG_LIST()
 187 };
 188
 189 static const struct dce_abm_shift abm_shift = {
 190                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 191 };
 192
 193 static const struct dce_abm_mask abm_mask = {
 194                 ABM_MASK_SH_LIST_DCN20(_MASK)
 195 };
 196
 197 #define audio_regs(id)\
 198 [id] = {\
 199                 AUD_COMMON_REG_LIST(id)\
 200 }
 201
 202 static const struct dce_audio_registers audio_regs[] = {
 203         audio_regs(0),
 204         audio_regs(1),
 205         audio_regs(2),
 206         audio_regs(3),
 207         audio_regs(4),
 208         audio_regs(5),
 209 };
 210
 211 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 212                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 213                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 214                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 215
 216 static const struct dce_audio_shift audio_shift = {
 217                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 218 };
 219
 220 static const struct dce_audio_mask audio_mask = {
 221                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 222 };
 223
 224 static const struct dccg_registers dccg_regs = {
 225                 DCCG_COMMON_REG_LIST_DCN_BASE()
 226 };
 227
 228 static const struct dccg_shift dccg_shift = {
 229                 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
 230 };
 231
 232 static const struct dccg_mask dccg_mask = {
 233                 DCCG_MASK_SH_LIST_DCN2_1(_MASK)
 234 };
 235
 236 #define opp_regs(id)\
 237 [id] = {\
 238         OPP_REG_LIST_DCN20(id),\
 239 }
 240
 241 static const struct dcn20_opp_registers opp_regs[] = {
 242         opp_regs(0),
 243         opp_regs(1),
 244         opp_regs(2),
 245         opp_regs(3),
 246         opp_regs(4),
 247         opp_regs(5),
 248 };
 249
 250 static const struct dcn20_opp_shift opp_shift = {
 251                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 252 };
 253
 254 static const struct dcn20_opp_mask opp_mask = {
 255                 OPP_MASK_SH_LIST_DCN20(_MASK)
 256 };
 257
 258 #define tg_regs(id)\
 259 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 260
 261 static const struct dcn_optc_registers tg_regs[] = {
 262         tg_regs(0),
 263         tg_regs(1),
 264         tg_regs(2),
 265         tg_regs(3)
 266 };
 267
 268 static const struct dcn_optc_shift tg_shift = {
 269         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 270 };
 271
 272 static const struct dcn_optc_mask tg_mask = {
 273         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 274 };
 275
 276 static const struct dcn20_mpc_registers mpc_regs = {
 277                 MPC_REG_LIST_DCN2_0(0),
 278                 MPC_REG_LIST_DCN2_0(1),
 279                 MPC_REG_LIST_DCN2_0(2),
 280                 MPC_REG_LIST_DCN2_0(3),
 281                 MPC_REG_LIST_DCN2_0(4),
 282                 MPC_REG_LIST_DCN2_0(5),
 283                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 284                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 285                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 286                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 287                 MPC_DBG_REG_LIST_DCN2_0()
 288 };
 289
 290 static const struct dcn20_mpc_shift mpc_shift = {
 291         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
 292         MPC_DEBUG_REG_LIST_SH_DCN20
 293 };
 294
 295 static const struct dcn20_mpc_mask mpc_mask = {
 296         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
 297         MPC_DEBUG_REG_LIST_MASK_DCN20
 298 };
 299
 300 #define hubp_regs(id)\
 301 [id] = {\
 302         HUBP_REG_LIST_DCN21(id)\
 303 }
 304
 305 static const struct dcn_hubp2_registers hubp_regs[] = {
 306                 hubp_regs(0),
 307                 hubp_regs(1),
 308                 hubp_regs(2),
 309                 hubp_regs(3)
 310 };
 311
 312 static const struct dcn_hubp2_shift hubp_shift = {
 313                 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
 314 };
 315
 316 static const struct dcn_hubp2_mask hubp_mask = {
 317                 HUBP_MASK_SH_LIST_DCN21(_MASK)
 318 };
 319
 320 static const struct dcn_hubbub_registers hubbub_reg = {
 321                 HUBBUB_REG_LIST_DCN21()
 322 };
 323
 324 static const struct dcn_hubbub_shift hubbub_shift = {
 325                 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
 326 };
 327
 328 static const struct dcn_hubbub_mask hubbub_mask = {
 329                 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
 330 };
 331
 332
 333 #define vmid_regs(id)\
 334 [id] = {\
 335                 DCN20_VMID_REG_LIST(id)\
 336 }
 337
 338 static const struct dcn_vmid_registers vmid_regs[] = {
 339         vmid_regs(0),
 340         vmid_regs(1),
 341         vmid_regs(2),
 342         vmid_regs(3),
 343         vmid_regs(4),
 344         vmid_regs(5),
 345         vmid_regs(6),
 346         vmid_regs(7),
 347         vmid_regs(8),
 348         vmid_regs(9),
 349         vmid_regs(10),
 350         vmid_regs(11),
 351         vmid_regs(12),
 352         vmid_regs(13),
 353         vmid_regs(14),
 354         vmid_regs(15)
 355 };
 356
 357 static const struct dcn20_vmid_shift vmid_shifts = {
 358                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 359 };
 360
 361 static const struct dcn20_vmid_mask vmid_masks = {
 362                 DCN20_VMID_MASK_SH_LIST(_MASK)
 363 };
 364
 365 #define dsc_regsDCN20(id)\
 366 [id] = {\
 367         DSC_REG_LIST_DCN20(id)\
 368 }
 369
 370 static const struct dcn20_dsc_registers dsc_regs[] = {
 371         dsc_regsDCN20(0),
 372         dsc_regsDCN20(1),
 373         dsc_regsDCN20(2),
 374         dsc_regsDCN20(3),
 375         dsc_regsDCN20(4),
 376         dsc_regsDCN20(5)
 377 };
 378
 379 static const struct dcn20_dsc_shift dsc_shift = {
 380         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 381 };
 382
 383 static const struct dcn20_dsc_mask dsc_mask = {
 384         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 385 };
 386
 387 #define ipp_regs(id)\
 388 [id] = {\
 389         IPP_REG_LIST_DCN20(id),\
 390 }
 391
 392 static const struct dcn10_ipp_registers ipp_regs[] = {
 393         ipp_regs(0),
 394         ipp_regs(1),
 395         ipp_regs(2),
 396         ipp_regs(3),
 397 };
 398
 399 static const struct dcn10_ipp_shift ipp_shift = {
 400                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 401 };
 402
 403 static const struct dcn10_ipp_mask ipp_mask = {
 404                 IPP_MASK_SH_LIST_DCN20(_MASK),
 405 };
 406
 407 #define opp_regs(id)\
 408 [id] = {\
 409         OPP_REG_LIST_DCN20(id),\
 410 }
 411
 412
 413 #define aux_engine_regs(id)\
 414 [id] = {\
 415         AUX_COMMON_REG_LIST0(id), \
 416         .AUXN_IMPCAL = 0, \
 417         .AUXP_IMPCAL = 0, \
 418         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 419 }
 420
 421 static const struct dce110_aux_registers aux_engine_regs[] = {
 422                 aux_engine_regs(0),
 423                 aux_engine_regs(1),
 424                 aux_engine_regs(2),
 425                 aux_engine_regs(3),
 426                 aux_engine_regs(4),
 427 };
 428
 429 #define tf_regs(id)\
 430 [id] = {\
 431         TF_REG_LIST_DCN20(id),\
 432         TF_REG_LIST_DCN20_COMMON_APPEND(id),\
 433 }
 434
 435 static const struct dcn2_dpp_registers tf_regs[] = {
 436         tf_regs(0),
 437         tf_regs(1),
 438         tf_regs(2),
 439         tf_regs(3),
 440 };
 441
 442 static const struct dcn2_dpp_shift tf_shift = {
 443                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 444                 TF_DEBUG_REG_LIST_SH_DCN20
 445 };
 446
 447 static const struct dcn2_dpp_mask tf_mask = {
 448                 TF_REG_LIST_SH_MASK_DCN20(_MASK),
 449                 TF_DEBUG_REG_LIST_MASK_DCN20
 450 };
 451
 452 #define stream_enc_regs(id)\
 453 [id] = {\
 454         SE_DCN2_REG_LIST(id)\
 455 }
 456
 457 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 458         stream_enc_regs(0),
 459         stream_enc_regs(1),
 460         stream_enc_regs(2),
 461         stream_enc_regs(3),
 462         stream_enc_regs(4),
 463 };
 464
 465 static const struct dce110_aux_registers_shift aux_shift = {
 466         DCN_AUX_MASK_SH_LIST(__SHIFT)
 467 };
 468
 469 static const struct dce110_aux_registers_mask aux_mask = {
 470         DCN_AUX_MASK_SH_LIST(_MASK)
 471 };
 472
 473 static const struct dcn10_stream_encoder_shift se_shift = {
 474                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 475 };
 476
 477 static const struct dcn10_stream_encoder_mask se_mask = {
 478                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 479 };
 480
 481 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
 482
 483 static struct input_pixel_processor *dcn21_ipp_create(
 484         struct dc_context *ctx, uint32_t inst)
 485 {
 486         struct dcn10_ipp *ipp =
 487                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 488
 489         if (!ipp) {
 490                 BREAK_TO_DEBUGGER();
 491                 return NULL;
 492         }
 493
 494         dcn20_ipp_construct(ipp, ctx, inst,
 495                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 496         return &ipp->base;
 497 }
 498
 499 static struct dpp *dcn21_dpp_create(
 500         struct dc_context *ctx,
 501         uint32_t inst)
 502 {
 503         struct dcn20_dpp *dpp =
 504                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 505
 506         if (!dpp)
 507                 return NULL;
 508
 509         if (dpp2_construct(dpp, ctx, inst,
 510                         &tf_regs[inst], &tf_shift, &tf_mask))
 511                 return &dpp->base;
 512
 513         BREAK_TO_DEBUGGER();
 514         kfree(dpp);
 515         return NULL;
 516 }
 517
 518 static struct dce_aux *dcn21_aux_engine_create(
 519         struct dc_context *ctx,
 520         uint32_t inst)
 521 {
 522         struct aux_engine_dce110 *aux_engine =
 523                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 524
 525         if (!aux_engine)
 526                 return NULL;
 527
 528         dce110_aux_engine_construct(aux_engine, ctx, inst,
 529                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 530                                     &aux_engine_regs[inst],
 531                                         &aux_mask,
 532                                         &aux_shift,
 533                                         ctx->dc->caps.extended_aux_timeout_support);
 534
 535         return &aux_engine->base;
 536 }
 537
 538 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 539
 540 static const struct dce_i2c_registers i2c_hw_regs[] = {
 541                 i2c_inst_regs(1),
 542                 i2c_inst_regs(2),
 543                 i2c_inst_regs(3),
 544                 i2c_inst_regs(4),
 545                 i2c_inst_regs(5),
 546 };
 547
 548 static const struct dce_i2c_shift i2c_shifts = {
 549                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 550 };
 551
 552 static const struct dce_i2c_mask i2c_masks = {
 553                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 554 };
 555
 556 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
 557                                               uint32_t inst)
 558 {
 559         struct dce_i2c_hw *dce_i2c_hw =
 560                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 561
 562         if (!dce_i2c_hw)
 563                 return NULL;
 564
 565         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 566                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 567
 568         return dce_i2c_hw;
 569 }
 570
 571 static const struct resource_caps res_cap_rn = {
 572                 .num_timing_generator = 4,
 573                 .num_opp = 4,
 574                 .num_video_plane = 4,
 575                 .num_audio = 4, // 4 audio endpoints.  4 audio streams
 576                 .num_stream_encoder = 5,
 577                 .num_pll = 5,  // maybe 3 because the last two used for USB-c
 578                 .num_dwb = 1,
 579                 .num_ddc = 5,
 580                 .num_vmid = 16,
 581                 .num_dsc = 3,
 582 };
 583
 584 #ifdef DIAGS_BUILD
 585 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
 586                 .num_timing_generator = 4,
 587                 .num_opp = 4,
 588                 .num_video_plane = 4,
 589                 .num_audio = 7,
 590                 .num_stream_encoder = 4,
 591                 .num_pll = 4,
 592                 .num_dwb = 1,
 593                 .num_ddc = 4,
 594                 .num_dsc = 0,
 595 };
 596
 597 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
 598                 .num_timing_generator = 2,
 599                 .num_opp = 2,
 600                 .num_video_plane = 2,
 601                 .num_audio = 7,
 602                 .num_stream_encoder = 2,
 603                 .num_pll = 4,
 604                 .num_dwb = 1,
 605                 .num_ddc = 4,
 606                 .num_dsc = 2,
 607 };
 608 #endif
 609
 610 static const struct dc_plane_cap plane_cap = {
 611         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 612         .per_pixel_alpha = true,
 613
 614         .pixel_format_support = {
 615                         .argb8888 = true,
 616                         .nv12 = true,
 617                         .fp16 = true,
 618                         .p010 = true
 619         },
 620
 621         .max_upscale_factor = {
 622                         .argb8888 = 16000,
 623                         .nv12 = 16000,
 624                         .fp16 = 16000
 625         },
 626
 627         .max_downscale_factor = {
 628                         .argb8888 = 250,
 629                         .nv12 = 250,
 630                         .fp16 = 250
 631         },
 632         64,
 633         64
 634 };
 635
 636 static const struct dc_debug_options debug_defaults_drv = {
 637                 .disable_dmcu = false,
 638                 .force_abm_enable = false,
 639                 .timing_trace = false,
 640                 .clock_trace = true,
 641                 .disable_pplib_clock_request = true,
 642                 .min_disp_clk_khz = 100000,
 643                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 644                 .force_single_disp_pipe_split = false,
 645                 .disable_dcc = DCC_ENABLE,
 646                 .vsr_support = true,
 647                 .performance_trace = false,
 648                 .max_downscale_src_width = 4096,
 649                 .disable_pplib_wm_range = false,
 650                 .scl_reset_length10 = true,
 651                 .sanity_checks = true,
 652                 .disable_48mhz_pwrdwn = false,
 653                 .usbc_combo_phy_reset_wa = true,
 654                 .dmub_command_table = true,
 655                 .use_max_lb = true,
 656                 .enable_legacy_fast_update = true,
 657 };
 658
 659 static const struct dc_panel_config panel_config_defaults = {
 660                 .psr = {
 661                         .disable_psr = false,
 662                         .disallow_psrsu = false,
 663                         .disallow_replay = false,
 664                 },
 665                 .ilr = {
 666                         .optimize_edp_link_rate = true,
 667                 },
 668 };
 669
 670 enum dcn20_clk_src_array_id {
 671         DCN20_CLK_SRC_PLL0,
 672         DCN20_CLK_SRC_PLL1,
 673         DCN20_CLK_SRC_PLL2,
 674         DCN20_CLK_SRC_PLL3,
 675         DCN20_CLK_SRC_PLL4,
 676         DCN20_CLK_SRC_TOTAL_DCN21
 677 };
 678
 679 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
 680 {
 681         unsigned int i;
 682
 683         for (i = 0; i < pool->base.stream_enc_count; i++) {
 684                 if (pool->base.stream_enc[i] != NULL) {
 685                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 686                         pool->base.stream_enc[i] = NULL;
 687                 }
 688         }
 689
 690         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
 691                 if (pool->base.dscs[i] != NULL)
 692                         dcn20_dsc_destroy(&pool->base.dscs[i]);
 693         }
 694
 695         if (pool->base.mpc != NULL) {
 696                 kfree(TO_DCN20_MPC(pool->base.mpc));
 697                 pool->base.mpc = NULL;
 698         }
 699         if (pool->base.hubbub != NULL) {
 700                 kfree(pool->base.hubbub);
 701                 pool->base.hubbub = NULL;
 702         }
 703         for (i = 0; i < pool->base.pipe_count; i++) {
 704                 if (pool->base.dpps[i] != NULL)
 705                         dcn20_dpp_destroy(&pool->base.dpps[i]);
 706
 707                 if (pool->base.ipps[i] != NULL)
 708                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 709
 710                 if (pool->base.hubps[i] != NULL) {
 711                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
 712                         pool->base.hubps[i] = NULL;
 713                 }
 714
 715                 if (pool->base.irqs != NULL) {
 716                         dal_irq_service_destroy(&pool->base.irqs);
 717                 }
 718         }
 719
 720         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 721                 if (pool->base.engines[i] != NULL)
 722                         dce110_engine_destroy(&pool->base.engines[i]);
 723                 if (pool->base.hw_i2cs[i] != NULL) {
 724                         kfree(pool->base.hw_i2cs[i]);
 725                         pool->base.hw_i2cs[i] = NULL;
 726                 }
 727                 if (pool->base.sw_i2cs[i] != NULL) {
 728                         kfree(pool->base.sw_i2cs[i]);
 729                         pool->base.sw_i2cs[i] = NULL;
 730                 }
 731         }
 732
 733         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
 734                 if (pool->base.opps[i] != NULL)
 735                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 736         }
 737
 738         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
 739                 if (pool->base.timing_generators[i] != NULL)    {
 740                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 741                         pool->base.timing_generators[i] = NULL;
 742                 }
 743         }
 744
 745         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
 746                 if (pool->base.dwbc[i] != NULL) {
 747                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
 748                         pool->base.dwbc[i] = NULL;
 749                 }
 750                 if (pool->base.mcif_wb[i] != NULL) {
 751                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
 752                         pool->base.mcif_wb[i] = NULL;
 753                 }
 754         }
 755
 756         for (i = 0; i < pool->base.audio_count; i++) {
 757                 if (pool->base.audios[i])
 758                         dce_aud_destroy(&pool->base.audios[i]);
 759         }
 760
 761         for (i = 0; i < pool->base.clk_src_count; i++) {
 762                 if (pool->base.clock_sources[i] != NULL) {
 763                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
 764                         pool->base.clock_sources[i] = NULL;
 765                 }
 766         }
 767
 768         if (pool->base.dp_clock_source != NULL) {
 769                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
 770                 pool->base.dp_clock_source = NULL;
 771         }
 772
 773         if (pool->base.abm != NULL) {
 774                 if (pool->base.abm->ctx->dc->config.disable_dmcu)
 775                         dmub_abm_destroy(&pool->base.abm);
 776                 else
 777                         dce_abm_destroy(&pool->base.abm);
 778         }
 779
 780         if (pool->base.dmcu != NULL)
 781                 dce_dmcu_destroy(&pool->base.dmcu);
 782
 783         if (pool->base.psr != NULL)
 784                 dmub_psr_destroy(&pool->base.psr);
 785
 786         if (pool->base.dccg != NULL)
 787                 dcn_dccg_destroy(&pool->base.dccg);
 788
 789         if (pool->base.pp_smu != NULL)
 790                 dcn21_pp_smu_destroy(&pool->base.pp_smu);
 791 }
 792
 793 bool dcn21_fast_validate_bw(struct dc *dc,
 794                             struct dc_state *context,
 795                             display_e2e_pipe_params_st *pipes,
 796                             int *pipe_cnt_out,
 797                             int *pipe_split_from,
 798                             int *vlevel_out,
 799                             bool fast_validate)
 800 {
 801         bool out = false;
 802         int split[MAX_PIPES] = { 0 };
 803         int pipe_cnt, i, pipe_idx, vlevel;
 804
 805         ASSERT(pipes);
 806         if (!pipes)
 807                 return false;
 808
 809         dcn20_merge_pipes_for_validate(dc, context);
 810
 811         DC_FP_START();
 812         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
 813         DC_FP_END();
 814
 815         *pipe_cnt_out = pipe_cnt;
 816
 817         if (!pipe_cnt) {
 818                 out = true;
 819                 goto validate_out;
 820         }
 821         /*
 822          * DML favors voltage over p-state, but we're more interested in
 823          * supporting p-state over voltage. We can't support p-state in
 824          * prefetch mode > 0 so try capping the prefetch mode to start.
 825          */
 826         context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
 827                                 dm_allow_self_refresh_and_mclk_switch;
 828         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 829
 830         if (vlevel > context->bw_ctx.dml.soc.num_states) {
 831                 /*
 832                  * If mode is unsupported or there's still no p-state support then
 833                  * fall back to favoring voltage.
 834                  *
 835                  * We don't actually support prefetch mode 2, so require that we
 836                  * at least support prefetch mode 1.
 837                  */
 838                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
 839                                         dm_allow_self_refresh;
 840                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 841                 if (vlevel > context->bw_ctx.dml.soc.num_states)
 842                         goto validate_fail;
 843         }
 844
 845         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
 846
 847         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 848                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 849                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
 850                 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 851
 852                 if (!pipe->stream)
 853                         continue;
 854
 855                 /* We only support full screen mpo with ODM */
 856                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
 857                                 && pipe->plane_state && mpo_pipe
 858                                 && memcmp(&mpo_pipe->plane_state->clip_rect,
 859                                                 &pipe->stream->src,
 860                                                 sizeof(struct rect)) != 0) {
 861                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
 862                         goto validate_fail;
 863                 }
 864                 pipe_idx++;
 865         }
 866
 867         /*initialize pipe_just_split_from to invalid idx*/
 868         for (i = 0; i < MAX_PIPES; i++)
 869                 pipe_split_from[i] = -1;
 870
 871         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
 872                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 873                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
 874
 875                 if (!pipe->stream || pipe_split_from[i] >= 0)
 876                         continue;
 877
 878                 pipe_idx++;
 879
 880                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
 881                         hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
 882                         ASSERT(hsplit_pipe);
 883                         if (!dcn20_split_stream_for_odm(
 884                                         dc, &context->res_ctx,
 885                                         pipe, hsplit_pipe))
 886                                 goto validate_fail;
 887                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
 888                         dcn20_build_mapped_resource(dc, context, pipe->stream);
 889                 }
 890
 891                 if (!pipe->plane_state)
 892                         continue;
 893                 /* Skip 2nd half of already split pipe */
 894                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
 895                         continue;
 896
 897                 if (split[i] == 2) {
 898                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
 899                                 /* pipe not split previously needs split */
 900                                 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
 901                                 ASSERT(hsplit_pipe);
 902                                 if (!hsplit_pipe) {
 903                                         DC_FP_START();
 904                                         dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
 905                                         DC_FP_END();
 906                                         continue;
 907                                 }
 908                                 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
 909                                         if (!dcn20_split_stream_for_odm(
 910                                                         dc, &context->res_ctx,
 911                                                         pipe, hsplit_pipe))
 912                                                 goto validate_fail;
 913                                         dcn20_build_mapped_resource(dc, context, pipe->stream);
 914                                 } else {
 915                                         dcn20_split_stream_for_mpc(
 916                                                         &context->res_ctx, dc->res_pool,
 917                                                         pipe, hsplit_pipe);
 918                                         resource_build_scaling_params(pipe);
 919                                         resource_build_scaling_params(hsplit_pipe);
 920                                 }
 921                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
 922                         }
 923                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
 924                         /* merge should already have been done */
 925                         ASSERT(0);
 926                 }
 927         }
 928         /* Actual dsc count per stream dsc validation*/
 929         if (!dcn20_validate_dsc(dc, context)) {
 930                 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
 931                                 DML_FAIL_DSC_VALIDATION_FAILURE;
 932                 goto validate_fail;
 933         }
 934
 935         *vlevel_out = vlevel;
 936
 937         out = true;
 938         goto validate_out;
 939
 940 validate_fail:
 941         out = false;
 942
 943 validate_out:
 944         return out;
 945 }
 946
 947 /*
 948  * Some of the functions further below use the FPU, so we need to wrap this
 949  * with DC_FP_START()/DC_FP_END(). Use the same approach as for
 950  * dcn20_validate_bandwidth in dcn20_resource.c.
 951  */
 952 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
 953                 bool fast_validate)
 954 {
 955         bool voltage_supported;
 956         display_e2e_pipe_params_st *pipes;
 957
 958         pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
 959         if (!pipes)
 960                 return false;
 961
 962         DC_FP_START();
 963         voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate, pipes);
 964         DC_FP_END();
 965
 966         kfree(pipes);
 967         return voltage_supported;
 968 }
 969
 970 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
 971 {
 972         struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
 973
 974         dcn21_resource_destruct(dcn21_pool);
 975         kfree(dcn21_pool);
 976         *pool = NULL;
 977 }
 978
 979 static struct clock_source *dcn21_clock_source_create(
 980                 struct dc_context *ctx,
 981                 struct dc_bios *bios,
 982                 enum clock_source_id id,
 983                 const struct dce110_clk_src_regs *regs,
 984                 bool dp_clk_src)
 985 {
 986         struct dce110_clk_src *clk_src =
 987                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 988
 989         if (!clk_src)
 990                 return NULL;
 991
 992         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
 993                         regs, &cs_shift, &cs_mask)) {
 994                 clk_src->base.dp_clk_src = dp_clk_src;
 995                 return &clk_src->base;
 996         }
 997
 998         kfree(clk_src);
 999         BREAK_TO_DEBUGGER();
1000         return NULL;
1001 }
1002
1003 static struct hubp *dcn21_hubp_create(
1004         struct dc_context *ctx,
1005         uint32_t inst)
1006 {
1007         struct dcn21_hubp *hubp21 =
1008                 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1009
1010         if (!hubp21)
1011                 return NULL;
1012
1013         if (hubp21_construct(hubp21, ctx, inst,
1014                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1015                 return &hubp21->base;
1016
1017         BREAK_TO_DEBUGGER();
1018         kfree(hubp21);
1019         return NULL;
1020 }
1021
1022 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1023 {
1024         int i;
1025
1026         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1027                                           GFP_KERNEL);
1028
1029         if (!hubbub)
1030                 return NULL;
1031
1032         hubbub21_construct(hubbub, ctx,
1033                         &hubbub_reg,
1034                         &hubbub_shift,
1035                         &hubbub_mask);
1036
1037         for (i = 0; i < res_cap_rn.num_vmid; i++) {
1038                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1039
1040                 vmid->ctx = ctx;
1041
1042                 vmid->regs = &vmid_regs[i];
1043                 vmid->shifts = &vmid_shifts;
1044                 vmid->masks = &vmid_masks;
1045         }
1046         hubbub->num_vmid = res_cap_rn.num_vmid;
1047
1048         return &hubbub->base;
1049 }
1050
1051 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1052                                                        uint32_t inst)
1053 {
1054         struct dcn20_opp *opp =
1055                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1056
1057         if (!opp) {
1058                 BREAK_TO_DEBUGGER();
1059                 return NULL;
1060         }
1061
1062         dcn20_opp_construct(opp, ctx, inst,
1063                         &opp_regs[inst], &opp_shift, &opp_mask);
1064         return &opp->base;
1065 }
1066
1067 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1068                                                               uint32_t instance)
1069 {
1070         struct optc *tgn10 =
1071                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1072
1073         if (!tgn10)
1074                 return NULL;
1075
1076         tgn10->base.inst = instance;
1077         tgn10->base.ctx = ctx;
1078
1079         tgn10->tg_regs = &tg_regs[instance];
1080         tgn10->tg_shift = &tg_shift;
1081         tgn10->tg_mask = &tg_mask;
1082
1083         dcn20_timing_generator_init(tgn10);
1084
1085         return &tgn10->base;
1086 }
1087
1088 static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1089 {
1090         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1091                                           GFP_KERNEL);
1092
1093         if (!mpc20)
1094                 return NULL;
1095
1096         dcn20_mpc_construct(mpc20, ctx,
1097                         &mpc_regs,
1098                         &mpc_shift,
1099                         &mpc_mask,
1100                         6);
1101
1102         return &mpc20->base;
1103 }
1104
1105 static void read_dce_straps(
1106         struct dc_context *ctx,
1107         struct resource_straps *straps)
1108 {
1109         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1110                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1111
1112 }
1113
1114
1115 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1116                                                           uint32_t inst)
1117 {
1118         struct dcn20_dsc *dsc =
1119                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1120
1121         if (!dsc) {
1122                 BREAK_TO_DEBUGGER();
1123                 return NULL;
1124         }
1125
1126         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1127         return &dsc->base;
1128 }
1129
1130 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1131 {
1132         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1133
1134         if (!pp_smu)
1135                 return pp_smu;
1136
1137         dm_pp_get_funcs(ctx, pp_smu);
1138
1139         if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1140                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1141
1142
1143         return pp_smu;
1144 }
1145
1146 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1147 {
1148         if (pp_smu && *pp_smu) {
1149                 kfree(*pp_smu);
1150                 *pp_smu = NULL;
1151         }
1152 }
1153
1154 static struct audio *dcn21_create_audio(
1155                 struct dc_context *ctx, unsigned int inst)
1156 {
1157         return dce_audio_create(ctx, inst,
1158                         &audio_regs[inst], &audio_shift, &audio_mask);
1159 }
1160
1161 static struct dc_cap_funcs cap_funcs = {
1162         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1163 };
1164
1165 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1166                                                           struct dc_context *ctx)
1167 {
1168         struct dcn10_stream_encoder *enc1 =
1169                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1170
1171         if (!enc1)
1172                 return NULL;
1173
1174         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1175                                         &stream_enc_regs[eng_id],
1176                                         &se_shift, &se_mask);
1177
1178         return &enc1->base;
1179 }
1180
1181 static const struct dce_hwseq_registers hwseq_reg = {
1182                 HWSEQ_DCN21_REG_LIST()
1183 };
1184
1185 static const struct dce_hwseq_shift hwseq_shift = {
1186                 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1187 };
1188
1189 static const struct dce_hwseq_mask hwseq_mask = {
1190                 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1191 };
1192
1193 static struct dce_hwseq *dcn21_hwseq_create(
1194         struct dc_context *ctx)
1195 {
1196         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1197
1198         if (hws) {
1199                 hws->ctx = ctx;
1200                 hws->regs = &hwseq_reg;
1201                 hws->shifts = &hwseq_shift;
1202                 hws->masks = &hwseq_mask;
1203                 hws->wa.DEGVIDCN21 = true;
1204                 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1205         }
1206         return hws;
1207 }
1208
1209 static const struct resource_create_funcs res_create_funcs = {
1210         .read_dce_straps = read_dce_straps,
1211         .create_audio = dcn21_create_audio,
1212         .create_stream_encoder = dcn21_stream_encoder_create,
1213         .create_hwseq = dcn21_hwseq_create,
1214 };
1215
1216 static const struct encoder_feature_support link_enc_feature = {
1217                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1218                 .max_hdmi_pixel_clock = 600000,
1219                 .hdmi_ycbcr420_supported = true,
1220                 .dp_ycbcr420_supported = true,
1221                 .fec_supported = true,
1222                 .flags.bits.IS_HBR2_CAPABLE = true,
1223                 .flags.bits.IS_HBR3_CAPABLE = true,
1224                 .flags.bits.IS_TPS3_CAPABLE = true,
1225                 .flags.bits.IS_TPS4_CAPABLE = true
1226 };
1227
1228
1229 #define link_regs(id, phyid)\
1230 [id] = {\
1231         LE_DCN2_REG_LIST(id), \
1232         UNIPHY_DCN2_REG_LIST(phyid), \
1233         DPCS_DCN21_REG_LIST(id), \
1234         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1235 }
1236
1237 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1238         link_regs(0, A),
1239         link_regs(1, B),
1240         link_regs(2, C),
1241         link_regs(3, D),
1242         link_regs(4, E),
1243 };
1244
1245 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1246         { DCN_PANEL_CNTL_REG_LIST() }
1247 };
1248
1249 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1250         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1251 };
1252
1253 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1254         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1255 };
1256
1257 #define aux_regs(id)\
1258 [id] = {\
1259         DCN2_AUX_REG_LIST(id)\
1260 }
1261
1262 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1263                 aux_regs(0),
1264                 aux_regs(1),
1265                 aux_regs(2),
1266                 aux_regs(3),
1267                 aux_regs(4)
1268 };
1269
1270 #define hpd_regs(id)\
1271 [id] = {\
1272         HPD_REG_LIST(id)\
1273 }
1274
1275 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1276                 hpd_regs(0),
1277                 hpd_regs(1),
1278                 hpd_regs(2),
1279                 hpd_regs(3),
1280                 hpd_regs(4)
1281 };
1282
1283 static const struct dcn10_link_enc_shift le_shift = {
1284         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1285         DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1286 };
1287
1288 static const struct dcn10_link_enc_mask le_mask = {
1289         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1290         DPCS_DCN21_MASK_SH_LIST(_MASK)
1291 };
1292
1293 static int map_transmitter_id_to_phy_instance(
1294         enum transmitter transmitter)
1295 {
1296         switch (transmitter) {
1297         case TRANSMITTER_UNIPHY_A:
1298                 return 0;
1299         break;
1300         case TRANSMITTER_UNIPHY_B:
1301                 return 1;
1302         break;
1303         case TRANSMITTER_UNIPHY_C:
1304                 return 2;
1305         break;
1306         case TRANSMITTER_UNIPHY_D:
1307                 return 3;
1308         break;
1309         case TRANSMITTER_UNIPHY_E:
1310                 return 4;
1311         break;
1312         default:
1313                 ASSERT(0);
1314                 return 0;
1315         }
1316 }
1317
1318 static struct link_encoder *dcn21_link_encoder_create(
1319         struct dc_context *ctx,
1320         const struct encoder_init_data *enc_init_data)
1321 {
1322         struct dcn21_link_encoder *enc21 =
1323                 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1324         int link_regs_id;
1325
1326         if (!enc21)
1327                 return NULL;
1328
1329         link_regs_id =
1330                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1331
1332         dcn21_link_encoder_construct(enc21,
1333                                       enc_init_data,
1334                                       &link_enc_feature,
1335                                       &link_enc_regs[link_regs_id],
1336                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1337                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1338                                       &le_shift,
1339                                       &le_mask);
1340
1341         return &enc21->enc10.base;
1342 }
1343
1344 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1345 {
1346         struct dce_panel_cntl *panel_cntl =
1347                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1348
1349         if (!panel_cntl)
1350                 return NULL;
1351
1352         dce_panel_cntl_construct(panel_cntl,
1353                         init_data,
1354                         &panel_cntl_regs[init_data->inst],
1355                         &panel_cntl_shift,
1356                         &panel_cntl_mask);
1357
1358         return &panel_cntl->base;
1359 }
1360
1361 static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)
1362 {
1363         *panel_config = panel_config_defaults;
1364 }
1365
1366 #define CTX ctx
1367
1368 #define REG(reg_name) \
1369         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1370
1371 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1372 {
1373         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1374         /* RV1 support max 4 pipes */
1375         value = value & 0xf;
1376         return value;
1377 }
1378
1379 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1380 {
1381         if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1382                 plane_state->dcc.enable = 1;
1383                 /* align to our worst case block width */
1384                 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1385         }
1386
1387         return dcn20_patch_unknown_plane_state(plane_state);
1388 }
1389
1390 static const struct resource_funcs dcn21_res_pool_funcs = {
1391         .destroy = dcn21_destroy_resource_pool,
1392         .link_enc_create = dcn21_link_encoder_create,
1393         .panel_cntl_create = dcn21_panel_cntl_create,
1394         .validate_bandwidth = dcn21_validate_bandwidth,
1395         .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1396         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1397         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1398         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1399         .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1400         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1401         .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1402         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1403         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1404         .update_bw_bounding_box = dcn21_update_bw_bounding_box,
1405         .get_panel_config_defaults = dcn21_get_panel_config_defaults,
1406 };
1407
1408 static bool dcn21_resource_construct(
1409         uint8_t num_virtual_links,
1410         struct dc *dc,
1411         struct dcn21_resource_pool *pool)
1412 {
1413         int i, j;
1414         struct dc_context *ctx = dc->ctx;
1415         struct irq_service_init_data init_data;
1416         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1417         uint32_t num_pipes;
1418
1419         ctx->dc_bios->regs = &bios_regs;
1420
1421         pool->base.res_cap = &res_cap_rn;
1422 #ifdef DIAGS_BUILD
1423         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1424                 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1425                 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1426 #endif
1427
1428         pool->base.funcs = &dcn21_res_pool_funcs;
1429
1430         /*************************************************
1431          *  Resource + asic cap harcoding                *
1432          *************************************************/
1433         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1434
1435         /* max pipe num for ASIC before check pipe fuses */
1436         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1437
1438         dc->caps.max_downscale_ratio = 200;
1439         dc->caps.i2c_speed_in_khz = 100;
1440         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1441         dc->caps.max_cursor_size = 256;
1442         dc->caps.min_horizontal_blanking_period = 80;
1443         dc->caps.dmdata_alloc_size = 2048;
1444
1445         dc->caps.max_slave_planes = 1;
1446         dc->caps.max_slave_yuv_planes = 1;
1447         dc->caps.max_slave_rgb_planes = 1;
1448         dc->caps.post_blend_color_processing = true;
1449         dc->caps.force_dp_tps4_for_cp2520 = true;
1450         dc->caps.extended_aux_timeout_support = true;
1451         dc->caps.dmcub_support = true;
1452         dc->caps.is_apu = true;
1453
1454         /* Color pipeline capabilities */
1455         dc->caps.color.dpp.dcn_arch = 1;
1456         dc->caps.color.dpp.input_lut_shared = 0;
1457         dc->caps.color.dpp.icsc = 1;
1458         dc->caps.color.dpp.dgam_ram = 1;
1459         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1460         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1461         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1462         dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1463         dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1464         dc->caps.color.dpp.post_csc = 0;
1465         dc->caps.color.dpp.gamma_corr = 0;
1466         dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1467
1468         dc->caps.color.dpp.hw_3d_lut = 1;
1469         dc->caps.color.dpp.ogam_ram = 1;
1470         // no OGAM ROM on DCN2
1471         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1472         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1473         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1474         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1475         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1476         dc->caps.color.dpp.ocsc = 0;
1477
1478         dc->caps.color.mpc.gamut_remap = 0;
1479         dc->caps.color.mpc.num_3dluts = 0;
1480         dc->caps.color.mpc.shared_3d_lut = 0;
1481         dc->caps.color.mpc.ogam_ram = 1;
1482         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1483         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1484         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1485         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1486         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1487         dc->caps.color.mpc.ocsc = 1;
1488
1489         dc->caps.dp_hdmi21_pcon_support = true;
1490
1491         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1492                 dc->debug = debug_defaults_drv;
1493
1494         // Init the vm_helper
1495         if (dc->vm_helper)
1496                 vm_helper_init(dc->vm_helper, 16);
1497
1498         /*************************************************
1499          *  Create resources                             *
1500          *************************************************/
1501
1502         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1503                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1504                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1505                                 &clk_src_regs[0], false);
1506         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1507                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1508                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1509                                 &clk_src_regs[1], false);
1510         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1511                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1512                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1513                                 &clk_src_regs[2], false);
1514         pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1515                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1516                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1517                                 &clk_src_regs[3], false);
1518         pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1519                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1520                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1521                                 &clk_src_regs[4], false);
1522
1523         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1524
1525         /* todo: not reuse phy_pll registers */
1526         pool->base.dp_clock_source =
1527                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1528                                 CLOCK_SOURCE_ID_DP_DTO,
1529                                 &clk_src_regs[0], true);
1530
1531         for (i = 0; i < pool->base.clk_src_count; i++) {
1532                 if (pool->base.clock_sources[i] == NULL) {
1533                         dm_error("DC: failed to create clock sources!\n");
1534                         BREAK_TO_DEBUGGER();
1535                         goto create_fail;
1536                 }
1537         }
1538
1539         pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1540         if (pool->base.dccg == NULL) {
1541                 dm_error("DC: failed to create dccg!\n");
1542                 BREAK_TO_DEBUGGER();
1543                 goto create_fail;
1544         }
1545
1546         if (!dc->config.disable_dmcu) {
1547                 pool->base.dmcu = dcn21_dmcu_create(ctx,
1548                                 &dmcu_regs,
1549                                 &dmcu_shift,
1550                                 &dmcu_mask);
1551                 if (pool->base.dmcu == NULL) {
1552                         dm_error("DC: failed to create dmcu!\n");
1553                         BREAK_TO_DEBUGGER();
1554                         goto create_fail;
1555                 }
1556
1557                 dc->debug.dmub_command_table = false;
1558         }
1559
1560         if (dc->config.disable_dmcu) {
1561                 pool->base.psr = dmub_psr_create(ctx);
1562
1563                 if (pool->base.psr == NULL) {
1564                         dm_error("DC: failed to create psr obj!\n");
1565                         BREAK_TO_DEBUGGER();
1566                         goto create_fail;
1567                 }
1568         }
1569
1570         if (dc->config.disable_dmcu)
1571                 pool->base.abm = dmub_abm_create(ctx,
1572                         &abm_regs,
1573                         &abm_shift,
1574                         &abm_mask);
1575         else
1576                 pool->base.abm = dce_abm_create(ctx,
1577                         &abm_regs,
1578                         &abm_shift,
1579                         &abm_mask);
1580
1581         pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1582
1583         num_pipes = dcn2_1_ip.max_num_dpp;
1584
1585         for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1586                 if (pipe_fuses & 1 << i)
1587                         num_pipes--;
1588         dcn2_1_ip.max_num_dpp = num_pipes;
1589         dcn2_1_ip.max_num_otg = num_pipes;
1590
1591         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1592
1593         init_data.ctx = dc->ctx;
1594         pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1595         if (!pool->base.irqs)
1596                 goto create_fail;
1597
1598         j = 0;
1599         /* mem input -> ipp -> dpp -> opp -> TG */
1600         for (i = 0; i < pool->base.pipe_count; i++) {
1601                 /* if pipe is disabled, skip instance of HW pipe,
1602                  * i.e, skip ASIC register instance
1603                  */
1604                 if ((pipe_fuses & (1 << i)) != 0)
1605                         continue;
1606
1607                 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1608                 if (pool->base.hubps[j] == NULL) {
1609                         BREAK_TO_DEBUGGER();
1610                         dm_error(
1611                                 "DC: failed to create memory input!\n");
1612                         goto create_fail;
1613                 }
1614
1615                 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1616                 if (pool->base.ipps[j] == NULL) {
1617                         BREAK_TO_DEBUGGER();
1618                         dm_error(
1619                                 "DC: failed to create input pixel processor!\n");
1620                         goto create_fail;
1621                 }
1622
1623                 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1624                 if (pool->base.dpps[j] == NULL) {
1625                         BREAK_TO_DEBUGGER();
1626                         dm_error(
1627                                 "DC: failed to create dpps!\n");
1628                         goto create_fail;
1629                 }
1630
1631                 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1632                 if (pool->base.opps[j] == NULL) {
1633                         BREAK_TO_DEBUGGER();
1634                         dm_error(
1635                                 "DC: failed to create output pixel processor!\n");
1636                         goto create_fail;
1637                 }
1638
1639                 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1640                                 ctx, i);
1641                 if (pool->base.timing_generators[j] == NULL) {
1642                         BREAK_TO_DEBUGGER();
1643                         dm_error("DC: failed to create tg!\n");
1644                         goto create_fail;
1645                 }
1646                 j++;
1647         }
1648
1649         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1650                 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1651                 if (pool->base.engines[i] == NULL) {
1652                         BREAK_TO_DEBUGGER();
1653                         dm_error(
1654                                 "DC:failed to create aux engine!!\n");
1655                         goto create_fail;
1656                 }
1657                 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1658                 if (pool->base.hw_i2cs[i] == NULL) {
1659                         BREAK_TO_DEBUGGER();
1660                         dm_error(
1661                                 "DC:failed to create hw i2c!!\n");
1662                         goto create_fail;
1663                 }
1664                 pool->base.sw_i2cs[i] = NULL;
1665         }
1666
1667         pool->base.timing_generator_count = j;
1668         pool->base.pipe_count = j;
1669         pool->base.mpcc_count = j;
1670
1671         pool->base.mpc = dcn21_mpc_create(ctx);
1672         if (pool->base.mpc == NULL) {
1673                 BREAK_TO_DEBUGGER();
1674                 dm_error("DC: failed to create mpc!\n");
1675                 goto create_fail;
1676         }
1677
1678         pool->base.hubbub = dcn21_hubbub_create(ctx);
1679         if (pool->base.hubbub == NULL) {
1680                 BREAK_TO_DEBUGGER();
1681                 dm_error("DC: failed to create hubbub!\n");
1682                 goto create_fail;
1683         }
1684
1685         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1686                 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1687                 if (pool->base.dscs[i] == NULL) {
1688                         BREAK_TO_DEBUGGER();
1689                         dm_error("DC: failed to create display stream compressor %d!\n", i);
1690                         goto create_fail;
1691                 }
1692         }
1693
1694         if (!dcn20_dwbc_create(ctx, &pool->base)) {
1695                 BREAK_TO_DEBUGGER();
1696                 dm_error("DC: failed to create dwbc!\n");
1697                 goto create_fail;
1698         }
1699         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1700                 BREAK_TO_DEBUGGER();
1701                 dm_error("DC: failed to create mcif_wb!\n");
1702                 goto create_fail;
1703         }
1704
1705         if (!resource_construct(num_virtual_links, dc, &pool->base,
1706                         &res_create_funcs))
1707                 goto create_fail;
1708
1709         dcn21_hw_sequencer_construct(dc);
1710
1711         dc->caps.max_planes =  pool->base.pipe_count;
1712
1713         for (i = 0; i < dc->caps.max_planes; ++i)
1714                 dc->caps.planes[i] = plane_cap;
1715
1716         dc->cap_funcs = cap_funcs;
1717
1718         return true;
1719
1720 create_fail:
1721
1722         dcn21_resource_destruct(pool);
1723
1724         return false;
1725 }
1726
1727 struct resource_pool *dcn21_create_resource_pool(
1728                 const struct dc_init_data *init_data,
1729                 struct dc *dc)
1730 {
1731         struct dcn21_resource_pool *pool =
1732                 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1733
1734         if (!pool)
1735                 return NULL;
1736
1737         if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1738                 return &pool->base;
1739
1740         BREAK_TO_DEBUGGER();
1741         kfree(pool);
1742         return NULL;
1743 }