2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/delay.h>
27 #include "dm_services.h"
28 #include "basics/dc_common.h"
29 #include "dm_helpers.h"
30 #include "core_types.h"
32 #include "dcn20_resource.h"
33 #include "dcn20_hwseq.h"
34 #include "dce/dce_hwseq.h"
35 #include "dcn20_dsc.h"
36 #include "dcn20_optc.h"
41 #include "timing_generator.h"
47 #include "reg_helper.h"
48 #include "dcn10/dcn10_cm_common.h"
49 #include "vm_helper.h"
51 #include "dc_dmub_srv.h"
52 #include "dce/dmub_hw_lock_mgr.h"
53 #include "hw_sequencer.h"
54 #include "dpcd_defs.h"
55 #include "inc/link_enc_cfg.h"
56 #include "link_hwss.h"
59 #define DC_LOGGER_INIT(logger)
67 #define FN(reg_name, field_name) \
68 hws->shifts->field_name, hws->masks->field_name
70 static int find_free_gsl_group(const struct dc *dc)
72 if (dc->res_pool->gsl_groups.gsl_0 == 0)
74 if (dc->res_pool->gsl_groups.gsl_1 == 0)
76 if (dc->res_pool->gsl_groups.gsl_2 == 0)
82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
83 * This is only used to lock pipes in pipe splitting case with immediate flip
84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
85 * so we get tearing with freesync since we cannot flip multiple pipes
87 * We use GSL for this:
88 * - immediate flip: find first available GSL group if not already assigned
89 * program gsl with that group, set current OTG as master
90 * and always us 0x4 = AND of flip_ready from all pipes
91 * - vsync flip: disable GSL if used
93 * Groups in stream_res are stored as +1 from HW registers, i.e.
94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
95 * Using a magic value like -1 would require tracking all inits/resets
97 static void dcn20_setup_gsl_group_as_lock(
99 struct pipe_ctx *pipe_ctx,
102 struct gsl_params gsl;
105 memset(&gsl, 0, sizeof(struct gsl_params));
108 /* return if group already assigned since GSL was set up
109 * for vsync flip, we would unassign so it can't be "left over"
111 if (pipe_ctx->stream_res.gsl_group > 0)
114 group_idx = find_free_gsl_group(dc);
115 ASSERT(group_idx != 0);
116 pipe_ctx->stream_res.gsl_group = group_idx;
118 /* set gsl group reg field and mark resource used */
122 dc->res_pool->gsl_groups.gsl_0 = 1;
126 dc->res_pool->gsl_groups.gsl_1 = 1;
130 dc->res_pool->gsl_groups.gsl_2 = 1;
134 return; // invalid case
136 gsl.gsl_master_en = 1;
138 group_idx = pipe_ctx->stream_res.gsl_group;
140 return; // if not in use, just return
142 pipe_ctx->stream_res.gsl_group = 0;
144 /* unset gsl group reg field and mark resource free */
148 dc->res_pool->gsl_groups.gsl_0 = 0;
152 dc->res_pool->gsl_groups.gsl_1 = 0;
156 dc->res_pool->gsl_groups.gsl_2 = 0;
162 gsl.gsl_master_en = 0;
165 /* at this point we want to program whether it's to enable or disable */
166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
168 pipe_ctx->stream_res.tg->funcs->set_gsl(
169 pipe_ctx->stream_res.tg,
172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
178 void dcn20_set_flip_control_gsl(
179 struct pipe_ctx *pipe_ctx,
182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
184 pipe_ctx->plane_res.hubp, flip_immediate);
188 void dcn20_enable_power_gating_plane(
189 struct dce_hwseq *hws,
192 bool force_on = true; /* disable power gating */
193 uint32_t org_ip_request_cntl = 0;
198 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
199 if (org_ip_request_cntl == 0)
200 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
202 /* DCHUBP0/1/2/3/4/5 */
203 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
204 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
205 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
206 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
207 if (REG(DOMAIN8_PG_CONFIG))
208 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
209 if (REG(DOMAIN10_PG_CONFIG))
210 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
213 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
214 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
215 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
216 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
217 if (REG(DOMAIN9_PG_CONFIG))
218 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
219 if (REG(DOMAIN11_PG_CONFIG))
220 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
223 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
224 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
225 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
226 if (REG(DOMAIN19_PG_CONFIG))
227 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
228 if (REG(DOMAIN20_PG_CONFIG))
229 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
230 if (REG(DOMAIN21_PG_CONFIG))
231 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
233 if (org_ip_request_cntl == 0)
234 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
238 void dcn20_dccg_init(struct dce_hwseq *hws)
241 * set MICROSECOND_TIME_BASE_DIV
242 * 100Mhz refclk -> 0x120264
243 * 27Mhz refclk -> 0x12021b
244 * 48Mhz refclk -> 0x120230
247 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
250 * set MILLISECOND_TIME_BASE_DIV
251 * 100Mhz refclk -> 0x1186a0
252 * 27Mhz refclk -> 0x106978
253 * 48Mhz refclk -> 0x10bb80
256 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
258 /* This value is dependent on the hardware pipeline delay so set once per SOC */
259 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
262 void dcn20_disable_vga(
263 struct dce_hwseq *hws)
265 REG_WRITE(D1VGA_CONTROL, 0);
266 REG_WRITE(D2VGA_CONTROL, 0);
267 REG_WRITE(D3VGA_CONTROL, 0);
268 REG_WRITE(D4VGA_CONTROL, 0);
269 REG_WRITE(D5VGA_CONTROL, 0);
270 REG_WRITE(D6VGA_CONTROL, 0);
273 void dcn20_program_triple_buffer(
275 struct pipe_ctx *pipe_ctx,
276 bool enable_triple_buffer)
278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
280 pipe_ctx->plane_res.hubp,
281 enable_triple_buffer);
285 /* Blank pixel data during initialization */
286 void dcn20_init_blank(
288 struct timing_generator *tg)
290 struct dce_hwseq *hws = dc->hwseq;
291 enum dc_color_space color_space;
292 struct tg_color black_color = {0};
293 struct output_pixel_processor *opp = NULL;
294 struct output_pixel_processor *bottom_opp = NULL;
295 uint32_t num_opps, opp_id_src0, opp_id_src1;
296 uint32_t otg_active_width, otg_active_height;
298 /* program opp dpg blank color */
299 color_space = COLOR_SPACE_SRGB;
300 color_space_to_black_color(dc, color_space, &black_color);
302 /* get the OTG active size */
303 tg->funcs->get_otg_active_size(tg,
307 /* get the OPTC source */
308 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
310 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
314 opp = dc->res_pool->opps[opp_id_src0];
317 otg_active_width = otg_active_width / 2;
319 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
323 bottom_opp = dc->res_pool->opps[opp_id_src1];
326 opp->funcs->opp_set_disp_pattern_generator(
328 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
329 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
330 COLOR_DEPTH_UNDEFINED,
337 bottom_opp->funcs->opp_set_disp_pattern_generator(
339 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
340 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
341 COLOR_DEPTH_UNDEFINED,
348 hws->funcs.wait_for_blank_complete(opp);
351 void dcn20_dsc_pg_control(
352 struct dce_hwseq *hws,
353 unsigned int dsc_inst,
356 uint32_t power_gate = power_on ? 0 : 1;
357 uint32_t pwr_status = power_on ? 0 : 2;
358 uint32_t org_ip_request_cntl = 0;
360 if (hws->ctx->dc->debug.disable_dsc_power_gate)
363 if (REG(DOMAIN16_PG_CONFIG) == 0)
366 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
367 if (org_ip_request_cntl == 0)
368 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
372 REG_UPDATE(DOMAIN16_PG_CONFIG,
373 DOMAIN16_POWER_GATE, power_gate);
375 REG_WAIT(DOMAIN16_PG_STATUS,
376 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
380 REG_UPDATE(DOMAIN17_PG_CONFIG,
381 DOMAIN17_POWER_GATE, power_gate);
383 REG_WAIT(DOMAIN17_PG_STATUS,
384 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
388 REG_UPDATE(DOMAIN18_PG_CONFIG,
389 DOMAIN18_POWER_GATE, power_gate);
391 REG_WAIT(DOMAIN18_PG_STATUS,
392 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
396 REG_UPDATE(DOMAIN19_PG_CONFIG,
397 DOMAIN19_POWER_GATE, power_gate);
399 REG_WAIT(DOMAIN19_PG_STATUS,
400 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
404 REG_UPDATE(DOMAIN20_PG_CONFIG,
405 DOMAIN20_POWER_GATE, power_gate);
407 REG_WAIT(DOMAIN20_PG_STATUS,
408 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
412 REG_UPDATE(DOMAIN21_PG_CONFIG,
413 DOMAIN21_POWER_GATE, power_gate);
415 REG_WAIT(DOMAIN21_PG_STATUS,
416 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
424 if (org_ip_request_cntl == 0)
425 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
428 void dcn20_dpp_pg_control(
429 struct dce_hwseq *hws,
430 unsigned int dpp_inst,
433 uint32_t power_gate = power_on ? 0 : 1;
434 uint32_t pwr_status = power_on ? 0 : 2;
436 if (hws->ctx->dc->debug.disable_dpp_power_gate)
438 if (REG(DOMAIN1_PG_CONFIG) == 0)
443 REG_UPDATE(DOMAIN1_PG_CONFIG,
444 DOMAIN1_POWER_GATE, power_gate);
446 REG_WAIT(DOMAIN1_PG_STATUS,
447 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
451 REG_UPDATE(DOMAIN3_PG_CONFIG,
452 DOMAIN3_POWER_GATE, power_gate);
454 REG_WAIT(DOMAIN3_PG_STATUS,
455 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
459 REG_UPDATE(DOMAIN5_PG_CONFIG,
460 DOMAIN5_POWER_GATE, power_gate);
462 REG_WAIT(DOMAIN5_PG_STATUS,
463 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
467 REG_UPDATE(DOMAIN7_PG_CONFIG,
468 DOMAIN7_POWER_GATE, power_gate);
470 REG_WAIT(DOMAIN7_PG_STATUS,
471 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
475 REG_UPDATE(DOMAIN9_PG_CONFIG,
476 DOMAIN9_POWER_GATE, power_gate);
478 REG_WAIT(DOMAIN9_PG_STATUS,
479 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
484 * Do not power gate DPP5, should be left at HW default, power on permanently.
485 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
487 * REG_UPDATE(DOMAIN11_PG_CONFIG,
488 * DOMAIN11_POWER_GATE, power_gate);
490 * REG_WAIT(DOMAIN11_PG_STATUS,
491 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
502 void dcn20_hubp_pg_control(
503 struct dce_hwseq *hws,
504 unsigned int hubp_inst,
507 uint32_t power_gate = power_on ? 0 : 1;
508 uint32_t pwr_status = power_on ? 0 : 2;
510 if (hws->ctx->dc->debug.disable_hubp_power_gate)
512 if (REG(DOMAIN0_PG_CONFIG) == 0)
516 case 0: /* DCHUBP0 */
517 REG_UPDATE(DOMAIN0_PG_CONFIG,
518 DOMAIN0_POWER_GATE, power_gate);
520 REG_WAIT(DOMAIN0_PG_STATUS,
521 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
524 case 1: /* DCHUBP1 */
525 REG_UPDATE(DOMAIN2_PG_CONFIG,
526 DOMAIN2_POWER_GATE, power_gate);
528 REG_WAIT(DOMAIN2_PG_STATUS,
529 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
532 case 2: /* DCHUBP2 */
533 REG_UPDATE(DOMAIN4_PG_CONFIG,
534 DOMAIN4_POWER_GATE, power_gate);
536 REG_WAIT(DOMAIN4_PG_STATUS,
537 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
540 case 3: /* DCHUBP3 */
541 REG_UPDATE(DOMAIN6_PG_CONFIG,
542 DOMAIN6_POWER_GATE, power_gate);
544 REG_WAIT(DOMAIN6_PG_STATUS,
545 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
548 case 4: /* DCHUBP4 */
549 REG_UPDATE(DOMAIN8_PG_CONFIG,
550 DOMAIN8_POWER_GATE, power_gate);
552 REG_WAIT(DOMAIN8_PG_STATUS,
553 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
556 case 5: /* DCHUBP5 */
558 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
559 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
561 * REG_UPDATE(DOMAIN10_PG_CONFIG,
562 * DOMAIN10_POWER_GATE, power_gate);
564 * REG_WAIT(DOMAIN10_PG_STATUS,
565 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
576 /* disable HW used by plane.
577 * note: cannot disable until disconnect is complete
579 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
581 struct dce_hwseq *hws = dc->hwseq;
582 struct hubp *hubp = pipe_ctx->plane_res.hubp;
583 struct dpp *dpp = pipe_ctx->plane_res.dpp;
585 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
587 /* In flip immediate with pipe splitting case GSL is used for
588 * synchronization so we must disable it when the plane is disabled.
590 if (pipe_ctx->stream_res.gsl_group != 0)
591 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
593 if (hubp->funcs->hubp_update_mall_sel)
594 hubp->funcs->hubp_update_mall_sel(hubp, 0, false);
596 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
598 hubp->funcs->hubp_clk_cntl(hubp, false);
600 dpp->funcs->dpp_dppclk_control(dpp, false, false);
602 hubp->power_gated = true;
604 hws->funcs.plane_atomic_power_down(dc,
605 pipe_ctx->plane_res.dpp,
606 pipe_ctx->plane_res.hubp);
608 pipe_ctx->stream = NULL;
609 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
610 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
611 pipe_ctx->top_pipe = NULL;
612 pipe_ctx->bottom_pipe = NULL;
613 pipe_ctx->plane_state = NULL;
617 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
619 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom;
620 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;
622 DC_LOGGER_INIT(dc->ctx->logger);
624 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
627 dcn20_plane_atomic_disable(dc, pipe_ctx);
629 /* Turn back off the phantom OTG after the phantom plane is fully disabled
632 if (tg && tg->funcs->disable_phantom_crtc)
633 tg->funcs->disable_phantom_crtc(tg);
635 DC_LOG_DC("Power down front end %d\n",
639 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
641 dcn20_blank_pixel_data(dc, pipe_ctx, blank);
644 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
647 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
651 hblank_halved = true;
653 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
654 stream->timing.h_border_left -
655 stream->timing.h_border_right;
660 /* ODM combine 4:1 case */
664 return flow_ctrl_cnt;
667 enum dc_status dcn20_enable_stream_timing(
668 struct pipe_ctx *pipe_ctx,
669 struct dc_state *context,
672 struct dce_hwseq *hws = dc->hwseq;
673 struct dc_stream_state *stream = pipe_ctx->stream;
674 struct drr_params params = {0};
675 unsigned int event_triggers = 0;
676 struct pipe_ctx *odm_pipe;
678 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
679 bool interlace = stream->timing.flags.INTERLACE;
681 struct mpc_dwb_flow_control flow_control;
682 struct mpc *mpc = dc->res_pool->mpc;
683 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
684 unsigned int k1_div = PIXEL_RATE_DIV_NA;
685 unsigned int k2_div = PIXEL_RATE_DIV_NA;
687 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
688 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
690 dc->res_pool->dccg->funcs->set_pixel_rate_div(
692 pipe_ctx->stream_res.tg->inst,
695 /* by upper caller loop, pipe0 is parent pipe and be called first.
696 * back end is set up by for pipe0. Other children pipe share back end
697 * with pipe 0. No program is needed.
699 if (pipe_ctx->top_pipe != NULL)
702 /* TODO check if timing_changed, disable stream if timing changed */
704 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
705 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
710 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
711 pipe_ctx->stream_res.tg,
713 &pipe_ctx->stream->timing);
715 /* HW program guide assume display already disable
716 * by unplug sequence. OTG assume stop.
718 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
720 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
721 pipe_ctx->clock_source,
722 &pipe_ctx->stream_res.pix_clk_params,
723 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
724 &pipe_ctx->pll_settings)) {
726 return DC_ERROR_UNEXPECTED;
729 if (dc_is_hdmi_tmds_signal(stream->signal)) {
730 stream->link->phy_state.symclk_ref_cnts.otg = 1;
731 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
732 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
734 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
737 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
738 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
740 pipe_ctx->stream_res.tg->funcs->program_timing(
741 pipe_ctx->stream_res.tg,
743 pipe_ctx->pipe_dlg_param.vready_offset,
744 pipe_ctx->pipe_dlg_param.vstartup_start,
745 pipe_ctx->pipe_dlg_param.vupdate_offset,
746 pipe_ctx->pipe_dlg_param.vupdate_width,
747 pipe_ctx->stream->signal,
750 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
751 flow_control.flow_ctrl_mode = 0;
752 flow_control.flow_ctrl_cnt0 = 0x80;
753 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
754 if (mpc->funcs->set_out_rate_control) {
755 for (i = 0; i < opp_cnt; ++i) {
756 mpc->funcs->set_out_rate_control(
759 rate_control_2x_pclk,
764 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
765 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
766 odm_pipe->stream_res.opp,
769 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
770 pipe_ctx->stream_res.opp,
773 hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
775 /* VTG is within DCHUB command block. DCFCLK is always on */
776 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
778 return DC_ERROR_UNEXPECTED;
781 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
783 params.vertical_total_min = stream->adjust.v_total_min;
784 params.vertical_total_max = stream->adjust.v_total_max;
785 params.vertical_total_mid = stream->adjust.v_total_mid;
786 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
787 if (pipe_ctx->stream_res.tg->funcs->set_drr)
788 pipe_ctx->stream_res.tg->funcs->set_drr(
789 pipe_ctx->stream_res.tg, ¶ms);
791 // DRR should set trigger event to monitor surface update event
792 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
793 event_triggers = 0x80;
794 /* Event triggers and num frames initialized for DRR, but can be
795 * later updated for PSR use. Note DRR trigger events are generated
796 * regardless of whether num frames met.
798 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
799 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
800 pipe_ctx->stream_res.tg, event_triggers, 2);
802 /* TODO program crtc source select for non-virtual signal*/
803 /* TODO program FMT */
804 /* TODO setup link_enc */
805 /* TODO set stream attributes */
806 /* TODO program audio */
807 /* TODO enable stream if timing changed */
808 /* TODO unblank stream if DP */
810 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
811 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
812 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
817 void dcn20_program_output_csc(struct dc *dc,
818 struct pipe_ctx *pipe_ctx,
819 enum dc_color_space colorspace,
823 struct mpc *mpc = dc->res_pool->mpc;
824 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
825 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
827 if (mpc->funcs->power_on_mpc_mem_pwr)
828 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
830 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
831 if (mpc->funcs->set_output_csc != NULL)
832 mpc->funcs->set_output_csc(mpc,
837 if (mpc->funcs->set_ocsc_default != NULL)
838 mpc->funcs->set_ocsc_default(mpc,
845 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
846 const struct dc_stream_state *stream)
848 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
849 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
850 struct pwl_params *params = NULL;
852 * program OGAM only for the top pipe
853 * if there is a pipe split then fix diagnostic is required:
854 * how to pass OGAM parameter for stream.
855 * if programming for all pipes is required then remove condition
856 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
858 if (mpc->funcs->power_on_mpc_mem_pwr)
859 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
860 if (pipe_ctx->top_pipe == NULL
861 && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
862 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
863 params = &stream->out_transfer_func->pwl;
864 else if (pipe_ctx->stream->out_transfer_func->type ==
865 TF_TYPE_DISTRIBUTED_POINTS &&
866 cm_helper_translate_curve_to_hw_format(
867 stream->out_transfer_func,
868 &mpc->blender_params, false))
869 params = &mpc->blender_params;
873 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
877 * if above if is not executed then 'params' equal to 0 and set in bypass
879 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
884 bool dcn20_set_blend_lut(
885 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
887 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
889 struct pwl_params *blend_lut = NULL;
891 if (plane_state->blend_tf) {
892 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
893 blend_lut = &plane_state->blend_tf->pwl;
894 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
895 cm_helper_translate_curve_to_hw_format(
896 plane_state->blend_tf,
897 &dpp_base->regamma_params, false);
898 blend_lut = &dpp_base->regamma_params;
901 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
906 bool dcn20_set_shaper_3dlut(
907 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
909 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
911 struct pwl_params *shaper_lut = NULL;
913 if (plane_state->in_shaper_func) {
914 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
915 shaper_lut = &plane_state->in_shaper_func->pwl;
916 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
917 cm_helper_translate_curve_to_hw_format(
918 plane_state->in_shaper_func,
919 &dpp_base->shaper_params, true);
920 shaper_lut = &dpp_base->shaper_params;
924 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
925 if (plane_state->lut3d_func &&
926 plane_state->lut3d_func->state.bits.initialized == 1)
927 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
928 &plane_state->lut3d_func->lut_3d);
930 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
935 bool dcn20_set_input_transfer_func(struct dc *dc,
936 struct pipe_ctx *pipe_ctx,
937 const struct dc_plane_state *plane_state)
939 struct dce_hwseq *hws = dc->hwseq;
940 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
941 const struct dc_transfer_func *tf = NULL;
943 bool use_degamma_ram = false;
945 if (dpp_base == NULL || plane_state == NULL)
948 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
949 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
951 if (plane_state->in_transfer_func)
952 tf = plane_state->in_transfer_func;
956 dpp_base->funcs->dpp_set_degamma(dpp_base,
957 IPP_DEGAMMA_MODE_BYPASS);
961 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
962 use_degamma_ram = true;
964 if (use_degamma_ram == true) {
965 if (tf->type == TF_TYPE_HWPWL)
966 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
968 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
969 cm_helper_translate_curve_to_degamma_hw_format(tf,
970 &dpp_base->degamma_params);
971 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
972 &dpp_base->degamma_params);
976 /* handle here the optimized cases when de-gamma ROM could be used.
979 if (tf->type == TF_TYPE_PREDEFINED) {
981 case TRANSFER_FUNCTION_SRGB:
982 dpp_base->funcs->dpp_set_degamma(dpp_base,
983 IPP_DEGAMMA_MODE_HW_sRGB);
985 case TRANSFER_FUNCTION_BT709:
986 dpp_base->funcs->dpp_set_degamma(dpp_base,
987 IPP_DEGAMMA_MODE_HW_xvYCC);
989 case TRANSFER_FUNCTION_LINEAR:
990 dpp_base->funcs->dpp_set_degamma(dpp_base,
991 IPP_DEGAMMA_MODE_BYPASS);
993 case TRANSFER_FUNCTION_PQ:
994 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
995 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
996 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
1003 } else if (tf->type == TF_TYPE_BYPASS)
1004 dpp_base->funcs->dpp_set_degamma(dpp_base,
1005 IPP_DEGAMMA_MODE_BYPASS);
1008 * if we are here, we did not handle correctly.
1009 * fix is required for this use case
1011 BREAK_TO_DEBUGGER();
1012 dpp_base->funcs->dpp_set_degamma(dpp_base,
1013 IPP_DEGAMMA_MODE_BYPASS);
1019 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1021 struct pipe_ctx *odm_pipe;
1023 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
1025 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1026 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
1031 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1032 pipe_ctx->stream_res.tg,
1034 &pipe_ctx->stream->timing);
1036 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1037 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1040 void dcn20_blank_pixel_data(
1042 struct pipe_ctx *pipe_ctx,
1045 struct tg_color black_color = {0};
1046 struct stream_resource *stream_res = &pipe_ctx->stream_res;
1047 struct dc_stream_state *stream = pipe_ctx->stream;
1048 enum dc_color_space color_space = stream->output_color_space;
1049 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
1050 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1051 struct pipe_ctx *odm_pipe;
1054 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1055 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1057 if (stream->link->test_pattern_enabled)
1060 /* get opp dpg blank color */
1061 color_space_to_black_color(dc, color_space, &black_color);
1063 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1066 width = width / odm_cnt;
1069 dc->hwss.set_abm_immediate_disable(pipe_ctx);
1071 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
1072 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1073 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1076 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1079 dc->hwss.set_disp_pattern_generator(dc,
1082 test_pattern_color_space,
1083 stream->timing.display_color_depth,
1089 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1090 dc->hwss.set_disp_pattern_generator(dc,
1092 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
1093 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
1094 test_pattern_color_space,
1095 stream->timing.display_color_depth,
1102 if (!blank && dc->debug.enable_single_display_2to1_odm_policy) {
1103 /* when exiting dynamic ODM need to reinit DPG state for unused pipes */
1104 struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe;
1106 odm_pipe = pipe_ctx->next_odm_pipe;
1108 while (old_odm_pipe) {
1109 if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx)
1110 dc->hwss.set_disp_pattern_generator(dc,
1112 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
1113 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1119 old_odm_pipe = old_odm_pipe->next_odm_pipe;
1121 odm_pipe = odm_pipe->next_odm_pipe;
1126 if (stream_res->abm) {
1127 dc->hwss.set_pipe(pipe_ctx);
1128 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1133 static void dcn20_power_on_plane_resources(
1134 struct dce_hwseq *hws,
1135 struct pipe_ctx *pipe_ctx)
1137 DC_LOGGER_INIT(hws->ctx->logger);
1139 if (hws->funcs.dpp_root_clock_control)
1140 hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1142 if (REG(DC_IP_REQUEST_CNTL)) {
1143 REG_SET(DC_IP_REQUEST_CNTL, 0,
1146 if (hws->funcs.dpp_pg_control)
1147 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1149 if (hws->funcs.hubp_pg_control)
1150 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1152 REG_SET(DC_IP_REQUEST_CNTL, 0,
1155 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1159 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1160 struct dc_state *context)
1162 //if (dc->debug.sanity_checks) {
1163 // dcn10_verify_allow_pstate_change_high(dc);
1165 dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);
1167 /* enable DCFCLK current DCHUB */
1168 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1170 /* initialize HUBP on power up */
1171 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1173 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1174 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1175 pipe_ctx->stream_res.opp,
1178 /* TODO: enable/disable in dm as per update type.
1180 DC_LOG_DC(dc->ctx->logger,
1181 "Pipe:%d 0x%x: addr hi:0x%x, "
1184 " %d; dst: %d, %d, %d, %d;\n",
1187 plane_state->address.grph.addr.high_part,
1188 plane_state->address.grph.addr.low_part,
1189 plane_state->src_rect.x,
1190 plane_state->src_rect.y,
1191 plane_state->src_rect.width,
1192 plane_state->src_rect.height,
1193 plane_state->dst_rect.x,
1194 plane_state->dst_rect.y,
1195 plane_state->dst_rect.width,
1196 plane_state->dst_rect.height);
1198 DC_LOG_DC(dc->ctx->logger,
1199 "Pipe %d: width, height, x, y format:%d\n"
1200 "viewport:%d, %d, %d, %d\n"
1201 "recout: %d, %d, %d, %d\n",
1203 plane_state->format,
1204 pipe_ctx->plane_res.scl_data.viewport.width,
1205 pipe_ctx->plane_res.scl_data.viewport.height,
1206 pipe_ctx->plane_res.scl_data.viewport.x,
1207 pipe_ctx->plane_res.scl_data.viewport.y,
1208 pipe_ctx->plane_res.scl_data.recout.width,
1209 pipe_ctx->plane_res.scl_data.recout.height,
1210 pipe_ctx->plane_res.scl_data.recout.x,
1211 pipe_ctx->plane_res.scl_data.recout.y);
1212 print_rq_dlg_ttu(dc, pipe_ctx);
1215 if (dc->vm_pa_config.valid) {
1216 struct vm_system_aperture_param apt;
1218 apt.sys_default.quad_part = 0;
1220 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1221 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1223 // Program system aperture settings
1224 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1227 if (!pipe_ctx->top_pipe
1228 && pipe_ctx->plane_state
1229 && pipe_ctx->plane_state->flip_int_enabled
1230 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1231 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1233 // if (dc->debug.sanity_checks) {
1234 // dcn10_verify_allow_pstate_change_high(dc);
1238 void dcn20_pipe_control_lock(
1240 struct pipe_ctx *pipe,
1243 struct pipe_ctx *temp_pipe;
1244 bool flip_immediate = false;
1246 /* use TG master update lock to lock everything on the TG
1247 * therefore only top pipe need to lock
1249 if (!pipe || pipe->top_pipe)
1252 if (pipe->plane_state != NULL)
1253 flip_immediate = pipe->plane_state->flip_immediate;
1255 if (pipe->stream_res.gsl_group > 0) {
1256 temp_pipe = pipe->bottom_pipe;
1257 while (!flip_immediate && temp_pipe) {
1258 if (temp_pipe->plane_state != NULL)
1259 flip_immediate = temp_pipe->plane_state->flip_immediate;
1260 temp_pipe = temp_pipe->bottom_pipe;
1264 if (flip_immediate && lock) {
1265 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1270 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1271 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1272 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1277 /* no reason it should take this long for immediate flips */
1278 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
1280 temp_pipe = temp_pipe->bottom_pipe;
1284 /* In flip immediate and pipe splitting case, we need to use GSL
1285 * for synchronization. Only do setup on locking and on flip type change.
1287 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
1288 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1289 (!flip_immediate && pipe->stream_res.gsl_group > 0))
1290 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1292 if (pipe->plane_state != NULL)
1293 flip_immediate = pipe->plane_state->flip_immediate;
1295 temp_pipe = pipe->bottom_pipe;
1296 while (flip_immediate && temp_pipe) {
1297 if (temp_pipe->plane_state != NULL)
1298 flip_immediate = temp_pipe->plane_state->flip_immediate;
1299 temp_pipe = temp_pipe->bottom_pipe;
1302 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1304 dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1306 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1307 union dmub_hw_lock_flags hw_locks = { 0 };
1308 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1310 hw_locks.bits.lock_pipe = 1;
1311 inst_flags.otg_inst = pipe->stream_res.tg->inst;
1313 if (pipe->plane_state != NULL)
1314 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1316 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1320 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1322 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1324 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1327 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1329 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1333 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1335 new_pipe->update_flags.raw = 0;
1337 /* If non-phantom pipe is being transitioned to a phantom pipe,
1338 * set disable and return immediately. This is because the pipe
1339 * that was previously in use must be fully disabled before we
1340 * can "enable" it as a phantom pipe (since the OTG will certainly
1341 * be different). The post_unlock sequence will set the correct
1342 * update flags to enable the phantom pipe.
1344 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom &&
1345 new_pipe->plane_state && new_pipe->plane_state->is_phantom) {
1346 new_pipe->update_flags.bits.disable = 1;
1350 /* Exit on unchanged, unused pipe */
1351 if (!old_pipe->plane_state && !new_pipe->plane_state)
1353 /* Detect pipe enable/disable */
1354 if (!old_pipe->plane_state && new_pipe->plane_state) {
1355 new_pipe->update_flags.bits.enable = 1;
1356 new_pipe->update_flags.bits.mpcc = 1;
1357 new_pipe->update_flags.bits.dppclk = 1;
1358 new_pipe->update_flags.bits.hubp_interdependent = 1;
1359 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1360 new_pipe->update_flags.bits.gamut_remap = 1;
1361 new_pipe->update_flags.bits.scaler = 1;
1362 new_pipe->update_flags.bits.viewport = 1;
1363 new_pipe->update_flags.bits.det_size = 1;
1364 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1365 new_pipe->update_flags.bits.odm = 1;
1366 new_pipe->update_flags.bits.global_sync = 1;
1371 /* For SubVP we need to unconditionally enable because any phantom pipes are
1372 * always removed then newly added for every full updates whenever SubVP is in use.
1373 * The remove-add sequence of the phantom pipe always results in the pipe
1374 * being blanked in enable_stream_timing (DPG).
1376 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1377 new_pipe->update_flags.bits.enable = 1;
1379 /* Phantom pipes are effectively disabled, if the pipe was previously phantom
1382 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom &&
1383 new_pipe->plane_state && !new_pipe->plane_state->is_phantom)
1384 new_pipe->update_flags.bits.enable = 1;
1386 if (old_pipe->plane_state && !new_pipe->plane_state) {
1387 new_pipe->update_flags.bits.disable = 1;
1391 /* Detect plane change */
1392 if (old_pipe->plane_state != new_pipe->plane_state) {
1393 new_pipe->update_flags.bits.plane_changed = true;
1396 /* Detect top pipe only changes */
1397 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1398 /* Detect odm changes */
1399 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1400 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1401 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1402 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1403 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1404 new_pipe->update_flags.bits.odm = 1;
1406 /* Detect global sync changes */
1407 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1408 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1409 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1410 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1411 new_pipe->update_flags.bits.global_sync = 1;
1414 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
1415 new_pipe->update_flags.bits.det_size = 1;
1418 * Detect opp / tg change, only set on change, not on enable
1419 * Assume mpcc inst = pipe index, if not this code needs to be updated
1420 * since mpcc is what is affected by these. In fact all of our sequence
1421 * makes this assumption at the moment with how hubp reset is matched to
1422 * same index mpcc reset.
1424 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1425 new_pipe->update_flags.bits.opp_changed = 1;
1426 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1427 new_pipe->update_flags.bits.tg_changed = 1;
1430 * Detect mpcc blending changes, only dpp inst and opp matter here,
1431 * mpccs getting removed/inserted update connected ones during their own
1434 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1435 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1436 new_pipe->update_flags.bits.mpcc = 1;
1438 /* Detect dppclk change */
1439 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1440 new_pipe->update_flags.bits.dppclk = 1;
1442 /* Check for scl update */
1443 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1444 new_pipe->update_flags.bits.scaler = 1;
1445 /* Check for vp update */
1446 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1447 || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1448 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1449 new_pipe->update_flags.bits.viewport = 1;
1451 /* Detect dlg/ttu/rq updates */
1453 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1454 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1455 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1456 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1458 /* Detect pipe interdependent updates */
1459 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1460 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1461 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1462 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1463 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1464 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1465 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1466 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1467 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1468 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1469 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1470 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1471 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1472 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1473 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1474 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1475 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1476 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1477 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1478 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1479 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1480 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1481 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1482 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1483 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1484 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1485 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1486 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1487 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1488 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1489 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1490 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1491 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1492 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1493 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1494 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1495 new_pipe->update_flags.bits.hubp_interdependent = 1;
1497 /* Detect any other updates to ttu/rq/dlg */
1498 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1499 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1500 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1501 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1505 static void dcn20_update_dchubp_dpp(
1507 struct pipe_ctx *pipe_ctx,
1508 struct dc_state *context)
1510 struct dce_hwseq *hws = dc->hwseq;
1511 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1512 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1513 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1514 struct dccg *dccg = dc->res_pool->dccg;
1515 bool viewport_changed = false;
1517 if (pipe_ctx->update_flags.bits.dppclk)
1518 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1520 if (pipe_ctx->update_flags.bits.enable)
1521 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
1523 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1524 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1525 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1527 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1528 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1530 hubp->funcs->hubp_setup(
1532 &pipe_ctx->dlg_regs,
1533 &pipe_ctx->ttu_regs,
1535 &pipe_ctx->pipe_dlg_param);
1537 if (hubp->funcs->set_unbounded_requesting)
1538 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
1540 if (pipe_ctx->update_flags.bits.hubp_interdependent)
1541 hubp->funcs->hubp_setup_interdependent(
1543 &pipe_ctx->dlg_regs,
1544 &pipe_ctx->ttu_regs);
1546 if (pipe_ctx->update_flags.bits.enable ||
1547 pipe_ctx->update_flags.bits.plane_changed ||
1548 plane_state->update_flags.bits.bpp_change ||
1549 plane_state->update_flags.bits.input_csc_change ||
1550 plane_state->update_flags.bits.color_space_change ||
1551 plane_state->update_flags.bits.coeff_reduction_change) {
1552 struct dc_bias_and_scale bns_params = {0};
1554 // program the input csc
1555 dpp->funcs->dpp_setup(dpp,
1556 plane_state->format,
1557 EXPANSION_MODE_ZERO,
1558 plane_state->input_csc_color_matrix,
1559 plane_state->color_space,
1562 if (dpp->funcs->dpp_program_bias_and_scale) {
1563 //TODO :for CNVC set scale and bias registers if necessary
1564 build_prescale_params(&bns_params, plane_state);
1565 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1569 if (pipe_ctx->update_flags.bits.mpcc
1570 || pipe_ctx->update_flags.bits.plane_changed
1571 || plane_state->update_flags.bits.global_alpha_change
1572 || plane_state->update_flags.bits.per_pixel_alpha_change) {
1573 // MPCC inst is equal to pipe index in practice
1574 int mpcc_inst = hubp->inst;
1576 int opp_count = dc->res_pool->pipe_count;
1578 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1579 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1580 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1581 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1585 hws->funcs.update_mpcc(dc, pipe_ctx);
1588 if (pipe_ctx->update_flags.bits.scaler ||
1589 plane_state->update_flags.bits.scaling_change ||
1590 plane_state->update_flags.bits.position_change ||
1591 plane_state->update_flags.bits.per_pixel_alpha_change ||
1592 pipe_ctx->stream->update_flags.bits.scaling) {
1593 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1594 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
1595 /* scaler configuration */
1596 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1597 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1600 if (pipe_ctx->update_flags.bits.viewport ||
1601 (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
1602 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1603 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1605 hubp->funcs->mem_program_viewport(
1607 &pipe_ctx->plane_res.scl_data.viewport,
1608 &pipe_ctx->plane_res.scl_data.viewport_c);
1609 viewport_changed = true;
1612 /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1613 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1614 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1615 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1616 dc->hwss.set_cursor_position(pipe_ctx);
1617 dc->hwss.set_cursor_attribute(pipe_ctx);
1619 if (dc->hwss.set_cursor_sdr_white_level)
1620 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1623 /* Any updates are handled in dc interface, just need
1624 * to apply existing for plane enable / opp change */
1625 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1626 || pipe_ctx->update_flags.bits.plane_changed
1627 || pipe_ctx->stream->update_flags.bits.gamut_remap
1628 || pipe_ctx->stream->update_flags.bits.out_csc) {
1629 /* dpp/cm gamut remap*/
1630 dc->hwss.program_gamut_remap(pipe_ctx);
1632 /*call the dcn2 method which uses mpc csc*/
1633 dc->hwss.program_output_csc(dc,
1635 pipe_ctx->stream->output_color_space,
1636 pipe_ctx->stream->csc_color_matrix.matrix,
1640 if (pipe_ctx->update_flags.bits.enable ||
1641 pipe_ctx->update_flags.bits.plane_changed ||
1642 pipe_ctx->update_flags.bits.opp_changed ||
1643 plane_state->update_flags.bits.pixel_format_change ||
1644 plane_state->update_flags.bits.horizontal_mirror_change ||
1645 plane_state->update_flags.bits.rotation_change ||
1646 plane_state->update_flags.bits.swizzle_change ||
1647 plane_state->update_flags.bits.dcc_change ||
1648 plane_state->update_flags.bits.bpp_change ||
1649 plane_state->update_flags.bits.scaling_change ||
1650 plane_state->update_flags.bits.plane_size_change) {
1651 struct plane_size size = plane_state->plane_size;
1653 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1654 hubp->funcs->hubp_program_surface_config(
1656 plane_state->format,
1657 &plane_state->tiling_info,
1659 plane_state->rotation,
1661 plane_state->horizontal_mirror,
1663 hubp->power_gated = false;
1666 if (pipe_ctx->update_flags.bits.enable ||
1667 pipe_ctx->update_flags.bits.plane_changed ||
1668 plane_state->update_flags.bits.addr_update)
1669 hws->funcs.update_plane_addr(dc, pipe_ctx);
1671 if (pipe_ctx->update_flags.bits.enable)
1672 hubp->funcs->set_blank(hubp, false);
1673 /* If the stream paired with this plane is phantom, the plane is also phantom */
1674 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
1675 && hubp->funcs->phantom_hubp_post_enable)
1676 hubp->funcs->phantom_hubp_post_enable(hubp);
1679 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)
1681 struct pipe_ctx *other_pipe;
1682 int vready_offset = pipe->pipe_dlg_param.vready_offset;
1684 /* Always use the largest vready_offset of all connected pipes */
1685 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) {
1686 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1687 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1689 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) {
1690 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1691 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1693 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) {
1694 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1695 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1697 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) {
1698 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1699 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1702 return vready_offset;
1705 static void dcn20_program_pipe(
1707 struct pipe_ctx *pipe_ctx,
1708 struct dc_state *context)
1710 struct dce_hwseq *hws = dc->hwseq;
1711 /* Only need to unblank on top pipe */
1713 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1714 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1715 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1717 /* Only update TG on top pipe */
1718 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1719 && !pipe_ctx->prev_odm_pipe) {
1720 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1721 pipe_ctx->stream_res.tg,
1722 calculate_vready_offset_for_group(pipe_ctx),
1723 pipe_ctx->pipe_dlg_param.vstartup_start,
1724 pipe_ctx->pipe_dlg_param.vupdate_offset,
1725 pipe_ctx->pipe_dlg_param.vupdate_width);
1727 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM)
1728 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
1730 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1731 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1733 if (hws->funcs.setup_vupdate_interrupt)
1734 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1737 if (pipe_ctx->update_flags.bits.odm)
1738 hws->funcs.update_odm(dc, context, pipe_ctx);
1740 if (pipe_ctx->update_flags.bits.enable) {
1741 dcn20_enable_plane(dc, pipe_ctx, context);
1742 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1743 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1746 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
1747 dc->res_pool->hubbub->funcs->program_det_size(
1748 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
1750 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1751 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1753 if (pipe_ctx->update_flags.bits.enable
1754 || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1755 hws->funcs.set_hdr_multiplier(pipe_ctx);
1757 if (pipe_ctx->update_flags.bits.enable ||
1758 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1759 pipe_ctx->plane_state->update_flags.bits.gamma_change)
1760 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1762 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1763 * only do gamma programming for powering on, internal memcmp to avoid
1764 * updating on slave planes
1766 if (pipe_ctx->update_flags.bits.enable ||
1767 pipe_ctx->update_flags.bits.plane_changed ||
1768 pipe_ctx->stream->update_flags.bits.out_tf ||
1769 pipe_ctx->plane_state->update_flags.bits.output_tf_change)
1770 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1772 /* If the pipe has been enabled or has a different opp, we
1773 * should reprogram the fmt. This deals with cases where
1774 * interation between mpc and odm combine on different streams
1775 * causes a different pipe to be chosen to odm combine with.
1777 if (pipe_ctx->update_flags.bits.enable
1778 || pipe_ctx->update_flags.bits.opp_changed) {
1780 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1781 pipe_ctx->stream_res.opp,
1782 COLOR_SPACE_YCBCR601,
1783 pipe_ctx->stream->timing.display_color_depth,
1784 pipe_ctx->stream->signal);
1786 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1787 pipe_ctx->stream_res.opp,
1788 &pipe_ctx->stream->bit_depth_params,
1789 &pipe_ctx->stream->clamping);
1792 /* Set ABM pipe after other pipe configurations done */
1793 if (pipe_ctx->plane_state->visible) {
1794 if (pipe_ctx->stream_res.abm) {
1795 dc->hwss.set_pipe(pipe_ctx);
1796 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,
1797 pipe_ctx->stream->abm_level);
1802 void dcn20_program_front_end_for_ctx(
1804 struct dc_state *context)
1807 struct dce_hwseq *hws = dc->hwseq;
1808 DC_LOGGER_INIT(dc->ctx->logger);
1810 /* Carry over GSL groups in case the context is changing. */
1811 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1812 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1813 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1815 if (pipe_ctx->stream == old_pipe_ctx->stream)
1816 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
1819 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1820 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1821 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1823 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1824 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1825 /*turn off triple buffer for full update*/
1826 dc->hwss.program_triplebuffer(
1827 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1832 /* Set pipe update flags and lock pipes */
1833 for (i = 0; i < dc->res_pool->pipe_count; i++)
1834 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1835 &context->res_ctx.pipe_ctx[i]);
1837 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double
1838 * buffer updates properly)
1840 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1841 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
1843 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&
1844 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1845 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
1847 if (tg->funcs->enable_crtc)
1848 tg->funcs->enable_crtc(tg);
1851 /* OTG blank before disabling all front ends */
1852 for (i = 0; i < dc->res_pool->pipe_count; i++)
1853 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1854 && !context->res_ctx.pipe_ctx[i].top_pipe
1855 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1856 && context->res_ctx.pipe_ctx[i].stream)
1857 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1860 /* Disconnect mpcc */
1861 for (i = 0; i < dc->res_pool->pipe_count; i++)
1862 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1863 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1864 struct hubbub *hubbub = dc->res_pool->hubbub;
1866 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom
1867 * then we want to do the programming here (effectively it's being disabled). If we do
1868 * the programming later the DET won't be updated until the OTG for the phantom pipe is
1869 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with
1872 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||
1873 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom)))
1874 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
1875 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1876 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1880 * Program all updated pipes, order matters for mpcc setup. Start with
1881 * top pipe and program all pipes that follow in order
1883 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1884 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1886 if (pipe->plane_state && !pipe->top_pipe) {
1888 if (hws->funcs.program_pipe)
1889 hws->funcs.program_pipe(dc, pipe, context);
1891 /* Don't program phantom pipes in the regular front end programming sequence.
1892 * There is an MPO transition case where a pipe being used by a video plane is
1893 * transitioned directly to be a phantom pipe when closing the MPO video. However
1894 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away),
1895 * but the MPO still exists until the double buffered update of the main pipe so we
1896 * will get a frame of underflow if the phantom pipe is programmed here.
1898 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM)
1899 dcn20_program_pipe(dc, pipe, context);
1902 pipe = pipe->bottom_pipe;
1905 /* Program secondary blending tree and writeback pipes */
1906 pipe = &context->res_ctx.pipe_ctx[i];
1907 if (!pipe->top_pipe && !pipe->prev_odm_pipe
1908 && pipe->stream && pipe->stream->num_wb_info > 0
1909 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
1910 || pipe->stream->update_flags.raw)
1911 && hws->funcs.program_all_writeback_pipes_in_tree)
1912 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1914 /* Avoid underflow by check of pipe line read when adding 2nd plane. */
1915 if (hws->wa.wait_hubpret_read_start_during_mpo_transition &&
1918 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&
1919 dc->current_state->stream_status[0].plane_count == 1 &&
1920 context->stream_status[0].plane_count > 1) {
1921 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
1924 /* when dynamic ODM is active, pipes must be reconfigured when all planes are
1925 * disabled, as some transitions will leave software and hardware state
1928 if (dc->debug.enable_single_display_2to1_odm_policy &&
1930 pipe->update_flags.bits.disable &&
1931 !pipe->prev_odm_pipe &&
1932 hws->funcs.update_odm)
1933 hws->funcs.update_odm(dc, context, pipe);
1937 void dcn20_post_unlock_program_front_end(
1939 struct dc_state *context)
1942 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1943 struct dce_hwseq *hwseq = dc->hwseq;
1945 DC_LOGGER_INIT(dc->ctx->logger);
1947 for (i = 0; i < dc->res_pool->pipe_count; i++)
1948 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1949 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1952 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1953 * part of the enable operation otherwise, DM may request an immediate flip which
1954 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1955 * is unsupported on DCN.
1957 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1958 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1959 // Don't check flip pending on phantom pipes
1960 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&
1961 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1962 struct hubp *hubp = pipe->plane_res.hubp;
1965 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1966 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1971 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1972 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1974 if (pipe->plane_state && !pipe->top_pipe) {
1975 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition
1976 * case (if a pipe being used for a video plane transitions to a phantom pipe, it
1977 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end
1978 * programming sequence).
1981 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1982 /* When turning on the phantom pipe we want to run through the
1983 * entire enable sequence, so apply all the "enable" flags.
1985 if (dc->hwss.apply_update_flags_for_phantom)
1986 dc->hwss.apply_update_flags_for_phantom(pipe);
1987 if (dc->hwss.update_phantom_vp_position)
1988 dc->hwss.update_phantom_vp_position(dc, context, pipe);
1989 dcn20_program_pipe(dc, pipe, context);
1991 pipe = pipe->bottom_pipe;
1996 /* P-State support transitions:
1997 * Natural -> FPO: P-State disabled in prepare, force disallow anytime is safe
1998 * FPO -> Natural: Unforce anytime after FW disable is safe (P-State will assert naturally)
1999 * Unsupported -> FPO: P-State enabled in optimize, force disallow anytime is safe
2000 * FPO -> Unsupported: P-State disabled in prepare, unforce disallow anytime is safe
2001 * FPO <-> SubVP: Force disallow is maintained on the FPO / SubVP pipes
2003 if (hwseq && hwseq->funcs.update_force_pstate)
2004 dc->hwseq->funcs.update_force_pstate(dc, context);
2006 /* Only program the MALL registers after all the main and phantom pipes
2007 * are done programming.
2009 if (hwseq->funcs.program_mall_pipe_config)
2010 hwseq->funcs.program_mall_pipe_config(dc, context);
2012 /* WA to apply WM setting*/
2013 if (hwseq->wa.DEGVIDCN21)
2014 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
2017 /* WA for stutter underflow during MPO transitions when adding 2nd plane */
2018 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
2020 if (dc->current_state->stream_status[0].plane_count == 1 &&
2021 context->stream_status[0].plane_count > 1) {
2023 struct timing_generator *tg = dc->res_pool->timing_generators[0];
2025 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
2027 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
2028 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
2033 void dcn20_prepare_bandwidth(
2035 struct dc_state *context)
2037 struct hubbub *hubbub = dc->res_pool->hubbub;
2038 unsigned int compbuf_size_kb = 0;
2039 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns;
2042 dc->clk_mgr->funcs->update_clocks(
2047 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2048 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2050 // At optimize don't restore the original watermark value
2051 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2052 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2057 /* program dchubbub watermarks:
2058 * For assigning wm_optimized_required, use |= operator since we don't want
2059 * to clear the value if the optimize has not happened yet
2061 dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub,
2062 &context->bw_ctx.bw.dcn.watermarks,
2063 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2066 // Restore the real watermark so we can commit the value to DMCUB
2067 // DMCUB uses the "original" watermark value in SubVP MCLK switch
2068 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a;
2070 /* decrease compbuf size */
2071 if (hubbub->funcs->program_compbuf_size) {
2072 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) {
2073 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
2074 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);
2076 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
2077 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);
2080 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
2084 void dcn20_optimize_bandwidth(
2086 struct dc_state *context)
2088 struct hubbub *hubbub = dc->res_pool->hubbub;
2091 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2092 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2094 // At optimize don't need to restore the original watermark value
2095 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2096 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2101 /* program dchubbub watermarks */
2102 hubbub->funcs->program_watermarks(hubbub,
2103 &context->bw_ctx.bw.dcn.watermarks,
2104 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2107 if (dc->clk_mgr->dc_mode_softmax_enabled)
2108 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
2109 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
2110 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
2112 /* increase compbuf size */
2113 if (hubbub->funcs->program_compbuf_size)
2114 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
2116 dc->clk_mgr->funcs->update_clocks(
2120 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
2121 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
2122 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2124 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank
2125 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max
2126 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
2127 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,
2128 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start);
2133 bool dcn20_update_bandwidth(
2135 struct dc_state *context)
2138 struct dce_hwseq *hws = dc->hwseq;
2140 /* recalculate DML parameters */
2141 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
2144 /* apply updated bandwidth parameters */
2145 dc->hwss.prepare_bandwidth(dc, context);
2147 /* update hubp configs for all pipes */
2148 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2149 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2151 if (pipe_ctx->plane_state == NULL)
2154 if (pipe_ctx->top_pipe == NULL) {
2155 bool blank = !is_pipe_tree_visible(pipe_ctx);
2157 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2158 pipe_ctx->stream_res.tg,
2159 calculate_vready_offset_for_group(pipe_ctx),
2160 pipe_ctx->pipe_dlg_param.vstartup_start,
2161 pipe_ctx->pipe_dlg_param.vupdate_offset,
2162 pipe_ctx->pipe_dlg_param.vupdate_width);
2164 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2165 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
2167 if (pipe_ctx->prev_odm_pipe == NULL)
2168 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
2170 if (hws->funcs.setup_vupdate_interrupt)
2171 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
2174 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
2175 pipe_ctx->plane_res.hubp,
2176 &pipe_ctx->dlg_regs,
2177 &pipe_ctx->ttu_regs,
2179 &pipe_ctx->pipe_dlg_param);
2185 void dcn20_enable_writeback(
2187 struct dc_writeback_info *wb_info,
2188 struct dc_state *context)
2191 struct mcif_wb *mcif_wb;
2192 struct timing_generator *optc;
2194 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
2195 ASSERT(wb_info->wb_enabled);
2196 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
2197 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
2199 /* set the OPTC source mux */
2200 optc = dc->res_pool->timing_generators[dwb->otg_inst];
2201 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
2202 /* set MCIF_WB buffer and arbitration configuration */
2203 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
2204 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
2205 /* Enable MCIF_WB */
2206 mcif_wb->funcs->enable_mcif(mcif_wb);
2208 dwb->funcs->enable(dwb, &wb_info->dwb_params);
2209 /* TODO: add sequence to enable/disable warmup */
2212 void dcn20_disable_writeback(
2214 unsigned int dwb_pipe_inst)
2217 struct mcif_wb *mcif_wb;
2219 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
2220 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
2221 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
2223 dwb->funcs->disable(dwb);
2224 mcif_wb->funcs->disable_mcif(mcif_wb);
2227 bool dcn20_wait_for_blank_complete(
2228 struct output_pixel_processor *opp)
2232 for (counter = 0; counter < 1000; counter++) {
2233 if (opp->funcs->dpg_is_blanked(opp))
2239 if (counter == 1000) {
2240 dm_error("DC: failed to blank crtc!\n");
2247 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
2249 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2253 return hubp->funcs->dmdata_status_done(hubp);
2256 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2258 struct dce_hwseq *hws = dc->hwseq;
2260 if (pipe_ctx->stream_res.dsc) {
2261 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2263 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
2265 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
2266 odm_pipe = odm_pipe->next_odm_pipe;
2271 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2273 struct dce_hwseq *hws = dc->hwseq;
2275 if (pipe_ctx->stream_res.dsc) {
2276 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2278 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
2280 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
2281 odm_pipe = odm_pipe->next_odm_pipe;
2286 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
2288 struct dc_dmdata_attributes attr = { 0 };
2289 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2291 attr.dmdata_mode = DMDATA_HW_MODE;
2293 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2294 attr.address.quad_part =
2295 pipe_ctx->stream->dmdata_address.quad_part;
2296 attr.dmdata_dl_delta = 0;
2297 attr.dmdata_qos_mode = 0;
2298 attr.dmdata_qos_level = 0;
2299 attr.dmdata_repeat = 1; /* always repeat */
2300 attr.dmdata_updated = 1;
2301 attr.dmdata_sw_data = NULL;
2303 hubp->funcs->dmdata_set_attributes(hubp, &attr);
2306 void dcn20_init_vm_ctx(
2307 struct dce_hwseq *hws,
2309 struct dc_virtual_addr_space_config *va_config,
2312 struct dcn_hubbub_virt_addr_config config;
2315 ASSERT(0); /* VMID cannot be 0 for vm context */
2319 config.page_table_start_addr = va_config->page_table_start_addr;
2320 config.page_table_end_addr = va_config->page_table_end_addr;
2321 config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2322 config.page_table_depth = va_config->page_table_depth;
2323 config.page_table_base_addr = va_config->page_table_base_addr;
2325 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2328 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
2330 struct dcn_hubbub_phys_addr_config config;
2332 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2333 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2334 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2335 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2336 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2337 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2338 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2339 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2340 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
2341 config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
2343 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
2346 static bool patch_address_for_sbs_tb_stereo(
2347 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2349 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2350 bool sec_split = pipe_ctx->top_pipe &&
2351 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2352 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2353 (pipe_ctx->stream->timing.timing_3d_format ==
2354 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2355 pipe_ctx->stream->timing.timing_3d_format ==
2356 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2357 *addr = plane_state->address.grph_stereo.left_addr;
2358 plane_state->address.grph_stereo.left_addr =
2359 plane_state->address.grph_stereo.right_addr;
2363 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2364 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2365 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2366 plane_state->address.grph_stereo.right_addr =
2367 plane_state->address.grph_stereo.left_addr;
2368 plane_state->address.grph_stereo.right_meta_addr =
2369 plane_state->address.grph_stereo.left_meta_addr;
2374 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
2376 bool addr_patched = false;
2377 PHYSICAL_ADDRESS_LOC addr;
2378 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2380 if (plane_state == NULL)
2383 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2385 // Call Helper to track VMID use
2386 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
2388 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2389 pipe_ctx->plane_res.hubp,
2390 &plane_state->address,
2391 plane_state->flip_immediate);
2393 plane_state->status.requested_address = plane_state->address;
2395 if (plane_state->flip_immediate)
2396 plane_state->status.current_address = plane_state->address;
2399 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2402 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2403 struct dc_link_settings *link_settings)
2405 struct encoder_unblank_param params = {0};
2406 struct dc_stream_state *stream = pipe_ctx->stream;
2407 struct dc_link *link = stream->link;
2408 struct dce_hwseq *hws = link->dc->hwseq;
2409 struct pipe_ctx *odm_pipe;
2412 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2415 /* only 3 items below are used by unblank */
2416 params.timing = pipe_ctx->stream->timing;
2418 params.link_settings.link_rate = link_settings->link_rate;
2420 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
2421 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
2422 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
2423 pipe_ctx->stream_res.hpo_dp_stream_enc,
2424 pipe_ctx->stream_res.tg->inst);
2425 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2426 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
2427 params.timing.pix_clk_100hz /= 2;
2428 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
2429 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
2430 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);
2433 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2434 hws->funcs.edp_backlight_control(link, true);
2438 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2440 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2441 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2446 if (tg->funcs->setup_vertical_interrupt2)
2447 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2450 static void dcn20_reset_back_end_for_pipe(
2452 struct pipe_ctx *pipe_ctx,
2453 struct dc_state *context)
2456 struct dc_link *link = pipe_ctx->stream->link;
2457 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2459 DC_LOGGER_INIT(dc->ctx->logger);
2460 if (pipe_ctx->stream_res.stream_enc == NULL) {
2461 pipe_ctx->stream = NULL;
2465 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2466 /* DPMS may already disable or */
2467 /* dpms_off status is incorrect due to fastboot
2468 * feature. When system resume from S4 with second
2469 * screen only, the dpms_off would be true but
2470 * VBIOS lit up eDP, so check link status too.
2472 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2473 dc->link_srv->set_dpms_off(pipe_ctx);
2474 else if (pipe_ctx->stream_res.audio)
2475 dc->hwss.disable_audio_stream(pipe_ctx);
2477 /* free acquired resources */
2478 if (pipe_ctx->stream_res.audio) {
2479 /*disable az_endpoint*/
2480 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2483 if (dc->caps.dynamic_audio == true) {
2484 /*we have to dynamic arbitrate the audio endpoints*/
2485 /*we free the resource, need reset is_audio_acquired*/
2486 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2487 pipe_ctx->stream_res.audio, false);
2488 pipe_ctx->stream_res.audio = NULL;
2492 else if (pipe_ctx->stream_res.dsc) {
2493 dc->link_srv->set_dsc_enable(pipe_ctx, false);
2496 /* by upper caller loop, parent pipe: pipe0, will be reset last.
2497 * back end share by all pipes and will be disable only when disable
2500 if (pipe_ctx->top_pipe == NULL) {
2502 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2504 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2506 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2507 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2508 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2509 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2511 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2512 pipe_ctx->stream_res.tg->funcs->set_drr(
2513 pipe_ctx->stream_res.tg, NULL);
2514 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve
2515 * the case where the same symclk is shared across multiple otg
2518 link->phy_state.symclk_ref_cnts.otg = 0;
2519 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
2520 link_hwss->disable_link_output(link,
2521 &pipe_ctx->link_res, pipe_ctx->stream->signal);
2522 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
2526 for (i = 0; i < dc->res_pool->pipe_count; i++)
2527 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2530 if (i == dc->res_pool->pipe_count)
2533 pipe_ctx->stream = NULL;
2534 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2535 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2538 void dcn20_reset_hw_ctx_wrap(
2540 struct dc_state *context)
2543 struct dce_hwseq *hws = dc->hwseq;
2546 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2547 struct pipe_ctx *pipe_ctx_old =
2548 &dc->current_state->res_ctx.pipe_ctx[i];
2549 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2551 if (!pipe_ctx_old->stream)
2554 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2557 if (!pipe_ctx->stream ||
2558 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2559 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2561 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2562 if (hws->funcs.enable_stream_gating)
2563 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
2565 old_clk->funcs->cs_power_down(old_clk);
2570 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
2572 struct mpc *mpc = dc->res_pool->mpc;
2574 // input to MPCC is always RGB, by default leave black_color at 0
2575 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
2576 get_hdr_visual_confirm_color(pipe_ctx, color);
2577 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
2578 get_surface_visual_confirm_color(pipe_ctx, color);
2579 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
2580 get_mpctree_visual_confirm_color(pipe_ctx, color);
2581 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
2582 get_surface_tile_visual_confirm_color(pipe_ctx, color);
2583 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
2584 get_subvp_visual_confirm_color(dc, pipe_ctx, color);
2586 if (mpc->funcs->set_bg_color) {
2587 memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
2588 mpc->funcs->set_bg_color(mpc, color, mpcc_id);
2592 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2594 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2595 struct mpcc_blnd_cfg blnd_cfg = {0};
2596 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2598 struct mpcc *new_mpcc;
2599 struct mpc *mpc = dc->res_pool->mpc;
2600 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2602 blnd_cfg.overlap_only = false;
2603 blnd_cfg.global_gain = 0xff;
2605 if (per_pixel_alpha) {
2606 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;
2607 if (pipe_ctx->plane_state->global_alpha) {
2608 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2609 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2611 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2614 blnd_cfg.pre_multiplied_alpha = false;
2615 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2618 if (pipe_ctx->plane_state->global_alpha)
2619 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2621 blnd_cfg.global_alpha = 0xff;
2623 blnd_cfg.background_color_bpc = 4;
2624 blnd_cfg.bottom_gain_mode = 0;
2625 blnd_cfg.top_gain = 0x1f000;
2626 blnd_cfg.bottom_inside_gain = 0x1f000;
2627 blnd_cfg.bottom_outside_gain = 0x1f000;
2629 if (pipe_ctx->plane_state->format
2630 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2631 blnd_cfg.pre_multiplied_alpha = false;
2635 * Note: currently there is a bug in init_hw such that
2636 * on resume from hibernate, BIOS sets up MPCC0, and
2637 * we do mpcc_remove but the mpcc cannot go to idle
2638 * after remove. This cause us to pick mpcc1 here,
2639 * which causes a pstate hang for yet unknown reason.
2641 mpcc_id = hubp->inst;
2643 /* If there is no full update, don't need to touch MPC tree*/
2644 if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2645 !pipe_ctx->update_flags.bits.mpcc) {
2646 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2647 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2651 /* check if this MPCC is already being used */
2652 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2653 /* remove MPCC if being used */
2654 if (new_mpcc != NULL)
2655 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2657 if (dc->debug.sanity_checks)
2658 mpc->funcs->assert_mpcc_idle_before_connect(
2659 dc->res_pool->mpc, mpcc_id);
2661 /* Call MPC to insert new plane */
2662 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2669 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2671 ASSERT(new_mpcc != NULL);
2672 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2673 hubp->mpcc_id = mpcc_id;
2676 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
2678 switch (link->link_enc->transmitter) {
2679 case TRANSMITTER_UNIPHY_A:
2681 case TRANSMITTER_UNIPHY_B:
2683 case TRANSMITTER_UNIPHY_C:
2685 case TRANSMITTER_UNIPHY_D:
2687 case TRANSMITTER_UNIPHY_E:
2694 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
2696 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2699 while (odm_pipe != NULL) {
2701 odm_pipe = odm_pipe->next_odm_pipe;
2707 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2709 enum dc_lane_count lane_count =
2710 pipe_ctx->stream->link->cur_link_settings.lane_count;
2712 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2713 struct dc_link *link = pipe_ctx->stream->link;
2715 uint32_t active_total_with_borders;
2716 uint32_t early_control = 0;
2717 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2718 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2719 struct dc *dc = pipe_ctx->stream->ctx->dc;
2720 struct dtbclk_dto_params dto_params = {0};
2721 struct dccg *dccg = dc->res_pool->dccg;
2722 enum phyd32clk_clock_source phyd32clk;
2724 struct dce_hwseq *hws = dc->hwseq;
2725 unsigned int k1_div = PIXEL_RATE_DIV_NA;
2726 unsigned int k2_div = PIXEL_RATE_DIV_NA;
2728 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
2729 if (dc->hwseq->funcs.setup_hpo_hw_control)
2730 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
2733 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
2734 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
2735 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
2737 phyd32clk = get_phyd32clk_src(link);
2738 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
2740 dto_params.otg_inst = tg->inst;
2741 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
2742 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
2743 dto_params.timing = &pipe_ctx->stream->timing;
2744 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
2745 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
2748 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
2749 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
2751 dc->res_pool->dccg->funcs->set_pixel_rate_div(
2753 pipe_ctx->stream_res.tg->inst,
2757 link_hwss->setup_stream_encoder(pipe_ctx);
2759 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2760 if (dc->hwss.program_dmdata_engine)
2761 dc->hwss.program_dmdata_engine(pipe_ctx);
2764 dc->hwss.update_info_frame(pipe_ctx);
2766 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2767 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
2769 /* enable early control to avoid corruption on DP monitor*/
2770 active_total_with_borders =
2771 timing->h_addressable
2772 + timing->h_border_left
2773 + timing->h_border_right;
2775 if (lane_count != 0)
2776 early_control = active_total_with_borders % lane_count;
2778 if (early_control == 0)
2779 early_control = lane_count;
2781 tg->funcs->set_early_control(tg, early_control);
2783 if (dc->hwseq->funcs.set_pixels_per_cycle)
2784 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
2787 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2789 struct dc_stream_state *stream = pipe_ctx->stream;
2790 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2791 bool enable = false;
2792 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
2793 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
2797 /* if using dynamic meta, don't set up generic infopackets */
2798 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2799 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2806 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2809 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2813 void dcn20_fpga_init_hw(struct dc *dc)
2816 struct dce_hwseq *hws = dc->hwseq;
2817 struct resource_pool *res_pool = dc->res_pool;
2818 struct dc_state *context = dc->current_state;
2820 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2821 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2823 // Initialize the dccg
2824 if (res_pool->dccg->funcs->dccg_init)
2825 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2827 //Enable ability to power gate / don't force power on permanently
2828 hws->funcs.enable_power_gating_plane(hws, true);
2830 // Specific to FPGA dccg and registers
2831 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2832 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2834 hws->funcs.dccg_init(hws);
2836 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2837 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2838 if (REG(REFCLK_CNTL))
2839 REG_WRITE(REFCLK_CNTL, 0);
2843 /* Blank pixel data with OPP DPG */
2844 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2845 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2847 if (tg->funcs->is_tg_enabled(tg))
2848 dcn20_init_blank(dc, tg);
2851 for (i = 0; i < res_pool->timing_generator_count; i++) {
2852 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2854 if (tg->funcs->is_tg_enabled(tg))
2855 tg->funcs->lock(tg);
2858 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2859 struct dpp *dpp = res_pool->dpps[i];
2861 dpp->funcs->dpp_reset(dpp);
2864 /* Reset all MPCC muxes */
2865 res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2867 /* initialize OPP mpc_tree parameter */
2868 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2869 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2870 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2871 for (j = 0; j < MAX_PIPES; j++)
2872 res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2875 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2876 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2877 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2878 struct hubp *hubp = dc->res_pool->hubps[i];
2879 struct dpp *dpp = dc->res_pool->dpps[i];
2881 pipe_ctx->stream_res.tg = tg;
2882 pipe_ctx->pipe_idx = i;
2884 pipe_ctx->plane_res.hubp = hubp;
2885 pipe_ctx->plane_res.dpp = dpp;
2886 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2887 hubp->mpcc_id = dpp->inst;
2888 hubp->opp_id = OPP_ID_INVALID;
2889 hubp->power_gated = false;
2890 pipe_ctx->stream_res.opp = NULL;
2892 hubp->funcs->hubp_init(hubp);
2894 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2895 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2896 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2897 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2899 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2902 /* initialize DWB pointer to MCIF_WB */
2903 for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2904 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2906 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2907 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2909 if (tg->funcs->is_tg_enabled(tg))
2910 tg->funcs->unlock(tg);
2913 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2914 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2916 dc->hwss.disable_plane(dc, pipe_ctx);
2918 pipe_ctx->stream_res.tg = NULL;
2919 pipe_ctx->plane_res.hubp = NULL;
2922 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2923 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2925 tg->funcs->tg_init(tg);
2928 if (dc->res_pool->hubbub->funcs->init_crb)
2929 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
2932 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2933 struct dc_crtc_timing *timing,
2934 unsigned int max_input_rate_in_khz)
2936 unsigned int old_v_front_porch;
2937 unsigned int old_v_total;
2938 unsigned int max_input_rate_in_100hz;
2939 unsigned long long new_v_total;
2941 max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2942 if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2945 old_v_total = timing->v_total;
2946 old_v_front_porch = timing->v_front_porch;
2948 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2949 timing->pix_clk_100hz = max_input_rate_in_100hz;
2951 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2953 timing->v_total = new_v_total;
2954 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2959 void dcn20_set_disp_pattern_generator(const struct dc *dc,
2960 struct pipe_ctx *pipe_ctx,
2961 enum controller_dp_test_pattern test_pattern,
2962 enum controller_dp_color_space color_space,
2963 enum dc_color_depth color_depth,
2964 const struct tg_color *solid_color,
2965 int width, int height, int offset)
2967 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2968 color_space, color_depth, solid_color, width, height, offset);