drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28
  29 #include "resource.h"
  30 #include "include/irq_service_interface.h"
  31 #include "dcn10/dcn10_resource.h"
  32
  33 #include "dcn10/dcn10_ipp.h"
  34 #include "dcn10/dcn10_mpc.h"
  35 #include "irq/dcn10/irq_service_dcn10.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_timing_generator.h"
  38 #include "dcn10/dcn10_hw_sequencer.h"
  39 #include "dce110/dce110_hw_sequencer.h"
  40 #include "dcn10/dcn10_opp.h"
  41 #include "dce/dce_link_encoder.h"
  42 #include "dce/dce_stream_encoder.h"
  43 #include "dce/dce_clocks.h"
  44 #include "dce/dce_clock_source.h"
  45 #include "dce/dce_audio.h"
  46 #include "dce/dce_hwseq.h"
  47 #include "../virtual/virtual_stream_encoder.h"
  48 #include "dce110/dce110_resource.h"
  49 #include "dce112/dce112_resource.h"
  50 #include "dcn10_hubp.h"
  51 #include "dcn10_hubbub.h"
  52
  53 #include "soc15ip.h"
  54
  55 #include "dcn/dcn_1_0_offset.h"
  56 #include "dcn/dcn_1_0_sh_mask.h"
  57
  58 #include "nbio/nbio_7_0_offset.h"
  59
  60 #include "mmhub/mmhub_9_1_offset.h"
  61 #include "mmhub/mmhub_9_1_sh_mask.h"
  62
  63 #include "reg_helper.h"
  64 #include "dce/dce_abm.h"
  65 #include "dce/dce_dmcu.h"
  66
  67 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
  68         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
  69         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  70         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
  71         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  72         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
  73         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  74         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
  75         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  76         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
  77         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  78         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
  79         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  80         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
  81         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  82 #endif
  83
  84
  85 enum dcn10_clk_src_array_id {
  86         DCN10_CLK_SRC_PLL0,
  87         DCN10_CLK_SRC_PLL1,
  88         DCN10_CLK_SRC_PLL2,
  89         DCN10_CLK_SRC_PLL3,
  90         DCN10_CLK_SRC_TOTAL
  91 };
  92
  93 /* begin *********************
  94  * macros to expend register list macro defined in HW object header file */
  95
  96 /* DCN */
  97 #define BASE_INNER(seg) \
  98         DCE_BASE__INST0_SEG ## seg
  99
 100 #define BASE(seg) \
 101         BASE_INNER(seg)
 102
 103 #define SR(reg_name)\
 104                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 105                                         mm ## reg_name
 106
 107 #define SRI(reg_name, block, id)\
 108         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 109                                         mm ## block ## id ## _ ## reg_name
 110
 111
 112 #define SRII(reg_name, block, id)\
 113         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 114                                         mm ## block ## id ## _ ## reg_name
 115
 116 /* NBIO */
 117 #define NBIO_BASE_INNER(seg) \
 118         NBIF_BASE__INST0_SEG ## seg
 119
 120 #define NBIO_BASE(seg) \
 121         NBIO_BASE_INNER(seg)
 122
 123 #define NBIO_SR(reg_name)\
 124                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
 125                                         mm ## reg_name
 126
 127 /* MMHUB */
 128 #define MMHUB_BASE_INNER(seg) \
 129         MMHUB_BASE__INST0_SEG ## seg
 130
 131 #define MMHUB_BASE(seg) \
 132         MMHUB_BASE_INNER(seg)
 133
 134 #define MMHUB_SR(reg_name)\
 135                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
 136                                         mm ## reg_name
 137
 138 /* macros to expend register list macro defined in HW object header file
 139  * end *********************/
 140
 141
 142 static const struct dce_dmcu_registers dmcu_regs = {
 143                 DMCU_DCN10_REG_LIST()
 144 };
 145
 146 static const struct dce_dmcu_shift dmcu_shift = {
 147                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 148 };
 149
 150 static const struct dce_dmcu_mask dmcu_mask = {
 151                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 152 };
 153
 154 static const struct dce_abm_registers abm_regs = {
 155                 ABM_DCN10_REG_LIST(0)
 156 };
 157
 158 static const struct dce_abm_shift abm_shift = {
 159                 ABM_MASK_SH_LIST_DCN10(__SHIFT)
 160 };
 161
 162 static const struct dce_abm_mask abm_mask = {
 163                 ABM_MASK_SH_LIST_DCN10(_MASK)
 164 };
 165
 166 #define stream_enc_regs(id)\
 167 [id] = {\
 168         SE_DCN_REG_LIST(id),\
 169         .TMDS_CNTL = 0,\
 170         .AFMT_AVI_INFO0 = 0,\
 171         .AFMT_AVI_INFO1 = 0,\
 172         .AFMT_AVI_INFO2 = 0,\
 173         .AFMT_AVI_INFO3 = 0,\
 174 }
 175
 176 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 177         stream_enc_regs(0),
 178         stream_enc_regs(1),
 179         stream_enc_regs(2),
 180         stream_enc_regs(3),
 181 };
 182
 183 static const struct dce_stream_encoder_shift se_shift = {
 184                 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
 185 };
 186
 187 static const struct dce_stream_encoder_mask se_mask = {
 188                 SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
 189                 .AFMT_GENERIC0_UPDATE = 0,
 190                 .AFMT_GENERIC2_UPDATE = 0,
 191                 .DP_DYN_RANGE = 0,
 192                 .DP_YCBCR_RANGE = 0,
 193                 .HDMI_AVI_INFO_SEND = 0,
 194                 .HDMI_AVI_INFO_CONT = 0,
 195                 .HDMI_AVI_INFO_LINE = 0,
 196                 .DP_SEC_AVI_ENABLE = 0,
 197                 .AFMT_AVI_INFO_VERSION = 0
 198 };
 199
 200 #define audio_regs(id)\
 201 [id] = {\
 202                 AUD_COMMON_REG_LIST(id)\
 203 }
 204
 205 static const struct dce_audio_registers audio_regs[] = {
 206         audio_regs(0),
 207         audio_regs(1),
 208         audio_regs(2),
 209         audio_regs(3),
 210 };
 211
 212 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 213                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 214                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 215                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 216
 217 static const struct dce_audio_shift audio_shift = {
 218                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 219 };
 220
 221 static const struct dce_aduio_mask audio_mask = {
 222                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 223 };
 224
 225 #define aux_regs(id)\
 226 [id] = {\
 227         AUX_REG_LIST(id)\
 228 }
 229
 230 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 231                 aux_regs(0),
 232                 aux_regs(1),
 233                 aux_regs(2),
 234                 aux_regs(3),
 235                 aux_regs(4),
 236                 aux_regs(5)
 237 };
 238
 239 #define hpd_regs(id)\
 240 [id] = {\
 241         HPD_REG_LIST(id)\
 242 }
 243
 244 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 245                 hpd_regs(0),
 246                 hpd_regs(1),
 247                 hpd_regs(2),
 248                 hpd_regs(3),
 249                 hpd_regs(4),
 250                 hpd_regs(5)
 251 };
 252
 253 #define link_regs(id)\
 254 [id] = {\
 255         LE_DCN10_REG_LIST(id), \
 256         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 257 }
 258
 259 static const struct dce110_link_enc_registers link_enc_regs[] = {
 260         link_regs(0),
 261         link_regs(1),
 262         link_regs(2),
 263         link_regs(3),
 264         link_regs(4),
 265         link_regs(5),
 266         link_regs(6),
 267 };
 268
 269 #define ipp_regs(id)\
 270 [id] = {\
 271         IPP_REG_LIST_DCN10(id),\
 272 }
 273
 274 static const struct dcn10_ipp_registers ipp_regs[] = {
 275         ipp_regs(0),
 276         ipp_regs(1),
 277         ipp_regs(2),
 278         ipp_regs(3),
 279 };
 280
 281 static const struct dcn10_ipp_shift ipp_shift = {
 282                 IPP_MASK_SH_LIST_DCN10(__SHIFT)
 283 };
 284
 285 static const struct dcn10_ipp_mask ipp_mask = {
 286                 IPP_MASK_SH_LIST_DCN10(_MASK),
 287 };
 288
 289 #define opp_regs(id)\
 290 [id] = {\
 291         OPP_REG_LIST_DCN10(id),\
 292 }
 293
 294 static const struct dcn10_opp_registers opp_regs[] = {
 295         opp_regs(0),
 296         opp_regs(1),
 297         opp_regs(2),
 298         opp_regs(3),
 299 };
 300
 301 static const struct dcn10_opp_shift opp_shift = {
 302                 OPP_MASK_SH_LIST_DCN10(__SHIFT)
 303 };
 304
 305 static const struct dcn10_opp_mask opp_mask = {
 306                 OPP_MASK_SH_LIST_DCN10(_MASK),
 307 };
 308
 309 #define tf_regs(id)\
 310 [id] = {\
 311         TF_REG_LIST_DCN10(id),\
 312 }
 313
 314 static const struct dcn_dpp_registers tf_regs[] = {
 315         tf_regs(0),
 316         tf_regs(1),
 317         tf_regs(2),
 318         tf_regs(3),
 319 };
 320
 321 static const struct dcn_dpp_shift tf_shift = {
 322         TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
 323 };
 324
 325 static const struct dcn_dpp_mask tf_mask = {
 326         TF_REG_LIST_SH_MASK_DCN10(_MASK),
 327 };
 328
 329 static const struct dcn_mpc_registers mpc_regs = {
 330                 MPC_COMMON_REG_LIST_DCN1_0(0),
 331                 MPC_COMMON_REG_LIST_DCN1_0(1),
 332                 MPC_COMMON_REG_LIST_DCN1_0(2),
 333                 MPC_COMMON_REG_LIST_DCN1_0(3),
 334                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
 335                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
 336                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
 337                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
 338 };
 339
 340 static const struct dcn_mpc_shift mpc_shift = {
 341         MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 342 };
 343
 344 static const struct dcn_mpc_mask mpc_mask = {
 345         MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
 346 };
 347
 348 #define tg_regs(id)\
 349 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
 350
 351 static const struct dcn_optc_registers tg_regs[] = {
 352         tg_regs(0),
 353         tg_regs(1),
 354         tg_regs(2),
 355         tg_regs(3),
 356 };
 357
 358 static const struct dcn_optc_shift tg_shift = {
 359         TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 360 };
 361
 362 static const struct dcn_optc_mask tg_mask = {
 363         TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 364 };
 365
 366
 367 static const struct bios_registers bios_regs = {
 368                 NBIO_SR(BIOS_SCRATCH_6)
 369 };
 370
 371 #define hubp_regs(id)\
 372 [id] = {\
 373         HUBP_REG_LIST_DCN10(id)\
 374 }
 375
 376
 377 static const struct dcn_mi_registers hubp_regs[] = {
 378         hubp_regs(0),
 379         hubp_regs(1),
 380         hubp_regs(2),
 381         hubp_regs(3),
 382 };
 383
 384 static const struct dcn_mi_shift hubp_shift = {
 385                 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
 386 };
 387
 388 static const struct dcn_mi_mask hubp_mask = {
 389                 HUBP_MASK_SH_LIST_DCN10(_MASK)
 390 };
 391
 392
 393 static const struct dcn_hubbub_registers hubbub_reg = {
 394                 HUBBUB_REG_LIST_DCN10(0)
 395 };
 396
 397 static const struct dcn_hubbub_shift hubbub_shift = {
 398                 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
 399 };
 400
 401 static const struct dcn_hubbub_mask hubbub_mask = {
 402                 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
 403 };
 404
 405 #define clk_src_regs(index, pllid)\
 406 [index] = {\
 407         CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
 408 }
 409
 410 static const struct dce110_clk_src_regs clk_src_regs[] = {
 411         clk_src_regs(0, A),
 412         clk_src_regs(1, B),
 413         clk_src_regs(2, C),
 414         clk_src_regs(3, D)
 415 };
 416
 417 static const struct dce110_clk_src_shift cs_shift = {
 418                 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 419 };
 420
 421 static const struct dce110_clk_src_mask cs_mask = {
 422                 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 423 };
 424
 425
 426 static const struct resource_caps res_cap = {
 427                 .num_timing_generator = 4,
 428                 .num_video_plane = 4,
 429                 .num_audio = 4,
 430                 .num_stream_encoder = 4,
 431                 .num_pll = 4,
 432 };
 433
 434 static const struct dc_debug debug_defaults_drv = {
 435                 .sanity_checks = true,
 436                 .disable_dmcu = true,
 437                 .force_abm_enable = false,
 438                 .timing_trace = false,
 439                 .clock_trace = true,
 440
 441                 .min_disp_clk_khz = 300000,
 442
 443                 .disable_pplib_clock_request = true,
 444                 .disable_pplib_wm_range = false,
 445                 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
 446                 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 447                 .force_single_disp_pipe_split = true,
 448                 .disable_dcc = DCC_ENABLE,
 449                 .voltage_align_fclk = true,
 450                 .disable_stereo_support = true,
 451                 .vsr_support = true,
 452                 .performance_trace = false,
 453 };
 454
 455 static const struct dc_debug debug_defaults_diags = {
 456                 .disable_dmcu = true,
 457                 .force_abm_enable = false,
 458                 .timing_trace = true,
 459                 .clock_trace = true,
 460                 .disable_stutter = true,
 461                 .disable_pplib_clock_request = true,
 462                 .disable_pplib_wm_range = true
 463 };
 464
 465 static void dcn10_dpp_destroy(struct dpp **dpp)
 466 {
 467         kfree(TO_DCN10_DPP(*dpp));
 468         *dpp = NULL;
 469 }
 470
 471 static struct dpp *dcn10_dpp_create(
 472         struct dc_context *ctx,
 473         uint32_t inst)
 474 {
 475         struct dcn10_dpp *dpp =
 476                 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
 477
 478         if (!dpp)
 479                 return NULL;
 480
 481         dpp1_construct(dpp, ctx, inst,
 482                        &tf_regs[inst], &tf_shift, &tf_mask);
 483         return &dpp->base;
 484 }
 485
 486 static struct input_pixel_processor *dcn10_ipp_create(
 487         struct dc_context *ctx, uint32_t inst)
 488 {
 489         struct dcn10_ipp *ipp =
 490                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 491
 492         if (!ipp) {
 493                 BREAK_TO_DEBUGGER();
 494                 return NULL;
 495         }
 496
 497         dcn10_ipp_construct(ipp, ctx, inst,
 498                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 499         return &ipp->base;
 500 }
 501
 502
 503 static struct output_pixel_processor *dcn10_opp_create(
 504         struct dc_context *ctx, uint32_t inst)
 505 {
 506         struct dcn10_opp *opp =
 507                 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
 508
 509         if (!opp) {
 510                 BREAK_TO_DEBUGGER();
 511                 return NULL;
 512         }
 513
 514         dcn10_opp_construct(opp, ctx, inst,
 515                         &opp_regs[inst], &opp_shift, &opp_mask);
 516         return &opp->base;
 517 }
 518
 519 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
 520 {
 521         struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
 522                                           GFP_KERNEL);
 523
 524         if (!mpc10)
 525                 return NULL;
 526
 527         dcn10_mpc_construct(mpc10, ctx,
 528                         &mpc_regs,
 529                         &mpc_shift,
 530                         &mpc_mask,
 531                         4);
 532
 533         return &mpc10->base;
 534 }
 535
 536 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
 537 {
 538         struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
 539                                           GFP_KERNEL);
 540
 541         if (!hubbub)
 542                 return NULL;
 543
 544         hubbub1_construct(hubbub, ctx,
 545                         &hubbub_reg,
 546                         &hubbub_shift,
 547                         &hubbub_mask);
 548
 549         return hubbub;
 550 }
 551
 552 static struct timing_generator *dcn10_timing_generator_create(
 553                 struct dc_context *ctx,
 554                 uint32_t instance)
 555 {
 556         struct optc *tgn10 =
 557                 kzalloc(sizeof(struct optc), GFP_KERNEL);
 558
 559         if (!tgn10)
 560                 return NULL;
 561
 562         tgn10->base.inst = instance;
 563         tgn10->base.ctx = ctx;
 564
 565         tgn10->tg_regs = &tg_regs[instance];
 566         tgn10->tg_shift = &tg_shift;
 567         tgn10->tg_mask = &tg_mask;
 568
 569         dcn10_timing_generator_init(tgn10);
 570
 571         return &tgn10->base;
 572 }
 573
 574 static const struct encoder_feature_support link_enc_feature = {
 575                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 576                 .max_hdmi_pixel_clock = 600000,
 577                 .ycbcr420_supported = true,
 578                 .flags.bits.IS_HBR2_CAPABLE = true,
 579                 .flags.bits.IS_HBR3_CAPABLE = true,
 580                 .flags.bits.IS_TPS3_CAPABLE = true,
 581                 .flags.bits.IS_TPS4_CAPABLE = true,
 582                 .flags.bits.IS_YCBCR_CAPABLE = true
 583 };
 584
 585 struct link_encoder *dcn10_link_encoder_create(
 586         const struct encoder_init_data *enc_init_data)
 587 {
 588         struct dce110_link_encoder *enc110 =
 589                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 590
 591         if (!enc110)
 592                 return NULL;
 593
 594         dce110_link_encoder_construct(enc110,
 595                                       enc_init_data,
 596                                       &link_enc_feature,
 597                                       &link_enc_regs[enc_init_data->transmitter],
 598                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 599                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 600
 601         return &enc110->base;
 602 }
 603
 604 struct clock_source *dcn10_clock_source_create(
 605         struct dc_context *ctx,
 606         struct dc_bios *bios,
 607         enum clock_source_id id,
 608         const struct dce110_clk_src_regs *regs,
 609         bool dp_clk_src)
 610 {
 611         struct dce110_clk_src *clk_src =
 612                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 613
 614         if (!clk_src)
 615                 return NULL;
 616
 617         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 618                         regs, &cs_shift, &cs_mask)) {
 619                 clk_src->base.dp_clk_src = dp_clk_src;
 620                 return &clk_src->base;
 621         }
 622
 623         BREAK_TO_DEBUGGER();
 624         return NULL;
 625 }
 626
 627 static void read_dce_straps(
 628         struct dc_context *ctx,
 629         struct resource_straps *straps)
 630 {
 631         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 632                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 633 }
 634
 635 static struct audio *create_audio(
 636                 struct dc_context *ctx, unsigned int inst)
 637 {
 638         return dce_audio_create(ctx, inst,
 639                         &audio_regs[inst], &audio_shift, &audio_mask);
 640 }
 641
 642 static struct stream_encoder *dcn10_stream_encoder_create(
 643         enum engine_id eng_id,
 644         struct dc_context *ctx)
 645 {
 646         struct dce110_stream_encoder *enc110 =
 647                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 648
 649         if (!enc110)
 650                 return NULL;
 651
 652         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 653                                         &stream_enc_regs[eng_id],
 654                                         &se_shift, &se_mask);
 655         return &enc110->base;
 656 }
 657
 658 static const struct dce_hwseq_registers hwseq_reg = {
 659                 HWSEQ_DCN1_REG_LIST()
 660 };
 661
 662 static const struct dce_hwseq_shift hwseq_shift = {
 663                 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
 664 };
 665
 666 static const struct dce_hwseq_mask hwseq_mask = {
 667                 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
 668 };
 669
 670 static struct dce_hwseq *dcn10_hwseq_create(
 671         struct dc_context *ctx)
 672 {
 673         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 674
 675         if (hws) {
 676                 hws->ctx = ctx;
 677                 hws->regs = &hwseq_reg;
 678                 hws->shifts = &hwseq_shift;
 679                 hws->masks = &hwseq_mask;
 680                 hws->wa.DEGVIDCN10_253 = true;
 681                 hws->wa.false_optc_underflow = true;
 682         }
 683         return hws;
 684 }
 685
 686 static const struct resource_create_funcs res_create_funcs = {
 687         .read_dce_straps = read_dce_straps,
 688         .create_audio = create_audio,
 689         .create_stream_encoder = dcn10_stream_encoder_create,
 690         .create_hwseq = dcn10_hwseq_create,
 691 };
 692
 693 static const struct resource_create_funcs res_create_maximus_funcs = {
 694         .read_dce_straps = NULL,
 695         .create_audio = NULL,
 696         .create_stream_encoder = NULL,
 697         .create_hwseq = dcn10_hwseq_create,
 698 };
 699
 700 void dcn10_clock_source_destroy(struct clock_source **clk_src)
 701 {
 702         kfree(TO_DCE110_CLK_SRC(*clk_src));
 703         *clk_src = NULL;
 704 }
 705
 706 static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx)
 707 {
 708         struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
 709
 710         if (!pp_smu)
 711                 return pp_smu;
 712
 713         dm_pp_get_funcs_rv(ctx, pp_smu);
 714         return pp_smu;
 715 }
 716
 717 static void destruct(struct dcn10_resource_pool *pool)
 718 {
 719         unsigned int i;
 720
 721         for (i = 0; i < pool->base.stream_enc_count; i++) {
 722                 if (pool->base.stream_enc[i] != NULL) {
 723                         /* TODO: free dcn version of stream encoder once implemented
 724                          * rather than using virtual stream encoder
 725                          */
 726                         kfree(pool->base.stream_enc[i]);
 727                         pool->base.stream_enc[i] = NULL;
 728                 }
 729         }
 730
 731         if (pool->base.mpc != NULL) {
 732                 kfree(TO_DCN10_MPC(pool->base.mpc));
 733                 pool->base.mpc = NULL;
 734         }
 735
 736         if (pool->base.hubbub != NULL) {
 737                 kfree(pool->base.hubbub);
 738                 pool->base.hubbub = NULL;
 739         }
 740
 741         for (i = 0; i < pool->base.pipe_count; i++) {
 742                 if (pool->base.opps[i] != NULL)
 743                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 744
 745                 if (pool->base.dpps[i] != NULL)
 746                         dcn10_dpp_destroy(&pool->base.dpps[i]);
 747
 748                 if (pool->base.ipps[i] != NULL)
 749                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 750
 751                 if (pool->base.hubps[i] != NULL) {
 752                         kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
 753                         pool->base.hubps[i] = NULL;
 754                 }
 755
 756                 if (pool->base.irqs != NULL) {
 757                         dal_irq_service_destroy(&pool->base.irqs);
 758                 }
 759
 760                 if (pool->base.timing_generators[i] != NULL)    {
 761                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 762                         pool->base.timing_generators[i] = NULL;
 763                 }
 764         }
 765
 766         for (i = 0; i < pool->base.stream_enc_count; i++)
 767                 kfree(pool->base.stream_enc[i]);
 768
 769         for (i = 0; i < pool->base.audio_count; i++) {
 770                 if (pool->base.audios[i])
 771                         dce_aud_destroy(&pool->base.audios[i]);
 772         }
 773
 774         for (i = 0; i < pool->base.clk_src_count; i++) {
 775                 if (pool->base.clock_sources[i] != NULL) {
 776                         dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
 777                         pool->base.clock_sources[i] = NULL;
 778                 }
 779         }
 780
 781         if (pool->base.dp_clock_source != NULL) {
 782                 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
 783                 pool->base.dp_clock_source = NULL;
 784         }
 785
 786         if (pool->base.abm != NULL)
 787                 dce_abm_destroy(&pool->base.abm);
 788
 789         if (pool->base.dmcu != NULL)
 790                 dce_dmcu_destroy(&pool->base.dmcu);
 791
 792         if (pool->base.display_clock != NULL)
 793                 dce_disp_clk_destroy(&pool->base.display_clock);
 794
 795         kfree(pool->base.pp_smu);
 796 }
 797
 798 static struct hubp *dcn10_hubp_create(
 799         struct dc_context *ctx,
 800         uint32_t inst)
 801 {
 802         struct dcn10_hubp *hubp1 =
 803                 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
 804
 805         if (!hubp1)
 806                 return NULL;
 807
 808         dcn10_hubp_construct(hubp1, ctx, inst,
 809                              &hubp_regs[inst], &hubp_shift, &hubp_mask);
 810         return &hubp1->base;
 811 }
 812
 813 static void get_pixel_clock_parameters(
 814         const struct pipe_ctx *pipe_ctx,
 815         struct pixel_clk_params *pixel_clk_params)
 816 {
 817         const struct dc_stream_state *stream = pipe_ctx->stream;
 818         pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
 819         pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
 820         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
 821         pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
 822         /* TODO: un-hardcode*/
 823         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
 824                 LINK_RATE_REF_FREQ_IN_KHZ;
 825         pixel_clk_params->flags.ENABLE_SS = 0;
 826         pixel_clk_params->color_depth =
 827                 stream->timing.display_color_depth;
 828         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
 829         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
 830
 831         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 832                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
 833
 834         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
 835                 pixel_clk_params->requested_pix_clk  /= 2;
 836
 837 }
 838
 839 static void build_clamping_params(struct dc_stream_state *stream)
 840 {
 841         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
 842         stream->clamping.c_depth = stream->timing.display_color_depth;
 843         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
 844 }
 845
 846 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
 847 {
 848
 849         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
 850
 851         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
 852                 pipe_ctx->clock_source,
 853                 &pipe_ctx->stream_res.pix_clk_params,
 854                 &pipe_ctx->pll_settings);
 855
 856         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 857
 858         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
 859                                         &pipe_ctx->stream->bit_depth_params);
 860         build_clamping_params(pipe_ctx->stream);
 861 }
 862
 863 static enum dc_status build_mapped_resource(
 864                 const struct dc *dc,
 865                 struct dc_state *context,
 866                 struct dc_stream_state *stream)
 867 {
 868         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 869
 870         /*TODO Seems unneeded anymore */
 871         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
 872                         if (stream != NULL && old_context->streams[i] != NULL) {
 873                                  todo: shouldn't have to copy missing parameter here
 874                                 resource_build_bit_depth_reduction_params(stream,
 875                                                 &stream->bit_depth_params);
 876                                 stream->clamping.pixel_encoding =
 877                                                 stream->timing.pixel_encoding;
 878
 879                                 resource_build_bit_depth_reduction_params(stream,
 880                                                                 &stream->bit_depth_params);
 881                                 build_clamping_params(stream);
 882
 883                                 continue;
 884                         }
 885                 }
 886         */
 887
 888         if (!pipe_ctx)
 889                 return DC_ERROR_UNEXPECTED;
 890
 891         build_pipe_hw_param(pipe_ctx);
 892         return DC_OK;
 893 }
 894
 895 enum dc_status dcn10_add_stream_to_ctx(
 896                 struct dc *dc,
 897                 struct dc_state *new_ctx,
 898                 struct dc_stream_state *dc_stream)
 899 {
 900         enum dc_status result = DC_ERROR_UNEXPECTED;
 901
 902         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
 903
 904         if (result == DC_OK)
 905                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
 906
 907
 908         if (result == DC_OK)
 909                 result = build_mapped_resource(dc, new_ctx, dc_stream);
 910
 911         return result;
 912 }
 913
 914 enum dc_status dcn10_validate_guaranteed(
 915                 struct dc *dc,
 916                 struct dc_stream_state *dc_stream,
 917                 struct dc_state *context)
 918 {
 919         enum dc_status result = DC_ERROR_UNEXPECTED;
 920
 921         context->streams[0] = dc_stream;
 922         dc_stream_retain(context->streams[0]);
 923         context->stream_count++;
 924
 925         result = resource_map_pool_resources(dc, context, dc_stream);
 926
 927         if (result == DC_OK)
 928                 result = resource_map_phy_clock_resources(dc, context, dc_stream);
 929
 930         if (result == DC_OK)
 931                 result = build_mapped_resource(dc, context, dc_stream);
 932
 933         if (result == DC_OK) {
 934                 validate_guaranteed_copy_streams(
 935                                 context, dc->caps.max_streams);
 936                 result = resource_build_scaling_params_for_context(dc, context);
 937         }
 938         if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
 939                 return DC_FAIL_BANDWIDTH_VALIDATE;
 940
 941         return result;
 942 }
 943
 944 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
 945                 struct dc_state *context,
 946                 const struct resource_pool *pool,
 947                 struct dc_stream_state *stream)
 948 {
 949         struct resource_context *res_ctx = &context->res_ctx;
 950         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
 951         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
 952
 953         if (!head_pipe) {
 954                 ASSERT(0);
 955                 return NULL;
 956         }
 957
 958         if (!idle_pipe)
 959                 return NULL;
 960
 961         idle_pipe->stream = head_pipe->stream;
 962         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
 963         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
 964
 965         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
 966         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
 967         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
 968
 969         return idle_pipe;
 970 }
 971
 972 enum dcc_control {
 973         dcc_control__256_256_xxx,
 974         dcc_control__128_128_xxx,
 975         dcc_control__256_64_64,
 976 };
 977
 978 enum segment_order {
 979         segment_order__na,
 980         segment_order__contiguous,
 981         segment_order__non_contiguous,
 982 };
 983
 984 static bool dcc_support_pixel_format(
 985                 enum surface_pixel_format format,
 986                 unsigned int *bytes_per_element)
 987 {
 988         /* DML: get_bytes_per_element */
 989         switch (format) {
 990         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 991         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 992                 *bytes_per_element = 2;
 993                 return true;
 994         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 995         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 996         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 997         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 998                 *bytes_per_element = 4;
 999                 return true;
1000         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1001         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1002         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1003                 *bytes_per_element = 8;
1004                 return true;
1005         default:
1006                 return false;
1007         }
1008 }
1009
1010 static bool dcc_support_swizzle(
1011                 enum swizzle_mode_values swizzle,
1012                 unsigned int bytes_per_element,
1013                 enum segment_order *segment_order_horz,
1014                 enum segment_order *segment_order_vert)
1015 {
1016         bool standard_swizzle = false;
1017         bool display_swizzle = false;
1018
1019         switch (swizzle) {
1020         case DC_SW_4KB_S:
1021         case DC_SW_64KB_S:
1022         case DC_SW_VAR_S:
1023         case DC_SW_4KB_S_X:
1024         case DC_SW_64KB_S_X:
1025         case DC_SW_VAR_S_X:
1026                 standard_swizzle = true;
1027                 break;
1028         case DC_SW_4KB_D:
1029         case DC_SW_64KB_D:
1030         case DC_SW_VAR_D:
1031         case DC_SW_4KB_D_X:
1032         case DC_SW_64KB_D_X:
1033         case DC_SW_VAR_D_X:
1034                 display_swizzle = true;
1035                 break;
1036         default:
1037                 break;
1038         }
1039
1040         if (bytes_per_element == 1 && standard_swizzle) {
1041                 *segment_order_horz = segment_order__contiguous;
1042                 *segment_order_vert = segment_order__na;
1043                 return true;
1044         }
1045         if (bytes_per_element == 2 && standard_swizzle) {
1046                 *segment_order_horz = segment_order__non_contiguous;
1047                 *segment_order_vert = segment_order__contiguous;
1048                 return true;
1049         }
1050         if (bytes_per_element == 4 && standard_swizzle) {
1051                 *segment_order_horz = segment_order__non_contiguous;
1052                 *segment_order_vert = segment_order__contiguous;
1053                 return true;
1054         }
1055         if (bytes_per_element == 8 && standard_swizzle) {
1056                 *segment_order_horz = segment_order__na;
1057                 *segment_order_vert = segment_order__contiguous;
1058                 return true;
1059         }
1060         if (bytes_per_element == 8 && display_swizzle) {
1061                 *segment_order_horz = segment_order__contiguous;
1062                 *segment_order_vert = segment_order__non_contiguous;
1063                 return true;
1064         }
1065
1066         return false;
1067 }
1068
1069 static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
1070                 unsigned int bytes_per_element)
1071 {
1072         /* copied from DML.  might want to refactor DML to leverage from DML */
1073         /* DML : get_blk256_size */
1074         if (bytes_per_element == 1) {
1075                 *blk256_width = 16;
1076                 *blk256_height = 16;
1077         } else if (bytes_per_element == 2) {
1078                 *blk256_width = 16;
1079                 *blk256_height = 8;
1080         } else if (bytes_per_element == 4) {
1081                 *blk256_width = 8;
1082                 *blk256_height = 8;
1083         } else if (bytes_per_element == 8) {
1084                 *blk256_width = 8;
1085                 *blk256_height = 4;
1086         }
1087 }
1088
1089 static void det_request_size(
1090                 unsigned int height,
1091                 unsigned int width,
1092                 unsigned int bpe,
1093                 bool *req128_horz_wc,
1094                 bool *req128_vert_wc)
1095 {
1096         unsigned int detile_buf_size = 164 * 1024;  /* 164KB for DCN1.0 */
1097
1098         unsigned int blk256_height = 0;
1099         unsigned int blk256_width = 0;
1100         unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
1101
1102         get_blk256_size(&blk256_width, &blk256_height, bpe);
1103
1104         swath_bytes_horz_wc = height * blk256_height * bpe;
1105         swath_bytes_vert_wc = width * blk256_width * bpe;
1106
1107         *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
1108                         false : /* full 256B request */
1109                         true; /* half 128b request */
1110
1111         *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
1112                         false : /* full 256B request */
1113                         true; /* half 128b request */
1114 }
1115
1116 static bool get_dcc_compression_cap(const struct dc *dc,
1117                 const struct dc_dcc_surface_param *input,
1118                 struct dc_surface_dcc_cap *output)
1119 {
1120         /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
1121         enum dcc_control dcc_control;
1122         unsigned int bpe;
1123         enum segment_order segment_order_horz, segment_order_vert;
1124         bool req128_horz_wc, req128_vert_wc;
1125
1126         memset(output, 0, sizeof(*output));
1127
1128         if (dc->debug.disable_dcc == DCC_DISABLE)
1129                 return false;
1130
1131         if (!dcc_support_pixel_format(input->format,
1132                         &bpe))
1133                 return false;
1134
1135         if (!dcc_support_swizzle(input->swizzle_mode, bpe,
1136                         &segment_order_horz, &segment_order_vert))
1137                 return false;
1138
1139         det_request_size(input->surface_size.height,  input->surface_size.width,
1140                         bpe, &req128_horz_wc, &req128_vert_wc);
1141
1142         if (!req128_horz_wc && !req128_vert_wc) {
1143                 dcc_control = dcc_control__256_256_xxx;
1144         } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
1145                 if (!req128_horz_wc)
1146                         dcc_control = dcc_control__256_256_xxx;
1147                 else if (segment_order_horz == segment_order__contiguous)
1148                         dcc_control = dcc_control__128_128_xxx;
1149                 else
1150                         dcc_control = dcc_control__256_64_64;
1151         } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
1152                 if (!req128_vert_wc)
1153                         dcc_control = dcc_control__256_256_xxx;
1154                 else if (segment_order_vert == segment_order__contiguous)
1155                         dcc_control = dcc_control__128_128_xxx;
1156                 else
1157                         dcc_control = dcc_control__256_64_64;
1158         } else {
1159                 if ((req128_horz_wc &&
1160                         segment_order_horz == segment_order__non_contiguous) ||
1161                         (req128_vert_wc &&
1162                         segment_order_vert == segment_order__non_contiguous))
1163                         /* access_dir not known, must use most constraining */
1164                         dcc_control = dcc_control__256_64_64;
1165                 else
1166                         /* reg128 is true for either horz and vert
1167                          * but segment_order is contiguous
1168                          */
1169                         dcc_control = dcc_control__128_128_xxx;
1170         }
1171
1172         if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
1173                 dcc_control != dcc_control__256_256_xxx)
1174                 return false;
1175
1176         switch (dcc_control) {
1177         case dcc_control__256_256_xxx:
1178                 output->grph.rgb.max_uncompressed_blk_size = 256;
1179                 output->grph.rgb.max_compressed_blk_size = 256;
1180                 output->grph.rgb.independent_64b_blks = false;
1181                 break;
1182         case dcc_control__128_128_xxx:
1183                 output->grph.rgb.max_uncompressed_blk_size = 128;
1184                 output->grph.rgb.max_compressed_blk_size = 128;
1185                 output->grph.rgb.independent_64b_blks = false;
1186                 break;
1187         case dcc_control__256_64_64:
1188                 output->grph.rgb.max_uncompressed_blk_size = 256;
1189                 output->grph.rgb.max_compressed_blk_size = 64;
1190                 output->grph.rgb.independent_64b_blks = true;
1191                 break;
1192         }
1193
1194         output->capable = true;
1195         output->const_color_support = false;
1196
1197         return true;
1198 }
1199
1200
1201 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1202 {
1203         struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1204
1205         destruct(dcn10_pool);
1206         kfree(dcn10_pool);
1207         *pool = NULL;
1208 }
1209
1210 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1211 {
1212         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1213                         && caps->max_video_width != 0
1214                         && plane_state->src_rect.width > caps->max_video_width)
1215                 return DC_FAIL_SURFACE_VALIDATE;
1216
1217         return DC_OK;
1218 }
1219
1220 static struct dc_cap_funcs cap_funcs = {
1221         .get_dcc_compression_cap = get_dcc_compression_cap
1222 };
1223
1224 static struct resource_funcs dcn10_res_pool_funcs = {
1225         .destroy = dcn10_destroy_resource_pool,
1226         .link_enc_create = dcn10_link_encoder_create,
1227         .validate_guaranteed = dcn10_validate_guaranteed,
1228         .validate_bandwidth = dcn_validate_bandwidth,
1229         .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1230         .validate_plane = dcn10_validate_plane,
1231         .add_stream_to_ctx = dcn10_add_stream_to_ctx
1232 };
1233
1234 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1235 {
1236         uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1237         /* RV1 support max 4 pipes */
1238         value = value & 0xf;
1239         return value;
1240 }
1241
1242 static bool construct(
1243         uint8_t num_virtual_links,
1244         struct dc *dc,
1245         struct dcn10_resource_pool *pool)
1246 {
1247         int i;
1248         int j;
1249         struct dc_context *ctx = dc->ctx;
1250         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1251
1252         ctx->dc_bios->regs = &bios_regs;
1253
1254         pool->base.res_cap = &res_cap;
1255         pool->base.funcs = &dcn10_res_pool_funcs;
1256
1257         /*
1258          * TODO fill in from actual raven resource when we create
1259          * more than virtual encoder
1260          */
1261
1262         /*************************************************
1263          *  Resource + asic cap harcoding                *
1264          *************************************************/
1265         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1266
1267         /* max pipe num for ASIC before check pipe fuses */
1268         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1269
1270         dc->caps.max_video_width = 3840;
1271         dc->caps.max_downscale_ratio = 200;
1272         dc->caps.i2c_speed_in_khz = 100;
1273         dc->caps.max_cursor_size = 256;
1274         dc->caps.max_slave_planes = 1;
1275         dc->caps.is_apu = true;
1276
1277         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1278                 dc->debug = debug_defaults_drv;
1279         else
1280                 dc->debug = debug_defaults_diags;
1281
1282         /*************************************************
1283          *  Create resources                             *
1284          *************************************************/
1285
1286         pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1287                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1288                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1289                                 &clk_src_regs[0], false);
1290         pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1291                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1292                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1293                                 &clk_src_regs[1], false);
1294         pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1295                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1296                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1297                                 &clk_src_regs[2], false);
1298         pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1299                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1300                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1301                                 &clk_src_regs[3], false);
1302
1303         pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1304
1305         pool->base.dp_clock_source =
1306                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1307                                 CLOCK_SOURCE_ID_DP_DTO,
1308                                 /* todo: not reuse phy_pll registers */
1309                                 &clk_src_regs[0], true);
1310
1311         for (i = 0; i < pool->base.clk_src_count; i++) {
1312                 if (pool->base.clock_sources[i] == NULL) {
1313                         dm_error("DC: failed to create clock sources!\n");
1314                         BREAK_TO_DEBUGGER();
1315                         goto fail;
1316                 }
1317         }
1318
1319         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1320                 pool->base.display_clock = dce120_disp_clk_create(ctx);
1321                 if (pool->base.display_clock == NULL) {
1322                         dm_error("DC: failed to create display clock!\n");
1323                         BREAK_TO_DEBUGGER();
1324                         goto fail;
1325                 }
1326         }
1327
1328         pool->base.dmcu = dcn10_dmcu_create(ctx,
1329                         &dmcu_regs,
1330                         &dmcu_shift,
1331                         &dmcu_mask);
1332         if (pool->base.dmcu == NULL) {
1333                 dm_error("DC: failed to create dmcu!\n");
1334                 BREAK_TO_DEBUGGER();
1335                 goto fail;
1336         }
1337
1338         pool->base.abm = dce_abm_create(ctx,
1339                         &abm_regs,
1340                         &abm_shift,
1341                         &abm_mask);
1342         if (pool->base.abm == NULL) {
1343                 dm_error("DC: failed to create abm!\n");
1344                 BREAK_TO_DEBUGGER();
1345                 goto fail;
1346         }
1347
1348         dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
1349         memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1350         memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1351
1352         if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1353                 dc->dcn_soc->urgent_latency = 3;
1354                 dc->debug.disable_dmcu = true;
1355                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1356         }
1357
1358
1359         dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1360         ASSERT(dc->dcn_soc->number_of_channels < 3);
1361         if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
1362                 dc->dcn_soc->number_of_channels = 2;
1363
1364         if (dc->dcn_soc->number_of_channels == 1) {
1365                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
1366                 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
1367                 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
1368                 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1369                 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1370                         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1371                 }
1372         }
1373
1374         pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1375
1376         if (!dc->debug.disable_pplib_clock_request)
1377                 dcn_bw_update_from_pplib(dc);
1378         dcn_bw_sync_calcs_and_dml(dc);
1379         if (!dc->debug.disable_pplib_wm_range) {
1380                 dc->res_pool = &pool->base;
1381                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1382         }
1383
1384         {
1385                 struct irq_service_init_data init_data;
1386                 init_data.ctx = dc->ctx;
1387                 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1388                 if (!pool->base.irqs)
1389                         goto fail;
1390         }
1391
1392         /* index to valid pipe resource  */
1393         j = 0;
1394         /* mem input -> ipp -> dpp -> opp -> TG */
1395         for (i = 0; i < pool->base.pipe_count; i++) {
1396                 /* if pipe is disabled, skip instance of HW pipe,
1397                  * i.e, skip ASIC register instance
1398                  */
1399                 if ((pipe_fuses & (1 << i)) != 0)
1400                         continue;
1401
1402                 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1403                 if (pool->base.hubps[j] == NULL) {
1404                         BREAK_TO_DEBUGGER();
1405                         dm_error(
1406                                 "DC: failed to create memory input!\n");
1407                         goto fail;
1408                 }
1409
1410                 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1411                 if (pool->base.ipps[j] == NULL) {
1412                         BREAK_TO_DEBUGGER();
1413                         dm_error(
1414                                 "DC: failed to create input pixel processor!\n");
1415                         goto fail;
1416                 }
1417
1418                 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1419                 if (pool->base.dpps[j] == NULL) {
1420                         BREAK_TO_DEBUGGER();
1421                         dm_error(
1422                                 "DC: failed to create dpp!\n");
1423                         goto fail;
1424                 }
1425
1426                 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1427                 if (pool->base.opps[j] == NULL) {
1428                         BREAK_TO_DEBUGGER();
1429                         dm_error(
1430                                 "DC: failed to create output pixel processor!\n");
1431                         goto fail;
1432                 }
1433
1434                 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1435                                 ctx, i);
1436                 if (pool->base.timing_generators[j] == NULL) {
1437                         BREAK_TO_DEBUGGER();
1438                         dm_error("DC: failed to create tg!\n");
1439                         goto fail;
1440                 }
1441
1442                 /* check next valid pipe */
1443                 j++;
1444         }
1445
1446         /* valid pipe num */
1447         pool->base.pipe_count = j;
1448
1449         /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1450          * the value may be changed
1451          */
1452         dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1453         dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1454
1455         pool->base.mpc = dcn10_mpc_create(ctx);
1456         if (pool->base.mpc == NULL) {
1457                 BREAK_TO_DEBUGGER();
1458                 dm_error("DC: failed to create mpc!\n");
1459                 goto fail;
1460         }
1461
1462         pool->base.hubbub = dcn10_hubbub_create(ctx);
1463         if (pool->base.hubbub == NULL) {
1464                 BREAK_TO_DEBUGGER();
1465                 dm_error("DC: failed to create hubbub!\n");
1466                 goto fail;
1467         }
1468
1469         if (!resource_construct(num_virtual_links, dc, &pool->base,
1470                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1471                         &res_create_funcs : &res_create_maximus_funcs)))
1472                         goto fail;
1473
1474         dcn10_hw_sequencer_construct(dc);
1475         dc->caps.max_planes =  pool->base.pipe_count;
1476
1477         dc->cap_funcs = cap_funcs;
1478
1479         return true;
1480
1481 fail:
1482
1483         destruct(pool);
1484
1485         return false;
1486 }
1487
1488 struct resource_pool *dcn10_create_resource_pool(
1489                 uint8_t num_virtual_links,
1490                 struct dc *dc)
1491 {
1492         struct dcn10_resource_pool *pool =
1493                 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1494
1495         if (!pool)
1496                 return NULL;
1497
1498         if (construct(num_virtual_links, dc, pool))
1499                 return &pool->base;
1500
1501         BREAK_TO_DEBUGGER();
1502         return NULL;
1503 }