drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "reg_helper.h"
  28 #include "dcn10_optc.h"
  29 #include "dc.h"
  30
  31 #define REG(reg)\
  32         optc1->tg_regs->reg
  33
  34 #define CTX \
  35         optc1->base.ctx
  36
  37 #undef FN
  38 #define FN(reg_name, field_name) \
  39         optc1->tg_shift->field_name, optc1->tg_mask->field_name
  40
  41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
  42
  43 /**
  44 * apply_front_porch_workaround  TODO FPGA still need?
  45 *
  46 * This is a workaround for a bug that has existed since R5xx and has not been
  47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
  48 */
  49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
  50 {
  51         if (timing->flags.INTERLACE == 1) {
  52                 if (timing->v_front_porch < 2)
  53                         timing->v_front_porch = 2;
  54         } else {
  55                 if (timing->v_front_porch < 1)
  56                         timing->v_front_porch = 1;
  57         }
  58 }
  59
  60 void optc1_program_global_sync(
  61                 struct timing_generator *optc,
  62                 int vready_offset,
  63                 int vstartup_start,
  64                 int vupdate_offset,
  65                 int vupdate_width)
  66 {
  67         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  68
  69         optc1->vready_offset = vready_offset;
  70         optc1->vstartup_start = vstartup_start;
  71         optc1->vupdate_offset = vupdate_offset;
  72         optc1->vupdate_width = vupdate_width;
  73
  74         if (optc1->vstartup_start == 0) {
  75                 BREAK_TO_DEBUGGER();
  76                 return;
  77         }
  78
  79         REG_SET(OTG_VSTARTUP_PARAM, 0,
  80                 VSTARTUP_START, optc1->vstartup_start);
  81
  82         REG_SET_2(OTG_VUPDATE_PARAM, 0,
  83                         VUPDATE_OFFSET, optc1->vupdate_offset,
  84                         VUPDATE_WIDTH, optc1->vupdate_width);
  85
  86         REG_SET(OTG_VREADY_PARAM, 0,
  87                         VREADY_OFFSET, optc1->vready_offset);
  88 }
  89
  90 static void optc1_disable_stereo(struct timing_generator *optc)
  91 {
  92         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  93
  94         REG_SET(OTG_STEREO_CONTROL, 0,
  95                 OTG_STEREO_EN, 0);
  96
  97         REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
  98                 OTG_3D_STRUCTURE_EN, 0,
  99                 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
 100 }
 101
 102 void optc1_setup_vertical_interrupt0(
 103                 struct timing_generator *optc,
 104                 uint32_t start_line,
 105                 uint32_t end_line)
 106 {
 107         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 108
 109         REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
 110                         OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
 111                         OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
 112 }
 113
 114 void optc1_setup_vertical_interrupt1(
 115                 struct timing_generator *optc,
 116                 uint32_t start_line)
 117 {
 118         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 119
 120         REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
 121                                 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
 122 }
 123
 124 void optc1_setup_vertical_interrupt2(
 125                 struct timing_generator *optc,
 126                 uint32_t start_line)
 127 {
 128         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 129
 130         REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
 131                         OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
 132 }
 133
 134 /**
 135  * Vupdate keepout can be set to a window to block the update lock for that pipe from changing.
 136  * Start offset begins with vstartup and goes for x number of clocks,
 137  * end offset starts from end of vupdate to x number of clocks.
 138  */
 139 void optc1_set_vupdate_keepout(struct timing_generator *optc,
 140                                struct vupdate_keepout_params *params)
 141 {
 142         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 143
 144         REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
 145                   MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, params->start_offset,
 146                   MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, params->end_offset,
 147                   OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable);
 148 }
 149
 150 /**
 151  * program_timing_generator   used by mode timing set
 152  * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
 153  * Including SYNC. Call BIOS command table to program Timings.
 154  */
 155 void optc1_program_timing(
 156         struct timing_generator *optc,
 157         const struct dc_crtc_timing *dc_crtc_timing,
 158         int vready_offset,
 159         int vstartup_start,
 160         int vupdate_offset,
 161         int vupdate_width,
 162         const enum signal_type signal,
 163         bool use_vbios)
 164 {
 165         struct dc_crtc_timing patched_crtc_timing;
 166         uint32_t asic_blank_end;
 167         uint32_t asic_blank_start;
 168         uint32_t v_total;
 169         uint32_t v_sync_end;
 170         uint32_t h_sync_polarity, v_sync_polarity;
 171         uint32_t start_point = 0;
 172         uint32_t field_num = 0;
 173         enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
 174
 175         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 176
 177         optc1->signal = signal;
 178         optc1->vready_offset = vready_offset;
 179         optc1->vstartup_start = vstartup_start;
 180         optc1->vupdate_offset = vupdate_offset;
 181         optc1->vupdate_width = vupdate_width;
 182         patched_crtc_timing = *dc_crtc_timing;
 183         apply_front_porch_workaround(&patched_crtc_timing);
 184
 185         /* Load horizontal timing */
 186
 187         /* CRTC_H_TOTAL = vesa.h_total - 1 */
 188         REG_SET(OTG_H_TOTAL, 0,
 189                         OTG_H_TOTAL,  patched_crtc_timing.h_total - 1);
 190
 191         /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
 192         REG_UPDATE_2(OTG_H_SYNC_A,
 193                         OTG_H_SYNC_A_START, 0,
 194                         OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
 195
 196         /* blank_start = line end - front porch */
 197         asic_blank_start = patched_crtc_timing.h_total -
 198                         patched_crtc_timing.h_front_porch;
 199
 200         /* blank_end = blank_start - active */
 201         asic_blank_end = asic_blank_start -
 202                         patched_crtc_timing.h_border_right -
 203                         patched_crtc_timing.h_addressable -
 204                         patched_crtc_timing.h_border_left;
 205
 206         REG_UPDATE_2(OTG_H_BLANK_START_END,
 207                         OTG_H_BLANK_START, asic_blank_start,
 208                         OTG_H_BLANK_END, asic_blank_end);
 209
 210         /* h_sync polarity */
 211         h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
 212                         0 : 1;
 213
 214         REG_UPDATE(OTG_H_SYNC_A_CNTL,
 215                         OTG_H_SYNC_A_POL, h_sync_polarity);
 216
 217         v_total = patched_crtc_timing.v_total - 1;
 218
 219         REG_SET(OTG_V_TOTAL, 0,
 220                         OTG_V_TOTAL, v_total);
 221
 222         /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
 223          * OTG_V_TOTAL_MIN are equal to V_TOTAL.
 224          */
 225         REG_SET(OTG_V_TOTAL_MAX, 0,
 226                 OTG_V_TOTAL_MAX, v_total);
 227         REG_SET(OTG_V_TOTAL_MIN, 0,
 228                 OTG_V_TOTAL_MIN, v_total);
 229
 230         /* v_sync_start = 0, v_sync_end = v_sync_width */
 231         v_sync_end = patched_crtc_timing.v_sync_width;
 232
 233         REG_UPDATE_2(OTG_V_SYNC_A,
 234                         OTG_V_SYNC_A_START, 0,
 235                         OTG_V_SYNC_A_END, v_sync_end);
 236
 237         /* blank_start = frame end - front porch */
 238         asic_blank_start = patched_crtc_timing.v_total -
 239                         patched_crtc_timing.v_front_porch;
 240
 241         /* blank_end = blank_start - active */
 242         asic_blank_end = asic_blank_start -
 243                         patched_crtc_timing.v_border_bottom -
 244                         patched_crtc_timing.v_addressable -
 245                         patched_crtc_timing.v_border_top;
 246
 247         REG_UPDATE_2(OTG_V_BLANK_START_END,
 248                         OTG_V_BLANK_START, asic_blank_start,
 249                         OTG_V_BLANK_END, asic_blank_end);
 250
 251         /* v_sync polarity */
 252         v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
 253                         0 : 1;
 254
 255         REG_UPDATE(OTG_V_SYNC_A_CNTL,
 256                 OTG_V_SYNC_A_POL, v_sync_polarity);
 257
 258         if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
 259                         optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
 260                         optc1->signal == SIGNAL_TYPE_EDP) {
 261                 start_point = 1;
 262                 if (patched_crtc_timing.flags.INTERLACE == 1)
 263                         field_num = 1;
 264         }
 265
 266         /* Interlace */
 267         if (REG(OTG_INTERLACE_CONTROL)) {
 268                 if (patched_crtc_timing.flags.INTERLACE == 1)
 269                         REG_UPDATE(OTG_INTERLACE_CONTROL,
 270                                         OTG_INTERLACE_ENABLE, 1);
 271                 else
 272                         REG_UPDATE(OTG_INTERLACE_CONTROL,
 273                                         OTG_INTERLACE_ENABLE, 0);
 274         }
 275
 276         /* VTG enable set to 0 first VInit */
 277         REG_UPDATE(CONTROL,
 278                         VTG0_ENABLE, 0);
 279
 280         /* original code is using VTG offset to address OTG reg, seems wrong */
 281         REG_UPDATE_2(OTG_CONTROL,
 282                         OTG_START_POINT_CNTL, start_point,
 283                         OTG_FIELD_NUMBER_CNTL, field_num);
 284
 285         optc->funcs->program_global_sync(optc,
 286                         vready_offset,
 287                         vstartup_start,
 288                         vupdate_offset,
 289                         vupdate_width);
 290
 291         optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);
 292
 293         /* TODO
 294          * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
 295          * program_horz_count_by_2
 296          * for DVI 30bpp mode, 0 otherwise
 297          * program_horz_count_by_2(optc, &patched_crtc_timing);
 298          */
 299
 300         /* Enable stereo - only when we need to pack 3D frame. Other types
 301          * of stereo handled in explicit call
 302          */
 303
 304         if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
 305                 h_div = H_TIMING_DIV_BY2;
 306
 307         if (REG(OPTC_DATA_FORMAT_CONTROL)) {
 308                 uint32_t data_fmt = 0;
 309
 310                 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 311                         data_fmt = 1;
 312                 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
 313                         data_fmt = 2;
 314
 315                 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
 316         }
 317
 318         if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
 319                 if (optc1->opp_count == 4)
 320                         h_div = H_TIMING_DIV_BY4;
 321
 322                 REG_UPDATE(OTG_H_TIMING_CNTL,
 323                 OTG_H_TIMING_DIV_MODE, h_div);
 324         } else {
 325                 REG_UPDATE(OTG_H_TIMING_CNTL,
 326                 OTG_H_TIMING_DIV_BY2, h_div);
 327         }
 328 }
 329
 330 void optc1_set_vtg_params(struct timing_generator *optc,
 331                 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
 332 {
 333         struct dc_crtc_timing patched_crtc_timing;
 334         uint32_t asic_blank_end;
 335         uint32_t v_init;
 336         uint32_t v_fp2 = 0;
 337         int32_t vertical_line_start;
 338
 339         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 340
 341         patched_crtc_timing = *dc_crtc_timing;
 342         apply_front_porch_workaround(&patched_crtc_timing);
 343
 344         /* VCOUNT_INIT is the start of blank */
 345         v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
 346
 347         /* end of blank = v_init - active */
 348         asic_blank_end = v_init -
 349                         patched_crtc_timing.v_border_bottom -
 350                         patched_crtc_timing.v_addressable -
 351                         patched_crtc_timing.v_border_top;
 352
 353         /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
 354         vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
 355         if (vertical_line_start < 0)
 356                 v_fp2 = -vertical_line_start;
 357
 358         /* Interlace */
 359         if (REG(OTG_INTERLACE_CONTROL)) {
 360                 if (patched_crtc_timing.flags.INTERLACE == 1) {
 361                         v_init = v_init / 2;
 362                         if ((optc1->vstartup_start/2)*2 > asic_blank_end)
 363                                 v_fp2 = v_fp2 / 2;
 364                 }
 365         }
 366
 367         if (program_fp2)
 368                 REG_UPDATE_2(CONTROL,
 369                                 VTG0_FP2, v_fp2,
 370                                 VTG0_VCOUNT_INIT, v_init);
 371         else
 372                 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);
 373 }
 374
 375 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
 376 {
 377         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 378
 379         uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
 380
 381         REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
 382                         OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
 383 }
 384
 385 /**
 386  * optc1_set_timing_double_buffer() - DRR double buffering control
 387  *
 388  * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
 389  * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
 390  *
 391  * Options: any time,  start of frame, dp start of frame (range timing)
 392  */
 393 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
 394 {
 395         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 396         uint32_t mode = enable ? 2 : 0;
 397
 398         REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
 399                    OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
 400 }
 401
 402 /**
 403  * unblank_crtc
 404  * Call ASIC Control Object to UnBlank CRTC.
 405  */
 406 static void optc1_unblank_crtc(struct timing_generator *optc)
 407 {
 408         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 409
 410         REG_UPDATE_2(OTG_BLANK_CONTROL,
 411                         OTG_BLANK_DATA_EN, 0,
 412                         OTG_BLANK_DE_MODE, 0);
 413
 414         /* W/A for automated testing
 415          * Automated testing will fail underflow test as there
 416          * sporadic underflows which occur during the optc blank
 417          * sequence.  As a w/a, clear underflow on unblank.
 418          * This prevents the failure, but will not mask actual
 419          * underflow that affect real use cases.
 420          */
 421         optc1_clear_optc_underflow(optc);
 422 }
 423
 424 /**
 425  * blank_crtc
 426  * Call ASIC Control Object to Blank CRTC.
 427  */
 428
 429 static void optc1_blank_crtc(struct timing_generator *optc)
 430 {
 431         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 432
 433         REG_UPDATE_2(OTG_BLANK_CONTROL,
 434                         OTG_BLANK_DATA_EN, 1,
 435                         OTG_BLANK_DE_MODE, 0);
 436
 437         optc1_set_blank_data_double_buffer(optc, false);
 438 }
 439
 440 void optc1_set_blank(struct timing_generator *optc,
 441                 bool enable_blanking)
 442 {
 443         if (enable_blanking)
 444                 optc1_blank_crtc(optc);
 445         else
 446                 optc1_unblank_crtc(optc);
 447 }
 448
 449 bool optc1_is_blanked(struct timing_generator *optc)
 450 {
 451         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 452         uint32_t blank_en;
 453         uint32_t blank_state;
 454
 455         REG_GET_2(OTG_BLANK_CONTROL,
 456                         OTG_BLANK_DATA_EN, &blank_en,
 457                         OTG_CURRENT_BLANK_STATE, &blank_state);
 458
 459         return blank_en && blank_state;
 460 }
 461
 462 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
 463 {
 464         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 465
 466         if (enable) {
 467                 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
 468                                 OPTC_INPUT_CLK_EN, 1,
 469                                 OPTC_INPUT_CLK_GATE_DIS, 1);
 470
 471                 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
 472                                 OPTC_INPUT_CLK_ON, 1,
 473                                 1, 1000);
 474
 475                 /* Enable clock */
 476                 REG_UPDATE_2(OTG_CLOCK_CONTROL,
 477                                 OTG_CLOCK_EN, 1,
 478                                 OTG_CLOCK_GATE_DIS, 1);
 479                 REG_WAIT(OTG_CLOCK_CONTROL,
 480                                 OTG_CLOCK_ON, 1,
 481                                 1, 1000);
 482         } else  {
 483                 REG_UPDATE_2(OTG_CLOCK_CONTROL,
 484                                 OTG_CLOCK_GATE_DIS, 0,
 485                                 OTG_CLOCK_EN, 0);
 486
 487                 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
 488                                 OPTC_INPUT_CLK_GATE_DIS, 0,
 489                                 OPTC_INPUT_CLK_EN, 0);
 490         }
 491 }
 492
 493 /**
 494  * Enable CRTC
 495  * Enable CRTC - call ASIC Control Object to enable Timing generator.
 496  */
 497 static bool optc1_enable_crtc(struct timing_generator *optc)
 498 {
 499         /* TODO FPGA wait for answer
 500          * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
 501          * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
 502          */
 503         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 504
 505         /* opp instance for OTG. For DCN1.0, ODM is remoed.
 506          * OPP and OPTC should 1:1 mapping
 507          */
 508         REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
 509                         OPTC_SRC_SEL, optc->inst);
 510
 511         /* VTG enable first is for HW workaround */
 512         REG_UPDATE(CONTROL,
 513                         VTG0_ENABLE, 1);
 514
 515         REG_SEQ_START();
 516
 517         /* Enable CRTC */
 518         REG_UPDATE_2(OTG_CONTROL,
 519                         OTG_DISABLE_POINT_CNTL, 3,
 520                         OTG_MASTER_EN, 1);
 521
 522         REG_SEQ_SUBMIT();
 523         REG_SEQ_WAIT_DONE();
 524
 525         return true;
 526 }
 527
 528 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
 529 bool optc1_disable_crtc(struct timing_generator *optc)
 530 {
 531         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 532
 533         /* disable otg request until end of the first line
 534          * in the vertical blank region
 535          */
 536         REG_UPDATE_2(OTG_CONTROL,
 537                         OTG_DISABLE_POINT_CNTL, 3,
 538                         OTG_MASTER_EN, 0);
 539
 540         REG_UPDATE(CONTROL,
 541                         VTG0_ENABLE, 0);
 542
 543         /* CRTC disabled, so disable  clock. */
 544         REG_WAIT(OTG_CLOCK_CONTROL,
 545                         OTG_BUSY, 0,
 546                         1, 100000);
 547
 548         return true;
 549 }
 550
 551
 552 void optc1_program_blank_color(
 553                 struct timing_generator *optc,
 554                 const struct tg_color *black_color)
 555 {
 556         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 557
 558         REG_SET_3(OTG_BLACK_COLOR, 0,
 559                         OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
 560                         OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
 561                         OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
 562 }
 563
 564 bool optc1_validate_timing(
 565         struct timing_generator *optc,
 566         const struct dc_crtc_timing *timing)
 567 {
 568         uint32_t v_blank;
 569         uint32_t h_blank;
 570         uint32_t min_v_blank;
 571         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 572
 573         ASSERT(timing != NULL);
 574
 575         v_blank = (timing->v_total - timing->v_addressable -
 576                                         timing->v_border_top - timing->v_border_bottom);
 577
 578         h_blank = (timing->h_total - timing->h_addressable -
 579                 timing->h_border_right -
 580                 timing->h_border_left);
 581
 582         if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
 583                 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
 584                 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
 585                 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
 586                 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
 587                 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
 588                 return false;
 589
 590         /* Temporarily blocking interlacing mode until it's supported */
 591         if (timing->flags.INTERLACE == 1)
 592                 return false;
 593
 594         /* Check maximum number of pixels supported by Timing Generator
 595          * (Currently will never fail, in order to fail needs display which
 596          * needs more than 8192 horizontal and
 597          * more than 8192 vertical total pixels)
 598          */
 599         if (timing->h_total > optc1->max_h_total ||
 600                 timing->v_total > optc1->max_v_total)
 601                 return false;
 602
 603
 604         if (h_blank < optc1->min_h_blank)
 605                 return false;
 606
 607         if (timing->h_sync_width  < optc1->min_h_sync_width ||
 608                  timing->v_sync_width  < optc1->min_v_sync_width)
 609                 return false;
 610
 611         min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
 612
 613         if (v_blank < min_v_blank)
 614                 return false;
 615
 616         return true;
 617
 618 }
 619
 620 /*
 621  * get_vblank_counter
 622  *
 623  * @brief
 624  * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
 625  * holds the counter of frames.
 626  *
 627  * @param
 628  * struct timing_generator *optc - [in] timing generator which controls the
 629  * desired CRTC
 630  *
 631  * @return
 632  * Counter of frames, which should equal to number of vblanks.
 633  */
 634 uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
 635 {
 636         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 637         uint32_t frame_count;
 638
 639         REG_GET(OTG_STATUS_FRAME_COUNT,
 640                 OTG_FRAME_COUNT, &frame_count);
 641
 642         return frame_count;
 643 }
 644
 645 void optc1_lock(struct timing_generator *optc)
 646 {
 647         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 648         uint32_t regval = 0;
 649
 650         regval = REG_READ(OTG_CONTROL);
 651
 652         /* otg is not running, do not need to be locked */
 653         if ((regval & 0x1) == 0x0)
 654                 return;
 655
 656         REG_SET(OTG_GLOBAL_CONTROL0, 0,
 657                         OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
 658         REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 659                         OTG_MASTER_UPDATE_LOCK, 1);
 660
 661         /* Should be fast, status does not update on maximus */
 662         if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
 663
 664                 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
 665                                 UPDATE_LOCK_STATUS, 1,
 666                                 1, 10);
 667         }
 668 }
 669
 670 void optc1_unlock(struct timing_generator *optc)
 671 {
 672         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 673
 674         REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 675                         OTG_MASTER_UPDATE_LOCK, 0);
 676 }
 677
 678 bool optc1_is_locked(struct timing_generator *optc)
 679 {
 680         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 681         uint32_t locked;
 682
 683         REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &locked);
 684
 685         return (locked == 1);
 686 }
 687
 688 void optc1_get_position(struct timing_generator *optc,
 689                 struct crtc_position *position)
 690 {
 691         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 692
 693         REG_GET_2(OTG_STATUS_POSITION,
 694                         OTG_HORZ_COUNT, &position->horizontal_count,
 695                         OTG_VERT_COUNT, &position->vertical_count);
 696
 697         REG_GET(OTG_NOM_VERT_POSITION,
 698                         OTG_VERT_COUNT_NOM, &position->nominal_vcount);
 699 }
 700
 701 bool optc1_is_counter_moving(struct timing_generator *optc)
 702 {
 703         struct crtc_position position1, position2;
 704
 705         optc->funcs->get_position(optc, &position1);
 706         optc->funcs->get_position(optc, &position2);
 707
 708         if (position1.horizontal_count == position2.horizontal_count &&
 709                 position1.vertical_count == position2.vertical_count)
 710                 return false;
 711         else
 712                 return true;
 713 }
 714
 715 bool optc1_did_triggered_reset_occur(
 716         struct timing_generator *optc)
 717 {
 718         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 719         uint32_t occurred_force, occurred_vsync;
 720
 721         REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
 722                 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
 723
 724         REG_GET(OTG_VERT_SYNC_CONTROL,
 725                 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
 726
 727         return occurred_vsync != 0 || occurred_force != 0;
 728 }
 729
 730 void optc1_disable_reset_trigger(struct timing_generator *optc)
 731 {
 732         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 733
 734         REG_WRITE(OTG_TRIGA_CNTL, 0);
 735
 736         REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 737                 OTG_FORCE_COUNT_NOW_CLEAR, 1);
 738
 739         REG_SET(OTG_VERT_SYNC_CONTROL, 0,
 740                 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
 741 }
 742
 743 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
 744 {
 745         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 746         uint32_t falling_edge;
 747
 748         REG_GET(OTG_V_SYNC_A_CNTL,
 749                         OTG_V_SYNC_A_POL, &falling_edge);
 750
 751         if (falling_edge)
 752                 REG_SET_3(OTG_TRIGA_CNTL, 0,
 753                                 /* vsync signal from selected OTG pipe based
 754                                  * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 755                                  */
 756                                 OTG_TRIGA_SOURCE_SELECT, 20,
 757                                 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 758                                 /* always detect falling edge */
 759                                 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
 760         else
 761                 REG_SET_3(OTG_TRIGA_CNTL, 0,
 762                                 /* vsync signal from selected OTG pipe based
 763                                  * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 764                                  */
 765                                 OTG_TRIGA_SOURCE_SELECT, 20,
 766                                 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 767                                 /* always detect rising edge */
 768                                 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
 769
 770         REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 771                         /* force H count to H_TOTAL and V count to V_TOTAL in
 772                          * progressive mode and V_TOTAL-1 in interlaced mode
 773                          */
 774                         OTG_FORCE_COUNT_NOW_MODE, 2);
 775 }
 776
 777 void optc1_enable_crtc_reset(
 778                 struct timing_generator *optc,
 779                 int source_tg_inst,
 780                 struct crtc_trigger_info *crtc_tp)
 781 {
 782         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 783         uint32_t falling_edge = 0;
 784         uint32_t rising_edge = 0;
 785
 786         switch (crtc_tp->event) {
 787
 788         case CRTC_EVENT_VSYNC_RISING:
 789                 rising_edge = 1;
 790                 break;
 791
 792         case CRTC_EVENT_VSYNC_FALLING:
 793                 falling_edge = 1;
 794                 break;
 795         }
 796
 797         REG_SET_4(OTG_TRIGA_CNTL, 0,
 798                  /* vsync signal from selected OTG pipe based
 799                   * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 800                   */
 801                   OTG_TRIGA_SOURCE_SELECT, 20,
 802                   OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 803                   /* always detect falling edge */
 804                   OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
 805                   OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
 806
 807         switch (crtc_tp->delay) {
 808         case TRIGGER_DELAY_NEXT_LINE:
 809                 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
 810                                 OTG_AUTO_FORCE_VSYNC_MODE, 1);
 811                 break;
 812         case TRIGGER_DELAY_NEXT_PIXEL:
 813                 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 814                         /* force H count to H_TOTAL and V count to V_TOTAL in
 815                          * progressive mode and V_TOTAL-1 in interlaced mode
 816                          */
 817                         OTG_FORCE_COUNT_NOW_MODE, 2);
 818                 break;
 819         }
 820 }
 821
 822 void optc1_wait_for_state(struct timing_generator *optc,
 823                 enum crtc_state state)
 824 {
 825         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 826
 827         switch (state) {
 828         case CRTC_STATE_VBLANK:
 829                 REG_WAIT(OTG_STATUS,
 830                                 OTG_V_BLANK, 1,
 831                                 1, 100000); /* 1 vupdate at 10hz */
 832                 break;
 833
 834         case CRTC_STATE_VACTIVE:
 835                 REG_WAIT(OTG_STATUS,
 836                                 OTG_V_ACTIVE_DISP, 1,
 837                                 1, 100000); /* 1 vupdate at 10hz */
 838                 break;
 839
 840         default:
 841                 break;
 842         }
 843 }
 844
 845 void optc1_set_early_control(
 846         struct timing_generator *optc,
 847         uint32_t early_cntl)
 848 {
 849         /* asic design change, do not need this control
 850          * empty for share caller logic
 851          */
 852 }
 853
 854
 855 void optc1_set_static_screen_control(
 856         struct timing_generator *optc,
 857         uint32_t event_triggers,
 858         uint32_t num_frames)
 859 {
 860         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 861
 862         // By register spec, it only takes 8 bit value
 863         if (num_frames > 0xFF)
 864                 num_frames = 0xFF;
 865
 866         /* Bit 8 is no longer applicable in RV for PSR case,
 867          * set bit 8 to 0 if given
 868          */
 869         if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
 870                         != 0)
 871                 event_triggers = event_triggers &
 872                 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
 873
 874         REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
 875                         OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
 876                         OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
 877 }
 878
 879 void optc1_setup_manual_trigger(struct timing_generator *optc)
 880 {
 881         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 882
 883         REG_SET(OTG_GLOBAL_CONTROL2, 0,
 884                         MANUAL_FLOW_CONTROL_SEL, optc->inst);
 885
 886         REG_SET_8(OTG_TRIGA_CNTL, 0,
 887                         OTG_TRIGA_SOURCE_SELECT, 22,
 888                         OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
 889                         OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
 890                         OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
 891                         OTG_TRIGA_POLARITY_SELECT, 0,
 892                         OTG_TRIGA_FREQUENCY_SELECT, 0,
 893                         OTG_TRIGA_DELAY, 0,
 894                         OTG_TRIGA_CLEAR, 1);
 895 }
 896
 897 void optc1_program_manual_trigger(struct timing_generator *optc)
 898 {
 899         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 900
 901         REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
 902                         MANUAL_FLOW_CONTROL, 1);
 903
 904         REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
 905                         MANUAL_FLOW_CONTROL, 0);
 906 }
 907
 908
 909 /**
 910  *****************************************************************************
 911  *  Function: set_drr
 912  *
 913  *  @brief
 914  *     Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
 915  *
 916  *****************************************************************************
 917  */
 918 void optc1_set_drr(
 919         struct timing_generator *optc,
 920         const struct drr_params *params)
 921 {
 922         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 923
 924         if (params != NULL &&
 925                 params->vertical_total_max > 0 &&
 926                 params->vertical_total_min > 0) {
 927
 928                 if (params->vertical_total_mid != 0) {
 929
 930                         REG_SET(OTG_V_TOTAL_MID, 0,
 931                                 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
 932
 933                         REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
 934                                         OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
 935                                         OTG_VTOTAL_MID_FRAME_NUM,
 936                                         (uint8_t)params->vertical_total_mid_frame_num);
 937
 938                 }
 939
 940                 REG_SET(OTG_V_TOTAL_MAX, 0,
 941                         OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
 942
 943                 REG_SET(OTG_V_TOTAL_MIN, 0,
 944                         OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
 945
 946                 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
 947                                 OTG_V_TOTAL_MIN_SEL, 1,
 948                                 OTG_V_TOTAL_MAX_SEL, 1,
 949                                 OTG_FORCE_LOCK_ON_EVENT, 0,
 950                                 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
 951                                 OTG_SET_V_TOTAL_MIN_MASK, 0);
 952
 953                 // Setup manual flow control for EOF via TRIG_A
 954                 optc->funcs->setup_manual_trigger(optc);
 955
 956         } else {
 957                 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
 958                                 OTG_SET_V_TOTAL_MIN_MASK, 0,
 959                                 OTG_V_TOTAL_MIN_SEL, 0,
 960                                 OTG_V_TOTAL_MAX_SEL, 0,
 961                                 OTG_FORCE_LOCK_ON_EVENT, 0);
 962
 963                 REG_SET(OTG_V_TOTAL_MIN, 0,
 964                         OTG_V_TOTAL_MIN, 0);
 965
 966                 REG_SET(OTG_V_TOTAL_MAX, 0,
 967                         OTG_V_TOTAL_MAX, 0);
 968         }
 969 }
 970
 971 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
 972 {
 973         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 974
 975         REG_SET(OTG_V_TOTAL_MAX, 0,
 976                 OTG_V_TOTAL_MAX, vtotal_max);
 977
 978         REG_SET(OTG_V_TOTAL_MIN, 0,
 979                 OTG_V_TOTAL_MIN, vtotal_min);
 980 }
 981
 982 static void optc1_set_test_pattern(
 983         struct timing_generator *optc,
 984         /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
 985          * because this is not DP-specific (which is probably somewhere in DP
 986          * encoder) */
 987         enum controller_dp_test_pattern test_pattern,
 988         enum dc_color_depth color_depth)
 989 {
 990         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 991         enum test_pattern_color_format bit_depth;
 992         enum test_pattern_dyn_range dyn_range;
 993         enum test_pattern_mode mode;
 994         uint32_t pattern_mask;
 995         uint32_t pattern_data;
 996         /* color ramp generator mixes 16-bits color */
 997         uint32_t src_bpc = 16;
 998         /* requested bpc */
 999         uint32_t dst_bpc;
1000         uint32_t index;
1001         /* RGB values of the color bars.
1002          * Produce two RGB colors: RGB0 - white (all Fs)
1003          * and RGB1 - black (all 0s)
1004          * (three RGB components for two colors)
1005          */
1006         uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
1007                                                 0x0000, 0x0000};
1008         /* dest color (converted to the specified color format) */
1009         uint16_t dst_color[6];
1010         uint32_t inc_base;
1011
1012         /* translate to bit depth */
1013         switch (color_depth) {
1014         case COLOR_DEPTH_666:
1015                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
1016         break;
1017         case COLOR_DEPTH_888:
1018                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
1019         break;
1020         case COLOR_DEPTH_101010:
1021                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
1022         break;
1023         case COLOR_DEPTH_121212:
1024                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
1025         break;
1026         default:
1027                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
1028         break;
1029         }
1030
1031         switch (test_pattern) {
1032         case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
1033         case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
1034         {
1035                 dyn_range = (test_pattern ==
1036                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
1037                                 TEST_PATTERN_DYN_RANGE_CEA :
1038                                 TEST_PATTERN_DYN_RANGE_VESA);
1039                 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
1040
1041                 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
1042                                 OTG_TEST_PATTERN_VRES, 6,
1043                                 OTG_TEST_PATTERN_HRES, 6);
1044
1045                 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1046                                 OTG_TEST_PATTERN_EN, 1,
1047                                 OTG_TEST_PATTERN_MODE, mode,
1048                                 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
1049                                 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1050         }
1051         break;
1052
1053         case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
1054         case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
1055         {
1056                 mode = (test_pattern ==
1057                         CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
1058                         TEST_PATTERN_MODE_VERTICALBARS :
1059                         TEST_PATTERN_MODE_HORIZONTALBARS);
1060
1061                 switch (bit_depth) {
1062                 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1063                         dst_bpc = 6;
1064                 break;
1065                 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1066                         dst_bpc = 8;
1067                 break;
1068                 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1069                         dst_bpc = 10;
1070                 break;
1071                 default:
1072                         dst_bpc = 8;
1073                 break;
1074                 }
1075
1076                 /* adjust color to the required colorFormat */
1077                 for (index = 0; index < 6; index++) {
1078                         /* dst = 2^dstBpc * src / 2^srcBpc = src >>
1079                          * (srcBpc - dstBpc);
1080                          */
1081                         dst_color[index] =
1082                                 src_color[index] >> (src_bpc - dst_bpc);
1083                 /* CRTC_TEST_PATTERN_DATA has 16 bits,
1084                  * lowest 6 are hardwired to ZERO
1085                  * color bits should be left aligned aligned to MSB
1086                  * XXXXXXXXXX000000 for 10 bit,
1087                  * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
1088                  */
1089                         dst_color[index] <<= (16 - dst_bpc);
1090                 }
1091
1092                 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1093
1094                 /* We have to write the mask before data, similar to pipeline.
1095                  * For example, for 8 bpc, if we want RGB0 to be magenta,
1096                  * and RGB1 to be cyan,
1097                  * we need to make 7 writes:
1098                  * MASK   DATA
1099                  * 000001 00000000 00000000                     set mask to R0
1100                  * 000010 11111111 00000000     R0 255, 0xFF00, set mask to G0
1101                  * 000100 00000000 00000000     G0 0,   0x0000, set mask to B0
1102                  * 001000 11111111 00000000     B0 255, 0xFF00, set mask to R1
1103                  * 010000 00000000 00000000     R1 0,   0x0000, set mask to G1
1104                  * 100000 11111111 00000000     G1 255, 0xFF00, set mask to B1
1105                  * 100000 11111111 00000000     B1 255, 0xFF00
1106                  *
1107                  * we will make a loop of 6 in which we prepare the mask,
1108                  * then write, then prepare the color for next write.
1109                  * first iteration will write mask only,
1110                  * but each next iteration color prepared in
1111                  * previous iteration will be written within new mask,
1112                  * the last component will written separately,
1113                  * mask is not changing between 6th and 7th write
1114                  * and color will be prepared by last iteration
1115                  */
1116
1117                 /* write color, color values mask in CRTC_TEST_PATTERN_MASK
1118                  * is B1, G1, R1, B0, G0, R0
1119                  */
1120                 pattern_data = 0;
1121                 for (index = 0; index < 6; index++) {
1122                         /* prepare color mask, first write PATTERN_DATA
1123                          * will have all zeros
1124                          */
1125                         pattern_mask = (1 << index);
1126
1127                         /* write color component */
1128                         REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1129                                         OTG_TEST_PATTERN_MASK, pattern_mask,
1130                                         OTG_TEST_PATTERN_DATA, pattern_data);
1131
1132                         /* prepare next color component,
1133                          * will be written in the next iteration
1134                          */
1135                         pattern_data = dst_color[index];
1136                 }
1137                 /* write last color component,
1138                  * it's been already prepared in the loop
1139                  */
1140                 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1141                                 OTG_TEST_PATTERN_MASK, pattern_mask,
1142                                 OTG_TEST_PATTERN_DATA, pattern_data);
1143
1144                 /* enable test pattern */
1145                 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1146                                 OTG_TEST_PATTERN_EN, 1,
1147                                 OTG_TEST_PATTERN_MODE, mode,
1148                                 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1149                                 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1150         }
1151         break;
1152
1153         case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1154         {
1155                 mode = (bit_depth ==
1156                         TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1157                         TEST_PATTERN_MODE_DUALRAMP_RGB :
1158                         TEST_PATTERN_MODE_SINGLERAMP_RGB);
1159
1160                 switch (bit_depth) {
1161                 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1162                         dst_bpc = 6;
1163                 break;
1164                 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1165                         dst_bpc = 8;
1166                 break;
1167                 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1168                         dst_bpc = 10;
1169                 break;
1170                 default:
1171                         dst_bpc = 8;
1172                 break;
1173                 }
1174
1175                 /* increment for the first ramp for one color gradation
1176                  * 1 gradation for 6-bit color is 2^10
1177                  * gradations in 16-bit color
1178                  */
1179                 inc_base = (src_bpc - dst_bpc);
1180
1181                 switch (bit_depth) {
1182                 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1183                 {
1184                         REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1185                                         OTG_TEST_PATTERN_INC0, inc_base,
1186                                         OTG_TEST_PATTERN_INC1, 0,
1187                                         OTG_TEST_PATTERN_HRES, 6,
1188                                         OTG_TEST_PATTERN_VRES, 6,
1189                                         OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1190                 }
1191                 break;
1192                 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1193                 {
1194                         REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1195                                         OTG_TEST_PATTERN_INC0, inc_base,
1196                                         OTG_TEST_PATTERN_INC1, 0,
1197                                         OTG_TEST_PATTERN_HRES, 8,
1198                                         OTG_TEST_PATTERN_VRES, 6,
1199                                         OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1200                 }
1201                 break;
1202                 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1203                 {
1204                         REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1205                                         OTG_TEST_PATTERN_INC0, inc_base,
1206                                         OTG_TEST_PATTERN_INC1, inc_base + 2,
1207                                         OTG_TEST_PATTERN_HRES, 8,
1208                                         OTG_TEST_PATTERN_VRES, 5,
1209                                         OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1210                 }
1211                 break;
1212                 default:
1213                 break;
1214                 }
1215
1216                 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1217
1218                 /* enable test pattern */
1219                 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1220
1221                 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1222                                 OTG_TEST_PATTERN_EN, 1,
1223                                 OTG_TEST_PATTERN_MODE, mode,
1224                                 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1225                                 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1226         }
1227         break;
1228         case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1229         {
1230                 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1231                 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1232                 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1233         }
1234         break;
1235         default:
1236                 break;
1237
1238         }
1239 }
1240
1241 void optc1_get_crtc_scanoutpos(
1242         struct timing_generator *optc,
1243         uint32_t *v_blank_start,
1244         uint32_t *v_blank_end,
1245         uint32_t *h_position,
1246         uint32_t *v_position)
1247 {
1248         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1249         struct crtc_position position;
1250
1251         REG_GET_2(OTG_V_BLANK_START_END,
1252                         OTG_V_BLANK_START, v_blank_start,
1253                         OTG_V_BLANK_END, v_blank_end);
1254
1255         optc1_get_position(optc, &position);
1256
1257         *h_position = position.horizontal_count;
1258         *v_position = position.vertical_count;
1259 }
1260
1261 static void optc1_enable_stereo(struct timing_generator *optc,
1262         const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1263 {
1264         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1265
1266         if (flags) {
1267                 uint32_t stereo_en;
1268                 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1269
1270                 if (flags->PROGRAM_STEREO)
1271                         REG_UPDATE_3(OTG_STEREO_CONTROL,
1272                                 OTG_STEREO_EN, stereo_en,
1273                                 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1274                                 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1275
1276                 if (flags->PROGRAM_POLARITY)
1277                         REG_UPDATE(OTG_STEREO_CONTROL,
1278                                 OTG_STEREO_EYE_FLAG_POLARITY,
1279                                 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1280
1281                 if (flags->DISABLE_STEREO_DP_SYNC)
1282                         REG_UPDATE(OTG_STEREO_CONTROL,
1283                                 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1284
1285                 if (flags->PROGRAM_STEREO)
1286                         REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1287                                 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1288                                 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1289
1290         }
1291 }
1292
1293 void optc1_program_stereo(struct timing_generator *optc,
1294         const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1295 {
1296         if (flags->PROGRAM_STEREO)
1297                 optc1_enable_stereo(optc, timing, flags);
1298         else
1299                 optc1_disable_stereo(optc);
1300 }
1301
1302
1303 bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1304 {
1305         bool ret = false;
1306         uint32_t left_eye = 0;
1307         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1308
1309         REG_GET(OTG_STEREO_STATUS,
1310                 OTG_STEREO_CURRENT_EYE, &left_eye);
1311         if (left_eye == 1)
1312                 ret = true;
1313         else
1314                 ret = false;
1315
1316         return ret;
1317 }
1318
1319 bool optc1_get_hw_timing(struct timing_generator *tg,
1320                 struct dc_crtc_timing *hw_crtc_timing)
1321 {
1322         struct dcn_otg_state s = {0};
1323
1324         if (tg == NULL || hw_crtc_timing == NULL)
1325                 return false;
1326
1327         optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1328
1329         hw_crtc_timing->h_total = s.h_total + 1;
1330         hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1331         hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
1332         hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1333
1334         hw_crtc_timing->v_total = s.v_total + 1;
1335         hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1336         hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
1337         hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1338
1339         return true;
1340 }
1341
1342
1343 void optc1_read_otg_state(struct optc *optc1,
1344                 struct dcn_otg_state *s)
1345 {
1346         REG_GET(OTG_CONTROL,
1347                         OTG_MASTER_EN, &s->otg_enabled);
1348
1349         REG_GET_2(OTG_V_BLANK_START_END,
1350                         OTG_V_BLANK_START, &s->v_blank_start,
1351                         OTG_V_BLANK_END, &s->v_blank_end);
1352
1353         REG_GET(OTG_V_SYNC_A_CNTL,
1354                         OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1355
1356         REG_GET(OTG_V_TOTAL,
1357                         OTG_V_TOTAL, &s->v_total);
1358
1359         REG_GET(OTG_V_TOTAL_MAX,
1360                         OTG_V_TOTAL_MAX, &s->v_total_max);
1361
1362         REG_GET(OTG_V_TOTAL_MIN,
1363                         OTG_V_TOTAL_MIN, &s->v_total_min);
1364
1365         REG_GET(OTG_V_TOTAL_CONTROL,
1366                         OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1367
1368         REG_GET(OTG_V_TOTAL_CONTROL,
1369                         OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1370
1371         REG_GET_2(OTG_V_SYNC_A,
1372                         OTG_V_SYNC_A_START, &s->v_sync_a_start,
1373                         OTG_V_SYNC_A_END, &s->v_sync_a_end);
1374
1375         REG_GET_2(OTG_H_BLANK_START_END,
1376                         OTG_H_BLANK_START, &s->h_blank_start,
1377                         OTG_H_BLANK_END, &s->h_blank_end);
1378
1379         REG_GET_2(OTG_H_SYNC_A,
1380                         OTG_H_SYNC_A_START, &s->h_sync_a_start,
1381                         OTG_H_SYNC_A_END, &s->h_sync_a_end);
1382
1383         REG_GET(OTG_H_SYNC_A_CNTL,
1384                         OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1385
1386         REG_GET(OTG_H_TOTAL,
1387                         OTG_H_TOTAL, &s->h_total);
1388
1389         REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1390                         OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1391 }
1392
1393 bool optc1_get_otg_active_size(struct timing_generator *optc,
1394                 uint32_t *otg_active_width,
1395                 uint32_t *otg_active_height)
1396 {
1397         uint32_t otg_enabled;
1398         uint32_t v_blank_start;
1399         uint32_t v_blank_end;
1400         uint32_t h_blank_start;
1401         uint32_t h_blank_end;
1402         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1403
1404
1405         REG_GET(OTG_CONTROL,
1406                         OTG_MASTER_EN, &otg_enabled);
1407
1408         if (otg_enabled == 0)
1409                 return false;
1410
1411         REG_GET_2(OTG_V_BLANK_START_END,
1412                         OTG_V_BLANK_START, &v_blank_start,
1413                         OTG_V_BLANK_END, &v_blank_end);
1414
1415         REG_GET_2(OTG_H_BLANK_START_END,
1416                         OTG_H_BLANK_START, &h_blank_start,
1417                         OTG_H_BLANK_END, &h_blank_end);
1418
1419         *otg_active_width = v_blank_start - v_blank_end;
1420         *otg_active_height = h_blank_start - h_blank_end;
1421         return true;
1422 }
1423
1424 void optc1_clear_optc_underflow(struct timing_generator *optc)
1425 {
1426         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1427
1428         REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1429 }
1430
1431 void optc1_tg_init(struct timing_generator *optc)
1432 {
1433         optc1_set_blank_data_double_buffer(optc, true);
1434         optc1_set_timing_double_buffer(optc, true);
1435         optc1_clear_optc_underflow(optc);
1436 }
1437
1438 bool optc1_is_tg_enabled(struct timing_generator *optc)
1439 {
1440         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1441         uint32_t otg_enabled = 0;
1442
1443         REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1444
1445         return (otg_enabled != 0);
1446
1447 }
1448
1449 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1450 {
1451         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1452         uint32_t underflow_occurred = 0;
1453
1454         REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1455                         OPTC_UNDERFLOW_OCCURRED_STATUS,
1456                         &underflow_occurred);
1457
1458         return (underflow_occurred == 1);
1459 }
1460
1461 bool optc1_configure_crc(struct timing_generator *optc,
1462                           const struct crc_params *params)
1463 {
1464         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1465
1466         /* Cannot configure crc on a CRTC that is disabled */
1467         if (!optc1_is_tg_enabled(optc))
1468                 return false;
1469
1470         REG_WRITE(OTG_CRC_CNTL, 0);
1471
1472         if (!params->enable)
1473                 return true;
1474
1475         /* Program frame boundaries */
1476         /* Window A x axis start and end. */
1477         REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1478                         OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1479                         OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1480
1481         /* Window A y axis start and end. */
1482         REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1483                         OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1484                         OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1485
1486         /* Window B x axis start and end. */
1487         REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1488                         OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1489                         OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1490
1491         /* Window B y axis start and end. */
1492         REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1493                         OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1494                         OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1495
1496         /* Set crc mode and selection, and enable. Only using CRC0*/
1497         REG_UPDATE_3(OTG_CRC_CNTL,
1498                         OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1499                         OTG_CRC0_SELECT, params->selection,
1500                         OTG_CRC_EN, 1);
1501
1502         return true;
1503 }
1504
1505 bool optc1_get_crc(struct timing_generator *optc,
1506                     uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1507 {
1508         uint32_t field = 0;
1509         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1510
1511         REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1512
1513         /* Early return if CRC is not enabled for this CRTC */
1514         if (!field)
1515                 return false;
1516
1517         REG_GET_2(OTG_CRC0_DATA_RG,
1518                         CRC0_R_CR, r_cr,
1519                         CRC0_G_Y, g_y);
1520
1521         REG_GET(OTG_CRC0_DATA_B,
1522                         CRC0_B_CB, b_cb);
1523
1524         return true;
1525 }
1526
1527 static const struct timing_generator_funcs dcn10_tg_funcs = {
1528                 .validate_timing = optc1_validate_timing,
1529                 .program_timing = optc1_program_timing,
1530                 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1531                 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1532                 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1533                 .program_global_sync = optc1_program_global_sync,
1534                 .enable_crtc = optc1_enable_crtc,
1535                 .disable_crtc = optc1_disable_crtc,
1536                 /* used by enable_timing_synchronization. Not need for FPGA */
1537                 .is_counter_moving = optc1_is_counter_moving,
1538                 .get_position = optc1_get_position,
1539                 .get_frame_count = optc1_get_vblank_counter,
1540                 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1541                 .get_otg_active_size = optc1_get_otg_active_size,
1542                 .set_early_control = optc1_set_early_control,
1543                 /* used by enable_timing_synchronization. Not need for FPGA */
1544                 .wait_for_state = optc1_wait_for_state,
1545                 .set_blank = optc1_set_blank,
1546                 .is_blanked = optc1_is_blanked,
1547                 .set_blank_color = optc1_program_blank_color,
1548                 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1549                 .enable_reset_trigger = optc1_enable_reset_trigger,
1550                 .enable_crtc_reset = optc1_enable_crtc_reset,
1551                 .disable_reset_trigger = optc1_disable_reset_trigger,
1552                 .lock = optc1_lock,
1553                 .is_locked = optc1_is_locked,
1554                 .unlock = optc1_unlock,
1555                 .enable_optc_clock = optc1_enable_optc_clock,
1556                 .set_drr = optc1_set_drr,
1557                 .get_last_used_drr_vtotal = NULL,
1558                 .set_static_screen_control = optc1_set_static_screen_control,
1559                 .set_test_pattern = optc1_set_test_pattern,
1560                 .program_stereo = optc1_program_stereo,
1561                 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1562                 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1563                 .tg_init = optc1_tg_init,
1564                 .is_tg_enabled = optc1_is_tg_enabled,
1565                 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1566                 .clear_optc_underflow = optc1_clear_optc_underflow,
1567                 .get_crc = optc1_get_crc,
1568                 .configure_crc = optc1_configure_crc,
1569                 .set_vtg_params = optc1_set_vtg_params,
1570                 .program_manual_trigger = optc1_program_manual_trigger,
1571                 .setup_manual_trigger = optc1_setup_manual_trigger,
1572                 .get_hw_timing = optc1_get_hw_timing,
1573 };
1574
1575 void dcn10_timing_generator_init(struct optc *optc1)
1576 {
1577         optc1->base.funcs = &dcn10_tg_funcs;
1578
1579         optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1580         optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1581
1582         optc1->min_h_blank = 32;
1583         optc1->min_v_blank = 3;
1584         optc1->min_v_blank_interlace = 5;
1585         optc1->min_h_sync_width = 4;
1586         optc1->min_v_sync_width = 1;
1587 }
1588
1589 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
1590  *
1591  * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1592  *   containter rate.
1593  *
1594  * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1595  *   halved to maintain the correct pixel rate.
1596  *
1597  * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1598  *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
1599  *
1600  */
1601 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
1602 {
1603         bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1604
1605         two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
1606                         && !timing->dsc_cfg.ycbcr422_simple);
1607         return two_pix;
1608 }
1609