2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "reg_helper.h"
27 #include "dcn10_mpc.h"
36 #define FN(reg_name, field_name) \
37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
40 void mpc1_set_bg_color(struct mpc *mpc,
41 struct tg_color *bg_color,
44 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
46 uint32_t bg_r_cr, bg_g_y, bg_b_cb;
48 bottommost_mpcc->blnd_cfg.black_color = *bg_color;
50 /* find bottommost mpcc. */
51 while (bottommost_mpcc->mpcc_bot) {
52 /* avoid circular linked link */
53 ASSERT(bottommost_mpcc != bottommost_mpcc->mpcc_bot);
54 if (bottommost_mpcc == bottommost_mpcc->mpcc_bot)
57 bottommost_mpcc = bottommost_mpcc->mpcc_bot;
60 /* mpc color is 12 bit. tg_color is 10 bit */
61 /* todo: might want to use 16 bit to represent color and have each
62 * hw block translate to correct color depth.
64 bg_r_cr = bg_color->color_r_cr << 2;
65 bg_g_y = bg_color->color_g_y << 2;
66 bg_b_cb = bg_color->color_b_cb << 2;
68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
69 MPCC_BG_R_CR, bg_r_cr);
70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
73 MPCC_BG_B_CB, bg_b_cb);
76 static void mpc1_update_blending(
78 struct mpcc_blnd_cfg *blnd_cfg,
81 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
84 REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
85 MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,
86 MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha,
87 MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only,
88 MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha,
89 MPCC_GLOBAL_GAIN, blnd_cfg->global_gain);
91 mpcc->blnd_cfg = *blnd_cfg;
94 void mpc1_update_stereo_mix(
96 struct mpcc_sm_cfg *sm_cfg,
99 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
101 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id],
102 MPCC_SM_EN, sm_cfg->enable,
103 MPCC_SM_MODE, sm_cfg->sm_mode,
104 MPCC_SM_FRAME_ALT, sm_cfg->frame_alt,
105 MPCC_SM_FIELD_ALT, sm_cfg->field_alt,
106 MPCC_SM_FORCE_NEXT_FRAME_POL, sm_cfg->force_next_frame_porlarity,
107 MPCC_SM_FORCE_NEXT_TOP_POL, sm_cfg->force_next_field_polarity);
109 void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)
111 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
113 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
114 REG_WAIT(MPCC_STATUS[id],
119 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
121 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
123 ASSERT(mpcc_id < mpc10->num_mpcc);
124 return &(mpc->mpcc_array[mpcc_id]);
127 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
129 struct mpcc *tmp_mpcc = tree->opp_list;
131 while (tmp_mpcc != NULL) {
132 if (tmp_mpcc->dpp_id == dpp_id)
134 tmp_mpcc = tmp_mpcc->mpcc_bot;
139 bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id)
141 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
142 unsigned int top_sel;
146 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
147 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
148 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle);
149 if (top_sel == 0xf && opp_id == 0xf && idle)
155 void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
157 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
158 unsigned int top_sel, mpc_busy, mpc_idle;
160 REG_GET(MPCC_TOP_SEL[mpcc_id],
161 MPCC_TOP_SEL, &top_sel);
163 if (top_sel == 0xf) {
164 REG_GET_2(MPCC_STATUS[mpcc_id],
165 MPCC_BUSY, &mpc_busy,
166 MPCC_IDLE, &mpc_idle);
168 ASSERT(mpc_busy == 0);
169 ASSERT(mpc_idle == 1);
174 * Insert DPP into MPC tree based on specified blending position.
175 * Only used for planes that are part of blending chain for OPP output
178 * [in/out] mpc - MPC context.
179 * [in/out] tree - MPC tree structure that plane will be added to.
180 * [in] blnd_cfg - MPCC blending configuration for the new blending layer.
181 * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer.
182 * stereo mix must disable for the very bottom layer of the tree config.
183 * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.
184 * [in] dpp_id - DPP instance for the plane to be added.
185 * [in] mpcc_id - The MPCC physical instance to use for blending.
187 * Return: struct mpcc* - MPCC that was added.
189 struct mpcc *mpc1_insert_plane(
191 struct mpc_tree *tree,
192 struct mpcc_blnd_cfg *blnd_cfg,
193 struct mpcc_sm_cfg *sm_cfg,
194 struct mpcc *insert_above_mpcc,
198 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
199 struct mpcc *new_mpcc = NULL;
201 /* sanity check parameters */
202 ASSERT(mpcc_id < mpc10->num_mpcc);
203 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
205 if (insert_above_mpcc) {
206 /* check insert_above_mpcc exist in tree->opp_list */
207 struct mpcc *temp_mpcc = tree->opp_list;
209 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
210 temp_mpcc = temp_mpcc->mpcc_bot;
211 if (temp_mpcc == NULL)
215 /* Get and update MPCC struct parameters */
216 new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
217 new_mpcc->dpp_id = dpp_id;
219 /* program mux and MPCC_MODE */
220 if (insert_above_mpcc) {
221 new_mpcc->mpcc_bot = insert_above_mpcc;
222 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);
223 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
225 new_mpcc->mpcc_bot = NULL;
226 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
227 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
229 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
230 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
232 /* Configure VUPDATE lock set for this MPCC to map to the OPP */
233 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
235 /* update mpc tree mux setting */
236 if (tree->opp_list == insert_above_mpcc) {
237 /* insert the toppest mpcc */
238 tree->opp_list = new_mpcc;
239 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
241 /* find insert position */
242 struct mpcc *temp_mpcc = tree->opp_list;
244 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
245 temp_mpcc = temp_mpcc->mpcc_bot;
246 if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) {
247 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);
248 temp_mpcc->mpcc_bot = new_mpcc;
249 if (!insert_above_mpcc)
250 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
251 MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
255 /* update the blending configuration */
256 mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
258 /* update the stereo mix settings, if provided */
259 if (sm_cfg != NULL) {
260 new_mpcc->sm_cfg = *sm_cfg;
261 mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);
264 /* mark this mpcc as in use */
265 mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
271 * Remove a specified MPCC from the MPC tree.
274 * [in/out] mpc - MPC context.
275 * [in/out] tree - MPC tree structure that plane will be removed from.
276 * [in/out] mpcc - MPCC to be removed from tree.
280 void mpc1_remove_mpcc(
282 struct mpc_tree *tree,
283 struct mpcc *mpcc_to_remove)
285 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
287 int mpcc_id = mpcc_to_remove->mpcc_id;
289 if (tree->opp_list == mpcc_to_remove) {
291 /* remove MPCC from top of tree */
292 if (mpcc_to_remove->mpcc_bot) {
293 /* set the next MPCC in list to be the top MPCC */
294 tree->opp_list = mpcc_to_remove->mpcc_bot;
295 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);
297 /* there are no other MPCC is list */
298 tree->opp_list = NULL;
299 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
302 /* find mpcc to remove MPCC list */
303 struct mpcc *temp_mpcc = tree->opp_list;
305 while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove)
306 temp_mpcc = temp_mpcc->mpcc_bot;
308 if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) {
310 temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot;
311 if (mpcc_to_remove->mpcc_bot) {
312 /* remove MPCC in middle of list */
313 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
314 MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id);
316 /* remove MPCC from bottom of list */
317 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
319 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
320 MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
326 /* turn off MPCC mux registers */
327 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
328 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
329 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
330 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
332 /* mark this mpcc as not in use */
333 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
334 mpcc_to_remove->dpp_id = 0xf;
335 mpcc_to_remove->mpcc_bot = NULL;
337 /* In case of resume from S3/S4, remove mpcc from bios left over */
338 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
339 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
340 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
341 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
345 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
347 mpcc->mpcc_id = mpcc_inst;
349 mpcc->mpcc_bot = NULL;
350 mpcc->blnd_cfg.overlap_only = false;
351 mpcc->blnd_cfg.global_alpha = 0xff;
352 mpcc->blnd_cfg.global_gain = 0xff;
353 mpcc->sm_cfg.enable = false;
357 * Reset the MPCC HW status by disconnecting all muxes.
360 * [in/out] mpc - MPC context.
364 void mpc1_mpc_init(struct mpc *mpc)
366 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
370 mpc10->mpcc_in_use_mask = 0;
371 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
372 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
373 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
374 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
375 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
377 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
380 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
381 if (REG(MUX[opp_id]))
382 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
386 void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
388 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
391 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
393 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
394 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
395 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
396 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
398 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
400 if (opp_id < MAX_OPP && REG(MUX[opp_id]))
401 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
405 void mpc1_init_mpcc_list_from_hw(
407 struct mpc_tree *tree)
409 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
411 unsigned int top_sel;
412 unsigned int bot_sel;
413 unsigned int out_mux;
418 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);
420 if (out_mux != 0xf) {
421 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
422 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
423 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
424 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel);
426 if (bot_sel == mpcc_id)
429 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
430 mpcc = mpc1_get_mpcc(mpc, mpcc_id);
431 mpcc->dpp_id = top_sel;
432 mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
434 if (out_mux == mpcc_id)
435 tree->opp_list = mpcc;
436 if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) {
437 bot_mpcc_id = bot_sel;
438 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id);
439 REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);
440 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
441 struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);
443 mpcc->mpcc_bot = mpcc_bottom;
451 void mpc1_read_mpcc_state(
454 struct mpcc_state *s)
456 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
458 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
459 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
460 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
461 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
462 MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
463 MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
464 MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
465 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
466 MPCC_BUSY, &s->busy);
469 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
471 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
473 REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
476 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
478 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
481 if (opp_id < MAX_OPP && REG(MUX[opp_id]))
482 REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);
487 static const struct mpc_funcs dcn10_mpc_funcs = {
488 .read_mpcc_state = mpc1_read_mpcc_state,
489 .insert_plane = mpc1_insert_plane,
490 .remove_mpcc = mpc1_remove_mpcc,
491 .mpc_init = mpc1_mpc_init,
492 .mpc_init_single_inst = mpc1_mpc_init_single_inst,
493 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
494 .wait_for_idle = mpc1_assert_idle_mpcc,
495 .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
496 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
497 .update_blending = mpc1_update_blending,
498 .cursor_lock = mpc1_cursor_lock,
500 .set_denorm_clamp = NULL,
501 .set_output_csc = NULL,
502 .set_output_gamma = NULL,
503 .get_mpc_out_mux = mpc1_get_mpc_out_mux,
504 .set_bg_color = mpc1_set_bg_color,
507 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
508 struct dc_context *ctx,
509 const struct dcn_mpc_registers *mpc_regs,
510 const struct dcn_mpc_shift *mpc_shift,
511 const struct dcn_mpc_mask *mpc_mask,
516 mpc10->base.ctx = ctx;
518 mpc10->base.funcs = &dcn10_mpc_funcs;
520 mpc10->mpc_regs = mpc_regs;
521 mpc10->mpc_shift = mpc_shift;
522 mpc10->mpc_mask = mpc_mask;
524 mpc10->mpcc_in_use_mask = 0;
525 mpc10->num_mpcc = num_mpcc;
527 for (i = 0; i < MAX_MPCC; i++)
528 mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i);